Motorola MCM63P631ATQ75, MCM63P631ATQ75R, MCM63P631ATQ66R, MCM63P631ATQ100R, MCM63P631ATQ117 Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

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64K x 32 Bit Pipelined BurstRAM
Synchronous Fast Static RAM

The MCM63P631A is a 2M bit synchronous fast static RAM designed to pro­vide a burstable, high performance, secondary cache for the 68K Family , Pow­erPC, and Pentium microprocessors. It is organized as 64K words of 32 bits
each. This device integrates input registers, an output register, a 2–bit address
counter, and high speed SRAM onto a single monolithic circuit for reduced parts
count in cache data RAM applications. Synchronous design allows precise cycle
control with the use of an external clock (K). CMOS circuitry reduces the overall
power consumption of the integrated functions for greater reliability .

Addresses (SA), data inputs (DQx), and all control signals except output
enable (G
trolled through positive–edge–triggered noninverting registers.

Bursts can be initiated with either ADSP
addresses can be generated internally by the MCM63P631A (burst sequence
operates in linear or interleaved mode dependent upon state of LBO
trolled by the burst address advance (ADV

Write cycles are internally self–timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.

Synchronous byte write (SBx
nous write enable SW
all bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa controls
DQa, SBb
writes SBx
or if all SBx

For read cycles, pipelined SRAMs output data is temporarily stored by an
edge–triggered output register and then released to the output buffers at the next
rising edge of clock (K).

The MCM63P631A operates from a 3.3 V power supply , all inputs and outputs
are L VTTL compatible.

• MCM63P631A–117 = 4.5 ns access / 8.5 ns cycle (117 MHz)

• Single 3.3 V + 10%, – 5% Power Supply

• ADSP

• Selectable Burst Sequencing Order (Linear/Interleaved)

• Internally Self–Timed Write Cycle

• Byte Write and Global Write Control

• Sleep Mode (ZZ)

• PB1 Version 2.0 Compatible

• Single–Cycle Deselect Timing

• JEDEC Standard 100–Pin TQFP Package

), sleep mode (ZZ), and Linear Burst Order (LBO) are clock (K) con-

or ADSC input pins. Subsequent burst

) and con-

) input pin.

), synchronous global write (SGW), and synchro-

are provided to allow writes to either individual bytes or to

controls DQb, etc. Individual bytes are written if the selected byte

are asserted with SW. All bytes are written if either SGW is asserted

and SW are asserted.

MCM63P631A–100 = 4.5 ns access / 10 ns cycle (100 MHz)
MCM63P631A–75 = 7 ns access / 13.3 ns cycle (75 MHz)
MCM63P631A–66 = 8 ns access / 15 ns cycle (66 MHz)

, ADSC, and ADV Burst Control Pins

Order this document

by MCM63P631A/D

MCM63P631A

TQ PACKAGE

TQFP

CASE 983A–01

The PowerPC name is a trademark of IBM Corp., used under license therefrom.
Pentium is a trademark of Intel Corp.

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

9/30/97

 Motorola, Inc. 1997

MOTOROLA FAST SRAM

MCM63P631A

1

LBO

ADV

K

ADSC
ADSP

SA
SA1
SA0

SGW

FUNCTIONAL BLOCK DIAGRAM

K2

ADDRESS

REGISTER

CLR

16

BURST

COUNTER

2

14

2

16

64K x 32 ARRAY

SW

SBa

SBb

SBc

SBd

SE1
SE2

SE3

WRITE

REGISTER

a

WRITE

REGISTER

b

WRITE

REGISTER

c

WRITE

REGISTER

d

K2 K

ENABLE

REGISTER

ENABLE

REGISTER

4

DATA–IN

REGISTER

K

32

32

DATA–OUT
REGISTER

G

ZZ

MCM63P631A
2

DQa – DQd

MOTOROLA FAST SRAM

PIN ASSIGNMENT

NC
DQc
DQc

V

DD
V

SS
DQc
DQc
DQc
DQc

V

SS

V

DD

DQc
DQc

NC

V

DD
NC

V

SS

DQd
DQd
V

DD

V

SS

DQd
DQd
DQd

DQd
V

SS

V

DD
DQd
DQd

NC

SASASE1

1
2

3
4

5
6
7
8

9
10

11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

26
27
28
29

30

31 32 33

SE2

SBc

SBd

SBb

94 9397 96 95 89 8892 91 90 86 8587100 99 98 81828384

37 3834 35 36 42 4339 40 41 45 4644

SBa

SE3

DD

VSSV

K

SW

SGW

G

ADSP

ADSC

ADV

SA

50494847

80
79
78
77
76
75
74
73

71
70

72

69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

SA

NC
DQb
DQb
V

DD

V

SS

DQb
DQb

DQb
DQb
V

SS

V

DD

DQb
DQb
V

SS

NC

V

DD

ZZ

DQa
DQa
V

DD

V

SS

DQa
DQa
DQa
DQa

V

SS

V

DD
DQa
DQa
NC

SASASA

LBO

SA

SA1

SA0

SS

NCNCNC

DD

V

V

NC

SASASA

SA

SA

SA

NC

MOTOROLA FAST SRAM

MCM63P631A

3

PIN DESCRIPTIONS

Pin Locations Symbol

85 ADSC Input Synchronous Address Status Controller: Active low, is used to latch a

84 ADSP Input Synchronous Address Status Processor: Initiates READ or chip

83 ADV Input Synchronous Address Advance: Increments address count in

(a) 52, 53, 56, 57, 58, 59, 62, 63
(b) 68, 69, 72, 73, 74, 75, 78, 79

(c) 2, 3, 6, 7, 8, 9, 12, 13

(d) 18, 19, 22, 23, 24, 25, 28, 29

86 G Input Asynchronous Output Enable.
89 K Input Clock: This signal registers the address, data in, and all control signals

31 LBO Input Linear Burst Order Input: This pin must remain in steady state (this

32, 33, 34, 35, 44, 45, 46,

47, 48, 49, 81, 82, 99, 100

36, 37 SA1, SA0 Input Synchronous Address Inputs: These pins must be wired to the two

93, 94, 95, 96

(a) (b) (c) (d)

98 SE1 Input Synchronous Chip Enable: Active low to enable chip.

97 SE2 Input Synchronous Chip Enable: Active high for depth expansion.
92 SE3 Input Synchronous Chip Enable: Active low for depth expansion.
88 SGW Input Synchronous Global Write: This signal writes all bytes regardless of the

87 SW Input Synchronous Write: This signal writes only those bytes that have been

64 ZZ Input Sleep Mode: This active high asynchronous signal places the RAM into

4, 11, 15, 20, 27, 41,

54, 61, 65, 70, 77, 91

5, 10, 17, 21, 26, 40,

55, 60, 67, 71, 76, 90

1, 14, 16, 30, 38, 39,

42, 43, 50, 51, 66, 80

Type Description

new external address. Used to initiate a READ, WRITE or chip
deselect.

deselect cycle (exception — chip deselect does not occur when ADSP
is asserted and SE1 is high).

accordance with counter type selected (linear/interleaved).

DQx I/O Synchronous Data I/O: “x” refers to the byte being read or written

SA Input Synchronous Address Inputs: These inputs are registered and must

SBx Input Synchronous Byte Write Inputs: “x” refers to the byte being written (byte

V

DD

V

SS

NC — No Connection: There is no connection to the chip.

Supply Power Supply: 3.3 V + 10%, – 5%.

Supply Ground.

(byte a, b, c, d).

except G

signal not registered or latched). It must be tied high or low.
Low — linear burst counter (68K/PowerPC).
High — interleaved burst counter (486/i960/Pentium).

meet setup and hold times.

LSBs of the address bus for proper burst operation. These inputs are
registered and must meet setup and hold times.

a, b, c, d). SGW

Negated high — blocks ADSP
asserted.

status of the SBx
being used, tie this pin high.

selected using the byte write SBx
are being used, tie this pin low.

the lowest power mode. The ZZ pin disables the RAMs internal clock
when placed in this mode. When ZZ is negated, the RAM remains in
low power mode until it is commanded to READ or WRITE. Data
integrity is maintained upon returning to normal operation.

, LBO, and ZZ.

overrides SBx.

or deselects chip when ADSC is

and SW signals. If only byte write signals SBx are

pins. If only byte write signals SBx

MCM63P631A
4

MOTOROLA FAST SRAM

TRUTH TABLE (See Notes 1 through 5)

Address

Next Cycle

Deselect None 1 X X X 0 X X High–Z X
Deselect None 0 X 1 0 X X X High–Z X
Deselect None 0 0 X 0 X X X High–Z X
Deselect None X X 1 1 0 X X High–Z X
Deselect None X 0 X 1 0 X X High–Z X
Begin Read External 0 1 0 0 X X X High–Z READ
Begin Read External 0 1 0 1 0 X X High–Z READ
Continue Read Next X X X 1 1 0 1 High–Z READ
Continue Read Next X X X 1 1 0 0 DQ READ
Continue Read Next 1 X X X 1 0 1 High–Z READ
Continue Read Next 1 X X X 1 0 0 DQ READ
Suspend Read Current X X X 1 1 1 1 High–Z READ
Suspend Read Current X X X 1 1 1 0 DQ READ
Suspend Read Current 1 X X X 1 1 1 High–Z READ
Suspend Read Current 1 X X X 1 1 0 DQ READ
Begin Write External 0 1 0 1 0 X X High–Z WRITE
Continue Write Next X X X 1 1 0 X High–Z WRITE
Continue Write Next 1 X X X 1 0 X High–Z WRITE
Suspend Write Current X X X 1 1 1 X High–Z WRITE
Suspend Write Current 1 X X X 1 1 X High–Z WRITE

NOTES:

1. X = Don’t Care. 1 = logic high. 0 = logic low.

2. Write is defined as either 1) any SBx

3. G

is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (t

4. On write cycles that follow read cycles, G
also remain negated at the completion of the write cycle to ensure proper write data hold times.

5. This READ assumes the RAM was previously deselected.

Used

SE1 SE2 SE3 ADSP ADSC ADV G

and SW low or 2) SGW is low.

must be negated prior to the start of the write cycle to ensure proper write data setup times. G must

3

DQx Write 2,

) following G going low.

GLQX

4

5
5

MOTOROLA FAST SRAM

MCM63P631A

5