Motorola MCM63F733ATQ11, MCM63F733ATQ11R, MCM63F733ATQ10R, MCM63F733ATQ10 Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

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Advance Information

128K x 32 Bit Flow–Through
BurstRAM Synchronous
Fast Static RAM

The MCM63F733A is a 4M–bit synchronous fast static RAM designed to pro­vide a burstable, high performance, secondary cache for the PowerPC and
other high performance microprocessors. It is organized as 128K words of 32
bits each, fabricated with high performance silicon gate CMOS technology.
This device integrates input registers, a 2–bit address counter , and high speed
SRAM onto a single monolithic circuit for reduced parts count in cache data
RAM applications. Synchronous design allows precise cycle control with the
use of an external clock (K). CMOS circuitry reduces the overall power con­sumption of the integrated functions for greater reliability.

Addresses (SA), data inputs (DQx), and all control signals except output
enable (G
positive–edge–triggered noninverting registers.

Bursts can be initiated with either ADSP
addresses can be generated internally by the MCM63F733A (burst sequence
operates in linear or interleaved mode dependent upon state of LBO
trolled by the burst address advance (ADV

Write cycles are internally self–timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.

Synchronous byte write (SBx
nous write enable (SW
to all bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa
DQa, SBb
writes SBx
or if all SBx

For read cycles, a flow–through SRAM allows output data to simply flow freely
from the memory array .

The MCM63F733A operates from a 3.3 V core power supply and all outputs
operate on a 2.5 V or 3.3 V power supply. All inputs and outputs are JEDEC
Standard JESD8–5 compatible.

• MCM63F733A–10 = 10 ns Access/13 ns Cycle (75 MHz)

• 3.3 V + 10%/– 5% Core, Power Supply , 2.5 V or 3.3 V I/O Supply

• ADSP

• Selectable Burst Sequencing Order (Linear/Interleaved)

• Internally Self–Timed Write Cycle

• Byte Write and Global Write Control

• Single–Cycle Deselect

• Sleep Mode (ZZ)

• 100–Pin TQFP Package

) and Linear Burst Order (LBO) are clock (K) controlled through

or ADSC input pins. Subsequent burst

) and con-

) input pin.

), synchronous global write (SGW), and synchro-

) are provided to allow writes to either individual bytes or

controls
controls DQb, etc. Individual bytes are written if the selected byte
are asserted with SW. All bytes are written if either SGW is asserted

and SW are asserted.

MCM63F733A–11 = 11 ns Access/15 ns Cycle (66 MHz)

, ADSC, and ADV Burst Control Pins

MCM63F733A

TQ PACKAGE

TQFP

CASE 983A–01

The PowerPC name is a trademark of IBM Corp., used under license therefrom.

This document contains information on a new product. Specifications and information herein are subject to change without notice.

REV 2
3/20/98

 Motorola, Inc. 1998

MOTOROLA FAST SRAM

MCM63F733A

1

LBO

ADV

K
ADSC
ADSP

SA
SA1
SA0

SGW

FUNCTIONAL BLOCK DIAGRAM

K2

ADDRESS

REGISTER

17

BURST

COUNTER

CLR

2

15

2

17

128K x 32 ARRAY

SW

SBa

SBb

SBc

SBd

SE1
SE2

SE3

WRITE

REGISTER

a

WRITE

REGISTER

b

WRITE

REGISTER

c

WRITE

REGISTER

d

K2

ENABLE

REGISTER

4

DATA–IN

REGISTER

K

32

32

G

MCM63F733A
2

DQa – DQd

MOTOROLA FAST SRAM

PIN ASSIGNMENT

V

DDQ

V

DDQ

V

DQd

V

DDQ

DQd
DQd
DQd
DQd

V

DDQ

DQd
DQd

NC
DQc
DQc

V

SS
DQc
DQc

DQc
DQc
V

SS
DQc

DQc

NC
DD

NC

V

SS
DQd

V

SS

V

SS

NC

1
2
3
4
5
6
7

8
9

10
11
12
13
14
15
16
17
18
19
20

21
22
23
24
25
26
27
28
29
30

31 3233

SASASE1

DD

SE2

SBc

SBa

SBb

SBd

94 93979695 89889291 90 86858710099 98 81828384

3738343536 42433940 41 454644

SE3

K

VSSV

SW

SGW

G

ADSP

ADSC

ADV

SA

SA

NC

80
79

DQb

78

DQb
V

77

DDQ

V

76

SS

DQb

75

DQb

74

DQb

73

DQb

72

V

71

SS

V

70

DDQ

DQb

69

DQb

68

V

67

SS

NC

66

V

65

DD

ZZ

64

DQa

63

DQa

62

V

61

DDQ

V

60

SS

DQa

59

DQa

58
57

DQa

56

DQa
V

55

SS

V

54

DDQ

DQa

53

DQa

52

NC

51

50494847

SASASA

LBO

SA

SA1

SA0

NC

NC

V

SS

DD

V

NC

NC

SASASA

SA

SA

SA

SA

MOTOROLA FAST SRAM

MCM63F733A

3

PIN DESCRIPTIONS

Pin Locations Symbol

85 ADSC Input Synchronous Address Status Controller: Active low, interrupts any

84 ADSP Input Synchronous Address Status Processor: Active low, interrupts any

83 ADV Input Synchronous Address Advance: Increments address count in

(a) 51, 52, 53, 56, 57, 58, 59, 62, 63
(b) 68, 69, 72, 73, 74, 75, 78, 79, 80
(c) 1, 2, 3, 6, 7, 8, 9, 12, 13
(d) 18, 19, 22, 23, 24, 25, 28, 29, 30

86 G Input Asynchronous Output Enable Input.
89 K Input Clock: This signal registers the address, data in, and all control signals

31 LBO Input Linear Burst Order Input: This pin may be left floating; it will default as

32, 33, 34, 35, 44, 45, 46,

47, 48, 49, 50, 81, 82, 99, 100

36, 37 SA1, SA0 Input Synchronous Address Inputs: These pins must be wired to the two

93, 94, 95, 96

(a) (b) (c) (d)

98 SE1 Input Synchronous Chip Enable: Active low to enable chip.

97 SE2 Input Synchronous Chip Enable: Active high for depth expansion.
92 SE3 Input Synchronous Chip Enable: Active low for depth expansion.
88 SGW Input Synchronous Global Write: This signal writes all bytes regardless of the

87 SW Input Synchronous Write: This signal writes only those bytes that have been

64 ZZ Input Sleep Mode: This active high asynchronous signal places the RAM into

15, 41, 65, 91 V

4, 11, 20, 27, 54, 61, 70, 77 V

5, 10, 17, 21, 26, 40,

55, 60, 67, 71, 76, 90

14, 16, 38, 39, 42, 43, 66 NC — No Connection: There is no connection to the chip.

Type Description

ongoing burst and latches a new external address. Used to initiate a
READ, WRITE, or chip deselect.

ongoing burst and latches a new external address. Used to initiate a
new READ, WRITE, or chip deselect (exception — chip deselect does
not occur when ADSP

accordance with counter type selected (linear/interleaved).

DQx I/O Synchronous Data I/O: “x” refers to the byte being read or written

SA Input Synchronous Address Inputs: These inputs are registered and must

SBx Input Synchronous Byte Write Inputs: “x” refers to the byte being written

DD

DDQ

V

SS

Supply Core Power Supply.
Supply I/O Power Supply.
Supply Ground.

(byte a, b, c, d).

except G

interleaved.
Low — linear burst counter (68K/PowerPC).
High — interleaved burst counter (486/i960/Pentium).

meet setup and hold times.

LSBs of the address bus for proper burst operation. These inputs are
registered and must meet setup and hold times.

(byte a, b, c, d). SGW

Negated high — blocks ADSP
asserted.

status of the SBx
being used, tie this pin high.

selected using the byte write SBx
are being used, tie this pin low.

the lowest power mode. The ZZ pin disables the RAMs internal clock
when placed in this mode. When ZZ is negated, the RAM remains in
low power mode until it is commanded to READ or WRITE. Data
integrity is maintained upon returning to normal operation.

, LBO, and ZZ.

is asserted and SE1 is high).

overrides SBx.

or deselects chip when ADSC is

and SW signals. If only byte write signals SBx are

pins. If only byte write signals SBx

MCM63F733A
4

MOTOROLA FAST SRAM

TRUTH TABLE (See Notes 1 through 5)

Address

Next Cycle

Deselect None 1 X X X 0 X X High–Z X
Deselect None 0 X 1 0 X X X High–Z X
Deselect None 0 0 X 0 X X X High–Z X
Deselect None X X 1 1 0 X X High–Z X
Deselect None X 0 X 1 0 X X High–Z X
Begin Read External 0 1 0 0 X X X High–Z X
Begin Read External 0 1 0 1 0 X X High–Z READ
Continue Read Next X X X 1 1 0 1 High–Z READ
Continue Read Next X X X 1 1 0 0 DQ READ
Continue Read Next 1 X X X 1 0 1 High–Z READ
Continue Read Next 1 X X X 1 0 0 DQ READ
Suspend Read Current X X X 1 1 1 1 High–Z READ
Suspend Read Current X X X 1 1 1 0 DQ READ
Suspend Read Current 1 X X X 1 1 1 High–Z READ
Suspend Read Current 1 X X X 1 1 0 DQ READ
Begin Write External 0 1 0 1 0 X X High–Z WRITE
Continue Write Next X X X 1 1 0 X High–Z WRITE
Continue Write Next 1 X X X 1 0 X High–Z WRITE
Suspend Write Current X X X 1 1 1 X High–Z WRITE
Suspend Write Current 1 X X X 1 1 X High–Z WRITE

NOTES:

1. X = Don’t Care. 1 = logic high. 0 = logic low.

2. Write is defined as either 1) any SBx

3. G

is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (t

4. On write cycles that follow read cycles, G
G

must also remain negated at the completion of the write cycle to ensure proper write data hold times.

Used

SE1 SE2 SE3 ADSP ADSC ADV G

and SW low, or 2) SGW is low.

must be negated prior to the start of the write cycle to ensure proper write data setup times.

3

DQx Write 2,

) following G going low.

GLQX

4

ASYNCHRONOUS TRUTH TABLE

Operation ZZ G I/O Status

Read L L Data Out (DQx)
Read L H High–Z
Write L X High–Z

Deselected L X High–Z

Selected H X High–Z

LINEAR BURST ADDRESS TABLE (LBO = V

1st Address (External)

X . . . X00 X . . . X01 X . . . X10 X . . . X11
X . . . X01 X . . . X10 X . . . X11 X . . . X00
X . . . X10 X . . . X11 X . . . X00 X . . . X01
X . . . X11 X . . . X00 X . . . X01 X . . . X10

2nd Address (Internal) 3rd Address (Internal) 4th Address (Internal)

SS

)

MOTOROLA FAST SRAM

MCM63F733A

5