Motorola MC74HC161AN, MC74HC163AD, MC74HC161AD, MC74HC163AN, MC54HC163AJ Datasheet
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SEMICONDUCTOR TECHNICAL DATA
3–1
REV 6
Motorola, Inc. 1995
10/95
High–Performance Silicon–Gate CMOS
The MC54/74HC161A and HCI63A are identical in pinout to the LS161
and LS163. The device inputs are compatible with standard CMOS outputs;
with pullup resistors, they are compatible with LSTTL outputs.
The HC161A and HC163A are programmable 4–bit binary counters with
asynchronous and synchronous reset, respectively.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 192 FETs or 48 Equivalent Gates
LOGIC DIAGRAM
PIN 16 = V
CC
PIN 8 = GND
11
12
13
14
Q0
Q1
Q2
Q3
15
RIPPLE
CARRY
OUT
BCD OR
BINARY
OUTPUT
3
4
5
6
P0
P1
P2
P3
2
CLOCK
RESET
LOAD
ENABLE P
ENABLE T
COUNT
ENABLES
PRESET
DATA
INPUTS
1
9
7
10
Device
Count
Mode
Reset Mode
HC161A
Binary
Asynchronous
HC163A
Binary
Synchronous
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
RESET
P0
CLOCK
GND
Q1
Q0
RIPPLE
CARRY OUT
V
CC
P1
P2
P3
ENABLE P
Q2
Q3
ENABLE T
LOAD
D SUFFIX
SOIC PACKAGE
CASE 751B–05
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD
Ceramic
Plastic
SOIC
1
16
1
16
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
1
16
Inputs Output
Clock Reset* Load Enable P Enable T Q
L X X X Reset
H L X X Load Preset Data
H H H H Count
H H L X No Count
H H X L No Count
FUNCTION TABLE
*HC163A only. HC161A is an Asynchronous Reset Device
H = high level
L = low level
X = don’t care
MC54/74HC161A MC54/74HC163A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
3–2
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
V
in
DC Input Voltage (Referenced to GND)
– 1.5 to VCC + 1.5
V
V
out
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
I
in
DC Input Current, per Pin
± 20
mA
I
out
DC Output Current, per Pin
± 25
mA
I
CC
DC Supply Current, VCC and GND Pins
± 50
mA
P
D
Power Dissipation in Still Air,Plastic or Ceramic DIP†
SOIC Package†
750
500
mW
T
stg
Storage Temperature
– 65 to + 150
_
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)
260
300
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
Vin, V
out
DC Input Voltage, Output Voltage (Referenced to GND)
0
V
CC
V
T
A
Operating Temperature, All Package Types
– 55
+ 125
_
C
tr, t
f
Input Rise and Fall Time (Figure 1) VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
0
0
0
1000
500
400
ns
DC ELECTRICAL CHARACTERISTICS (Voltages referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
V
CC
V
– 55 to
25_C
v
85_Cv 125_C
Unit
V
IH
Minimum High–Level Input
Voltage
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
IL
Maximum Low–Level Input
Voltage
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
2.0
4.5
6.0
0.50
1.35
1.80
0.50
1.35
1.80
0.50
1.35
1.80
V
Vin = VIH or V
IL
|I
out
| v 20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin = VIH or VIL|I
out
| v 4.0 mA
|I
out
| v 5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
V
Vin = VIH or V
IL
|I
out
| v 20 µA
2.0
4.5
6.0
0.10
0.10
0.10
0.10
0.10
0.10
0.10
0.10
0.10
V
Vin = VIH or VIL|I
out
| v 4.0 mA
|I
out
| v 5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
V
I
in
Maximum Input Leakage Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
µA
I
CC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
I
out
= 0 µA
6.0
4
40
160
µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
V
out
should be constrained to the
range GND v (Vin or V
out
) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
V
OH
V
OL
Minimum High–Level Output
Voltage
Maximum Low–Level Output
Voltage
MC54/74HC161A MC54/74HC163A
High–Speed CMOS Logic Data
DL129 — Rev 6
3–3 MOTOROLA
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
Symbol
Parameter
Fig.
V
CC
V
– 55 to
25_C
v
85_Cv 125_C
Unit
f
max
Maximum Clock Frequency (50% Duty Cycle)*
1, 7
2.0
4.5
6.0
6
30
35
5
24
28
4
20
24
MHz
t
PLH
1, 7
2.0
4.5
6.0
120
20
16
160
23
20
200
28
22
ns
t
PHL
1, 7
2.0
4.5
6.0
145
22
18
185
25
20
320
30
23
ns
t
PHL
Maximum Propagation Delay, Reset to Q (HC161A Only)
2, 7
2.0
4.5
6.0
145
20
17
185
22
19
220
25
21
ns
t
PLH
3, 7
2.0
4.5
6.0
110
16
14
150
18
15
190
20
17
ns
t
PHL
3, 7
2.0
4.5
6.0
135
18
15
175
20
16
210
22
20
ns
t
PLH
1, 7
2.0
4.5
6.0
120
22
18
160
27
22
200
30
25
ns
t
PHL
1, 7
2.0
4.5
6.0
145
22
20
185
28
24
220
35
28
ns
t
PHL
Maximum Propagation Delay, Reset to Ripple Carry Out
(HC161A Only)
2, 7
2.0
4.5
6.0
155
22
18
190
26
22
230
30
25
ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
2, 7
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
C
in
Maximum Input Capacitance
1, 7
—
10
10
10
pF
*Applies to noncascaded/nonsynchronous clocked configurations only with synchronously cascaded counters. (1) Clock to Ripple Carry Out
propagation delays. (2) Enable T or Enable P to Clock setup times and (3) Clock to Enable T or Enable P hold times determine f
max
. However,
if Ripple Carry out of each stage is tied to the Clock of the next stage (nonsynchronously clocked) the f
max
in the table above is applicable. See
Applications information in this data sheet.
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
30
*Used to determine the no–load dynamic power consumption: PD = CPD V
CC
2
f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
Maximum Propagation Delay, Clock to Q
Maximum Propagation Delay, Enable T to Ripple Carry Out
Maximum Propagation Delay, Clock to Ripple Carry Out
C
PD
Power Dissipation Capacitance (Per Gate)*
pF
MC54/74HC161A MC54/74HC163A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
3–4
TIMING REQUIREMENTS (C
L
= 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
Symbol
Parameter
Fig.
V
CC
V
– 55 to
25_C
v
85_Cv 125_C
Unit
t
su
Minimum Setup Time,
Preset Data Inputs to Clock
5
2.0
4.5
6.0
40
15
12
60
20
18
80
30
20
ns
t
su
Minimum Setup Time,
Load to Clock
5
2.0
4.5
6.0
60
15
12
75
20
18
90
30
20
ns
t
su
Minimum Setup Time,
Reset to Clock (HC163A Only)
4
2.0
4.5
6.0
60
20
17
75
25
23
90
35
25
ns
t
su
Minimum Setup Time,
Enable T or Enable P to Clock
6
2.0
4.5
6.0
80
20
17
95
25
23
110
35
25
ns
t
h
Minimum Hold Time,
Clock to Load or Preset Data Inputs
5
2.0
4.5
6.0
3
3
3
3
3
3
3
3
3
ns
t
h
Minimum Hold Time,
Clock to Reset (HC163A Only)
4
2.0
4.5
6.0
3
3
3
3
3
3
3
3
3
ns
t
h
Minimum Hold Time,
Clock to Enable T or Enable P
6
2.0
4.5
6.0
3
3
3
3
3
3
3
3
3
ns
t
rec
Minimum Recovery Time,
Reset Inactive to Clock (HC161A Only)
2
2.0
4.5
6.0
80
15
12
95
20
17
110
26
23
ns
t
rec
Minimum Recovery Time,
Load Inactive to Clock
5
2.0
4.5
6.0
80
15
12
95
20
17
110
26
23
ns
t
w
Minimum Pulse Width,
Clock
1
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
t
w
Minimum Pulse Width,
Reset (HC161A Only)
2
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
tr, tfMaximum Input Rise and Fall Times
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
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