Motorola MC14LC5540FU, MC14LC5540P, MC14LC5540DW Datasheet
MC14LC5540MOTOROLA
1
Technical Summary
This technical summary provides a brief description of the MC14LC5540
ADPCM Codec. A complete data book for the MC14LC5540 is available and
can be ordered from your local Motorola sales office. The data book number is
MC145540/D.
The MC14LC5540 ADPCM Codec is a single chip implementation of a PCM
Codec–Filter and an ADPCM encoder/decoder, and therefore provides an
efficient solution for applications requiring the digitization and compression of
voiceband signals. This device is designed to operate over a wide voltage
range, 2.7 to 5.25 V and, as such, is ideal for battery powered as well as ac
powered applications. The MC14LC5540 ADPCM Codec also includes a serial
control port and internal control and status registers that permit a microcomputer to exercise many built–in features.
The ADPCM Codec is designed to meet the 32 kbps ADPCM conformance
requirements of CCITT Recommendation G.721–1988 and ANSI T1.301. It
also meets ANSI T1.303 and CCITT Recommendation G.723–1988 for 24 kbps
ADPCM operation, and the 16 kbps ADPCM standard, CCITT Recommendation G.726. This device also meets the PCM conformance specification of the
CCITT G.714 Recommendation.
• Single 2.7 to 5.25 V Power Supply
• Typical 2.7 V Power Dissipation of 43 mW, Power–Down of 15 µW
• Differential Analog Circuit Design for Lowest Noise
• Complete Mu–Law and A–Law Companding PCM Codec–Filter
• ADPCM Transcoder for 64, 32, 24, and 16 kbps Data Rates
• Universal Programmable Dual Tone Generator
• Programmable Transmit Gain, Receive Gain, and Sidetone Gain
• Low Noise, High Gain, Three Terminal Input Operational Amplifier for
Microphone Interface
• Push–Pull, 300 Ω Power Drivers with External Gain Adjust for Receiver
Interface
• Push–Pull, 300 Ω Auxiliary Output Drivers for Ringer Interface
• Voltage Regulated Charge Pump to Power the Analog Circuitry in Low
Voltage Applications
• Receive Noise Burst Detect Algorithm
• Order Complete Document as MC145540/D
• Device Supported by MC145537EVK ADPCM Codec Evaluation Kit
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
Order this document
by MC14LC5540TS/D
SEMICONDUCTOR TECHNICAL DATA
P SUFFIX
PLASTIC DIP
CASE 710
DW SUFFIX
SOG PACKAGE
CASE 751F
ORDERING INFORMATION
MC14LC5540P Plastic DIP
MC14LC5540DW SOG Package
MC14LC5540FU TQFP
28
1
28
1
32
1
FU SUFFIX
TQFP
CASE 873A
Motorola, Inc. 1997
REV 2
6/97 TN97060200
MC14LC5540 MOTOROLA
2
PIN ASSIGNMENT
19
18
17
16
15
28
27
26
25
24
23
22
21
20
TG
TI–
TI+
V
AG
RO
AXO–
AXO+
V
DSP
V
EXT
PI
PO–
PO+
PDI
/RESET
SCPEN
V
DD
FSR
BCLKR
DR
C1+
V
SS
SPC
DT
BCLKT
FST
SCP Rx
SCP Tx
SCPCLK
C1–
10
11
12
13
14
1
2
3
4
5
6
7
8
9
•
28–LEAD PDIP, SOG
RO
AXO–
AXO+
NC
V
DSP
NC
V
EXT
PI
PO–
PO+
PDI/RESET
SCPEN
SCP CLK
FST
V
TI+
TI–
TG
V
32 31 30 29 28 27 26 25
4
3
2
6
5
8
7
1
17
18
20
21
19
22
23
24
9 10111213141516
V
SS
C1+
NC
C1–
NC
DT
SPC
BCLKT
SCP Rx
SCP Tx FSR
DR
BCLKR
32–LEAD TQFP
DD
AG
PDI/RESET
V
DSP
AXO–
DAC
SIDETONE
GAIN
ADC
SCP Tx
TRIM GAIN
AND FILTER
–
+
PI
PO–
PO+
–1
TI+
TRIM GAIN
AND FILTER
SCP Rx
SCPCLK
SCPEN
RO
–
+
DSP
ADPCM
TRANSCODER,
RECEIVE GAIN
AND
DUAL TONE
GENERAT OR
CHARGE–PUMP
CODEC–FIL TER
SEQUENCE/
CONTROL
C1–C1+
V
SS
V
AG
V
DD
V
EXT
TI–
TG
AXO+
SPC
FSR
BCLKR
DR
DT
FST
BCLKT
Σ
BLOCK DIAGRAM
MC14LC5540MOTOROLA
3
PIN DESCRIPTIONS
POWER SUPPLY PINS
V
SS
Negative Power Supply
(PDIP, SOG—Pin 22; TQFP—Pin 21)
This is the most negative power supply and is typically
connected to 0 V.
V
EXT
External Power Supply Input
(PDIP, SOG—Pin 9; TQFP—Pin 7)
This power supply input pin must be between 2.70 and
5.25 V. Internally, it is connected to the input of the V
DSP
voltage regulator, the 5 V regulated charge pump, and all
digital I/O including the Serial Control Port and the ADPCM
Serial Data Port. This pin is also connected to the analog output drivers (PO+, PO–, AXO+, and AXO–). This pin should
be decoupled to VSS with a 0.1 µF ceramic capacitor. This
pin is internally connected to the VDD and V
DSP
pins when
the device is powered down.
V
DSP
Digital Signal Processor Power Supply Output
(PDIP, SOG—Pin 8; TQFP—Pin 5)
This pin is connected to the output of the on–chip V
DSP
voltage regulator which supplies the positive voltage to the
DSP circuitry and to the other digital blocks of the ADPCM
Codec. This pin should be decoupled to VSS with a 0.1 µF
ceramic capacitor. This pin cannot be used for powering
external loads. This pin is internally connected to the V
EXT
pin during power–down to retain memory.
V
DD
Positive Power Supply Input/Output
(PDIP, SOG, TQFP—Pin 28)
This is the positive output of the on–chip voltage regulated
charge pump and the positive power supply input to the analog sections of the device. Depending on the supply voltage
available, this pin can function in one of two different operating modes:
1. When V
EXT
is supplied from a regulated 5 V (± 5%)
power supply, VDD is an input and should be externally
connected to V
EXT
. Charge pump capacitor C1 should
not be used and the charge pump should be disabled in
BR0 (b2). In this case V
EXT
and VDD can share the same
0.1 µF ceramic decoupling capacitor to VSS.
2. When V
EXT
is supplied from 2.70 to 5.25 V, such as
battery powered applications, the charge pump should
be used. In this case, VDD is the output of the on–chip
voltage regulated charge pump and must not be connected to V
EXT
. VDD should be decoupled to VSS with a
1.0 µF ceramic capacitor. This pin cannot be used for
powering external loads in this operating mode. This pin
is internally connected to the V
EXT
pin when the charge
pump is turned off or the device is powered down.
V
AG
Analog Ground Output
(PDIP, SOG—Pin 4; TQFP—Pin 32)
This output pin provides a mid–supply analog ground regulated to 2.4 V . All analog signal processing within this device
is referenced to this pin. This pin should be decoupled to V
SS
with a 0.01 µF ceramic capacitor. If the audio signals to be
processed are referenced to VSS, then special precautions
must be utilized to avoid noise between VSS and the VAG pin.
Refer to the applications information in this document for
more information. The VAG pin becomes high impedance
when in analog power–down mode.
C1–, C1+
Charge Pump Capacitor Pins
(PDIP, SOG, TQFP—Pins 23 and 24)
These are the capacitor connections to the internal voltage
regulated charge pump that generates the VDD supply voltage. A 0.1 µF capacitor should be placed between these
pins. Note that if an external VDD is supplied, this capacitor
should not be in the circuit.
ANALOG INTERFACE PINS
TG
Transmit Gain
(PDIP, SOG—Pin 1; TQFP—Pin 29)
This is the output of the transmit gain setting operational
amplifier and the input to the transmit band–pass filter. This
op amp is capable of driving a 2 kΩ load to the VAG pin.
When TI– and TI+ are connected to VDD, the TG op amp is
powered down and the TG pin becomes a high–impedance
input to the transmit filter. All signals at this pin are referenced to the VAG pin. This pin is high impedance when the
device is in the analog power–down mode. This op amp is
powered by the VDD pin.
TI–
Transmit Analog Input (Inverting)
(PDIP, SOG—Pin 2; TQFP—Pin 30)
This is the inverting input of the transmit gain setting operational amplifier. Gain setting resistors are usually connected from this pin to TG and from this pin to the analog
signal source. The common mode range of the TI+ and TI–
pins is from 1.0 V , to VDD – 2 V . Connecting this pin and TI+
to VDD will place this amplifier’s output (TG) in a high–impedance state, thus allowing the TG pin to serve as a high–impedance input to the transmit filter.
TI+
Transmit Analog Input (Non–Inverting)
(PDIP, SOG—Pin 3; TQFP—Pin 31)
This is the non–inverting input of the transmit input gain
setting operational amplifier . This pin accommodates a differential to single–ended circuit for the input gain setting op
amp. This allows input signals that are referenced to the V
SS
pin to be level shifted to the VAG pin with minimum noise.
This pin may be connected to the VAG pin for an inverting
amplifier configuration if the input signal is already referenced to the VAG pin. The common mode range of the TI+
and TI– pins is from 1.0 V to VDD – 2 V. Connecting this pin
and TI– to VDD will place this amplifier’s output (TG) in a
MC14LC5540 MOTOROLA
4
high–impedance state, thus allowing the TG pin to serve as a
high–impedance input to the transmit filter.
RO
Receive Analog Output
(PDIP, SOG—Pin 5; TQFP—Pin 1)
This is the non–inverting output of the receive smoothing
filter from the digital–to–analog converter. This output is
capable of driving a 2 kΩ load to 1.575 V peak referenced to
the VAG pin. This pin may be dc referenced to either the V
AG
pin or a voltage of half of V
EXT
by BR2 (b7). This pin is high
impedance when the device is in the analog power–down
mode. This pin is high impedance except when it is enabled
for analog signal output.
AXO–
Auxiliary Audio Power Output (Inverting)
(PDIP, SOG—Pin 6; TQFP—Pin 3)
This is the inverting output of the auxiliary power output
drivers. The Auxiliary Power Driver is capable of differentially
driving a 300 Ω load. This power amplifier is powered from
V
EXT
and its output can swing to within 0.5 V of VSS and
V
EXT
. This pin may be dc referenced to either the VAG pin or
a voltage of half of V
EXT
by BR2 (b7). This pin is high impedance in power down. This pin is high impedance except
when it is enabled for analog signal output.
AXO+
Auxiliary Audio Power Output (Non–Inverting)
(PDIP, SOG—Pin 7; TQFP—Pin 4)
This is the non–inverting output of the auxiliary power output drivers. The Auxiliary Power Driver is capable of differentially driving a 300 Ω load. This power amplifier is powered
from V
EXT
and its output can swing to within 0.5 V of VSS and
V
EXT
. This pin may be dc referenced to either the VAG pin or
a voltage of half of V
EXT
by BR2 (b7). This pin is high impedance in power down. This pin is high impedance except
when it is enabled for analog signal output.
PI
Power Amplifier Input
(PDIP, SOG—Pin 10; TQFP—Pin 8)
This is the inverting input to the PO– amplifier. The non–
inverting input to the PO– amplifier may be dc referenced to
either the VAG pin or a voltage of half of V
EXT
by BR2 (b7).
The PI and PO– pins are used with external resistors in an
inverting op amp gain circuit to set the gain of the PO+ and
PO– push–pull power amplifier outputs. Connecting PI to
VDD will power down these amplifiers and the PO+ and PO–
outputs will be high impedance.
PO–
Power Amplifier Output (Inverting)
(PDIP, SOG—Pin 11; TQFP—Pin 9)
This is the inverting power amplifier output that is used to
provide a feedback signal to the PI pin to set the gain of the
push–pull power amplifier outputs. This power amplifier is
powered from V
EXT
and its output can swing to within 0.5 V
of VSS and V
EXT
. This should be noted when setting the gain
of this amplifier. This pin is capable of driving a 300 Ω load to
PO+ independent of supply voltage. The PO+ and PO– outputs are differential (push–pull) and capable of driving a
300 Ω load to 3.15 V peak, which is 6.3 V peak–to–peak
when a nominal 5 V power supply is used for V
EXT
. The bias
voltage and signal reference for this pin may be dc referenced to either the VAG pin or a voltage of half of V
EXT
by
BR2 (b7). Low impedance loads must be between PO+ and
PO–. This pin is high impedance when the device is in the
analog power–down mode. This pin is high impedance except when it is enabled for analog signal output.
PO+
Power Amplifier Output (Non–Inverting)
(PDIP, SOG—Pin 12; TQFP—Pin 10)
This is the non–inverting power amplifier output that is an
inverted version of the signal at PO–. This power amplifier is
powered from V
EXT
and its output can swing to within 0.5 V
of VSS and V
EXT
. This pin is capable of driving a 300 Ω load
to PO–. This pin may be dc referenced to either the VAG pin
or a voltage of half of V
EXT
by BR2 (b7). This pin is high
impedance when the device is in the analog power–down
mode. See PI and PO– for more information. This pin is high
impedance except when it is enabled for analog signal output.
ADPCM/PCM SERIAL INTERFACE PINS
FST
Frame Sync, Transmit
(PDIP, SOG—Pin 18; TQFP—Pin 16)
When used in the Long Frame Sync or Short Frame Sync
mode, this pin accepts an 8 kHz clock that synchronizes the
output of the serial ADPCM data at the DT pin.
BCLKT
Bit Clock, Transmit
(PDIP, SOG—Pin 19; TQFP—Pin 17)
When used in the Long Frame Sync or Short Frame Sync
mode, this pin accepts any bit clock frequency from 64 to
5120 kHz.
DT
Data, Transmit (PDIP, SOG—Pin 20; TQFP—Pin 18)
This pin is controlled by FST and BCLKT and is high impedance except when outputting data.
SPC
Signal Processor Clock
(PDIP, SOG—Pin 21; TQFP—Pin 19)
This input requires a 20.48 to 24.32 MHz clock signal that
is used as the DSP engine master clock. Internally the device
divides down this clock to generate the 256 kHz clock required by the PCM Codec. The SPC clock should be a multiple of 256 kHz. (This clock may be optionally specified for
higher frequencies; contact the factory for more information.)
DR
Data, Receive (PDIP, SOG, TQFP—Pin 25)
ADPCM data to be decoded are applied to this input,
which operates synchronously with FSR and BCLKR to enter
the data in a serial format.
MC14LC5540MOTOROLA
5
BCLKR
Bit Clock, Receive (PDIP, SOG, TQFP—Pin 26)
When used in the Long Frame Sync or Short Frame Sync
mode, this pin accepts any bit clock frequency from 64 to
5120 kHz. This pin may be used for applying an external
256 kHz clock for sequencing the analog signal processing
functions of this device. This is selected by the SCP port at
BR0 (b7).
FSR
Frame Sync, Receive (PDIP, SOG, TQFP—Pin 27)
When used in the Long Frame Sync or Short Frame Sync
mode, this pin accepts an 8 kHz clock that synchronizes the
input of the serial ADPCM data at the DR pin. FSR can operate asynchronous to FST in the Long Frame Sync or Short
Frame Sync mode.
SERIAL CONTROL PORT INTERFACE PINS
PDI
/RESET
Power–Down Input/Reset
(PDIP, SOG—Pin 13; TQFP—Pin 11)
A logic 0 applied to this input forces the device into a low–
power dissipation mode. A rising edge on this pin causes
power to be restored and the ADPCM Reset state (specified
in the standards) to be forced.
SCPEN
Serial Control Port Enable Input
(PDIP, SOG—Pin 14; TQFP—Pin 12)
This pin, when held low, selects the Serial Control Port
(SCP) for the transfer of control and status information into
and out of the MC14LC5540 ADPCM Codec. This pin should
be held low for a total of 16 periods of the SCPCLK signal in
order for information to be transferred into or out of the
MC14LC5540 ADPCM Codec. The timing relationship between SCPEN
and SCPCLK is shown in Figures 6 through 9.
SCPCLK
Serial Control Port Clock Input
(PDIP, SOG—Pin 15; TQFP—Pin 13)
This input to the device is used for controlling the rate of
transfer of data into and out of the SCP Interface. Data are
clocked into the MC14LC5540 ADPCM Codec from SCP Rx
on rising edges of SCPCLK. Data are shifted out of the device on SCP Tx on falling edges of SCPCLK. SCPCLK can
be any frequency from 0 to 4.096 MHz. An SCP transaction
takes place when SCPEN
is brought low. Note that SCPCLK
is ignored when SCPEN is high ( i.e., it may be continuous or
it can operate in a burst mode).
SCP Tx
Serial Control Port Transmit Output
(PDIP, SOG—Pin 16; TQFP—Pin 14)
SCP Tx is used to output control and status information
from the MC14LC5540 ADPCM Codec. Data are shifted out
of SCP Tx on the falling edges of SCPCLK, most significant
bit first.
SCP Rx
Serial Control Port Receive Input
(PDIP, SOG—Pin 17; TQFP—Pin 15)
SCP Rx is used to input control and status information to
the MC14LC5540 ADPCM Codec. Data are shifted into the
device on rising edges of SCPCLK. SCP Rx is ignored when
data are being shifted out of SCP Tx or when SCPEN
is
high.
MC14LC5540 MOTOROLA
6
ADPCM/PCM SERIAL INTERFACE TIMING DIAGRAMS
DON’T CARE
DR
87654321
87654321
DT
BCLKT (BCLKR)
FST (FSR)
DON’T CARE
Figure 1. Long Frame Sync (64 kbps PCM Data Timing)
DR 4321
4321DT
BCLKT (BCLKR)
FST (FSR)
DON’T CARE DON’T CARE
Figure 2. Long Frame Sync (32 kbps ADPCM Data Timing)
DR 321
321DT
BCLKT (BCLKR)
FST (FSR)
DON’T CARE DON’T CARE
Figure 3. Long Frame Sync (24 kbps ADPCM Data Timing)
DR 21
21DT
BCLKT (BCLKR)
FST (FSR)
DON’T CARE DON’T CARE
Figure 4. Long Frame Sync (16 kbps ADPCM Data Timing)
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