Motorola MC14598BCP, MC14597BDW, MC14598BCL, MC14597BCL, MC14597BCP Datasheet
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MOTOROLA CMOS LOGIC DATA
1
MC14597B MC14598B
!
The MC14597B and MC14598B are 8–bit latches, one addressed with an
internal counter and the other addressed with an external binary address.
The 8 latch–outputs are high drive, three–state and bus line compatible. The
drive capability allows direct applications with MPU systems such as the
Motorola 6800 family.
With MC14597B, a 3–bit address counter (clocked on the falling edge of
Increment) selects the appropriate latch. The latches of the MC14598B are
accessed via the Address pins, A0, A1, and A2. A Full
Flag is provided on
the MC14597B to indicate the position of the Address counter.
All 8 outputs from the latches are available in parallel when Enable is in the
low state. Data is entered into a selected latch from the Data pin when the
Strobe is high. Master reset is available on both parts.
• Serial Data Input
• Three–State Bus Compatible Parallel Outputs
• Three–State Control Pin (Enable
) TTL Compatible Input
• Open Drain Full
Flag (Multiple Latch Wire–O Ring)
• Master Reset
• Level Shifting Inputs on All Except Enable
• Diode Protection — All Inputs
• Supply Voltage Range — 3.0 Vdc to 18 Vdc
• Capable of Driving TTL Over Rated Temperature Range
With Fanout as Follows:
1 TTL Load
4 LSTTL Loads
BLOCK DIAGRAMS
MC14598B
MC14597B
Enable Outputs
1 High Impedance
0 D
n
Dn = State of nth latch
OUTPUT
TRUTH TABLE
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
D4
D3
D2
D1
V
DD
D7
D6
D5
ENABLE
DATA
RESET
D0
V
SS
INCREMENT
STROBE
FULL
NC
DATA
RESET
D0
V
SS
A1
A0
STROBE
ENABLE
D3
D2
D1
V
DD
A2
D7
D6
D5
D4
14
15
16
17
18
10
11
12
13
5
4
3
2
1
9
8
7
6
NC = NO CONNECTION
THREE
STATE
OUTPUT
BUFFERS
8
LATCHES
ADDRESS
DECODER
3–BIT
ADDRESS
COUNTER
FULL
LOGIC
RESET
LOGIC
RESET
2 4 ENABLE
1
15
14
13
12
11
10
9
D0
D1
D2
D3
D4
D5
D6
D7
DATA 3
STROBE 6
INCREMENT
5
FULL
VDD = 16
VSS = 8
7
1
17
16
15
14
13
12
11
D0
D1
D2
D3
D4
D5
D6
D7
ENABLE
4
THREE
STATE
OUTPUT
BUFFERS
8
LATCHES
ADDRESS
DECODER
VDD = 18
VSS = 9
2
3
6
RESET
DATA
STROBE
A0
A1
A2
7
8
10
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
REV 3
1/94
L SUFFIX
CERAMIC
CASE 620
ORDERING INFORMATION
MC14597BCP Plastic
MC14597BCL Ceramic
MC14597BDW SOIC
TA = – 55° to 125°C for all packages.
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
L SUFFIX
CERAMIC
CASE 726
P SUFFIX
PLASTIC
CASE 707
ORDERING INFORMATION
MC14598BCP Plastic
MC14598BCL Ceramic
TA = – 55° to 125°C for all packages.
MOTOROLA CMOS LOGIC DATAMC14597B MC14598B
2
MAXIMUM RATINGS* (Voltages Referenced to V
SS
)
Symbol
Parameter Value Unit
V
DD
DC Supply Voltage – 0.5 to + 18.0 V
V
in
Input Voltage, Enable (DC or Transient) – 0.5 to VDD + 0.5 V
V
in
Input Voltage, All other Inputs
(DC or Transient)
– 0.5 to VDD + 12 V
V
out
Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
Iin, lout Input or Output Current (DC or Transient),
per Pin
± 10 mA
P
D
Power Dissipation, per Package† 500 mW
T
stg
Storage Temperature – 65 to + 150
_
C
T
L
Lead Temperature (8–Second Soldering) 260
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
“P and D/DW” Packages: – 7.0 mW/C From 65_C To 125_C Ceramic
“L” Packages: – 12 mW/_C From 100_C To 125_C
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
SS
)
V
– 55_C 25_C 125_C
Characteristic
Symbol
V
DD
Vdc
Min Max Min Typ # Max Min Max
Unit
Output Voltage “0” Level
Vin = VDD or 0
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
“1” Level
Vin = 0 or V
DD
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Input Voltage** — Enable “0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
V
IL
5.0
10
15
—
—
—
0.8
1.6
2.4
—
—
—
1.1
2.2
3.4
0.8
1.6
2.4
—
—
—
0.8
1.6
2.4
Vdc
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
V
IH
5.0
10
15
2.0
6.0
10
—
—
—
2.0
6.0
10
1.9
3.1
4.3
—
—
—
2.0
6.0
10
—
—
—
Vdc
Input Voltage “0” Level
Other Inputs
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
Vdc
(VO = 0.5 or 4.5 Vdc) “1” Level
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
V
IH
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
Vdc
Output Drive Current Source
(Full
— Sink Only)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
I
OH
5.0
10
1 5
– 1.0
—
—
–
—
—
– 1.0
—
—
– 2.0
– 6.0
– 12
—
—
—
– 1.0
—
—
—
—
—
mAdc
(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
I
OL
5.0
10
15
1.6
—
—
—
—
—
1.6
—
—
3.2
6.0
12
—
—
—
1.6
—
—
—
—
—
mAdc
Input Current I
in
15 — ±0.1 — ±0.00001 ±0.1 — ±1.0 µAdc
Three–State Leakage Current I
TL
15 — ±0.1 — ±0.00001 ±0.1 — ±3.0 µAdc
Input Capacitance (Vin = 0) C
in
— — — — 5.0 7.5 — — pF
Quiescent Current
(Per Package)
I
DD
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
**Total Supply Current at an
**External Load Capacitance of
**130 pF
I
T
5.0
10
IT = (2.0 µA/kHz) f + I
DD
IT = (4.0 µA/kHz) f + I
DD
IT = (6.0 µA/kHz) f + I
DD
µAdc
†Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**The formulas given are for the typical characteristics only at 25_C.
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, precautions must be taken to avoid applications of
any voltage higher than maximum rated voltages to this high–impedance circuit. For proper
operation, Vin and V
out
should be constrained
to the range VSS v (Vin or V
out
) v VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either V
SS
or VDD). Unused outputs must be left open.
MOTOROLA CMOS LOGIC DATA
3
MC14597B MC14598B
SWITCHING CHARACTERISTICS* (T
A
= 25_C, CL = 130 pF + 1 TTL Load)
V
All Types
Characteristic
Symbol
V
DD
Vdc
Min Typ # Max
Unit
Output Rise and Fall Time
t
TLH
, t
THL
= (0.5 ns/pF) CL + 35 ns
t
TLH
, t
THL
= (0.2 ns/pF) CL + 25 ns
t
TLH
, t
THL
= (0.16 ns/pF) CL + 20 ns
t
TLH
,
t
THL
5.0
10
15
—
—
—
100
50
40
200
100
80
ns
Propagation Delay Time
Enable
to Output
t
PLH
,
t
PHL
5.0
10
15
—
—
—
160
125
100
320
250
200
ns
Strobe to Output 5.0
10
15
—
—
—
200
100
80
400
200
160
Strobe to Full (MC14597B only) 5.0
10
15
—
—
—
200
100
80
400
200
160
Reset to Output 5.0
10
15
—
—
—
175
90
70
350
180
140
Pulse Width
Enable
tWH,
t
WL
5.0
10
15
320
240
160
160
120
80
—
—
—
ns
Strobe 5.0
10
15
200
100
80
100
50
40
—
—
—
Increment (MC14597B only) 5.0
10
15
200
100
80
100
50
40
—
—
—
Reset 5.0
10
15
300
160
100
150
80
50
—
—
—
Setup Time
Data
t
su
5.0
10
15
100
50
35
50
25
20
—
—
—
ns
Address (MC14598B only) 5.0
10
15
200
100
70
100
50
35
—
—
—
Increment (MC14597B only) 5.0
10
15
400
200
170
200
100
85
—
—
—
Hold Time
Data
t
h
5.0
10
15
100
50
35
50
25
20
—
—
—
ns
Address (MC14598B only) 5.0
10
15
100
50
35
50
25
20
—
—
—
Reset Removal Time t
rem
5.0
10
15
20
20
20
– 25
– 15
– 10
—
—
—
ns
*The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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