Motorola MC14051BCL, MC14053BCL, MC14051BCP, MC14051BD, MC14052BCL Datasheet

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MOTOROLA CMOS LOGIC DATA

MC14051B MC14052B MC14053B

Analog Multiplexers/Demultiplexers

The MC14051B, MC14052B, and MC14053B analog multiplexers are digitally–controlled analog switches. The MC14051B effectively implements an SP8T solid state switch, the MC14052B a DP4T, and the MC14053B a Triple SPDT. All three devices feature low ON impedance and very low OFF leakage current. Control of analog signals up to the complete supply voltage range can be achieved.

• Triple Diode Protection on Control Inputs

• Switch Function is Break Before Make

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Analog Voltage Range (VDD – VEE) = 3.0 to 18 V

Note: VEE must be v V

• Linearized Transfer Characteristics

• Low–noise – 12 nV/√Cycle

, f ≥ 1.0 kHz Typical

• Pin–for–Pin Replacement for CD4051, CD4052, and CD4053

• For 4PDT Switch, See MC14551B

• For Lower RON, Use the HC4051, HC4052, or HC4053 High–Speed

CMOS Devices

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

DC Supply Voltage (Referenced to VEE, VSS ≥ VEE)

– 0.5 to + 18.0

Vin, V

out

Input or Output Voltage (DC or Transient) (Referenced to VSS for Control Inputs and VEE for Switch I/O)

– 0.5 to VDD + 0.5

Input Current (DC or Transient), per Control Pin

± 10

Switch Through Current

± 25

Power Dissipation. per Package†

500

stg

Storage Temperature

– 65 to + 150

Lead Temperature (8–Second Soldering)

260

*Maximum Ratings are those values beyond which damage to the device may occur. †Temperature Derating:“P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

MC14051B

8–Channel Analog

Multiplexer/Demultiplexer

MC14052B

Dual 4–Channel Analog

Multiplexer/Demultiplexer

MC14053B

Triple 2–Channel Analog

Multiplexer/Demultiplexer

VDD = PIN 16

VSS = PIN 8 VEE = PIN 7

Note: Control Inputs referenced to VSS, Analog Inputs and Outputs reference to VEE. VEE must be ≤ VSS.

INHIBIT A B C X0 X1 X2 X3 X4 X5 X6 X7

CONTROLS

SWITCHES

IN/OUT

COMMON

OUT/IN

CONTROLS

SWITCHES

IN/OUT

COMMONS

OUT/IN

VDD = PIN 16

VSS = PIN 8 VEE = PIN 7

CONTROLS

SWITCHES

IN/OUT

COMMONS

OUT/IN

VDD = PIN 16

VSS = PIN 8 VEE = PIN 7

INHIBIT A B

X0 X1 X2 X3 Y0

Y1 Y2 Y3

INHIBIT A B

C X0

Y0 Y1 Z0 Z1

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

 Motorola, Inc. 1995

REV 3 1/94

MC14051B MC14052B MC14053B

L SUFFIX

CERAMIC

CASE 620

ORDERING INFORMATION

MC14XXXBCP Plastic MC14XXXBCL Ceramic MC14XXXBD SOIC

TA = – 55° to 125°C for all packages.

P SUFFIX

PLASTIC

CASE 648

D SUFFIX

SOIC

CASE 751B

MOTOROLA CMOS LOGIC DATAMC14051B MC14052B MC14053B

ELECTRICAL CHARACTERISTICS

– 55_C

25_C

125_C

Characteristic

Symbol

VDDTest Conditions

Min

Max

Min

Typ #

Max

Min

Max

Unit

SUPPLY REQUIREMENTS (Voltages Referenced to VEE)

Power Supply Voltage

Range

—

VDD – 3.0 ≥ VSS ≥ V

3.0

—

3.0

Quiescent Current Per

Package

5.0 10 15

Control Inputs:

Vin = VSS or VDD,

Switch I/O: VEE v V

I/O

VDD, and

∆V

switch

v 500 mV**

— — —

5.0 10 20

— — —

0.005

0.010

0.015

5.0 10 20

— — —

150 300 600

µA

Total Supply Current

(Dynamic Plus Quiescent, Per Package

D(AV)

5.0 10 15

TA = 25_C only (The

channel component, (Vin – V

out

)/Ron, is

not included.)

(0.07 µA/kHz) f + I

Typical (0.20 µA/kHz) f + I

(0.36 µA/kHz) f + I

µA

CONTROL INPUTS — INHIBIT, A, B, C (Voltages Referenced to VSS)

Low–Level Input Voltage

5.0 10 15

Ron = per spec, I

off

= per spec

— — —

1.5

3.0

4.0

— — —

2.25

4.50

6.75

1.5

3.0

4.0

— — —

1.5

3.0

4.0

High–Level Input Voltage

5.0 10 15

Ron = per spec, I

off

= per spec

3.5

7.0 11

— — —

3.5

7.0 11

2.75

5.50

8.25

— — —

3.5

7.0 11

— — —

Input Leakage Current

Vin = 0 or V

—

± 0.1

—

±0.00001

± 0.1

—

1.0

µA

Input Capacitance

—

5.0

7.5

—

SWITCHES IN/OUT AND COMMONS OUT/IN — X, Y, Z (Voltages Referenced to VEE)

Recommended

Peak–to–Peak Voltage Into or Out of the Switch

I/O

—

Channel On or Off

—

DDVPP

Recommended Static or

Dynamic Voltage Across the Switch** (Figure 5)

∆V

switch

—

Channel On

600

—

600

300

Output Offset Voltage

—

Vin = 0 V, No Load

—

µV

ON Resistance

5.0 10 15

∆V

switch

v 500 mV**,

Vin = VIL or V

(Control), and Vin = 0 to VDD (Switch)

— — —

800 400 220

— — —

250 120

1050

500 280

— — —

1200

520 300

Ω

∆ON Resistance Between

Any Two Channels in the Same Package

∆R

5.0 10 15

— — —

70 50 45

— — —

25 10 10

70 50 45

— — —

135

95 65

Ω

Off–Channel Leakage

Current (Figure 10)

off

Vin = VIL or V

(Control) Channel to Channel or Any One Channel

—

± 100

—

± 0.05

± 100

—

±1000

Capacitance, Switch I/O

I/O

—

Inhibit = V

—

Capacitance, Common O/I

O/I

—

Inhibit = V

(MC14051B) (MC14052B) (MC14053B)

— — —

60 32 17

— — —

Capacitance, Feedthrough

(Channel Off)

I/O

——Pins Not Adjacent

Pins Adjacent

———

—

— —

0.15

0.47

— —

————pF

#Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance. *For voltage drops across the switch (∆V

switch

) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn, i.e. the current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. (See first page of this data sheet.)

MOTOROLA CMOS LOGIC DATA

MC14051B MC14052B MC14053B

ELECTRICAL CHARACTERISTICS* (C

= 50 pF, TA = 25_C) (VEE v VSS unless otherwise indicated)

Characteristic

Symbol

VDD – V

Vdc

Typ #

All Types

Max

Unit

Propagation Delay Times (Figure 6)

Switch Input to Switch Output (RL = 10 kΩ)

MC14051

PLH

, t

PHL

= (0.17 ns/pF) CL + 26.5 ns

PLH

, t

PHL

= (0.08 ns/pF) CL + 11 ns

PLH

, t

PHL

= (0.06 ns/pF) CL + 9.0 ns

PLH

, t

PHL

5.0 10 15

35 15 12

90 40 30

MC14052

PLH

, t

PHL

= (0.17 ns/pF) CL + 21.5 ns

PLH

, t

PHL

= (0.08 ns/pF) CL + 8.0 ns

PLH

, t

PHL

= (0.06 ns/pF) CL + 7.0 ns

5.0 10 15

30 12 10

75 30 25

MC14053

PLH

, t

PHL

= (0.17 ns/pF) CL + 16.5 ns

PLH

, t

PHL

= (0.08 ns/pF) CL + 4.0 ns

PLH

, t

PHL

= (0.06 ns/pF) CL + 3.0 ns

5.0 10 15

8.0

6.0

65 20 15

Inhibit to Output (RL = 10 kΩ, VEE = VSS) Output “1” or “0” to High Impedance, or High Impedance to “1” or “0” Level

MC14051B

PHZ

, t

PLZ

PZH

, t

PZL

5.0 10 15

350 170 140

700 340 280

MC14052B

5.0 10 15

300 155 125

600 310 250

MC14053B

5.0 10 15

275 140 110

550 280 220

Control Input to Output (RL = 10 kΩ, VEE = VSS)

MC14051B

PLH

, t

PHL

5.0 10 15

360 160 120

720 320 240

MC14052B

5.0 10 15

325 130

650 260 180

MC14053B

5.0 10 15

300 120

600 240 160

Second Harmonic Distortion

(RL = 10KΩ, f = 1 kHz) Vin = 5 V

—

0.07

—

Bandwidth (Figure 7)

(RL = 1 kΩ, Vin = 1/2 (VDD–VEE) p–p, CL = 50pF 20 Log (V

out/Vin

) = – 3 dB)

—

MHz

Off Channel Feedthrough Attenuation (Figure 7)

RL = 1KΩ, Vin = 1/2 (VDD – VEE) p–p fin = 4.5 MHz — MC14051B fin = 30 MHz — MC14052B fin = 55 MHz — MC14053B

—

– 50

—

Channel Separation (Figure 8)

(RL = 1 kΩ, Vin = 1/2 (VDD–VEE) p–p, fin = 3.0 MHz

—

– 50

—

Crosstalk, Control Input to Common O/I (Figure 9)

(R1 = 1 kΩ, RL = 10 kΩ Control t

TLH

= t

THL

= 20 ns, Inhibit = VSS)

—

*The formulas given are for the typical characteristics only at 25_C. #Data labelled “Typ” is not lo be used for design purposes but In intended as an indication of the IC’s potential performance.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and V

out

should be constrained to the range VSS ≤ (Vin or V

out

) ≤ VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS, VEE, or VDD). Unused outputs must be left open.

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