
SEMICONDUCTOR TECHNICAL DATA
The MC10173 is a quad two channel multiplexer with latch. It incorporates
common clock and common data select inputs. The select input determines
which data input is enabled. A high (H) level enables data inputs D00, D10,
D20, and D30 and a low (L) level enables data inputs D01, D1 1, D21, D31. Any
change on the data input will be reflected at the outputs while the clock is low.
The outputs are latched on the positive transition of the clock. While the clock is
in the high state, a change in the information present at the data inputs will not
affect the output information.
PD= 275 mW typ/pkg (No Load)
tpd= 2.5 ns typ
tr, tf= 2.0 ns typ (20%–80%)
LOGIC DIAGRAM
SELECT 9
D00 6
D01 5
D10 4
D11 3
D20 13
D21 12
1 Q0
2 Q1
15 Q2
PIN ASSIGNMENT
Q0
Q1
D11
D10
D01
D00
CLOCK
V
EE
1
2
3
4
5
6
7
8
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
DIP
16
15
14
13
12
11
10
V
CC
Q2
Q3
D20
D21
D30
D31
SELECT
9
3/93
Motorola, Inc. 1996
D30 11
D31 10
CLOCK 7
TRUTH TABLE
SELECT CLOCK Q0
H L D00
L L D01
X H Q0
3–117
n+1
n
14 Q3
VCC= PIN 16
VEE= PIN 8
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
T ables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
REV 5

MC10173
ELECTRICAL CHARACTERISTICS
Test Limits
Pin
Characteristic Symbol
Power Supply Drain Current I
Input Current I
Output Voltage Logic 1 V
Output Voltage Logic 0 V
Threshold Voltage Logic 1 V
Threshold Voltage Logic 0 V
Switching Times (50Ω Load) ns
Propagation Data Input
Delay
Clock Input t
Select Input t
Setup TIme Data Input
Hold TIme Data Input
Rise Time (20 to 80%) t+ 1 1.2 4.0 1.5 2.0 3.5 1.4 4.0
Fall Time (20 to 80%) t– 1 1.2 4.0 1.5 2.0 3.5 1.4 4.0
*V
applied to each input pin, one at a time.
ILmin
Select Input
Select Input
E
inH
I
inL
OH
OL
OHA
OLA
t
6+1+
t
6–1–
t
5+1+
t
5–1–
7–1+
t
7–1–
9+1+
t
9+1–
t
9–1+
t
9–1–
t
setup
t
setup
t
hold
t
hold
Under
Test
8 73 66 73 mAdc
5
6
7
9
All 0.5 0.5 0.3 µAdc
1
2
1
2
1
2
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
–30°C +25°C +85°C
Min Max Min Typ Max Min Max
–1.060
–1.060
–1.890
–1.890
–1.080
–1.080
0.8
0.8
0.8
0.8
1.6
1.6
1.1
1.1
1.1
1.1
2.0
3.0
2.5
1.5
470
470
400
400
–0.890
–0.890
–1.675
–1.675
–1.655
–1.655
3.7
3.7
3.7
3.7
7.2
7.2
6.2
6.2
6.2
6.2
–0.960
–0.960
–1.850
–1.850
–0.980
–0.980
1.0
1.0
1.0
1.0
1.6
1.6
1.3
1.3
1.3
1.3
2.0
3.0
2.5
1.5
2.5
2.5
2.5
2.5
4.5
4.5
3.5
3.5
3.5
3.5
1.5
2.5
0.0
–0.5
295
295
250
250
–0.810
–0.810
–1.650
–1.650
–1.630
–1.630
3.5
3.5
3.5
3.5
6.8
6.8
5.7
5.7
5.7
5.7
–0.890
–0.890
–1.825
–1.825
–0.910
–0.910
1.1
1.1
1.1
1.1
1.4
1.4
1.2
1.2
1.2
1.2
2.0
3.0
2.5
1.5
–0.700
–0.700
–1.615
–1.615
–1.595
–1.595
295
295
250
250
5.3
5.3
5.3
5.3
6.8
6.8
6.7
6.7
6.7
6.7
Unit
µAdc
Vdc
Vdc
Vdc
Vdc
MOTOROLA MECL Data
3–118
DL122 — Rev 6

MC10173
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@ Test Temperature V
–30°C –0.890 –1.890 –1.205 –1.500 –5.2
+25°C –0.810 –1.850 –1.105 –1.475 –5.2
+85°C –0.700 –1.825 –1.035 –1.440 –5.2
Pin
Characteristic Symbol
Power Supply Drain Current I
Input Current 5
Output Voltage Logic 1 V
Output Voltage Logic 0 V
Threshold Voltage Logic 1 V
Threshold Voltage Logic 0 V
Switching Times (50Ω Load) +1.11V +0.31V Pulse In Pulse Out –3.2 V +2.0 V
Propagation Delay Data Input t
Clock Input t
Select Input t
Setup TIme Data Input
Hold TIme Data Input
Rise Time (20 to 80%) t+ 1 5 7 1 8 16
Fall Time (20 to 80%) t– 1 7 1 8 16
*V
applied to each input pin, one at a time.
ILmin
Select Input
Select Input
I
inL
OH
OL
OHA
OLA
6+1+
t
6–1–
t
5+1+
t
5–1–
7–1+
t
7–1–
9+1+
t
9+1–
t
9–1+
t
9–1–
t
setup
t
setup
t
hold
t
hold
E
er
Test
8 8 16
6
7
9
All * 8 16
1
2
1
2
1
2
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IHmax
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
V
IHmax
5
6
7
9
6, 9
5
9 7
9 7
9 7
9
9
6
5
5
6
6
6
V
ILmin
V
ILmin
V
IHAminVILAmax
V
IHAminVILAmax
7
7
7
7
7
7
7
7
7
7
7
7
7
6
5
6
6
5
5
5, 7
5, 7
9
9
9
9
5, 7
7, 9
5, 7
7, 9
6
5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
V
EE
V
EE
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
Gnd
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
3–119 MOTOROLAMECL Data
DL122 — Rev 6

MC10173
OUTLINE DIMENSIONS
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 775–02
ISSUE C
–L–
20 1
Z
C
G
G1
0.010 (0.250) N
S
T
–N–
L–M
S
Y BRK
–M–
W
V
A
0.007 (0.180) N
0.007 (0.180) N
R
E
0.004 (0.100)
J
PLANE
SEATING
–T–
VIEW S
S
0.007 (0.180) N
B
U
M
0.007 (0.180) N
S
L–M
T
M
S
S
L–M
T
S
D
Z
D
X
0.010 (0.250) N
G1
S
S
L–M
T
S
VIEW D–D
M
M
S
L–M
T
L–M
T
S
S
S
0.007 (0.180) N
H
M
S
L–M
T
S
K1
K
0.007 (0.180) N
F
M
S
L–M
T
S
VIEW S
NOTES:
1. DATUMS –L–, –M–, AND –N– DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS PLASTIC
BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DA TUM –T–, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300).
DIMENSIONS R AND U ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS,
GATE BURRS AND INTERLEAD FLASH, BUT
INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037 (0.940).
THE DAMBAR INTRUSION(S) SHALL NOT CAUSE
THE H DIMENSION TO BE SMALLER THAN 0.025
(0.635).
MOTOROLA MECL Data
DIM MIN MAX MIN MAX
A 0.385 0.395 9.78 10.03
B 0.385 0.395 9.78 10.03
C 0.165 0.180 4.20 4.57
E 0.090 0.110 2.29 2.79
F 0.013 0.019 0.33 0.48
G 0.050 BSC 1.27 BSC
H 0.026 0.032 0.66 0.81
J 0.020 ––– 0.51 –––
K 0.025 ––– 0.64 –––
R 0.350 0.356 8.89 9.04
U 0.350 0.356 8.89 9.04
V 0.042 0.048 1.07 1.21
W 0.042 0.048 1.07 1.21
X 0.042 0.056 1.07 1.42
Y ––– 0.020 ––– 0.50
Z 2 10 2 10
____
G1 0.310 0.330 7.88 8.38
K1 0.040 ––– 1.02 –––
3–120
MILLIMETERSINCHES
DL122 — Rev 6

OUTLINE DIMENSIONS
CERAMIC DIP PACKAGE
–A–
16 9
–B–
18
C
–T–
SEATING
PLANE
E
F
G
16 PLD
0.25 (0.010) T
M
–A–
916
B
18
F
C
S
H
G
D
16 PL
K
0.25 (0.010) T
K
N
S
A
PLASTIC DIP PACKAGE
SEATING
–T–
PLANE
M
M
A
L SUFFIX
CASE 620–10
ISSUE V
L
M
16 PLJ
0.25 (0.010) T
P SUFFIX
CASE 648–08
ISSUE R
L
J
MC10173
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
DIM MIN MAX MIN MAX
A 0.750 0.785 19.05 19.93
B 0.240 0.295 6.10 7.49
C ––– 0.200 ––– 5.08
D 0.015 0.020 0.39 0.50
E 0.050 BSC 1.27 BSC
F 0.055 0.065 1.40 1.65
G 0.100 BSC 2.54 BSC
H 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31
M
S
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
M
L 0.300 BSC 7.62 BSC
M 0 15 0 15
____
N 0.020 0.040 0.51 1.01
Y14.5M, 1982.
FORMED PARALLEL.
DIM MIN MAX MIN MAX
A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01
MILLIMETERSINCHES
MILLIMETERSINCHES
____
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MC10173/D
DL122 — Rev 6
◊
3–121 MOTOROLAMECL Data
*MC10173/D*