MOTOROLA MAC7100EC, MAC7100ED User Manual

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Advance Information

MAC7100EC/D Rev. 0.1, 10/2003

MAC7100 Microcontroller Family Hardware Specifications

Freescale Semiconductor, Inc.

32-bit Embedded Controller Division

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This document provides electrical specifications, pin assignments, and package diagrams for MAC7100 family of microcontroller devices. For functional characteristics of the family, refer to the MAC7100 Microcontroller Family Reference Manual (MAC7100RM/D).

This document contains the following topics:

Topic Page

Section 1, “Overview” 1

Section 2, “Ordering Information” 2

Section 3, “Electrical Characteristics” 3

Section 4, “Device Pin Assignments” 36

Section 5, “Mechanical Information” 41

1Overview

The MAC7100 Family of microcontrollers (MCUs) are members of a pin-compatible family of 32-bit Flash-memory-based devices developed specifically for embedded automotive applications. The pin-compatible family concept enables users to select between different memory and peripheral options for scalable designs. All MAC7100 Family members are composed of a 32-bit central processing unit (ARM7TDMI-S), up to 512Kbytes of embedded Flash EEPROM for program storage, up to 32Kbytes of embedded Flash for data and/or program storage, and up to 32Kbytes of RAM. The family is implemented with an enhanced DMA (eDMA) controller to improve performance for transfers between memory and many of the on-chip peripherals. The peripheral set includes asynchronous serial communications interfaces (eSCI), serial peripheral interfaces (DSPI), inter-integrated circuit (I controllers, FlexCAN interfaces, an enhanced modular I/O subsystem (eMIOS), 10-bit analog-to-digital converter (ATD) channels, general-purpose timers (PIT) and two special-purpose timers (RTI and SWT). The peripherals share a large number of general purpose input-output (GPIO) pins, all of which are bidirectional and available with interrupt capability to trigger wake-up from low-power chip modes.

2

C) bus

The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements. The operating frequency of devices in the family is up to a maximum of 50 MHz. The internal data paths between the CPU core, eDMA, memory and peripherals are all 32 bits wide, further improving performance for 32-bit applications. The

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Ordering Information

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MAC7111 and MAC7131 also offer a 16-bit wide external data bus with 22 address lines. The family of devices is capable of operating over a junction temperature range of -40° C to 150° C.

Table 1 provides a comparison of members of the MAC7100 Family and the availability of peripheral modules on the various devices.

Table 1. MAC7100 Family Device Derivatives

Module Options MAC7101 MAC7111 MAC7121 MAC7131 MAC7141

Program Flash 512Kbytes 512Kbytes 512Kbytes 512Kbytes 512Kbytes

Data Flash 32Kbytes 32Kbytes 32Kbytes 32Kbytes 32Kbytes

SRAM 32Kbytes 32Kbytes 32Kbytes 32Kbytes 32Kbytes

External Bus No Yes No Yes No

ATD Modules 2 1 1 2 1

CAN Modules 4 4 4 4 2

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eSCI Modules 4 4 4 4 2

DSPI Modules 2 2 2 2 2

I2C Modules 1 1 1 1 1

eMIOS Module 16 channels,

16-bit

Timer Module 10 channels,

24-bit

GPIO Pins (max.) 111 111 84 127 71

Package 144 LQFP 144 LQFP 112 LQFP 208 MAP BGA 100 LQFP

16 channels,

16-bit

10 channels,

24-bit

16 channels,

16-bit

10 channels,

24-bit

16 channels,

16-bit

10 channels,

24-bit

16 channels,

16-bit

10 channels,

24-bit

2 Ordering Information

M AC 7 1 0 1 C PV 50 xx

MC Status

Core Code

Core Number

Generation / Family

Package Option

Device Number

Temperature Range

Package Identifier

Speed (MHz)

Optional Package Identifiers

Figure 1. Order Part Number Example

Temperature Option

C = –40° C to 85° C V = –40° C to 105° C M = –40° C to 125° C

Package Option

FU = 100 QFP PV = 112 / 144 LQFP VF = 208 MAP BGA

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Electrical Characteristics

3 Electrical Characteristics

This section contains electrical information for MAC7100 Family microcontrollers. The information is preliminary and subject to change without notice.

MAC7100 Family devices are specified and tested over the 5 V and 3.3 V ranges. For operation at any voltage within that range, the 3.3 V specifications generally apply. However, no production testing is done to verify operation at intermediate supply voltage levels.

3.1 Parameter Classification

The electrical parameters shown in this appendix are derived by various methods. To provide a better understanding to the designer, the following classification is used. Parameters are tagged accordingly in in the column labeled “C” of the parametric tables, as appropriate.

Table 2. Parametric Value Classification

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P Parameters guaranteed during production testing on each individual device.

C Parameters derived by the design characterization and by measuring a statistically relevant

sample size across process variations.

T Parameters derived by design characterization on a small sample size from typical devices

under typical conditions (unless otherwise noted). All values shown in the typical column are within this classification, even if not so tagged.

D Parameters derived mainly from simulations.

3.2 Absolute Maximum Ratings

Absolute maximum ratings are stress ratings only. Functional operation outside these maximums is not guaranteed. Stress beyond these limits may affect reliability or cause permanent damage to the device.

MAC7100 Family devices contain circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either V

Table 3. Absolute Maximum Ratings

Num Rating Symbol Min Max Unit

A1 I/O, Regulator and Analog Supply Voltage VDD5–0.3 +6.0V

A2 Digital Logic Supply Voltage

A3 PLL Supply Voltage

A4 ATD Supply Voltage V

A5 Analog Reference V

A6 Voltage difference V

A7 Voltage difference V

A8 Voltage difference VRH – V

A9 Voltage difference V

A10 Digital I/O Input Voltage V

1

DD

SS

DD

1

VDDPLL –0.3 +3.0 V

X to VDDA ∆

X to VSSA ∆

VRH – V

VDDA – V

A – V

RL

RH

VDD2.5 –0.3 +3.0 V

A–0.3 +6.5V

DD

RH, VRL

VDDX

VSSX

RL

RH

IN

5 or VDD5).

SS

–0.3 +6.0 V

–0.3 +0.3 V

–0.3 +6.5 V

–6.5 +6.5 V

–0.3 +6.0 V

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Electrical Characteristics

Table 3. Absolute Maximum Ratings (continued)

Num Rating Symbol Min Max Unit

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A11 XFC, EXTAL, XTAL inputs V

A12 TEST input V

Instantaneous Maximum Current

A13 Single pin limit for XFC, EXTAL, XTAL

A14 Single pin limit for all digital I/O pins

A15 Single pin limit for all analog input pins

A16 Single pin limit for TEST

A17 Storage Temperature Range T

1

The device contains an internal voltage regulator to generate the logic and PLL supply from the I/O supply. The absolute maximum ratings apply when the device is powered from an external source.

2

Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values using V calculated values.

3

These pins are internally clamped to VSSPLL and VDDPLL.

4

All I/O pins are internally clamped to VSSX and VDDX, VSSR and VDDR or VSSA and VDDA.

5

This pin is clamped low to VSSX, but not clamped high, and must be tied low in applications.

2

5

POSCLAMP

3

4

= VDDA + 0.3 V and V

ILV

TEST

I

DL

I

D

I

DA

I

DT

stg

NEGCLAMP

–0.3 +3.0 V

–0.3 +10.0 V

–25 +25 mA

–0.25 0 mA

–65 +155 °C

= –0.3 V, then use the larger of the

3.3 ESD Protection and Latch-up Immunity

All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body Model (HBM), the Machine Model (MM) and the Charge Device Model.

A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise.

Table 4. ESD and Latch-up Test Conditions

Model Description Symbol Value Unit

Human Body Series Resistance R1 1500 Ohm

Storage Capacitance C 100 pF

Number of Pulses per pin

positive negative

Machine Series Resistance R1 0 Ohm

Storage Capacitance C 200 pF

Number of Pulse per pin

positive negative

Latch-up Minimum input voltage limit –2.5 V

Maximum input voltage limit 7.5 V

——

3 3

——

3 3

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Table 5. ESD and Latch-Up Protection Characteristics

Num C Rating Symbol Min Max Unit

Electrical Characteristics

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B1 C Human Body Model (HBM) V

B2 C Machine Model (MM) V

B3 C Charge Device Model (CDM) V

B4 C Latch-up Current at T

positive negative

B5 C Latch-up Current at T

positive negative

= 125°C

A

= 27°C

A

HBM

MM

CDM

I

LAT

I

LAT

2000 — V

200 — V

500 — V

mA +100 –100

+200 –200

—

—mA

3.4 Operating Conditions

Unless otherwise noted, the following conditions apply to all parametric data. Refer to the temperature rating of the device (C, V, M) with respect to ambient temperature (T power dissipation calculations refer to Section 3.5, “Power Dissipation and Thermal Characteristics.”

Table 6. MAC7100 Family Device Operating Conditions

Num Rating Symbol Min Typ Max Unit

C1 I/O, Regulator and Analog Supply Voltage VDD5 4.5 5 5.5 V

C2 Digital Logic Supply Voltage

C3 PLL Supply Voltage

C4 Voltage Difference VDDX to VDDA ∆

C5 Voltage Difference VSSX to VSSA ∆

C6 Oscillator Frequency f

C7 Bus Frequency f

C8a MAC7100C Operating Junction Temperature Range

C8b Operating Ambient Temperature Range

C9a MAC7100V Operating Junction Temperature Range

C9b Operating Ambient Temperature Range

C10a MAC7100M Operating Junction Temperature Range

C10b Operating Ambient Temperature Range

1

The device contains an internal voltage regulator to generate the logic and PLL supply from the I/O supply. The absolute maximum ratings apply when this regulator is disabled and the device is powered from an external source.

2

Please refer to Section 3.5, “Power Dissipation and Thermal Characteristics,” for more details about the relation between ambient temperature TA and device junction temperature TJ.

1

V

2.5 2.35 2.5 2.75 V

DD

VDDPLL 2.35 2.5 2.75 V

X –0.1 0 0.1 V

VDD

X –0.1 0 0.1 V

VSS

osc

bus

T

J

2

T

A

T

J

2

T

A

T

J

2

T

A

) and junction temperature (TJ). For

A

0.5 — 16 MHz

0.5 — 50 MHz

–40 — 110 °C

–40 25 85 °C –40 — 130 °C

–4025105°C –40 — 150 °C

–4025125°C

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Electrical Characteristics

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3.4.1 5 V I/O Pins

The I/O pins operate at a nominal level of 5 V. This class of pins is comprised of the clocks, control and general purpose/peripheral pins. The internal structure of these pins is identical; however, some functionality may be disabled (for example, for analog inputs the output drivers, pull-up/down resistors are permanently disabled).

3.4.2 Oscillator Pins

The pins XFC, EXTAL, XTAL are dedicated to the oscillator and operate at a nominal level of 2.5 V.

3.5 Power Dissipation and Thermal Characteristics

Power dissipation and thermal characteristics are closely related. The user must assure that the maximum operating junction temperature is not exceeded.

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Note that the JEDEC specification reserves the symbol R ambient thermal resistance on a 1s test board in natural convection environment. R

or θJA (Theta-JA) strictly for junction-to-

θJA

θJMA

or θ

JMA

(Theta-JMA) will be used for both junction-to-ambient on a 2s2p test board in natural convection and for junction-to-ambient with forced convection on both 1s and 2s2p test boards. It is anticipated that the generic name, θ

The average chip-junction temperature (T

, will continue to be commonly used.

JA

TJTAΘJA()+=

Junction Temperature (°C)=

T

J

T

Ambient Temperature (°C)=

A

Total Chip Power Dissipation (W)=

P

D

Package Thermal Resistance (°C/W)=

Θ

JA

) in °C is obtained from:

J

The total power dissipation is calculated from:

P

+=

INTPIO

P

INT

P

INT

Chip Internal Power Dissipation (W)=

IDDVDD×()IDDPLL VDDPLL×()IDDAVDDA×()++=

Two cases for P

P

D

, with the internal voltage regulator enabled and disabled, must be considered:

IO

1. Internal Voltage Regulator disabled:

∑

R

DSON

i

V

OL

----------

(for outputs driven low)=

I

OL

P

IO

P

is the sum of all output currents on I/O ports associated with VDDX and VDDR.

IO

R

DSON

I

()

⋅=

IO

i

2

or

VDD5V

–

R

DSON

-------------------------------

OH

I

(for outputs driven high)=

OL

2. Internal voltage regulator enabled:

P

I

R is the current shown in Table 12 and not the overall current flowing into VDDR, which

DD

INT

IDDRVDDR×()IDDAVDDA×()+=

additionally contains the current flowing into the external loads with output high.

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Electrical Characteristics

3.5.1 Power Dissipation Simulation Details

Table 7. Thermal Resistance for 100 lead 14x14 mm LQFP, 0.5 mm Pitch

Rating Value Unit Comments

Junction to Ambient (Natural Convection) Single layer board (1s) R Junction to Ambient (Natural Convection) Four layer board (2s2p) R Junction to Ambient (@ 200 ft./min.) Single layer board (1s) R Junction to Ambient (@ 200 ft./min.) Four layer board (2s2p) R Junction to Board R Junction to Case R Junction to Package Top Natural Convection Ψ

1

100 LQFP, Case Outline: 983–02

Table 8. Thermal Resistance for 112 lead 20x20 mm LQFP, 0.65 mm Pitch

Rating Value Unit Comments

Junction to Ambient (Natural Convection) Single layer board (1s) R Junction to Ambient (Natural Convection) Four layer board (2s2p) R Junction to Ambient (@ 200 ft./min.) Single layer board (1s) R Junction to Ambient (@ 200 ft./min.) Four layer board (2s2p) R Junction to Board R Junction to Case R Junction to Package Top Natural Convection Ψ

1

112 LQFP, Case Outline: 987–01

Table 9. Thermal Resistance for 144 lead 20x20 mm LQFP, 0.5 mm Pitch

Rating Value Unit Comments

Junction to Ambient (Natural Convection) Single layer board (1s) R Junction to Ambient (Natural Convection) Four layer board (2s2p) R Junction to Ambient (@ 200 ft./min.) Single layer board (1s) R Junction to Ambient (@ 200 ft./min.) Four layer board (2s2p) R Junction to Board R Junction to Case R Junction to Package Top Natural Convection Ψ

1

144 LQFP, Case Outline: 918–03

Table 10. Thermal Resistance for 208 lead 17x17 mm MAP, 1.0 mm Pitch

Rating Value Unit Comments

Junction to Ambient (Natural Convection) Single layer board (1s) R Junction to Ambient (Natural Convection) Four layer board (2s2p) R Junction to Ambient (@ 200 ft./min.) Single layer board (1s) R Junction to Ambient (@ 200 ft./min.) Four layer board (2s2p) R Junction to Board R Junction to Case R Junction to Package Top Natural Convection Ψ

1

208 MAP BGA, Case Outline: 1159A-01

Comments:

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal.

3. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.

4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board at the center lead. For fused lead packages, the adjacent lead is used.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).

6. Thermal characterization parameter indicating the temperature difference between package top and junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.

θJA θJMA θJMA θJMA

θJB

θJC

JT

θJA θJMA θJMA θJMA

θJB

θJC

JT

θJA θJMA θJMA θJMA

θJB

θJC

JT

θJA θJMA θJMA θJMA

θJB

θJC

JT

44 °C/W 1, 2 34 °C/W 1, 3 37 °C/W 1, 3 29 °C/W 1, 3 18 °C/W 4

7°C/W 5 2°C/W 6

42 °C/W 1, 2 34 °C/W 1, 3 35 °C/W 1, 3 30 °C/W 1, 3 22 °C/W 4

7°C/W 5 2°C/W 6

42 °C/W 1, 2 34 °C/W 1, 3 35 °C/W 1, 3 30 °C/W 1, 3 22 °C/W 4

7°C/W 5 2°C/W 6

46 °C/W 1, 2 29 °C/W 1, 3 38 °C/W 1, 3 26 °C/W 1, 3 19 °C/W 4

7°C/W 5 2°C/W 6

1

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Electrical Characteristics

Table 11. Power Dissipation 1/8 Simulation Model Packaging Parameters

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Component Conductivity

Mold Compound 0.9 W/m K

Leadframe (Copper) 263 W/m K

Die Attach 1.7 W/m K

3.6 Power Supply

The MAC7100 Family utilizes several pins to supply power to the oscillator, PLL, digital core, I/O ports and ATD. In the context of this section, V V

R or VSSX unless otherwise noted. IDD5 denotes the sum of the currents flowing into the VDDA, VDDX,

SS

and V sum of the currents flowing into V

R. VDD is used for VDD2.5, and VDDPLL, VSS is used for VSS2.5 and VSSPLL. IDD is used for the

DD

2.5 and VDDPLL.

DD

5 is used for VDDA, VDDR or VDDX; VSS5 is used for VSSA,

DD

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3.6.1 Current Injection

The power supply must maintain regulation within the VDD5 or VDD2.5 operating range during instantaneous and operating maximum current conditions. If positive injection current (V greater than I going out of regulation. It is important to ensure that the external V the maximum injection current. The greatest risk will be when the MCU is consuming very little power (for example, if no system clock is present, or if the clock rate is very low).

5, the injection current may flow out of VDD5 and could result in the external power supply

DD

5 load will shunt current greater than

DD

> VDD5) is

in

3.6.2 Power Supply Pins

The VDDR – VSSR pair supplies the internal voltage regulator. The VDDA – VSSA pair supplies the A/D converter and the reference circuit of the internal voltage regulator. The V pins. V

All V V

SS

are connected by anti-parallel diodes for ESD protection.

PLL – VSSPLL pair supplies the oscillator and PLL.

DD

X pins are internally connected by metal. All VSSX pins are internally connected by metal. All

DD

2.5 pins are internally connected by metal. VDDA, VDDX and VDDR as well as VSSA, VSSX and VSSR

X – VSSX pair supplies the I/O

DD

3.6.3 Supply Currents

All current measurements are without output loads. Unless otherwise noted the currents are measured in single chip mode, internal voltage regulator enabled and at 40MHz bus frequency using a 4MHz oscillator in low power mode. Production testing is performed using a square wave signal at the EXTAL input.

In expanded modes, the currents flowing in the system are highly dependent on the load at the address, data and control signals as well as on the duty cycle of those signals. No generally applicable numbers can be given. A good estimate is to take the single chip currents and add the currents due to the external loads.

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Electrical Characteristics

Table 12. Supply Current Characteristics

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Num C Rating Symbol Typ Max Unit

D1a C Run Supply Current

Single Chip

D1b C

D1c C

Core

Regulator

(if enabled)

Pins

–40° C

25° C

85° C 105° C 125° C –40° C

25° C

85° C 105° C 125° C –40° C

25° C

85° C 105° C 125° C

2

IDDR

core

reg

pins

2

— — — — — — — — — — — — — — —

1

— — — — — — — — — — — — — — —

1

D2 C Doze Supply Current Run ≥ Doze ≥ Pseudo Stop

D3a C Psuedo Stop Current

PLL on

Core

D3b C

Regulator

D3c C

Pins

D4a C Stop Current

= TA assumed

T

J

Core

D4b C

Regulator

D4c C

Pins

1

At the time of publication, this value is yet to be determined, and will be supplied when device characterization is complete.

2

85°C, 105°C, and 125°C refer to the "C", "V", and "M" Temperature Options, respectively.

3

RTI disabled / enabled.

–40° C

25° C

85° C 105° C 125° C –40° C

25° C

85° C 105° C 125° C –40° C

25° C

85° C 105° C 125° C –40° C

25° C

85° C 105° C 125° C –40° C

25° C

85° C 105° C 125° C –40° C

25° C

85° C 105° C 125° C

2

IDDPS

IDDS

core

reg

pins

core

reg

pins

2

1

—

1

—

1

—

1

—

1

—

1

—

— — — —

4 / 5

— — — — — — — — —

3

1

3

1

278 / 327

68 —

1

—

1

—

1

—

1

—

— — — — — — — — — — — — — — — — — — — — —

— — — —

1

4— 1µA — — —

1

— — —

1

mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA

µA µA µA µA µA µA µA µA µA µA µA µA µA µA µA µA µA µA µA µA µA µA µA µA µA µA

µA µA µA

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Electrical Characteristics

3.6.4 Voltage Regulator Characteristics

Table 13. VREG Operating Conditions

Num C Characteristic Symbol Min Typical Max Unit

E1 P Input Voltages V

E2 P Regulator Current

Reduced Power Mode Shutdown Mode

E3 P Output Voltage Core

Full Performance Mode Reduced Power Mode Shutdown Mode

E4 P Output Voltage PLL

Full Performance Mode Reduced Power Mode Reduced Power Mode

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E5 P Low Voltage Interrupt

E6 P Low Voltage Reset

E7 P Power On Reset

1

High Impedance Output.

2

Current IDDPLL = 1mA (Low Power Oscillator).

3

Current IDDPLL = 3mA (Standard Oscillator).

4

Monitors VDDA, active only in full performance mode. Indicated I/O and voltage.

5

Monitors VDD2.5, active only in full performance mode. Only POR is active in reduced performance mode.

6

Monitors VDD2.5, active in all modes.

Shutdown Mode

Assert Level Deassert Level

Assert Level

6

Assert Level Deassert Level

2

3

4

5

VDDRA

I

REG

V

DD

V V

V

LVR A

V

PORA

V

PORD

DD

PLL

LVI A

LVI D

cale Semiconductor,

2.97 — 5.5 V

— —

2.45

1.60 —

2.35

2.00

1.60 —

4.10

4.25

2.25 2.35 — V

0.97 —

ATD

performance degradation due to low supply

TBD TBD

2.5

1

—

2.5

2.5 —

4.37

4.52

— —

50 40

2.75

2.75 —

2.75

1

2.75 —

4.66

4.77

—

2.05

µA µA

V V V

V V V V

V V

Frees

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Electrical Characteristics

3.6.5 Chip Power Up and Voltage Drops

The VREG sub-modules LVI (low voltage interrupt), POR (power on reset) and LVR (low voltage reset) handle chip power-up or drops of the supply voltage. Refer to Figure 2.

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tage

V

LVI D

V

LVI A

V

LVR D

V

LVR A

V

PORD

LVI

POR

LVR

Note: Not to scale.

LVI Enabled

Figure 2. VREG Chip Power-up and Voltage Drops

LVI Disabled

due to LVR

VDDA

V

DD

Time

2.5

3.6.6 Output Loads

The on-chip voltage regulator is intended to supply the internal logic and oscillator circuits. No external DC load is allowed. Capacitive loads are specified in Table 14. Capacitors with X7R dielectricum are required.

Table 14. VREG Recommended Load Capacitances

Rating Symbol Min Typ Max Unit

Load Capacitance on each V

Load Capacitance on V

DD

2.5 pin C

DD

PLL pin C

LVD D

LVD Dfc PLL

200 440 12000 nF

90 220 5000 nF

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Electrical Characteristics

3.7 I/O Characteristics

This section describes the characteristics of all I/O pins in both 3.3 V and 5 V operating conditions. All parameters are not always applicable; for example, not all pins feature pull up/down resistances.

Table 15. 5 V I/O Characteristics

Conditions shown in Table 6 unless otherwise noted

Num C Rating Symbol Min Typ Max Unit

nc...

I

cale Semiconductor,

Frees

F1a P Input High Voltage V

F1b T Input High Voltage V

F2a P Input Low Voltage V

F2b T Input Low Voltage V

F3 C Input Hysteresis V

F4 P

F5 P Output High Voltage (pins in output mode)

F6 P Output Low Voltage (pins in output mode)

F7 P Internal Pull Up Device Current,

F8 P Internal Pull Up Device Current,

F9 P Internal Pull Down Device Current,

F10 P Internal Pull Down Device Current,

F11 D Input Capacitance C

F12 T Injection current

F13 P Port Interrupt Input Pulse filtered

F14 P Port Interrupt Input Pulse passed

1

Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each 8°C to 12°C in the temperature range from 50°C to 125°C.

2

Refer to Section 3.6.1, “Current Injection,” for more details

3

Parameter only applies in STOP or Pseudo STOP mode.

Input Leakage Current (pins in high impedance input mode)

= V

V

in

Partial Drive I Full Drive I

Partial Drive I Full Drive

tested at V

Single Pin limit Total Device Limit. Sum of all injected currents

5 or VSS5

DD

OH

I

OL

IL

IH

IL

= –2mA

OH

= –10mA

= +2mA

OL

= +10mA

Max.

Min.

Max.

2

3

HYS

1

I

V

I

PUL

I

PUH

I

PDH

I

PDL

I

ICS

I

ICP

t

PULSE

t

PULSE

IH

IL

in

OH

OL

0.65 ×

VDD5

——V

— — 0.35 ×

VSS5 –

0.3

—250—mV

TBD — TBD µA

VDD5 –

0.8

——0.8V

— — –130 µA

–10 — — µA

——130µA

10 — — µA

in

—6—pF

–2.5

–25

—— 3 µs

10 — — µs

—— V

5+

DD

0.3

VDD5

—— V

—

2.5 25

V

µA

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Table 16. 3.3 V I/O Characteristics

Conditions shown in Table 6, with VDDX = 3.3 V ±10% and a temperature maximum of +140°C unless otherwise noted.

Num C Rating Symbol Min Typ Max Unit

nc...

I

cale Semiconductor,

Frees

G1a P Input High Voltage V

G1b T Input High Voltage V

G2a P Input Low Voltage V

G2b T Input Low Voltage V

G3 C Input Hysteresis V

G4 P

G5 P Output High Voltage (pins in output mode)

G6 P Output Low Voltage (pins in output mode)

G7 P Internal Pull Up Device Current,

G8 P Internal Pull Up Device Current,

G9 P Internal Pull Down Device Current,

G10 P Internal Pull Down Device Current,

G11 D Input Capacitance C

G12 T Injection current

G13 P Port Interrupt Input Pulse filtered

G14 P Port Interrupt Input Pulse passed

1

Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each 8°C to 12°C in the temperature range from 50°C to 125°C.

2

Refer to Section 3.6.1, “Current Injection,” for more details

3

Parameter only applies in STOP or Pseudo STOP mode.

Input Leakage Current (pins in high impedance input mode)

= V

V

in

5 or VSS5

DD

I

Partial Drive Full Drive I

tested at VIL Max.

tested at VIH Min.

tested at VIL Max.

Single Pin limit Total Device Limit. Sum of all injected currents

OH

= –4.5mA

OH

I

OL

= +5.5mA

OL

2

= –0.75mA

= +0.9mA

3

HYS

1

I

V

I

PUL

I

PUH

I

PDH

I

PDL

I

ICS

I

ICP

t

PULSE

t

PULSE

IH

IL

in

OH

OL

0.65 ×

V

DD

——V

— — 0.35 ×

VSS5 –

0.3

—250—mV

TBD — TBD µA

VDD5 –

0.4

——0.4V

— — –60 µA

–6 — — µA

——60µA

6——µA

in

—6—pF

–2.5

–25

—— 3 µs

10 — — µs

—— V

5

5 +

DD

0.3

VDD5

—— V

—

2.5 25

V

µA

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Electrical Characteristics

Freescale Semiconductor, Inc.

3.8 Clock and Reset Generator Electrical Characteristics

This section describes the electrical characteristics for the oscillator, phase-locked loop, clock monitor and reset generator.

3.8.1 Oscillator Characteristics

The MAC7100 Family features an internal low power loop controlled Pierce oscillator and a full swing Pierce oscillator/external clock mode. The selection of loop controlled Pierce oscillator or full swing Pierce oscillator/external clock depends on the level of the XCLKS Before asserting the oscillator to the internal system clock distribution subsystem, the quality of the oscillation is checked for each start from either power on, STOP or oscillator fail. t maximum time before switching to the internal self clock mode after POR or STOP if a proper oscillation is not detected. The quality check also determines the minimum oscillator start-up time t features a clock monitor. A Clock Monitor Failure is asserted if the frequency of the incoming clock signal

nc...

I

is below the Clock Monitor Assert Frequency f

Table 17. Oscillator Characteristics

CMFA

.

signal at the rising edge of the RESET signal.

specifies the

CQOUT

. The device also

UPOSC

cale Semiconductor,

Frees

Num C Rating Symbol Min Typ Max Unit

H1a C Crystal oscillator range (loop controlled Pierce) f

H1b C Crystal oscillator range (full swing Pierce)

H2 P Startup Current I

H3 C Oscillator start-up time (loop controlled Pierce) t

H4 D Clock Quality check time-out t

H5 P Clock Monitor Failure Assert Frequency f

H6 P External square wave input frequency

H7 D External square wave pulse width low t

H8 D External square wave pulse width high t

H9 D External square wave rise time t

H10 D External square wave fall time t

H11 D Input Capacitance (EXTAL, XTAL pins) C

H12 C EXTAL pin DC Operating Bias in loop controlled

mode

1

Depending on the crystal; a damping series resistor might be necessary

2

XCLKS negated during reset

3

f

= 4 MHz, C = 22 pF.

osc

4

Maximum value is for extreme cases using high Q, low frequency crystals

1, 2

2

OSC

f

OSC

UPOSC

CQOUT

CMFA

f

EXT

EXTL

EXTH

EXTR

EXTF

V

DCBIAS

IN

4.0 — 16 MHz

0.5 — 40 MHz

100 — — µA

—TBD

0.45 — 2.5 s

50 100 200 KHz

0.5 — 40 MHz

9.5 — — ns

—— 1ns

—7—pF

—TBD—V

3

50

4

ms

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Electrical Characteristics

Freescale Semiconductor, Inc.

3.8.2 PLL Filter Characteristics

The oscillator provides the reference clock for the PLL. The voltage controlled oscillator (VCO) of the PLL is also the system clock source in self clock mode. In order to operate reliably, care must be taken to select proper values for external loop filter components.

VDDPLL

nc...

I

cale Semiconductor,

Frees

f

OSC

1

REFDV+1

C

Phase

Detector

f

REF

Figure 3. Basic PLL Functional Diagram

f

CMP

∆

K

Loop Divider

SYNR+1

S

R

φ

1

C

P

VCO

K

V

1

2

f

VCO

The procedure described below can be used to calculate the resistance and capacitance values using typical values for K

, f1 and ich from Table 18. First, the VCO Gain at the desired VCO output frequency is

1

approximated by:

f1f

–()

VCO

--------------------------

1V⋅

K

KVK1e

1

⋅=

The phase detector relationship is given by:

K

is the current in tracking mode. The loop bandwidth fC should be chosen to fulfill the Gardner’s stability

i

ch

ich– KV⋅=

Φ

criteria by at least a factor of 10, typical values are 50. ζ = 0.9 ensures a good transient response.

2 ζ f

<

f

-----------------------------------------

C

πζ 1 ζ

⋅⋅

1

ref



------



50

2

++()⋅

f

ref

-------------- ζ 0.9=();<→

f

C

450⋅

And finally the frequency relationship is defined as

f

VCO

n

------------2synr 1+()⋅==

f

ref

With the above inputs the resistance can be calculated as:

⋅⋅⋅

The capacitance C

2 π nf

----------------------------=

R

can now be calculated as:

S

2 ζ2⋅

---------------------

C

S

π f

C

should be chosen in the range of:

P

C

20÷ CPCS10÷≤≤

S

R⋅⋅

C

K

Φ

0.516

-------------- ζ 0.9=();≈=

R⋅

f

C

The stabilization delays shown in Table 18 are dependant on PLL operational settings and external component selection (for example, crystal, XFC filter).

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