Motorola H11AAV2, H11AAV1 Datasheet

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SEMICONDUCTOR TECHNICAL DATA

 Motorola, Inc. 1994

11/93

REV 3

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The MC74F803 is a high-speed, low-power, quad D-type flip-flop featuring
separate D-type inputs, and inverting outputs with closely matched
propagation delays. With a buffered clock (CP) input that is common to all
flip-flops, the F803 is useful in high-frequency systems as a clock driver,
providing multiple outputs that are synchronous. Because of the matched
propagation delays, the duty cycles of the output waveforms in a clock driver
application are symmetrical within 1.0 to 1.5 nanoseconds.

• Edge-Triggered D-Type Inputs

• Buffered Positive Edge-Triggered Clock

• Matched Outputs for Synchronous Clock Driver Applications

• Outputs Guaranteed for Simultaneous Switching

Pinout: 14-Lead Plastic (Top View)

14 13 12 11 10 9

123456

8

7

VCCNC O3

D3 D2 O2 CP

GND NC O0

D0 D1 O1 GND

GUARANTEED OPERATION RANGES

Symbol Parameter Min Typ Max Unit

V

CC

Supply Voltage 4.5 5.0 5.5 V

T

A

Operating Ambient
T emperature Range

0 25 70 °C

I

OH

Output Current — High — — –20 mA

I

OL

Output Current — Low — — 24 mA

LOGIC DIAGRAM

CP

D0

CP D

Q

O0

D1

CP D

Q

O1

D2

CP D

Q

O2

D3

CP D

Q

O3



CLOCK DRIVER QUAD

D-TYPE FLIP-FLOP WITH

MATCHED PROPAGATION

DELAYS

J SUFFIX

CERAMIC

CASE 632-08

N SUFFIX

PLASTIC

CASE 646-06

14

1

14

1

14

1

D SUFFIX

SOIC

CASE 751A-03

LOGIC SYMBOL

8

451011

36912

D0 D1 D2 D3

O1O0 O2 O3

CP

VCC = PIN 14
GND = PINS 1 AND 7
NC = PINS 2 AND 13

MC74F803

2

MOTOROLA TIMING SOLUTIONS

BR1333 — REV 4

FUNCTIONAL DESCRIPTION

The F803 consists of four positive edge-triggered flip-flops
with individual D-type inputs and inverting outputs. The
buffered clock is common to all flip-flops and the following
specifications allow for outputs switching simultaneously. The
four flip-flops store the state of their individual D inputs that
meet the setup and hold time requirements on the
LOW-to-HIGH Clock (CP) transition. The maximum frequency
of the clock input is 70 megahertz, and the LOW-to-HIGH and
HIGH-to-LOW propagation delays of the O

1

output vary by, at

most, 1 nanosecond. Therefore, the device is ideal for use as

a divide-by-two driver for high-frequency clock signals that
require symmetrical duty cycles. The difference between the
LOW-to-HIGH and HIGH-to-LOW propagation delays for the
O

0

, O2, and O3 outputs vary by at most 1.5 nanoseconds.
These outputs are very useful as clock drivers for circuits with
less stringent requirements. In addition, the output-to-output
skew is a maximum of 1.5 nanoseconds. Finally, the I

OH

specification at 2.5 volts is guaranteed to be at least – 20
milliamps. If their inputs are identical, multiple outputs can be
tied together and the IOH is commensurately increased.

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE

(unless otherwise specified)

Limits

Symbol Parameter

Min Typ Max

Unit Test Conditions*

V

IH

Input HIGH Voltage 2.0 — — V Guaranteed Input HIGH Voltage

V

IL

Input LOW Voltage — — 0.8 V Guaranteed Input LOW Voltage

V

IK

Input Clamp Diode Voltage — — – 1.2 V IIN = –18 mA VCC = MIN

V

OH

Output HIGH Voltage 2.5 — — V IOH = –20 mA VCC = 4.5 V

V

OL

Output LOW Voltage

— 0.35 0.5 V IOL = 24 mA VCC = MIN
— — 20

µA

VIN = 2.7 V VCC = MAX

I

IH

Input HIGH Current — — 100 VIN = 7.0 V VCC = MAX

I

IL

Input LOW Current — — –0.6 mA VIN = 0.5 V VCC = MAX

I

OS

Output Short Circuit Current

(Note 2)

–60 — –150 mA V

OUT

= 0 V VCC = MAX

I

CC

Power Supply Current — — 70 mA VCC = MAX

* Normal test conditions for this device are all four outputs switching simultaneously. Two outputs of the 74F803 can be tied together and the

IOH doubles.

1. For conditions such as MIN or MAX, use the appropriate value specified under guaranteed operating ranges.

2. Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (T

A

= 0 to 70°C, VCC = 5.0 V ± 10%, see Note 1)

CL = 50 pF CL = 100 pF

Symbol Parameter

Min Max Min Max

Unit

f

max

Maximum Clock Frequency 70 — 50 — MHz

t

PLH

t

PHL

Propagation Delay CP to On 3.0 7.5 3.0 10 ns

t

Pv

Propagation Delay CP to On Variation (see Note 3) — 3.0 — 4.0 ns

tps O

1

Propagation Delay Skew |t

PLH

Actual – t

PHL

Actual|

for O

1

Only

— 1.0 — 2.0 ns

tps O0,
O

2

, O

3

Propagation Delay Skew |t

PLH

Actual – t

PHL

Actual|

for O

0

, O2, O

3

— 1.5 — 2.0 ns

t

os

Output to Output Skew (see Note 2) |tp On – tp Om| — 1.5 — 2.5 ns

t

rise

, t

fall

O

1

Rise/Fall Time for O1 (0.8 to 2.0 V) — 3.0 — 4.0 ns

t

rise

, t

fall

O

0

, O2, O

3

Rise/Fall Time for O0, O2, O3 (0.8 to 2.0 V) — 3.5 — 4.5 ns

1. The test conditions used are all four outputs switching simultaneously. The AC characteristics described above (except for O

1

) are also

guaranteed when two outputs are tied together.

2. Where tp On

and tp Om are the actual propagation delays (any combination of high or low) for two separate outputs from a given high

transition of CP.

3. For a given set of conditions (i.e., capacitive load, temperature, VCC, and number of outputs switching simultaneously) the variation from
device to device is guaranteed to be less than or equal to the maximum.