Preliminary Spec.
DESCRIPTION
for easy interchange or addition of modules.
APPLICATION
4096 refresh cycle /64ms
(Component SDRAM)
Some contents are subject to change without notice.
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
The MH8S64AQFC is 8388608 - word by 64-bit
Synchronous DRAM module. This consists of four
industry standard 8Mx16 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual
Inline package provides any application where
high densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable
FEATURES
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
Utilizes industry standard 8M x 16 Synchronous DRAMs
TSOP and industry standard EEPROM in TSSOP
144-pin (72-pin dual in-line package)
single 3.3V±0.3V power supply
Max. Clock frequency -6:133MHz,-7,8:100MHz
Fully synchronous operation referenced to clock rising
edge
4 bank operation controlled by BA0,1(Bank Address)
/CAS latency- 2/3(programmable)
Burst length- 1/2/4/8/Full Page(programmable)
-6,-6L
-7,-7L
-8,-8L
PCB Outline
Frequency
133MHz
100MHz
CLK Access Time
5.4ns(CL=3)
6.0ns(CL=2)
6.0ns(CL=3)100MHz
Burst type- sequential / interleave(programmable)
Column access - random
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
LVTTL Interface
main memory or graphic memory in computer systems
(Front)
(Back)
1
2
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1
143
144
22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
Preliminary Spec.
PIN CONFIGURATION
Number
Pin Name
Pin Name
Number
13579111315171924681012141618
Number
Pin Name
Pin Name
Number
73
74
7980818283848586878889
90
212293942324959625269798272899
1002930
101
102
3334105
3536107
3738109
3940111
1124142
113
1144344
115
1164546
117
118
4950121
5152123
1245354
125
1265556
127
1285758
129
130
6566137
6768139
1406970
141
1427172
143
144
Vss
DQ1
DQ3
Vcc
DQ4
DQ6
Vss
DQ33
DQ35
Vcc
DQ36
DQ38
CLK1
NCNCNCNCVcc
Vcc
DQ16
DQ48
DQ17
DQ49
DQ19
DQ51
Vss
DQ20
DQMB0
DQMB4
DQ21
DQ53
DQMB1
DQMB5
DQ22
DQ54
Vcc
Vcc
DQ23
DQ55
A0A3Vcc
Vcc
A2A5A8
Vss
Vss
DQ8
A9
DQ9
DQ41
A10
A11
DQ10
DQ42
Vcc
Vcc
DQ11
DQ43
DQMB2
DQMB6
Vcc
Vcc
DQMB3
DQ13
DQ24
DQ14
DQ46
DQ25
DQ57
DQ15
DQ47
DQ26
DQ58
Vss
Vss
DQ27
DQ59
NCNCVcc
Vcc
/RAS
DQ31
/WE
CKE1
Vss
Vss
/S0NCSDA
SCL
/S1NCVcc
Vcc
Some contents are subject to change without notice.
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
PIN
31
Front side
DQ0
DQ2
DQ5
DQ7
A1
PIN
20
32
Back side
DQ32
DQ34
DQ37
DQ39
Vss
A4
Vss
DQ40
PIN
Front side
NC
75
Vss
77 78
DQ18
91
103
Vss
A6
PIN
76
92
104
106
108
110
Back side
Vss
DQ50
Vss
DQ52
A7
BA0
Vss
BA1
47
59
61
63
DQ12
NC
CLK0
Vcc
NC = No Connection
48
60
62
64
DQ44
DQ45
NC
CKE0
Vcc
/CAS
119
131
133
135
Vss
DQ28
DQ29
DQ30
120
122
132
134
136
138
DQMB7
Vss
DQ56
DQ60
DQ61
DQ62
DQ63
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22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
Preliminary Spec.
Block Diagram
Some contents are subject to change without notice.
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
/S0
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
DQMB0
DQMB1
DQMB2
DQMB3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
10Ω
DQML
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMU
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQML
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMU
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
/CS
D0
/CS
D1
DQMB4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQMB5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQMB6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQMB7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQML
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMU
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQML
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMU
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
/CS
D2
/CS
D3
BA0,BA1,A<11:0>
CLK0
CKE0
/RAS
/CAS
/WE
Vcc
Vss
D0 - D3
D0 - D3
D0 - D3
D0 - D3
D0 - D3
D0 - D3
D0 - D3
CLK1
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3
SCL
SERIAL PD
A0 A1 A2
SDA
22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
Preliminary Spec.
Serial Presence Detect Table I
Voltage interface standard of this assembly
Non-PARITY
Minimum Clock Delay,Back to Back Random Column Addresses
non-buffered,non-registered
Precharge All,Auto precharge
SDRAM Access form Clock(2nd highest CAS latency)
SDRAM Access form Clock(3rd highest CAS latency)
-8,-8L
-8,-8L
-6,-6L
-6,-6L
-6,-6L
-6,-6L
-6,-6L
-6,-6L
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
Byte Function described SPD enrty data SPD DATA(hex)
Defines # bytes written into serial memory at module mfgr 128
0
1 Total # bytes of SPD memory device
2
3
4
5
6
7
8
SDRAM Cycletime at Max.Supported CAS Latency (CL).
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DIMM Configuration type (Non-parity,Parity,ECC)
SDRAM Cycle time(2nd highest CAS latency)
SDRAM Cycle time(3rd highest CAS latency)
Fundamental memory type SDRAM 04
# Row Addresses on this assembly A0-A11 0C
# Column Addresses on this assembly
# Module Banks on this assembly
Data Width of this assembly... x64 40
... Data Width continuation 0 00
Cycle time for CL=3
SDRAM Access from Clock
tAC for CL=3
Refresh Rate/Type self refresh(15.625uS) 80
SDRAM width,Primary DRAM
Error Checking SDRAM data width N/A 00
Burst Lengths Supported
# Banks on Each SDRAM device 4bank 04
CAS# Latency 2/3 06
CS# Latency 0 01
Write Latency 0 01
SDRAM Module Attributes
SDRAM Device Attributes:General
Cycle time for CL=2
tAC for CL=2
Precharge to Active Minimum
Row Active to Row Active Min.
RAS to CAS Delay Min
Active to Precharge Min
-7,-7L,-8,-8L
-7,-7L,-8,-8L
-6,-6L,-7,-7L
-6,-6L,-7,-7L
-7,-7L,-8,-8L
-7,-7L,-8,-8L
-7,-7L,-8,-8L
-7,-7L,-8,-8L
256 Bytes 08
A0-A8 09
1BANK 01
LVTTL 01
7.5ns
10ns
5.4ns
6ns
x16 10
1 01
1/2/4/8/Full page 8F
10ns
13ns D0
6ns 60
7ns 70
N/A 00
N/A 00
22.5ns 17
20ns 14
15ns 0F
20ns 14
22.5ns 17
20ns 14
45ns 2D
50ns 32
80
75
A0
54
60
00
00
0E
A0
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22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
Preliminary Spec.
Serial Presence Detect Table II
4D4838533634415146432D37202020202020
-6,-6L,-7,7L
-8,8L
4D4838533634415146432D374C2020202020
4D4838533634415146432D38202020202020
4D4838533634415146432D384C2020202020
-6,-6L
-6,-6L
-6,-6L
-6,-6L
4D4838533634415146432D364C2020202020
4D4838533634415146432D36202020202020
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
31 Density of each bank on module 64MByte 10
Command and Address signal input setup time
32
Command and Address signal input hold time
33
34
Data signal input setup time
35
36-61
62 SPD Revision
63 Checksum for bytes 0-62
64-71 Manufactures Jedec ID code per JEP-108E MITSUBISHI 1CFFFFFFFFFFFFFF
72 Manufacturing location
73-90 Manufactures Part Number
91-92 Revision Code PCB revision rrrr
93-94 Manufacturing date year/week code yyww
95-98 Assembly Serial Number serial number ssssssss
99-125 Manufacture Specific Data option 00
126 Intetl specification frequency
127
128+ Unused storage locations open 00
Data signal input hold time
Superset Information (may be used in future) option 00
Intel specification CAS# Latency support
-7,-7L,-8,-8L
-7,-7L,-8,-8L
-7,-7L,-8,-8L
-7,-7L,-8,-8L
1.5ns
2ns
0.8ns
1ns
1.5ns
2ns
0.8ns
1ns
rev 1.2B
Check sum for -6,-6L AC
Check sum for -7,-7L 0D
Check sum for -8,-8L 4D
Miyoshi,Japan 01
Tajima,Japan 02
NC,USA 03
Germany 04
MH8S64AQFC-6
MH8S64AQFC-6L
MH8S64AQFC-7
MH8S64AQFC-7L
MH8S64AQFC-8
MH8S64AQFC-8L
100MHz 64
CL=2/3,AP,CK0,1
CL=3,AP,CK0,1
15
20
08
10
15
20
08
10
12
8F
8D
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22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
Preliminary Spec.
Power Supply
SDA
Some contents are subject to change without notice.
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
PIN FUNCTION
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
CLK0
CKE0 Input
/S0
/RAS,/CAS,/WE Input Combination of /RAS,/CAS,/WE defines basic commands.
A0-11 Input
Input
Input
Master Clock:All other inputs are referenced to the rising
edge of CK
Clock Enable:CKE controls internal clock.When CKE is
low,internal clock for the following cycle is ceased. CKE is
also used to select auto / self refresh. After self refresh
mode is started, CKE E becomes asynchronous input.Self
refresh is maintained as long as CKE is low.
Chip Select: When /S is high,any command means
No Operation.
A0-11 specify the Row/Column Address in conjunction with
BA0,1.The Row Address is specified by A0-11.The Column
Address is specified by A0-8.A10 is also used to indicate
precharge option.When A10 is high at a read / write
command, an auto precharge is performed. When A10 is
high at a precharge command, both banks are precharged.
BA0,1 Input
DQ0-63
DQMB0-7 Input
Vdd,Vss
SCL
Input/Output
Input
Output
Bank Address:BA0,1 is not simply BA.BA specifies the
bank to which a command is applied.BA0,1 must be set
with ACT,PRE,READ,WRITE commands
Data In and Data out are referenced to the rising edge
of CK
Din Mask/Output Disable:When DQMB is high in burst
write.Din for the current cycle is masked.When DQMB is
high in burst read,Dout is disabled at the next but one cycle.
Power Supply for the memory mounted module.
Serial clock for serial PD
Serial data for serial PD
22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
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6
Preliminary Spec.
The MH8S64AQFC provides basic functions,bank(row)activate,burst read / write,
To know the detailed definition of commands please see the command truth table.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
BASIC FUNCTIONS
bank(row)precharge,and auto / self refresh.
Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge.
In addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and
precharge option,respectively.
CK
/S
Chip Select : L=select, H=deselect
/RAS
/CAS
/WE
CKE
A10
Command
Command
Command
Refresh Option @refresh
command
Precharge Option @precharge or read/write
command
define basic commands
Activate(ACT) [/RAS =L, /CAS = /WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read(READ) [/RAS =H,/CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA.First output
data appears after /CAS latency. When A10 =H at this command,the bank is
deactivated after the burst read(auto-precharge,READA).
Write(WRITE) [/RAS =H, /CAS = /WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank is
deactivated after the burst write(auto-precharge,WRITEA).
Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]
PRE command deactivates the active bank indicated by BA. This command also
terminates burst read / write operation. When A10 =H at this command, both banks
are deactivated(precharge all, PREA).
Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]
PEFA command starts auto-refresh cycle. Refresh address including bank address
are generated internally. After this command, the banks are precharged automatically.
ELECTRIC
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7
22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
Preliminary Spec.
Precharge All Bank
Some contents are subject to change without notice.
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
COMMAND TRUTH TABLE
COMMAND
MNEMONIC
CKE
n-1
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
CKE
n
/S
/RAS
/CAS
/WE BA0,1 A10
A11
A0-9
Deselect DESEL H X H X X X X X X
No Operation NOP H X L H H H X X X
Row Adress Entry &
Bank Activate
Single Bank Precharge PRE H X L L H L V L X
Column Address Entry
& Write
Column Address Entry
& Write with Auto-
Precharge
Column Address Entry
& Read
Column Address Entry
& Read with Auto
Precharge
Auto-Refresh REFA H H L L L H X X X
Self-Refresh Entry REFS H L L L L H X X X
Self-Refresh Exit REFSX L H H X X X X X X
Burst Terminate TERM
Mode Register Set
ACT H X L L H H V V V
PREA
WRITE
WRITEA H X L H L L V H V
READ H X L H L H V L V
READA H X L H L H V H V
MRS
H X L L H L X H X
H X L H L L V L V
L H L H H H X X X
H X L H H L X X X
H X L L L L L L
X
X
V
X
X
V
V
V
V
X
X
X
X
X
L
V*1
H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number
NOTE:
1.A7-9 = 0, A0-6 = Mode Address
ELECTRIC
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8
22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
Preliminary Spec.
Some contents are subject to change without notice.
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
Current State /S /RAS /CAS /WE Address
IDLE H X X X X DESEL NOP
L H H H X NOP NOP
L H H L
L H L X
L L H H
L L H L
L L L H X REFA
L L L L
ROW ACTIVE H X X X X DESEL NOP
L H H H X NOP NOP
L H H L BA TBST NOP
L H L H BA,CA,A10 READ/READA
L H L L BA,CA,A10
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA Precharge/Precharge All
L L L H X REFA ILLEGAL
L L L L
READ H X X X X DESEL NOP(Continue Burst to END)
L H H H X NOP NOP(Continue Burst to END)
L H H L
L H L H BA,CA,A10 READ/READA
L H L L BA,CA,A10 WRITE/WRITEA
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA Terminate Burst,Precharge
L L L H X REFA ILLEGAL
L L L L
BA TBST ILLEGAL*2
BA,CA,A10
BA,RA
BA,A10 PRE/PREA NOP*4
Op-Code,
Mode-Add
Op-Code,
Mode-Add
BA
Op-Code,
Mode-Add
Command
READ/WRITE ILLEGAL*2
ACT Bank Active,Latch RA
Auto-Refresh*5
MRS Mode Register Set*5
Begin Read,Latch CA,
Determine Auto-Precharge
WRITE/
WRITEA
MRS ILLEGAL
TBST Terminate Burst
MRS ILLEGAL
Begin Write,Latch CA,
Determine Auto-Precharge
Terminate Burst,Latch CA,
Begin New Read,Determine
Auto-Precharge*3
Terminate Burst,Latch CA,
Begin Write,Determine AutoPrecharge*3
Action
ELECTRIC
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9
22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
Preliminary Spec.
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
MITSUBISHI LSIs
Current State /S /RAS /CAS /WE Address
WRITE H X X X X DESEL NOP(Continue Burst to END)
L H H H X NOP NOP(Continue Burst to END)
L H H L BA TBST Terminate Burst
L H L H BA,CA,A10
L H L L BA,CA,A10
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA Terminate Burst,Precharge
L L L H X REFA ILLEGAL
L L L L
READ with H X X X X DESEL NOP(Continue Burst to END)
AUTO L H H H X NOP NOP(Continue Burst to END)
PRECHARGE L H H L BA TBST ILLEGAL
L H L H BA,CA,A10 READ/READA ILLEGAL
L H L L BA,CA,A10
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
L L L L
WRITE with H X X X X DESEL NOP(Continue Burst to END)
AUTO L H H H X NOP NOP(Continue Burst to END)
PRECHARGE L H H L
L H L H BA,CA,A10 READ/READA ILLEGAL
L H L L BA,CA,A10
L L H H
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
L L L L
Op-Code,
Mode-Add
Op-Code,
Mode-Add
BA
BA,RA
Op-Code,
Mode-Add
Command
Terminate Burst,Latch CA,
READ/READA
WRITE/
WRITEA
MRS ILLEGAL
WRITE/
WRITEA
MRS ILLEGAL
TBST ILLEGAL
WRITE/
WRITEA
ACT Bank Active/ILLEGAL*2
MRS ILLEGAL
Begin Read,Determine AutoPrecharge*3
Terminate Burst,Latch CA,
Begin Write,Determine AutoPrecharge*3
ILLEGAL
ILLEGAL
Action
ELECTRIC
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10
22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
Preliminary Spec.
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
MITSUBISHI LSIs
Current State /S /RAS /CAS /WE Address
PRE - H X X X X DESEL NOP(Idle after tRP)
CHARGING L H H H X NOP NOP(Idle after tRP)
L H H L BA TBST ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA ACT ILLEGAL*2
L L H L BA,A10 PRE/PREA NOP*4(Idle after tRP)
L L L H X REFA ILLEGAL
L L L L
ROW H X X X X DESEL NOP(Row Active after tRCD
ACTIVATING L H H H X NOP NOP(Row Active after tRCD
L H H L BA TBST ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA ACT ILLEGAL*2
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
L L L L
Op-Code,
Mode-Add
Op-Code,
Mode-Add
Command
MRS ILLEGAL
MRS ILLEGAL
Action
WRITE RE- H X X X X DESEL NOP
COVERING L H H H X NOP NOP
L H H L BA TBST ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA ACT ILLEGAL*2
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
L L L L
Op-Code,
Mode-Add
MRS ILLEGAL
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22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
Preliminary Spec.
1. All entries assume that CKE was High during the preceding clock cycle and the current
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
Current State /S /RAS /CAS /WE Address Command Action
RE- H X X X X DESEL NOP(Idle after tRC)
FRESHING L H H H X NOP
L H H L BA TBST ILLEGAL
L H L X BA,CA,A10 READ/WRITE ILLEGAL
L L H H BA,RA ACT ILLEGAL
L L H L BA,A10 PRE/PREA ILLEGAL
L L L H X REFA ILLEGAL
L L L L
MODE H X X X X DESEL NOP(Idle after tRSC)
REGISTER L H H H X NOP NOP(Idle after tRSC)
SETTING L H H L BA TBST ILLEGAL
L H L X BA,CA,A10 READ/WRITE ILLEGAL
L L H H BA,RA ACT ILLEGAL
L L H L BA,A10 PRE/PREA ILLEGAL
L L L H X REFA ILLEGAL
L L L L
Op-Code,
MRS ILLEGAL
Mode-Add
Op-Code,
MRS ILLEGAL
Mode-Add
NOP(Idle after tRC)
ABBREVIATIONS:
H = Hige Level, L = Low Level, X = Don't Care
BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No Operation
NOTES:
clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA,
depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state.May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and / or date-integrity are not guaranteed.
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12
Preliminary Spec.
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE FOR CKE
MITSUBISHI LSIs
Current State
SELF - H X X X X X X
REFRESH*1 L H H X X X X
POWER H X X X X X X
DOWN L H X X X X X
ALL BANKS H H X X X X X
IDLE*2 H L L L L H X
CK
CK
n-1
L H L H H H X
L H L H H L X
L H L H L X X
L H L L X X X
L L X X X X X
L L X X X X X
H L H X X X X
H L L H H H X
H L L H H L X
H L L H L X X
H L L L X X X
n
/RAS /CAS /WE Add
/S
Action
INVALID
Exit Self-Refresh(Idle after tRC)
Exit Self-Refresh(Idle after tRC)
ILLEGAL
ILLEGAL
ILLEGAL
NOP(Maintain Self-Refresh)
INVALID
Exit Power Down to Idle
NOP(Maintain Self-Refresh)
Refer to Function Truth Table
Enter Self-Refresh
Enter Power Down
Enter Power Down
ILLEGAL
ILLEGAL
ILLEGAL
L X X X X X X
ANY STATE H H X X X X X
other than H L X X X X X
listed above L H X X X X X
L L X X X X X
Refer to Current State = Power Down
Refer to Function Truth Table
Begin CK0 Suspend at Next Cycle*3
Exit CK0 Suspend at Next Cycle*3
Maintain CK0 Suspend
ABBREVIATIONS:
H = High Level, L = Low Level, X = Don't Care
NOTES:
1. CKE Low to High transition will re-enable CK and other inputs asynchronously.
A minimum setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only form the All banks idle State.
3. Must be legal command.
22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
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13
Preliminary Spec.
READA
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
SIMPLIFIED STATE DIAGRAM
MITSUBISHI LSIs
SELF
REFRESH
REFS
REFSX
WRITE
SUSPEND
MODE
REGISTER
SET
CLK
SUSPEND
CKEL
WRITE
CKEH
WRITEA READA
MRS
IDLE
ACT
CKEL
CKEH
ROW
ACTIVE
WRITE READ
WRITEA
WRITE
WRITEA
READA
READ
READA
REFA
CKEL
CKEH
READ
AUTO
REFRESH
POWER
DOWN
CKEL
CKEH
READ
SUSPEND
WRITEA
SUSPEND
POWER
APPLIED
CKEL
CKEH
POWER
ON
WRITEA
PRE
PRE
PRE PRE
PRE
CHARGE
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14
CKEL
CKEH
READA
SUSPEND
Automatic Sequence
Command Sequence
22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
Preliminary Spec.
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode
SDRAM is ready for new command.
LENGTH
BURST
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
a SDRAM from damaged or malfunctioning.
1. Apply power and start clock.Attempt to maintain CKE high,DQM0-7 high and NOP
condition at the inputs.
2. Maintain stable power, stable cock, and NOP input conditions for a minimum of 200us.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
register(MRS). The mode register stores these date until the next MRS command, which
may be issued when both banks are in idle state. After tRSC from a MRS command, the
CK
/S
/RAS
/CAS
/WE
BT= 0 BT= 1
1
2
4
8
R
R
R
FP
SEQUENTIAL
INTERLEAVED
V
1
2
4
8
R
R
R
R
LATENCY
MODE
00
CL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0BA1BA0
0 0
/CAS LATENCY
WM
R
R
2
3
R
R
R
R
0 0
LTMODE BT BL
BURST
TYPE
BA0,1 A11-0
BL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0
1
WRITE
MODE
BURST
0
1
SINGLE BIT
R:Reserved for Future Use
FP: Full Page
22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
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15
Preliminary Spec.
Some contents are subject to change without notice.
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
CK
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
Command
Address
DQ
Initial Address
A2 A1 A0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
CL= 3
BL= 4
BL
8
Read
Y
Q0 Q1 Q2 Q3
/CAS Latency Burst Length Burst Length
Burst Type
Column Addressing
Sequential Interleaved
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6
2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5
3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4
4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3
Write
Y
D0 D1
D2
D3
1 0 1
1 1 0
1 1 1
- 0 0
- 0 1
- 1 0
- 1 1
- - 0
- - 1
5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2
6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1
7 0 1 2
0 1 2 3
1 2 3 0
4
2 3 0 1
3 0
0 1
2
1 0
3 4 5 6 3 2 1 0
1 2
7 6 5 4
0 1 2 3
1 0 3 2
2 3 0 1
3 2
0 1
1 0
1 0
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22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
Preliminary Spec.
OPERATION DESCRIPTION
defined by the Burst Type. Minimum delay time of a READ command after an ACT command
command can be issued after (BL + tRP) from the previous READA. In any case, tRCD+BL >
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
BANK ACTIVATE
One of four banks is activated by an ACT command.
An bank is selected by BA0-1. A row is selected by A0-11.
Multiple banks can be active state concurrently by issuing multiple ACT commands.
Minimum activation interval between one bank and another bank is tRRD.
PRECHARGE
An open bank is deactivated by a PRE command.
A bank to be deactivated is designated by BA0-1.
When multiple banks are active, a precharge all command (PREA, PRE + A10=H)
deactivates all of open banks at the same time. BA0-1 are "Don't Care" in this case.
Minimum delay time of an ACT command after a PRE command to the same bank is tRP.
Bank Activation and Precharge All (BL=4, CL=2)
CK
Command
A0-9,11
A10
BA0,1
DQ
ACT
Xa
Xa
00
tRRD
ACT
Xb
Xb
01
tRCD
READ
Yb
0
01
PRE
tRP
1
Qa0 Qa1 Qa2 Qa3
Precharge all
ACT
Xa
Xa
00
READ
A READ command can be issued to any active bank. The start address is specified by A0-8
(x16) . 1st output data is available after the /CAS Latency from the READ. The consecutive
data length is defined by the Burst Length. The address sequence of the burst data is
to the same bank is tRCD.
When A10 is high at a READ command, auto-precharge (READA) is performed. Any
command (READ, WRITE, PRE, ACT, TBST) to the same bank is inhibited till the internal
precharge is complete. The internal precharge starts at the BL after READA. The next ACT
tRASmin must be met.
22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
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17
Preliminary Spec.
Some contents are subject to change without notice.
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
Multi Bank Interleaving READ (BL=4, CL=2)
CK
Command
A0-9, 11
ACT
Xa
tRCD
READ
Ya
ACT
tRCD
Xb
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
READ
Yb
PRE
ACT
tRP
Xa
A10
BA0,1
DQ
CK
Command
A0-9, 11
A10
BA0,1
DQ
00
0
Xb
01
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2
Xa
00
READ with Auto-Precharge (BL=4, CL=2)
ACT
Xa
Xa
00
READ
tRCD tRP
Ya
1
00
BL
Qa0 Qa1 Qa2 Qa3
01
0
0
00
ACT
Xa
00
Qb3
Xa
Xa
00
CK
Command
CL=3
CL=2
Internal precharge starts
Auto-Precharge Timing (READ BL=4)
ACT READ
tRCD
BL
DQ Qa0 Qa1 Qa2 Qa3
DQ
Qa0 Qa1 Qa2 Qa3
Internal precharge starts
ACT
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22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
Preliminary Spec.
WRITE command can be issued to any active bank. The start address is specified by A0-8
performed. Any command (READ, WRITE, PRE, ACT, TBST) to the same bank is inhibited till
previous WRITEA. In any case, tRCD + BL + tWR -1 > tRASmin must be met.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
WRITE
A
(x16). 1st input data is set at the same cycle as the WRITE. The consecutive data length to
be written is defined by the Burst Length. The address sequence of burst data is defined by
the Burst Type. Minimum delay time of a WRITE command after an ACT command to the
same bank is tRCD. From the last input data to the PRE command, the write recovery time
(tWR) is required. When A10 is high at a WRITE command, auto-precharge (WRITEA) is
the internal precharge is complete. The internal precharge starts at tWR after the last input
data cycle. The next ACT command can be issued after (BL + tWR -1 + tRP) from the
WRITE (BL=4)
CK
Command
A0-9, 11
A10
BA0,1
DQ
CK
Command
A0-9, 11
ACT
tRCD BL
Xa
Xa
00
Write
Ya
0
00
Da0 Da1 Da2 Da3
WRITE with Auto-Precharge (BL=4)
ACT
tRCD
Xa
Write
Ya
BL
tWR
PRE
0
ACT
tRP
Xa
Xa
00
ACT
tRP
Xa
A10
BA0,1
DQ
Xa
00
1
00
Da0 Da1 Da2 Da3
Xa
00
tWR
Internal precharge begins
22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
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19
Preliminary Spec.
Burst read oparation can be interrupted by new read of the same or the other bank. Random
Output disable
by DQM
by WRITE
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
BURST INTERRUPTION
[ Read Interrupted by Read ]
column access is allowed READ to READ interval is minimum 1 CK
Read Interrupted by Read (BL=4, CL=2)
CK
MITSUBISHI LSIs
Command
A0-9,11
A10
BA0,1
DQ
READ
Ya
0
00
READ
READ
Yb
Yc
0
0
00
10
Qa0 Qa2 Qb0 Qc0Qa1 Qc1 Qc2
Qc3
[ Read Interrupted by Write ]
Burst read operation can be interrupted by write of any active bank. Random column access
is allowed. In this case, the DQ should be controlled adequately by using the DQMB0-7 to
prevent the bus contention. The output is disabled automatically 1 cycle after WRITE
assertion.
Read Interrupted by Write (BL=4, CL=2)
CK
Command
A0-9,11
A10
BA0,1
DQMB0-7
DQ
ACT
Xa
Xa
00
READ
Ya
0
00
Qa0
Write
Ya
0
00
Da0 Da1 Da2 Da3
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22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
Preliminary Spec.
/CAS Latency.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
[ Read Interrupted by Precharge ]
A burst read operation can be interrupted by precharge of the same bank . Read to PRE
interval is minimum 1 CK. A PRE command output disable latency is equivalent to the
Read Interrupted by Precharge (BL=4)
CK
CL=3
CL=2
Command
DQ
Command
DQ
Command
DQ
Command
DQ
Command
READ PRE
Q0 Q1
READ PRE
Q0 Q1
READ PRE
Q0
READ PRE
Q0 Q2Q1
READ PRE
Q2
DQ
Command
DQ
READ PRE
Q0
Q1
Q0
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22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
Preliminary Spec.
and disable the data output. The terminated bank remains active,READ to TBST interval is
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
[ Read Interrupted by Burst Terminate ]
Similarly to the precharge, burst terminate command can interrupt burst read operation
minimum of 1 CK. A TBSTcommand to output disable latency is equivalent to the /CAS
Latency.
Read Interrupted by Terminate (BL=4)
CK
CL=3
CL=2
Command
DQ
Command
DQ
Command
DQ
Command
DQ
Command
DQ
READ TBST
Q0 Q1
READ
READ TBST
READ
READ
TBST
Q0 Q1
Q0
TBST
Q0 Q1 Q2
TBST
Q0 Q1
Q2
Command
DQ
READ
TBST
Q0
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22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
Preliminary Spec.
Burst write operation can be interrupted by read of any active bank. Random column
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
[ Write Interrupted by Write ]
Burst write operation can be interrupted by new write of any active bank. Random
column access is allowed. WRITE to WRITE interval is minimum 1 CK.
Write Interrupted by Write (BL=4)
CK
Command
A0-9, 11
A10
BA0,1
DQ
Write
Ya
0
00
Da0 Da1 Da2 Db0 Dc0 Dc1
Write
Yb
0
00
Write
Yc
0
10
Dc2 Dc3
[ Write Interrupted by Read ]
access is allowed. WRITE to READ interval is minimum 1 CK. The input data on DQ
at the interrupting READ cycle is "don't care".
Write Interrupted by Read (BL=4, CL=2)
CK
Command
A0-9,11
A10
BA0,1
DQ
ACT
Xa
Xa
00
Write
Ya
0
00
READ
Da1
don't care
Yb
0
00
Qb0
ELECTRIC
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Qb1Da0
Qb2 Qb3
22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
[ Write Interrupted by Precharge ]
Burst write operation can be interrupted by precharge of the same bank. Write
recovery time(tWR) is required from the last data to PRE command. During write
recovery, data inputs must be masked by DQM.
Write Interrupted by Precharge (BL=4)
CK
Command
A0-9,11
A10
BA0,1
DQMB0-7
DQ
ACT
Xa
0
00
Write
Ya
0
00
Da0 Da1
tWR
PRE
0
00
ACT
tRP
Xa
0
00
[ Write Interrupted by Burst Terminate ]
Burst terminate command can terminate burst write operation. In this case, the
write recovery time is not required and the bank remains active.The WRITE to TBST
minimum interval is 1CK.
CK
Command
A0-9,11
A10
BA0,1
DQ
Write Interrupted by Burst Terminate (BL=4)
ACT
Xa
0
00
Write
Ya
0
00
Da0 Da1
TBST
Write
Yb
0
00
Db0 Db1 Db2 Db3
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22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
[ Write with Auto-Precharge interrupted by Write or Read to anotehr Bank ]
Burst write with auto-precharge can be interrupted by write or read toanother bank.
Next ACT command can be issued after (BL+tWR-1+tRP) from the WRITEA. Autoprecharge interrrupted by a command to the same bank is inhibited.
WRITEA Interrupted by WRITE to another bank (BL=4)
CK
Command
A0-9,11
A10
BA0,1
DQ
CK
Command
A0-9,11
A10
Write
Ya
1
00
Da0 Da1
auto-precharge
WRITEA interrupted by READ to another bank (CL=2,BL=4)
Write
Ya
1
Write
BL
Ya
tWR
0
10
Db0 Db1 Db2 Db3
interrupted
Read
BL
Yb
tWR
0
ACT
tRP
Xa
Xa
00
activate
ACT
tRP
Xa
Xa
BA0,1
DQ
00
Da0 Da1
auto-precharge
10
interrupted
00
Db0 Db1 Db2 Db3
activate
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25
22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
Preliminary Spec.
Full page burst length is available for only the sequential burst type. Full page burst
issued. In case of the full page burst , a read or write with auto-precharge command
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
[ Read with Auto-Precharge interrupted by Read to anotehr Bank ]
Burst read with auto-precharge can be interrupted by read toanother bank. Next
ACT command can be issued after (BL+tRP) from the READA. Auto-precharge
interrrupted by a command to the same bank is inhibited.
READA Interrupted by READ to another bank (CL=2,BL=4)
CK
Command
A0-9,11
A10
BA0,1
DQ
Read
Ya
1
00
auto-precharge
Read
BL
Ya
0
10
Qa0 Qa1
interrupted
ACT
tRP
Xa
tWR
Xa
00
Qb0 Qb1 Qb2 Qb3
activate
Full Page Burst
read or write is repeated untill aPrecharge or a Burst Terminate command is
is illegal.
Single Write
When single write mode is set, burst length for write is always one, independently
of Burst Length defined by (A2-0).
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26
22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
Preliminary Spec.
Some contents are subject to change without notice.
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
AUTO REFRESH
Single cycle of auto-refresh is initiated with a REFA(/CS=/RAS=/CAS=L,
/WE=/CKE=H) command. The refresh address is generated internally. 4096 REFA
cycle within 64ms refresh 128Mbit memory cells. The auto-refresh is performed on
4banks concurrently. Before performing an auto-refresh, all banks must be in the
idle state. Auto-refresh to auto-refresh interval is minimum tRFC. Any command
must not be issued before tRFC from the REFA command.
Auto-Refresh
CK
/S
/RAS
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
NOP or DESLECT
/CAS
/WE
CKE
A0-11
BA0,1
minimum tRFC
Auto Refresh on All Banks Auto Refresh on All Banks
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27
22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
Preliminary Spec.
new command
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
SELF REFRESH
Self-refresh mode is entered by issuing a REFS command (/CS=/RAS=/CAS=L,
/WE=H, CKE=L). Once the self-refresh is initiated, it is maintained as log as CKE is
kept low.During the self-refresh mode, CKE is asynchronous and the only enabled
input , all other inputs including CK are disabled and ignored, so that power
consumption due to synchronous inputs is saved. To exit the self-refresh, supplying
stable CK inputs, asserting DESEL or NOP command and then asserting CKE=H.
After tRFC from the 1st CK edge follwing CKE=H, all banks are in the idle state and
a new command can be issued after, but DESEL or NOP commands must be
asserted till then.
Self-Refresh
CK
Stable CK
/S
NOP
/RAS
/CAS
/WE
CKE
A0-11
BA0,1
Self Refresh Entry
Self Refresh Exit
X
00
minimum tRFC
for recovery
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22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
Preliminary Spec.
(ext.CLK)
Some contents are subject to change without notice.
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
CLK SUSPEND and POWER DOWN
CKE controls the internal CLK at the following cycle. Figure below shows how CKE
works. By negating CKE, the next internal CLK is suspended. The purpose of CLK
suspend is power down, output suspend or input suspend. CKE is a synchronous
input except during the self-refresh mode. CLK suspend can be performed either
when the banks are active or idle. A command at the suspended cycle is ignored.
CK
tIH tIS tIH tIS
CKE
int.CLK
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
CK
CKE
Command
CKE
Command
CK
CKE
PRE
ACT
NOP
NOP
Power Down by CKE
Standby Power Down
NOP NOP
Active Power Down
NOP NOP
DQ Suspend by CKE
Command
DQ
Write
D0 D1 D2 D3
29
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READ
Q0 Q1 Q2 Q3
22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
ELECTRIC
Preliminary Spec.
Some contents are subject to change without notice.
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
DQM CONTROL
DQMB0-7 is a dual function signal defined as the data mask for writes and the
output disable for reads. During writes, DQMB0-7 masks input data word by word.
DQMB0-7 to Data In latency is 0.
During reads, DQMB0-7 forces output to Hi-Z word by word. DQMB0-7 to output Hi-Z
latency is 2.
CK
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
DQM Function
Command
DQMB0-7
DQ
Write
D0 D2 D3
masked by DQMB=H
READ
Q0 Q1 Q3
disabled by DQMB=H
ELECTRIC
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30
22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
Preliminary Spec.
ABSOLUTE MAXIMUM RATINGS
mA
RECOMMENDED OPERATING CONDITION
CAPACITANCE
@1MHz
Some contents are subject to change without notice.
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
Symbol Parameter
Vdd
VI
VO
IO
Pd
Topr
Tstg
Supply Voltage
Input Voltage
Output Voltage
Output Current
Power Dissipation
Operating Temperature
Storage Temperature
(Ta=0 ~ 70°C, unless otherwise noted)
Symbol
Vdd
Parameter
Supply Voltage
Condition Ratings Unit
with respect to Vss
with respect to Vss
with respect to Vss
-0.5 ~ 4.6
-0.5 ~ 4.6
-0.5 ~ 4.6
50
Ta=25°C
4
0 ~ 70
-40 ~ 100
Limits
Min. Typ. Max.
3.0
3.3
3.6
V
V
V
W
°C
°C
Unit
V
Vss
VIH
VIL
Note)
1:VIH(max)=5.5V for pulse width less than 10ns.
2.VIL(min)=-1.0 for pulse width less than 10ns.
High-Level Input Voltage all inputs
Low-Level Input Voltage all inputs
Supply Voltage
0
2.0
-0.3
0
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Symbol
CI(A)
CI(C)
CI(K)
CI/O
Parameter
Input Capacitance, address pin
Input Capacitance, /RAS,/CAS,/WE
Input Capacitance, CK pin
Input Capacitance, I/O pin
Test Condition
1.4V bias
200mV swing
Limits(max.)
Vdd+0.3
35
35
35
22
0
0.8
V
V
V
Unit
pF
pF
pF
pF
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22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
ELECTRIC
31
Preliminary Spec.
AVERAGE SUPPLY CURRENT from Vdd
AC OPERATING CONDITIONS AND CHARACTERISTICS
precharge stanby
in power-down mode
precharge stanby current
in non power-down mode
active stanby current
one bank active (discrete)
Limits
(max)
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
(Ta=0 ~70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
MITSUBISHI LSIs
Parameter
operating current
one bank active (discrete)
current
in non power-down mode
burst current
auto-refresh current
self-refresh current
Note)
1:Icc(max) is specified at the output open condition.
2.Input signals are changed one time during 30ns.
Symbol
Icc1
Icc2P
Icc2PS
Icc2N
Icc2NS
Icc3N
Icc3NS
Icc4
Icc5
Icc6
tRC=min.tCLK=min, BL=1,CL=3
CKE=L,tCLK=15ns, /CS>Vcc-0.2V
CKE=CLK=L, /CS>Vcc-0.2V
CKE=H,tCLK=15ns,VIH>Vcc-0.2V,VIL<0.2V
CKE=H,CLK=L,VIH>Vcc-0.2V,VIL<0.2V(fixed)
CKE=H,tCLK=15ns
CKE=H,CLK=L
tCLK=min, BL=4, CL=3,all banks active(discerte)
tRC=min, tCLK=min
CKE <0.2V
Test Condition
-6,-7,-8
-6L,-7L,-8L
-6,-6L
520
8
4
100
60
120
80
640
640
8
3.2
-7,-7L
-8,-8L
480
8
4
100
60
120
80
520
640
8
3.2
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Limits
Symbol Parameter Test Condition
VOH(DC)
VOL(DC)
IOZ Off-stare Output Current
VOH(AC) High-Level Output Voltage(AC) CL=50pF, IOH=-
VOL(AC) Low-Level Output Voltage(AC) CL=50pF, IOL=2mA 0.8 V
High-Level Output Voltage(DC)
Low-Level Output Voltage(DC)
Ii
Input Current
IOH=-2mA
IOL=2mA
Q floating VO=0 ~ Vdd -10 10 uA
2mA
VIH=0 ~ Vdd+0.3V
Min. Max.
2.4 V
2 V
-40
Unit
0.4 V
uA
40
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32
22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
Preliminary Spec.
AC TIMING REQUIREMENTS
(SDRAM Component)
tSRX
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Input Pulse Levels: 0.8V to 2.0V
Input Timing Measurement Level: 1.4V
Limits
Symbol Parameter
-6,-6L
Min. Max.
-7,-7L
Min. Max.
MITSUBISHI LSIs
-8,-8L
Min. Max.
Unit
tCLK
tCH CK High pulse width 3
tCL CK Low pilse width 3 ns
tT Transition time of CK 1 10 ns
tIS Input Setup time(all inputs) 2 ns
tIH Input Hold time(all inputs) 1 ns
tRC Row cycle time 70 ns
tRCD Row to Column Delay 20 ns
tRAS Row Active time 50 100K ns
tRP Row Precharge time 20 ns
tWR Write Recovery time 12 ns
tRRD
tRSC Mode Register Set Cycle time 10 ns
tPDE Power Down Exit time 10 ns10
tREF Refresh Interval time 64 ms
CK cycle time
Act to Act Deley time
Self Refresh Exit time 10 ns
CL=2
CL=3
10
7.5
2.5
2.5
1 10
1.5
0.8
67.5
20
45 100K
20
12
15
10
7.5
7.5
64
10
10 10 ns
20 ns
13
3
3
1 10
2
1
70
20
50 100K
20
12
20
10
10
ns
ns
64
CK
Signal
ELECTRIC
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33
1.4V
1.4V
Any AC timing is
referenced to the input
signal crossing
through 1.4V.
22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
Preliminary Spec.
1.4V
1.4V
SWITCHING CHARACTERISTICS
(SDRAM Component)
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise note3)
Limits
Symbol Parameter
Min.
-6
Max.
-7
Min.
Max.
MITSUBISHI LSIs
-8
Unit
Min. Max.
tAC
tOH
Access time from CK
Output Hold time
from CK
tOLZ
tOHZ
Note)
1 If clock rising time is longer than 1ns,(tT/2-0.5)ns should be added to parameter.
Delay time, output low
impedance from CK
Delay time, output high
impedance from CK
Output Load Condition
VOUT
50pF
CL=2
CL=3
CL=2
6
5.4
3
2.7
0
2.7 5.4
CK
3
0
3 6
6
6
7
6
ns
ns
3 ns
3 ns3CL=3
0 ns
3 ns6
1.4V
CK
DQ
tOLZ
tAC tOH
ELECTRIC
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34
Output Timing
Measurement
Reference Point
tOHZ
DQ
1.4V
22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
Preliminary Spec.
Burst Write (single bank) @BL=4
/WE
Some contents are subject to change without notice.
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
/RAS
/CAS
CKE
DQM
A0-8
A10
tRAS
tRCD
tWR
X
X
Y
tRP
tRCD
X
X
Y
A9,11
BA0,1
DQ
X
0
ACT#0 WRITE#0 PRE#0 ACT#0 WRITE#0
0 0
D0 D0 D0 D0
X
0
Italic parameter indicates minimum case
0
D0 D0 D0 D0
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35
22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
Preliminary Spec.
Burst Write (multi bank) @BL=4
/WE
Some contents are subject to change without notice.
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
/CS
/RAS
/CAS
CKE
DQM
A0-8
A10
tRRD
tRAS
tRCD
tWR
X
X
Y
X
X
Y
tRP
tWR
tRRD
tRCD
X
X
Y
X
X
A9,11
BA0,1
DQ
X
0
ACT#0 WRITE#0 PRE#0 ACT#0 WRITE#0
X
0 1
1
D0 D0 D0 D0
ACT#1 WRITE#1 PRE#1
0
D1 D1 D1 D1
Italic parameter indicates minimum case
X
0
1
ACT#2
X
0
2
D0 D0 D0 D0
ELECTRIC
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36
22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
Preliminary Spec.
Burst Read (single bank) @BL=4 CL=3
/WE
Some contents are subject to change without notice.
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
/RAS
/CAS
CKE
DQM
A0-7
A10
tRAS
tRCD
DQM read latency =2
X
X
Y
tRP
tRCD
X
X
Y
A8,9,11
BA0,1
DQ
X
0
ACT#0 READ#0 PRE#0 ACT#0 READ#0
0 0
CL=3
Q0 Q0 Q0 Q0
READ to PRE ≥BL allows full data out
X
0
Italic parameter indicates minimum case
0
ELECTRIC
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37
Q0 Q0
22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
Preliminary Spec.
Burst Read (multiple bank) @BL=4 CL=3
/WE
Some contents are subject to change without notice.
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
tRC
/CS
/RAS
/CAS
CKE
DQM
A0-8
A10
X
X
tRRD
tRCD
tRRD
tRAS tRP
tRCD
DQM read latency =2
Y
X
X
Y
X
X
Y
X
X
A9,11
BA0,1
DQ
X
0
ACT#0 READ#0 PRE#0 ACT#0 READ#0
X
0 0
1
CL=3
ACT#1
1
CL=3
Q0 Q0 Q0 Q0
READ#1 PRE#1 ACT#2
Italic parameter indicates minimum case
X
0
Q1 Q1 Q1 Q1
X
21
0
ELECTRIC
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38
Q0
22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
Preliminary Spec.
Burst Write (multi bank) with Auto-Precharge @BL=4
/WE
Some contents are subject to change without notice.
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
tRRD
/RAS
tRCD
/CAS
BL-1+ tWR + tRP
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
tRRD
tRCD
BL-1+ tWR + tRP
tRCD
CKE
DQM
A0-8
A10
A9,11
BA0,1
DQ
X
X
X
0
ACT#0 WRITE#0 with
ACT#1 WRITE#1 with
Y
X
X
X
0 1
1
D0 D0 D0 D0
AutoPrecharge
Y X
D1 D1 D1 D1
AutoPrecharge
Y
X
X
0
ACT#0 WRITE#0
0
D0 D0 D0 D0
X
X
X
1
ACT#1 WRITE#1
Y
1
D1
Italic parameter indicates minimum case
ELECTRIC
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39
22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
Preliminary Spec.
Burst Read (multiple bank) with Auto-Precharge @BL=4 CL=3
/WE
Some contents are subject to change without notice.
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
tRRD
/RAS
tRCD
/CAS
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
tRRD
tRCD
BL+tRP
BL+tRP
tRCD
CKE
DQM
A0-8
A10
A9,11
BA0,1
DQ
DQM read latency =2
X
X
X
0
ACT#0 READ#0 with
ACT#1
Y
X
X
X
0
1
CL=3
Auto-Precharge
Y
1
CL=3
Q0 Q0 Q0 Q0
READ#1 with
Auto-Precharge
X
X
X
0
Q1 Q1 Q1 Q1
ACT#0 READ#0
Y
0
X
X
X
1
CL=3
ACT#1
Q0
Y
1
Q0
Italic parameter indicates minimum case
ELECTRIC
40
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22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
Preliminary Spec.
Page Mode Burst Write (multi bank) @BL=4
/WE
Some contents are subject to change without notice.
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
CKE
DQM
A0-8
A10
A9,11
BA0,1
DQ
X
X
X
0
ACT#0 WRITE#0 WRITE#0
Y
X
X
X
0 0
1
D0 D0 D0 D0
ACT#1
Y Y
D0 D0 D0 D0 D0 D0 D0
WRITE#0
Y
1
D1 D1 D1 D1
WRITE#1
0
ELECTRIC
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41
Italic parameter indicates minimum case
22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
Preliminary Spec.
Page Mode Burst Read (multi bank) @BL=4 CL=3
/WE
Some contents are subject to change without notice.
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
CKE
DQM
A0-8
A10
A9,11
BA0,1
DQ
DQM read latency=2
X
X
X
0
ACT#0 READ#0 READ#0
Y
X
X
X
0 0
1
CL=3 CL=3 CL=3
ACT#1
Y Y
Q0 Q0 Q0
Q0
READ#0
Y
1
Q0 Q0 Q0 Q0
READ#1
0
Q1 Q1 Q1 Q1
ELECTRIC
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42
Italic parameter indicates minimum case
22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
Preliminary Spec.
Write Interrupted by Write / Read @BL=4
/WE
Some contents are subject to change without notice.
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
tCCD
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
CKE
DQM
A0-8
A10
A9,11
BA0,1
DQ
X
X
X
0
ACT#0 WRITE#0
ACT#1
Y
X
X
X
0
1
D0 D0 D0 D0
Y Y
0 0 0
D0 D0 D1 D1 Q0 Q0 Q0
WRITE#0 READ#0
WRITE#0
Y
1
WRITE#1
Y
CL=3
Q0
Burst Write can be interrupted by Write or Read of any active bank.
( / 55 )
Italic parameter indicates minimum case
22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
ELECTRIC
43
Preliminary Spec.
Read Interrupted by Read / Write @BL=4 CL=3
/WE
Some contents are subject to change without notice.
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
CKE
DQM
A0-8
A10
A9,11
BA0,1
DQ
DQM read latency=2
X
X
X
0
ACT#0 READ#0 WRITE#0
ACT#1
Y
X
X
X
0 0
1
Y Y
Y
0
Q0 Q0 Q0
Q0
READ#0 READ#0
READ#0
Y
1
READ#1
Y
0
Q0 Q0 Q1 Q1
blank to prevent bus contention
0
Q0 D0 D0
Burst Read can be interrupted by Read or Write of any active bank.
ELECTRIC
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44
Italic parameter indicates minimum case
22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
Preliminary Spec.
Write Interrupted by Precharge @BL=4
/WE
Some contents are subject to change without notice.
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
CKE
DQM
A0-8
A10
A9,11
BA0,1
DQ
X
X
X
0
ACT#0 WRITE#0
ACT#1
Y
X
X
X
0
1
D0 D0 D0 D0
Y
0
1
PRE#1
1 1
D1 D1 D1 D1 D1
PRE#0
WRITE#1
X
X
X
1
ACT#1 WRITE#1
Y
Burst Write is not interrupted
by Precharge of the other bank.
ELECTRIC
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45
Burst Write is interrupted by
Precharge of the same bank.
Italic parameter indicates minimum case
22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
Preliminary Spec.
Read Interrupted by Precharge @BL=4 CL=3
/WE
Some contents are subject to change without notice.
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
/RAS
/CAS
CKE
DQM
A0-8
A10
X
X
tRRD
tRCD
tRP
tRCD
DQM read latency=2
Y
X
X
Y
X
X
Y
A9,11
BA0,1
DQ
X
0
ACT#0 READ#0
X
0
1
ACT#1
Burst Read is not interrupted
by Precharge of the other bank.
X
1
Q0 Q0 Q0
Q0
PRE#0
READ#1 ACT#1 READ#1
0
1
Q1 Q1
PRE#1
Burst Read is interrupted
by Precharge of the same bank.
Italic parameter indicates minimum case
1
1
22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
ELECTRIC
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46
Preliminary Spec.
Mode Register Setting
/WE
Some contents are subject to change without notice.
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
/CS
/RAS
/CAS
CKE
DQM
A0-8
A10
tRC
M
tRSC
tRCD
X
X
Y
A9,11
BA0,1
DQ
Auto-Ref (last of 8 cycles)
Mode
Register
Setting
ELECTRIC
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47
X
0
0
ACT#0 WRITE#0
Italic parameter indicates minimum case
0
D0
D0 D0 D0
22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
Preliminary Spec.
Auto-Refresh @BL=4
/WE
After tRC from Auto-Refresh,
Some contents are subject to change without notice.
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
tRC
/RAS
/CAS
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
tRCD
CKE
DQM
A0-8
A10
A9,11
BA0,1
DQ
Auto-Refresh
X
X
X
0
ACT#0 WRITE#0
Y
0
D0
D0 D0 D0
Before Auto-Refresh,
all banks must be idle state.
all banks are idle state.
ELECTRIC
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48
Italic parameter indicates minimum case
22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
Preliminary Spec.
Self-Refresh
/WE
Some contents are subject to change without notice.
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
CLK can be stopped
/CS
/RAS
/CAS
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
tRC
CKE
DQM
A0-8
A10
A9,11
BA0,1
DQ
tSRX
CKE must be low to maintain Self-Refresh
X
X
X
0
Self-Refresh Entry
Before Self-Refresh Entry,
all banks must be idle state.
After tRC from Self-Refresh Exit,
all banks are idle state.
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Self-Refresh Exit ACT#0
Italic parameter indicates minimum case
22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
Preliminary Spec.
DQM Write Mask @BL=4
/WE
Some contents are subject to change without notice.
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
/RAS
tRCD
/CAS
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
CKE
DQM
A0-8
A10
A9,11
BA0,1
DQ
X
X
X
0
ACT#0 WRITE#0 WRITE#0 WRITE#0
Y
0 0
D0 D0 D0 D0
Y
masked masked
Y
0
D0 D0 D0
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Italic parameter indicates minimum case
22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
Preliminary Spec.
DQM Read Mask @BL=4 CL=3
/WE
Some contents are subject to change without notice.
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
/RAS
tRCD
/CAS
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
CKE
DQM
A0-8
A10
A9,11
BA0,1
DQ
DQM read latency=2
X
X
X
0
ACT#0 READ#0 READ#0 READ#0
Y
0 0
Q0 Q0 Q0 Q0
Y
Y
0
masked
masked
Q0 Q0 Q0
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Italic parameter indicates minimum case
22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
Preliminary Spec.
Power Down
/WE
Some contents are subject to change without notice.
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
/RAS
/CAS
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
CKE
DQM
A0-8
A10
A9,11
BA0,1
DQ
Standby Power Down
CKE latency=1
X
X
X
0
Precharge All ACT#0
Active Power Down
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52
Italic parameter indicates minimum case
22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
Preliminary Spec.
CLK Suspend @BL=4 CL=3
/WE
Some contents are subject to change without notice.
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
/RAS
tRCD
/CAS
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
CKE
DQM
A0-8
A10
A9,11
BA0,1
DQ
CKE latency=1 CKE latency=1
X
X
X
0
ACT#0 WRITE#0 READ#0
Y
0 0
D0 D0 D0D0
Y
Q0 Q0 Q0 Q0
CLK suspendedCLK suspended
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53
Italic parameter indicates minimum case
22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
Preliminary Spec.
Some contents are subject to change without notice.
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
OUTLINE
31.75
20.00
4.00
6.00
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
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54
22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
Preliminary Spec.
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products
1.These materials are intended as a reference to assist our customers in the selection of the
a device or system that is used under circumstances in which human life is potentially at stake.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
Keep safety first in your circuit designs!
better and more reliable, but there is always the possibility that trouble may occur with them.
Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with
appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
Mitsubishi semiconductor product best suited to the customer's application; they do not
convey any license under any intellectual property rights, or any other rights, belonging to
Mitsubishi Electric Corporation or a third party.
2.Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement
of any third-party's rights, originating in the use of any product data, diagrams, charts,
programs, algorithms, or circuit application examples contained in these materials.
3.All information contained in these materials, including product data, diagrams, charts,
programs and algorithms represents information on products at the time of publication of
these materials, and are subject to change by Mitsubishi Electric Corporation without notice
due to product improvements or other reasons. It is therefore recommended that customers
contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other
loss rising from these inaccuracies or errors.
Please also pay attention to information published by Mitsubishi Electric Corporation by
various means, including the Mitsubishi Semiconductor home page
(http://www.mitsubishichips.com).
4.When using any or all of the information contained in these materials, including product
data, diagrams, charts, programs and algorithms, please be sure to evaluate all information
as a total system before making a final decision on the applicability of the information and
products.
Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other
loss resulting from the information contained herein.
5.Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in
Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor when considering the use of a product contained herein for any specific
purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace,
nuclear, or undersea repeater use.
6.The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or
reproduce in whole or in part these materials.
7.If these products or technologies are subject to the Japanese export control restrictions, they
must be exported under a license from the Japanese government and cannot be imported
into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or
the country of destination is prohibited.
8.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor for further details on these materials or the products contained therein.
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55
22.Sep.2000MIT-DS-0374-0.3 MITSUBISHI
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