Mitsubishi M5M4V4405CJ-6S, M5M4V4405CTP-7S, M5M4V4405CTP-7, M5M4V4405CTP-6, M5M4V4405CJ-7S Datasheet
...
This is a family of 1048576-word by 4-bit dynamic RAMS,
fabricated with the high performance CMOS process,and is ideal
for large-capacity memory systems where high speed, low power
dissipation , and low costs are essential.
The use of quadruple-layer polysilicon process combined with
silicide technology and a single-transistor dynamic storage stacked
capacitor cell provide high circuit density at reduced costs.
Multiplexed address inputs permit both a reduction in pins and an
increase in system densities.
Self or extended refresh current is low enough for battery
back-up application.
MITSUBISHI LSIs
Lap top personal computer,Solid state disc, Microcomputer
memory, Refresh memory for CRT
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
EDO (HYPER PAGE MODE) 4194304-BIT (1048576-WORD BY 4-BIT) DYNAMIC RAM
DESCRIPTION
FEATURES
access
time
(max.ns)
Address
access
time
(max.ns)
(max.ns)
*
OE
access
time
Cycle
time
(min.ns)
Power
dissipa-
tion
(typ.mW)
RAS CAS
Type name
M5M4V4405CXX-6, -6S
M5M4V4405CXX-7, -7S
XX=J, TP
access
time
(max.ns)
60 15 30 110 26415
70 20 35 130 23120
Standard 26 pin SOJ, 26 pin TSOP(II)
Single 3.3V±0.3V supply
Low stand-by power dissipation
CMOS lnput level .................................................1.8mW(Max)*
CMOS lnput level ................................................180µW(Max)
Low operating power dissipation
M5M4V4405Cxx-6, -6S .....................................288.0mW (Max)
M5M4V4405Cxx-7, -7S ....................................252.0mW (Max)
Self refresh capabiility
*
Self refresh current ..............................................100µA(max)
Extended refresh capability*
Extended refresh current ....................................100µA(max)
Hyper-page mode (1024-bit random access), Read-modify- write,
RAS-only refresh CAS before RAS refresh, Hidden refresh, CBR
self refresh(-6S,-7S) capabilities.
Early-write mode and OE and W to control output buffer impedance
1024 refresh cycles every 16.4ms (A0~A9)
1024refresh cycle every128ms (A0~A9)
*: Applicable to self refresh version (M5M4V4405Cxx-6S,-7S:
option) only
M5M4V4405CJ,TP-6,-7,-6S,-7S
PIN CONFIGURATION (TOP VIEW)
DQ1
1
DQ2
2
W
3
4
RAS
A9
5
9
A0
10
A1
A2
11
A3
12
13
VCC
Outline 26P0J (300mil SOJ)
DQ1
1
DQ2
2
W
3
4
RAS
A9
5
9
A0
10
A1
A2
11
A3
12
13
VCC
26
VSS
25
DQ4
24
DQ3
23
CAS
OE
22
A8
18
A7
17
A6A516
15
A4
14
26
VSS
25
DQ4
24
DQ3
23
CAS
22
OE
A8
18
A7
17
16
A6
15
A5
A4
14
APPLICATION
PIN DESCRIPTION
Pin name
A0~A9
DQ1~DQ4
RAS
CAS
W
OE
VCC
VSS
Address inputs
Data inputs / outputs
Row address strobe input
Column address strobe input
Write control input
Output enable input
Power supply (+3.3V)
Ground (0V)
1
Function
Outline 26P3Z-E (300mil TSOP)
M5M4V4405CJ,TP-6,-7,-6S,-7S
In addition to normal read, write, and read-modify-write operations
the M5M4V4405CJ,TP provide, a number of other functions, e.g.,
Hyper Page mode, RAS-only refresh, and delayed-write. The input
conditions for each are shown in Table 1.
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
FUNCTION
Table 1 Input conditions for each mode
Operation
Read
Write (Early write)
Write (Delayed write)
Read-modify-write
RAS-only refresh
Hidden refresh
CAS before RAS refresh
Self refresh
*
Stand-by
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open
RAS
ACT
ACT
ACT
ACT
ACT
ACT
ACT
CAS
ACT
ACT
ACT
ACT
NAC
ACT
ACT
ACT ACT NAC DNC DNC DNC DNC OPN YES
NAC
DNC
W
NAC
ACT
ACT
ACT
DNC
DNC
NAC
DNC
Inputs
OE
ACT
DNC
NAC
ACT
DNC
ACT
DNC
DNC
Row
address address
APD
APD
APD
APD
APD
DNC
DNC
DNC
Column
APD
APD
AP
D
APD
DNC
DNC
DNC
DNC
Input/Output
Input Output
OPN
APD
APD
APD
DNC
OPN
DNC
DNC
VLD
OPN
IVD
VLD
OPN
VLD
OPN
OPN
MITSUBISHI LSIs
Refresh Remark
YES
Hyper
YES
Page
mode
YES
identical
YES
YES
YES
YES
NO
BLOCK DIAGRAM
COLUMN ADDRESS
STROBE INPUT
ROW ADDRESS
STROBE INPUT
WRITE CONTROL
INPUT
ADDRESS INPUTS
2
CAS
RAS
W
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
ROW &
COLUMN
ADDRESS
BUFFER
A0~
A9
A0 ~ A9
ROW
DECODER
CLOCK GENERATOR
CIRCUIT
COLUMN DECODER
SENSE REFRESH
AMPLIFER & I /O CONTROL
MEMORY CELL
(4,194,304 BITS)
(4)
DATA IN
BUFFERS
(4)
DATA OUT
BUFFERS
VCC (3.3V)
VSS (0V)
DQ1
DATA
DQ2
INPUTS /
DQ3
OUTPUTS
DQ4
OUTPUT
OE
ENABLE
INPUT
M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
VI
VO
IO
Pd
Topr
Tstg
Supply voltage
Input voltage
Output voltage
Output current
Power dissipation
Operating temperature
Storage temperature
Parameter
With respect to VSS
Ta=25
RECOMMENDED OPERATING CONDITIONS (Ta=0~70˚C, unless otherwise noted) (Note 1)
Symbol
VCC
VSS
VIH
VIL
Note 1 : All voltage values are with respect to VSS.
Supply voltage
Supply voltage
High-level input voltage, all inputs
Low-level input voltage
Parameter
DQ1~DQ4
others
Min Nom Max
3.0
0
2.0
-0.3
C
Limits
3.3
Conditions
0
3.6
0
VCC+0.3
0.8-0.3
0.8
Unit
V
V
V
V
V
MITSUBISHI LSIs
Ratings
-0.5 ~ 4.6
-0.5 ~ 4.6
-0.5 ~ 4.6
50
1000
0 ~ 70
-65 ~ 150
Unit
V
V
V
mA
mW
C
C
ELECTRICAL CHARACTERISTICS
Symbol Parameter Test conditions
VOH
VOL
IOZ
II
ICC1 (AV)
ICC2 (AV)
ICC3 (AV)
ICC4(AV)
ICC6(AV)
High-level output voltage
Low-level output voltage
Off-state output current
Input current
Average supply current
from VCC
operating
(Note 3,4,5)
Supply current from VcC ,
stand-by
(Note 6)
Average supply current
from VCC
refreshing
Average supply current
from VCC
Hyper-Page-Mode
(Note 3,5)
(Note 3,4,5)
Average supply current
from VCC, CAS before
RAS refresh mode
(Note 3)
(Ta=0~70˚C, VCC=3.3V± 0.3V, VsS=0V, unless otherwise noted) (Note 2)
Min Typ Max
2.4
0
-5
-5
M5M4V4405C-6,-6S
M5M4V4405C-7,-7S
IOH=-2mA
IOL=2mA
Q floating, 0V≤VOUT≤VCC
0V≤VIN≤VCC+0.3V, Other inputs pins=0V
RAS, CAS cycling
tRC=tWC=min.
output open
RAS=CAS =VIH, output open
M5M4V4405C
M5M4V4405C(S)
M5M4V4405C-6,-6S
M5M4V4405C-7,-7S
M5M4V4405C-6,-6S
M5M4V4405C-7,-7S
M5M4V4405C-6,-6S
M5M4V4405C-7,-7S
RAS=CAS≥VCC -0.2V
output open
RAS cycling, CAS= VIH
tRC=min.
output open
RAS=VIL, CAS cycling
tPC=min.
output open
CAS before RAS refresh cycling
tRC=min.
output open
RAS cycling CAS≤0.2V or CAS
before RAS refresh cycling
RAS≤0.2V or ≥VCC-0.2V
CAS≤0.2V or ≥VCC-0.2V
ICC8(AV)*
Average supply current
from VCC
Extended-Refresh cycle
(Note 6)
W≤0.2V (Except for RAS falling
edge) or ≥VCC-0.2V
OE≤0.2V or ≥VCC-0.2V
A0~A9 ≤0.2V or≥VCC-0.2V
DQ=open
tRC=125µs, tRAS=tRAS min ~1µs
ICC9(AV)*
Note 2: Current flowing into an IC is positive, out is negative.
3: ICC1 (AV), ICC3 (AV), ICC4 (AV) and ICC6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
4: ICC1 (AV) and ICC4 (AV) are dependent on output loading. Specified values are obtained with the output open.
5: Column Addres can be changed once or less while RAS=VIL and CAS=VIH.
3
Average supply current
from VCC
Self-Refresh cycle
(Note 6)
M5M4V4405C(S)
RAS=CAS≤0.2V
output open
Limits
Vcc
0.4
5
5
80
70
2
0.5
0.05
80
70
80
70
70
60
100
100
Unit
V
V
µA
µA
mA
mA
*
mA
mA
mA
µA
µA
MITSUBISHI LSIs
Test conditions
15
303360
20
353870
Parameter
CAC
RAC
Parameter
5
7
7
(Note 12)
(Note 7)
15
20515
15
20
20
(Note 12)
151520
20
Å@
(Note 7)
M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
CAPACITANCE
Symbol
CI (A)
CI (CLK)
CI / O
(Ta=0~70˚C, VCC=3.3V±0.3V, Vss=0V, unless otherwise noted)
Input capacitance, address inputs
Input capacitance, clock inputs
Input/Output capacitance, data ports
VI=VSS
f=1MHz
VI=25mVrms
Limits
Min Max
Typ
Unit
pF
pF
pF
SWITCHING CHARACTERISTICS (Ta=0~70˚C, VCC=3.3V±0.3V, Vss=0V, unless otherwise noted, see notes 6,14,15)
Symbol
M5M4V4405C-6,-6S M5M4V4405C-7,-7S
Min Max Min Max
t
t
tAA
tCPA
tOEA
tOHC
tOHR
tCLZ
tOEZ
tWEZ
tOFF
tREZ
Note 6: An initial pause of 200µs is required after power-up followed by a minimum of eight initialization cycles (RAS only refresh or CAS before RAS refresh
cycles)ÅDÅ@Å@Å@Å@Å@Å@Å@Å@Å@Å@Å@Å@Å@ Å@
Note the RAS may be cycled during the initial pause. And eight initialization cycles are required after prolonged periods (greater than tREF(max)) of
RAS inactivity before proper device operation is achieved.
7: Measured with a load circuit equivalent to 100pF, VOH=2.4V(IOH=-2mA) and VOL=0.4V(IOL=2mA).
The reference levels for measuring of output signals are 2.0V(VOH) and 0.8V(VOL).
8: Assumes that tRCD≥tRCD(max) and tASC≥tASC(max) and tCP≥tCP(max).
9: Assumes that tRCD≤tRCD(max) and tRAD≤tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC will
increase by amount that tRCD exceeds the value shown.
10: Assumes that tRAD≥tRAD(max) and tASC≤tASC(max).
11: Assumes that tCP≤tCP(max) and tASC≥tASC(max).
12: tOEZ (max), tWEZ(max), tOFF(max) and tREZ(max) defines the time at which the output achieves the high impedance state(IOUT≤ | ±10µA |) and is
not reference to VOH(min) or VOL(max).
13: Output is disabled after both RAS and CAS go to high.
Access time from CAS
Access time from RAS
Column address access time
Access time from CAS precharge
Access time from OE
Output hold time from CAS
Output hold time from RAS
Output low impedance time from CAS low
Output disable time after OE high
Output disable time after WE low
Output disable time after CAS high
Output disable time after RAS high
(Note 7,8)
(Note 7,9)
(Note 7,10)
(Note 7,11)
(Note 13)
(Note 12,13)
(Note 12,13)
5
5
Limits
Unit
ns
ns
ns
ns
ns
5
5
5
ns
ns
ns
ns
ns
ns
ns
4
MITSUBISHI LSIs
Parameter
Parameter
(Note 21)
(Note 16)
(Note 17)
(Note 18)
16.445300401350
205101510
10
(Note 19)
(Note 20)
(Note 19)
(Note 20)
15
15
16.450350501350
205131510
10
20
20
RCDtCRPtRPCtCPNtRAD
RAHtCAH
CDD
(Note 22)
(Note 22)
RC
CSHtRSHtRCStRCHtRRHtRAL
CAL
(Note 20)
15
20
RDD
Transition time
M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
TIMING REQUIREMENTS
(For Read, Write, Read-Modify-Write, Refresh, and Hyper-Page Mode Cycles)
(Ta=0~70˚C, VCC = 3.3V±0.3V, VSS =0V, unless otherwise noted, see notes 14,15)
128
Limits
Unit
ms
128
ms
ns
ns
ns
ns
ns
ns
0
0
ns
ns
ns
ns
0
0
ns
ns
ns
ns
ns
1
ns
Symbol
M5M4V4405C-6,-6S M5M4V4405C-7,-7S
Min Max Min Max
tREF
tREF
tRP
t
Refresh cycle time
Refresh cycle time
*
RAS high pulse width
Delay time, RAS low to CAS low
Delay time, CAS high to RAS low
Delay time, RAS high to CAS low
CAS high pulse width
Column address delay time from RAS low
tASR
tASC
t
Row address setup time before RAS low
Column address setup time before CAS low
Row address hold time after RAS low
0
0
Column address hold time after CAS low
tDZC
tDZO
t
t
tODD
tT
Note 14: The timing requirements are assumed tT =2ns.
Å@ 15: VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
Å@ 16: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is
controlled exclusively by tCAC or tAA.
Å@ 17: tRAD(max) is specified as a reference point only. If tRAD ≥ tRAD(max) and tASC ≤ tASC(max), access time is controlled exclusively by tAA.
Å@ 18: tASC(max) is specified as a reference point only. If tRCD ≥ tRCD(max) and tASC ≥ tASC(max), access time is controlled exclusively by tCAC.
Å@ 19: Either tDZC or tDZO must be satisfied.
Å@ 20: Either tRDD or tCDD or tODD must be satisfied.
Å@ 21: tT is measured between VIH(min) and VIL(max).
Delay time, data to CAS low
Delay time, data to OE low
Delay time, RAS high to data
Delay time, CAS high to data
Delay time, OE high to data
0
0
1
Read and Refresh Cycles
Symbol
t
tRAS
tCAS
t
t
tORH
tOCH
Note 22: Either tRCH or tRRH must be satisfied for a read cycle.
5
Read cycle time
RAS low pulse width
CAS low pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Read Setup time before CAS low
Read hold time after CAS high
Read hold time after RAS high
Column address to RAS hold time
Column address to CAS hold time
RAS hold time after OE low
CAS hold time after OE low
M5M4V4405C-6,-6S M5M4V4405C-7,-7S
Min Max Min Max
Limits
110
60
15
0
30
10
48
10000
10000
0
0
130
70
13
55
20
0
35
10000
10000
0
0
18 23
15
20
15 20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MITSUBISHI LSIs
Parameter
Parameter
(Note 24)
CSHtRSH
DH
CSHtRSHtRCS
M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
Write Cycle (Early Write and Delayed Write)
10000
10000
10000
10000
Limits
Limits
130
70
13
55
13
13
13
13
161
107
57
107
57
0
42
92
57
13
13
0
0
10000
10000
10000
10000
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns 15 20
Symbol
M5M4V4405C-6,-6S M5M4V4405C-7,-7S
Min Max Min Max
tWC
tRAS
tCAS
t
tWCS
tWCH
tCWL
tRWL
tWP
tDS
t
Write cycle time
RAS low pulse width
CAS low pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Write setup time before CAS low
Write hold time after CAS low
CAS hold time after W low
RAS hold time after W low
Write pulse width
Data setup time before CAS low or W low
Data hold time after CAS low or W low
110
60
10
48
10
0
10
10
10
10
0
10
Read-Write and Read-Modify-Write Cycles
Symbol
tRWC
tRAS
tCAS
t
Read write/read modify write cycle time
RAS low pulse width
CAS low pulse width
CAS hold time after RAS low
(Note 23)
RAS hold time after CAS low
Read setup time before0 CAS low
tCWD
tRWD
tAWD
tOEH
Note 23: tRWC is specified as tRWC(min )=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT.
Å@ 24: tWCS, tCWD, tRWD, tAWD, and tCPWD are specified as reference points only. If tWCS≥tWCS(min) the cycle is an early write cycle and the DQ pins will
remain high impedance throughout the entire cycle. IftCWD≥tCWD(min), tRWD≥tRWD(min), tAWD≥tAWD(min) and tCPWD≥tCPWD (min) (for fast page
mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above
condition (delayed write) of the DQ (at access time and until CAS or OE goes back to VIH ) is indeterminate.
Delay time, CAS low to W low
Delay time, RAS low to W low
Delay time, address to W low
OE hold time after W low
(Note 24)
(Note 24)
(Note 24)
M5M4V4405C-6,-6S M5M4V4405C-7,-7S
Min Max Min Max
133
89
44
89
44
0
32
77
47
6
M5M4V4405CJ,TP-6,-7,-6S,-7S
28:
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
Hyper page Mode Cycle
(Read, Early Write, Read-Write, Read-Modify-Write Cycle, Read Write Mix Cycle, Hi-Z control by
100000
16
Limits
Symbol
tHPC
tHPRWC
tDOH
tRAS
tCP
tCPRH
tCPWD
tCHOL
tOEPE
tWPE
tHCWD
tHAWD
tHPWD
tHCOD
tHAOD
tHPOD
Note 25:
Hyper page mode read/write cycle time
Hyper Page Mode read write / read modify write cycle time
Output hold time from CAS low
RAS low pulse width for read or write cycle
CAS high pulse width
RAS hold time after CAS precharge
Delay time, CAS precharge to W low
Hold time to maintain the data Hi-Z until CAS access
OE Pulse Width (Hi-Z control)
W Pulse Width (Hi-Z control)
Delay time, CAS low to W low after read
Delay time, Address to W low after read
Delay time, CAS precharge to W low after read
Delay time, CAS low to OE high after read
Delay time, Address to OE high after read
Delay time, CAS precharge to OE high after read
All previously specified timing requirements and switching characteristics are applicable to their respective Hyper page mode cycle.
tHPC(min) is specified in the case of read-only and early write-only in Hyper page Mode.
26:
tRAS(min) is specified as two cycles of CAS input are performed.
27:
tCP(max)) is specified as a reference point only.
Parameter
(Note 26)
(Note 27)
(Note 28)
(Note 24)
M5M4V4405C-6,-6S M5M4V4405C-7,-7S
Min Max Min Max
25
66
5
77
10
33
50
7
7
7
32 42
47 57
50 60
15 20
30 35
33 38
MITSUBISHI LSIs
OE or W) (Note 25)
30
79
5
100000
92
13
38
60
7
7
7
16
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CAS before RAS Refresh Cycle (Note 29)
Symbol
tCSR
tCHR
tRSR
tRHP
tCAS
Note 29: Eight or more CAS before RAS cycles instead of eight RAS cycles are necessary for proper operation of CAS before RAS refresh mode.
Self Refresh Cycle
Symbol
tRASS
tRPS
tCHS
tRSR
tRHR
CAS setup time before RAS low
CAS hold time after RAS low
Read setup time before RAS low
Read hold time after RAS low
CAS low pulse width
*
(Note 30)
CBR self refresh RAS low pulse width
CBR self refresh RAS high precharge time
CBR self refresh CAS hold time
Read setup time before RAS low
Read hold time after RAS low
Parameter
Parameter
M5M4V4405C-6,-6S M5M4V4405C-7,-7S
Min Max Min Max
5
10
10
10
17
M5M4V4405C-6,-6S M5M4V4405C-7,-7S
Min Max Min Max
100
110
-50
10
10
Limits
5
15
10
Limits
100
130
-50
15
22
10
15
Unit
ns
ns
ns
ns
ns
Unit
µs
ns
ns
ns
ns
7
MITSUBISHI LSIs
Parameter
Parameter
Parameter
(Note 3,4,5)
85
CC4(AV)
(Note 3,5)
(Note 3,4,5)
(Note 3)
8575857575
65
75
CACtRAC
3538652040437525202520
1151553
35
6525 135
1860 40
75
CSHtRSHtRALtRC
20
2025 2549 1384994
37
9462166
62
112
47
10000
112
10000
10000
82
5297 62
CSHtRSH
CAL
23
28
M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
Test Mode Specification (Note 31)
ELECTRICAL CHARACTERISTICS
Symbol
ICC1 (AV)
Average supply current
from VCC
operating
Average supply current
ICC3 (AV)
I
ICC6(AV)
Note 31: All previously specified electrical characteristics, switing characteristics, and timing requirements are applicable to that of test mode.
from VCC
refreshing
Average supply current
from VCC
Hyper-Page-Mode
Average supply current
from VCC
CAS before RAS refresh
mode
Parameter
SWITCHING CHARACTERISTICS (Ta=0~70˚C, VCC=3.3V±0.3V, VSS=0V, unless otherwise noted, see notes 6,14,15)
Symbol
t
tAA
tCPA
tOEA
Access time from CAS
Access time from RAS
Column address access time
Access time from CAS precharge
Access time from OE
(Ta=0~70˚C, VCC=3.3V±0.3V, VSS=0V, unless otherwise noted) (Note 2)
Limits
Min Max
M5M4V4405C-6,-6S
M5M4V4405C-7,-7S
M5M4V4405C-6,-6S
M5M4V4405C-7,-7S
M5M4V4405C-6,-6S
M5M4V4405C-7,-7S
M5M4V4405C-6,-6S
M5M4V4405C-7,-7S
Test conditions
RAS, CAS cycling
tRC=tWC=min.
output open
RAS cycling, CAS= VIH
tRC=min.
output open
RAS=VIL, CAS cycling
tPC=min.
output open
CAS before RAS refresh cycling
tRC=min.
output open
Limits
M5M4V4405C-6,-6S M5M4V4405C-7,-7S
Min Max Min Max
(Note 7,8)
(Note 7,9)
(Note 7,10)
(Note 7,11)
(Note 7)
Typ
Unit
mA
mA
mA
mA
Unit
ns
ns
ns
ns
ns
TIMING REQUIREMENTS (Ta=0~70˚C, VCC=3.3V±0.3V, VSS=0V, unless otherwise noted, see notes 14,15)
Read and Refresh Cycles
Symbol
Read cycle time
tRAS
tCAS
t
RAS low pulse width
CAS low pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Column address to RAS hold time
t
tORH
tOCH
Column address to CAS hold time
RAS hold time after OE low
CAS hold time after OE low
Read-Write and Read-Modify-Write Cycles
Symbol
tRWC
tRAS
tCAS
t
Read write/read modify write cycle time
RAS low pulse width
CAS low pulse width
CAS hold time after RAS low
(Note 23)
RAS hold time after CAS low
tCWD
tRWD
tAWD
Delay time, CAS low to W low
Delay time, RAS low to W low
Delay time, address to W low
(Note 24)
(Note 24)
(Note 24)
8
M5M4V4405C-6,-6S M5M4V4405C-7,-7S
Min Max Min Max
10000 10000
Limits
10000
10000
Limits
M5M4V4405C-6,-6S M5M4V4405C-7,-7S
Min Max Min Max
10000
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
MITSUBISHI LSIs
Parameter
101010
15
(Note 26)
(Note 27)
HPCtHPRWC
CPRH
(Note 24)
HCWD
HCOD
383082
55
7143359765
84374752625565202535403843
Parameter
M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
Hyper page Mode Cycle
(Read, Early Write, Read-Write, Read-Modify-Write Cycle, Read Write Mix Cycle, Hi-Z control by
Limits
100000
Symbol
t
tRAS
t
tCPWD
t
tHAWD
tHPWD
t
tHAOD
tHPOD
M5M4V4405C-6,-6S M5M4V4405C-7,-7S
Min Max Min Max
Hyper page mode read/write cycle time
Hyper Page Mode read write / read modify write cycle time
RAS low pulse width for read or write cycle
RAS hold time after CAS precharge
Delay time, CAS precharge to W low
Delay time, CAS low to W low after read
Delay time, Address to W low after read
Delay time, CAS precharge to W low after read
Delay time, CAS low to OE high after read
Delay time, Address to OE high after read
Delay time, CAS precharge to OE high after read
Test Mode Set Cycle
Limits
Symbol
tWSR
tWHR
M5M4V4405C-6,-6S M5M4V4405C-7,-7S
Min Max Min Max
Write setup time before RAS low
Write hold time after RAS low
OE or W) (Note 25)
Unit
100000
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9
Timing Diagrams (Note 32)
Read Cycle
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
tRC
RAS
CAS
A0 ~A9
W
DQ1~DQ4
(INPUTS)
DQ1~DQ4
(OUTPUTS)
OE
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VIH
VIL
tCRP
tASR
ADDRESS
ROW
tRAH
tRAD
tRCD
tDZC
tRCS
tRAC
tASC
COLUMN
ADDRESS
tDZO
tRAS
tCAH
tCAC
tAA
tCLZ
tCSH
tOEA
tRAL
tCAL
tRSH
tCAS
Hi-Z
tORH
tOCH
tREZ
tOHR
DATA VALID
tRP
tCDD
tWEZ
tOFF
tOHC
tODD
tCRP
tRRH
tRCH
tOEZ
tASR
ADDRESS
ROW
Hi-ZHi-Z
Note 32
Indicates the don't care input.
VIH(min)≤VIN≤VIH(max) or VIL(min)≤VIN≤VIL(max)
Indicates the invalid output.
Early Write Cycle
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
tWC
RAS
CAS
A0~A9
W
DQ1~DQ4
(INPUTS)
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
tCRP
tASR
tRAH
ROW
ADDRESS
tRCD
tDS
tASC
tWCS
tRAS
tCAH
COLUMN
ADDRESS
DATA VALID
tWCH
tDH
tCSH
tRSH
tCAS
tRP
tCRP
tASR
ROW
ADDRESS
DQ1~DQ4
(OUTPUTS)
OE
VOH
VOL
VIH
VIL
Hi-Z
Delayed Write Cycle
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
tWC
RAS
CAS
A0~A9
W
DQ1~DQ4
(INPUTS)
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
tCRP
tASR
tRAH
ROW
ADDRESS
tRCD
tRCS
tASC
tDZC
tCSH
tCLZ
tRAS
tCAH
COLUMN
ADDRESS
Hi-Z
tCAS
tRSH
tWCH
tDS
tCWL
tWP
tDH
DATA
VALID
tRWL
tCRP
tRP
tASR
ROW
ADDRESS
DQ1~DQ4
(OUTPUTS)
OE
VOH
VOL
VIH
VIL
Hi-Z Hi-Z
tDZO
tOEZ
tODD
tOEH
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
Read-Write, Read-Modify-Write Cycle
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
tRWC
RAS
CAS
A0~A9
W
DQ1~DQ4
(INPUTS)
DQ1~DQ4
(OUTPUTS)
OE
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VIH
VIL
tCRP
tRCD
tRAD
tASR
tRAH
ROW
ADDRESS ADDRESS
Hi-Z
tASC
tRCS
tDZC
tRAC
tDZO
COLUMN
tCAC
tAA
tCLZ
tCSH
tOEA
tRAS
tCAH
Hi-Z
tAWD
tCWD
tRWD
DATA
VALID
tCAS
tRSH
tOEZ
tDS
tODD
tCWL
tRWL
tWP
DATA VALID
tOEH
tDH
Hi-Z
tCRP
tRP
tASR
ROW
ADDRESS
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
Hyper Page Mode Read Cycle
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
RAS
CAS
A0~A9
W
DQ1~DQ4
(INPUTS)
DQ1~DQ4
(OUTPUTS)
OE
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VIH
VIL
tCRP
tASR
tRAH
ROW
ADDRESS
Hi-Z
tRAD
tCSH tHPC
tRCD
tASC
tRCS
tDZC
tRAC
tDZO tOEA
tCAS
tCAH
COLUMN-1
tCAL tCAL tCAL
tCAC
tAA
tCLZ
VALID-1
tOCH
tRAS
tCP
DATA
tCAS
tCAHtASC tCAHtASC
COLUMN-2 COLUMN-3
Hi-Z
tCAC
tAA
tDOH
tCPA
tCP
DATA
VALID-2
tDOH
tCPA
tAA
tRSH
tCPRH
tRAL
tCAC
tCAS
tRP
tRRH
tRDD
tOHR
VALID-3
tASR
ADDRESS
tRCH
tCDD
tREZ
tOFF
tOHC
DATA
ROW
tWEZ
tOEZ
tODD
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
Hyper Page Mode Early Write Cycle
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
RAS
CAS
A0~A9
W
DQ1~DQ4
(INPUTS)
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
tCRP
tASR
tRAH
ROW
ADDRESS
tRAS
tRCD
tCSH
tCAS
tCP
tHPC
tCAS
tCAL tCAL
tASC
tWCS
tCAH
COLUMN-1
tWCH tWCS tWCH tWCS tWCH
tASC tASC
tCAH tCAH
COLUMN-2 COLUMN-3
tDS tDH tDS tDH tDS tDH
DATA
VALID-1
DATA
VALID-2
tRSH
tCP tCAS
DATA
VALID-3
tRP
tCRP
tASR
ROW
ADDRESS
DQ1~DQ4
(OUTPUTS)
OE
VOH
VOL
VIH
VIL
Hi-Z
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
Hyper Page Mode Read-Write, Read-Modify-Write Cycle
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
RAS
CAS
A0~A9
W
DQ1~DQ4
(INPUTS)
DQ1~DQ4
(OUTPUTS)
OE
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VIH
VIL
tCRP
tASR
tRAH
ROW
ADDRESS
tRAD
tRCD
tASC
tRAC
tRAS
tCSH
tCAS
tCAH
COLUMN-1
tAWD
tRCS
tCWD
tCWL
tWP
tRWD
tDZC
Hi-Z Hi-Z
tDS
tCAC
tDH
DATA
VALID-1
tAA
tCLZ
DATA
VALID-1
Hi-Z Hi-ZHi-Z
tODD
tOEA tDZO
tDZO
tOEZ
tCP
tRCS
tASC
COLUMN-2
tDZC
tCPA
tAA
tCAH
tAWD
tCPWD
tCAC
tOEA
tHPRWC
tCWD
tCLZ
DATA
VALID-2
tCAS
tDS
tODD
tOEZ
tRWL
tCWL
tWP
tDH
DATA
VALID-2
tOEH
tRP
tCRP
tASR
ROW
ADDRESS
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
Hyper Page Mode Mix Cycle (1)
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
RAS
CAS
A0~A9
W
DQ1~DQ4
(INPUTS)
DQ1~DQ4
(OUTPUTS)
OE
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VIH
VIL
tCRP
tASR
tRAH
ROW
ADDRESS
Hi-Z
tCSH tHPC
tRCD
tCAS
tRAD
tASC
tCAH
COLUMN-1
tRCS
tCAL
tDZC
tCAC
tAA
tCLZ
tRAC
tDZO
tOEA
tOCH
DATA
VALID-1
tOEZ
tRAS
tCP
tCAS tCP
tCAHtASC tCAHtASC
COLUMN-2 COLUMN-3
tWCS
tWCH
tCAL
tDH
tDS
DATA
VALID-2
tDZC
tWEZ
tDZO
tCPA
tAA
tCAC
tCLZ
tOEA
tCPWD
tAWD
DATA
VALID-3
tCWD
tOEZ
tHPRWC
tCAS
tDS
tWP
tDH
DATA
VALID-3
tOEH
tRWL
tCWL
tRP
tCRP
tASR
ROW
ADDRESS
tODD
tODD
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
Hyper Page Mode Mix Cycle (2)
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
RAS
CAS
A0~A9
W
DQ1~DQ4
(INPUTS)
DQ1~DQ4
(OUTPUTS)
OE
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VIH
VIL
tCPA
tHPOD
tCAH
tCAL
tHPWD
tAA
tHAOD
tCAS
tHAWD
tCAC
tHCWD
tHCOD
tRCH
DATA
VALID-1
tASC
tWCS
tDS
tWEZ
tOEZ
tODD
tCP
tASC
COLUMN-1 COLUMN-2 COLUMN-3
tCAL
tWCH
tDH
DATA
VALID-2
tCAS
tCAH
Hi-Z
tASC
tDZC
tCPA
tCLZ
tDZC
tAA
tCAC
tOEA
tCAH
Hi-ZHi-Z
DATA
VALID-3
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
Hyper Page Mode Read Cycle ( Hi-Z control by OE )
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
RAS
CAS
A0~A9
W
DQ1~DQ4
(INPUTS)
DQ1~DQ4
(OUTPUTS)
OE
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VIH
VIL
tCRP
tASR
tRAH
ROW
ADDRESS
tRAD
Hi-Z
tRCD
tASC
tRCS
tDZC
tRAC
tDZO tOEA
tCSH
tCAH
COLUMN-1
tCAC
tAA
tCLZ
tCAS
DATA
VALID-1
tRAS
tHPC
tCP
tASC tCAHtASC
tCAH
COLUMN-2 COLUMN-3
tCAC
tAA
tDOH
DATA
VALID-1
tOEZ
tCPA
tOCH
tOEA
tOEPE
tCAS
Hi-Z
tCHOL
tCP tCAS
DATA
VALID-2
tCPA
tOEZ
tOEPE
Hi-Z
tRSH
tCPRH
tRAL
tCAC
tAA
tCLZ
tRRH
tRDD
VALID-3
tRP
tCRP
tASR
tCDD
tREZ
tOHR
tOFF
tOHC
DATA
ROW
ADDRESS
tRCH
tWEZ
tOEZ
tODD
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
Hyper Page Mode Read Cycle ( Hi-Z control by W )
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
RAS
CAS
A0~A9
W
DQ1~DQ4
(INPUTS)
DQ1~DQ4
(OUTPUTS)
OE
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VIH
VIL
tCRP
tASR tRAH
ROW
ADDRESS
Hi-Z
tRAD
tRCD
tASC
tRAC
tCSH
tRCS
tDZC
tDZO
tCAH
COLUMN-1
tCAC
tAA
tCLZ
tCAS
tOCH
tOEA
tRAS
tHPC
tCP
tASC tCAHtASC
tCAS
tCAH
COLUMN-2 COLUMN-3
tRCH
Hi-Z
tCAC
tAA
tDOH
DATA
VALID-1
DATA
VALID-2
tCPA
tCP
tWPE
tWEZ
tCPA
tAA
Hi-Z
tRSH
tCPRH
tRAL
tRCS
tCAC
tCLZ
tCAS
tRRH
VALID-3
tRP
tCRP
tRDD
tCDD
tREZ
tOHR
tOFF
tOHC
DATA
tASR
ROW
ADDRESS
tRCH
tWEZ
tOEZ
tODD
RAS-only Refresh Cycle
RAS
VIH
VIL
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
tRC
tRAS
tRP
CAS
A0~A9
W
DQ1~DQ4
(INPUTS)
DQ1~DQ4
(OUTPUTS)
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
tCRP
tASR tRAH
ROW
ADDRESS
Hi-Z
tRPC
tCRP
tASR
ROW
ADDRESS
OE
VIH
VIL
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
CAS before RAS Refresh Cycle, Extended Refresh Cycle*
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
RAS
CAS
A0~A9
W
DQ1~DQ4
(INPUTS)
DQ1~DQ4
(OUTPUTS)
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
tRC
tCHR
tRAS
tCSRtRPC
tRP
tRPC
tCSR
tCPN
tRRH
tRSR tRHR tRSR tRHR
tRCH
tREZ
tOHR
tOFF
tOHC
tCHR
tRAS
Hi-Z
tRC
tRPC
tRP
tCRP
tASR
ROW
ADDRESS
COLUMN
ADDRESS
tRCS
OE
tOEZ
VIH
VIL
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
Hidden Refresh Cycle (Read) (Note 33)
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
RAS
CAS
A0~A9
W
DQ1~DQ4
(INPUTS)
DQ1~DQ4
(OUTPUTS)
OE
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VIH
VIL
tCRP
tASR
tRAH
ROW
ADDRESS
tRCD
tRAD
tASC
tRCS
tDZC
Hi-Z
tRAC
tRC
tRAS
tRSH
tCAH
COLUMN
ADDRESS
tRAL
tCAC
tAA
tCLZ
tDZO tOEA
tORH
tRP
tCHR
Hi-Z
DATA VALID
tRAS
tRC
tRCH
tCDD
tOFF
tOHC
tOEZ
tOHR
tODD
tRRH
tRDD
tREZ
tRP
tASR
ROW
ADDRESS
Hi-Z
Note 33: Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle.
Timing requirements and output state are the same as that of each cycle shown above.
Self Refresh Cycle* (Note 30)
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
RAS
CAS
A0~A9
W
DQ1~DQ4
(INPUTS)
DQ1~DQ4
(OUTPUTS)
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
tRPC
tCPN
tRRH
tRCH
tRDD
tCDD
Hi-Z
tRP
tREZ
tOHR
tOFF
tOHC
tCSR
tRSR tRHR
tRASS
tCHS
Hi-Z
tRPC
tRPS
tCRP
tASR
ADDRESS
ROW
tRCS
OE
tOEZ
tODD
VIH
VIL
Test Mode Set Cycle (Note 34)
tRP
RAS
CAS
VIH
VIL
tRPC
VIH
VIL
tCPN
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
tRC
tCSR
tRAS
tCHR
tRPC
tRP
tCRP
tASR
A0~A9
W
DQ1~DQ4
(INPUTS)
DQ1~DQ4
(OUTPUTS)
OE
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VIH
VIL
tRCH
tOFF
tOEZ
tWSR tWHR
Hi-Z
ROW
ADDRESS
COLUMN
ADDRESS
tRCS
Note 34:
The cycle is also avaiilable for initialization cycle, but in this case device enters test mode.
The test mode function is initiated with a W and CAS before RAS cycle(WCBR cycle) as specified above timing diagram.
The test mode function is terminated by either a CAS before RAS(CBR) refresh or a RAS only refresh cycle.
During the test mode, the device is internally organized as 4-bits wide (256 kilobytes deep) for each DQ (input / output) port.
No addressing of A0, A1(column only) is required.
During a write cycle, data on the each DQ (input) pin is written in parallel into all 4-bits for each DQ port and can be written
independently for each DQ port.
During a read cycle, the each DQ (output) pin indicates independently a HIGH state if all 4-bits are equal, and a LOW state
if any bits differ.
During the test mode operation, a WCBR cycle is used to perform refresh.
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
Two refreshing methods should be used properly depending on the
low pulse width(tRASS) of RAS signal during self refresh period.
The time interval from the falling edge of RAS signal in the last
CBR refresh cycle during read/write operation period to the
falling edge of RAS signal at the start of self refresh operation
should be set within tNSD (shown in table 2).
Note:
Hidden refresh may be used instead of CBR refresh.
RAS/CAS refresh may be used instead of RAS only refresh.
) are
selected during 1024 constant period(16µs max.) RAS only
refresh cycles within 16.4 ms.
The time interval from the rising edge of RAS signal at the end of
self refresh operation to the falling edge of RAS signal in the first
CBR refresh cycle during read/write operation period should be
set within tSND(shown in table 2).
from the falling edge of RAS signal in the
last RAS only refresh cycle during read/write operation period to
the falling edge of RAS signal at the start of self refresh operation
should be set within 16µs.
Switching from self refresh operation to read/write operation.
The time interval tSND from the rising edge of RAS signal at the
end of self refresh operation to the falling edge of RAS signal in
the first CBR refresh cycle during read/write operation period
should be set within 16µs.
Note 30 : Self refresh sequence
1. Distributed refresh during Read / Write operation
(A) Timing Diagram
Read / Write Cycle Self Refresh Cycle Read / Write Cycle
tNSD tRASS≥100µs tSND
RAS
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
last
refresh Cycle
Table 2
Read / Write Cycle
CBR distributed
refresh
RAS only
distributed refresh
Read / Write
Self Refresh
tNSD≤125µs tSND≤125µs
tNSD≤16µs
(B) Definition of distributed refresh
tREF/1024
RAS
refresh
cycle
read/write
cycles
Definition of CBR distributed refresh
(Including extended refresh)
The CBR distributed refresh performs more than 1024
constant period(125µs max.) CBR cycles within 128 ms.
Definition of RAS only distributed refresh
All combinations of nine row address signals (A0~A9
Self Refresh
Read / Write
tSND≤16µs
refresh
cycle
tREF
first
refresh cycle
tREF/1024
refresh
cycle
read/write
cycles
Switching from self refresh operation to read/write operation.
1.1 CBR distributed refresh
Switching from read/write operation to self refresh operation.
1.2 RAS only distributed refresh
Switching from read/write operation to self refresh operation.
The time interval tNSD
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
The time interval ns from the falling edge of RAS signal in the
first CBR refresh cycle during read/write operation period to the
falling edge of RAS signal at the start of self refresh operation
should be set within 16.4 ms.
Switching from self refresh operation to read/write operation.
The time interval snob from the rising edge of RAS signal at the
end of self refresh operation to the falling edge of RAS signal in
the last CBR refresh cycle during read/write operation period
should be set within 16.4 ms.
The time interval from the falling edge of RAS signal in the first
RAS only refresh cycle during read/write operation period to the
falling edge of RAS signal at the start of self refresh operation
should be set within tNSB(Shown in table 3).
Switching from self refresh operation to read/write operation.
The time interval from the rising edge of RAS signal at the end of
self refresh operation to the falling edge of RAS signal in the last
RAS only refresh cycle during read/write operation period should
be set within tSNB(shown in table 3).
2. Burst refresh during Read/Write operation
(A) Timing diagram
Read / Write Self Refresh Read / Write
RAS
MITSUBISHI LSIs
M5M4V4405CJ,TP-6,-7,-6S,-7S
tNSB tRASS≥100µs tSNB
first
refresh cycles
Table 3
Read / Write Cycle
CBR burst
refresh
RAS only
burst refresh
(B) Definition of burst refresh
RAS
Definition of CBR burst refresh
The CBR burst refresh performs more than 1024
continuous CBR cycles within 16.4 ms.
Definition of RAS only burst refresh
All combination of nine row address signals (A0 ~A9)
are selected during 1024 continuous RAS only refresh
cycles within 16.4 ms.
Read / Write
Self Refresh
tNSB≤16.4ms tSNB≤16.4ms
tNSB+tSNB≤16.4ms
1024cycles
refresh cycles
1024 cycles
Self Refresh
Read / Write
16.4ms
read/write cyclesrefresh cycles
refresh cycles
1024 cycles
last
refresh Cycles
2.1 CBR burst refresh
Switching from read/write operation to self refresh operation.
2.2 RAS only burst refresh
Switching from read/write operation to self refresh operation.
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