Mitsubishi M5M44800CTP-5S, M5M44800CTP-5, M5M44800CJ-7S, M5M44800CJ-7, M5M44800CJ-6S Datasheet

MITSUBISHI LSIs

with the high performance CMOS process, and is ideal for large­capacity memory systems where high speed, low power
dissipation, and low costs are essential.
The use of double-layer metalization process technology and a
single-transistor dynamic storage stacked capacitor cell provide
high circuit density at reduced costs. Multiplexed address inputs
permit both a reduction in pins and an increase in system
densities. Self or extended refresh current is low enough for
battery back-up application.

MITSUBISHI LSIs

M5M44800CJ,TP-5,-6,-7,

M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S

-5S,-6S,-7S

FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM

FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM

DESCRIPTION

This is a family of 524288-word by 8-bit dynamic RAMs, fabricated

FEATURES

RAS

CAS

Type name

M5M44800CXX-5,-5S
M5M44800CXX-6,-6S
M5M44800CXX-7,-7S

XX=J,TP

access

time

(max.ns)

Address

access

(max.ns)

access

time

(max.ns)

50 13 25 90 45013
6070152030

time

35

OE

access

time

(max.ns)

15
20

(min.ns)

Standard 28pin SOJ, 28pin TSOP (II)
Single 5V±10% supply
Low stand-by power dissipation
CMOS lnput level 5.5mW (Max)

CMOS Input level 550µW (Max) *
Operating power dissipation

M5M44800Cxx-5,-5S 495mW (Max)
M5M44800Cxx-6,-6S 413mW (Max)
M5M44800Cxx-7,-7S 358mW (Max)
Self refresh capability *
Self refresh current 150µA(Max)
Extended refresh capability
Extended refresh current 150µA(Max)
Fast page mode(1024-column random access),Read-modify-write,
RAS-only refresh, CAS before RAS refresh, Hidden refresh
capabilities.
Early-write mode, CAS and OE to control output buffer impedance
1024 refresh cycles every 16.4ms (A0 ~A9)
1024 refresh cycles every 128ms (A0 ~A9) *
* :Applicable to self refresh version (M5M44800CJ,TP-5S,-6S,-7S
:option) only

Cycle

time

110
130

Power

dissipa-

tion

(typ.mW)

375
325

PIN CONFIGURATION (TOP VIEW)

(5V)VCC

(5V)VCC 14

DQ1
DQ2
DQ3
DQ4

NC

W

RAS

A0
A1

A2
A3

1
2
3
4
5
6

8
9A9

10
11
12
13

13

Outline 28P0K(400mil SOJ)

(5V)VCC

(5V)VCC 14

DQ1
DQ2

DQ3
DQ4

NC

W

RAS

A0
A1

A2
A3

1
2
3
4
5
6

8
9A9

10
11
12
13

13

28

25
24
23
227

21
20
19
18
17
16
15

28
27

26
25

24
23
227

21
20
19
18
17
16
15

VSS(0V)
DQ827
DQ726
DQ6
DQ5
CAS
OE

NC
A8
A7
A6
A5
A4

VSS(0V)

VSS(0V)
DQ8
DQ7
DQ6
DQ5
CAS
OE

NC
A8
A7
A6
A5
A4

VSS(0V)

APPLICATION

Microcomputer memory, Refresh memory for CRT

PIN DESCRIPTION

Pin name
A0~A9
DQ1~DQ8
RAS
CAS
W
OE

Vcc
Vss

Address inputs
Data inputs/outputs

Row address strobe input
Column address strobe input
Write control input
Output enable input
Power supply (+5V)
Ground (0V)

1

M5M44800CJ,TP-5,-5S:Under development

Function

Outline 28P3Y-H(400mil TSOP Normal Bend)

NC:NO CONNECTION

FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM

In addition to normal read, write, and read-modify-write operations
the M5M44800CJ, TP provides a number of other functions, e.g.,

Row

address

address

Column

INPUTS / OUTPUTS

FUNCTION

Table 1 Input conditions for each mode

MITSUBISHI LSIs

M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S

fast page mode, RAS-only refresh, and delayed-write. The input
conditions for each are shown in Table 1.

Operation

RAS

Read
Write (Early write)

Write (Delayed write)
Read-modify-write

RAS only refresh
Hidden refresh

CAS before RAS (Extended *) refresh

Self refresh *
Stand-by

Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : invalid, APD : applied, OPN : open

ACT
ACT

ACT
ACT

ACT
ACT

ACT
ACT

NAC

CAS
ACT
ACT

ACT
ACT

NAC
ACT
ACT

ACT

DNC

W

NAC
ACT

ACT
ACT

DNC
DNC

DNC
DNC

Inputs

OE

ACT
DNC

DNC
ACT

DNC
ACT

DNC DNC DNC DNC OPN YESDNC
DNC

DNC

APD
APD

APD
APD

APD
DNC

DNC
DNC

APD
APD

APD
APD
DNC

DNC

DNC
DNC

Input/Output

Input Output

OPN

VLD
VLD
VLD

DNC
OPN

DNC
DNC

VLD

OPN

IVD

VLD

OPN

VLD

OPN
OPN

Refresh Remark

YES

Fast page

YES

mode

YES

identical

YES
YES

YES

YES

NO

BLOCK DIAGRAM

COLUMN ADDRESS
STROBE INPUT

ROW ADDRESS

STROBE INPUT

WRITE CONTROL

INPUT

ADDRESS INPUTS

2

M5M44800CJ,TP-5,-5S:Under development

CAS
RAS

W

A0
A1
A2
A3
A4

A5
A6
A7
A8
A9

ROW &

COLUMN

ADDRESS

BUFFER

A0~A8

A0~
A9

ROW

DECODER

CLOCK GENERATOR

CIRCUIT

COLUMN DECODER

SENSE REFRESH

AMPLIFIER & I /O CONTROL

MEMORY CELL

(4194304BITS)

(8)
DATA IN
BUFFER

(8)

DATA OUT

BUFFER

VCC (5V)
VCC (5V)

VSS (0V)
VSS (0V)

DQ1
DQ2
DQ3
DQ4

DATA

DQ5
DQ6
DQ7
DQ8

OUTPUT ENABLE

OE

INPUT

M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S

FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM

ABSOLUTE MAXIMUM RATINGS

Symbol

VCC
VI
VO

IO
Pd
Topr

Tstg

Supply voltage
Input voltage
Output voltage
Output current
Power dissipation
Operating temperature
Storage temperature

Parameter

With respect to VSS

Ta=25˚C

RECOMMENDED OPERATING CONDITIONS (Ta=0~70˚C, unless otherwise noted) (Note 1)

Symbol

VCC
VSS

VIH
VIL

Note 1 : All voltage values are with respect to Vss.
* * : VIL(min) is -2.0V when pulse width is less than 25ns. (Pulse width is with respect to VSS.)

Supply voltage
Supply voltage
High-level input voltage, all inputs
Low-level input voltage, all inputs

Parameter

Min Nom Max

4.5
0

2.4

-0.5 * *

Limits

5.0
0

Conditions

5.5
0

6.0

0.8

Unit

V
V
V

V

MITSUBISHI LSIs

Ratings

-1~7

-1~7

-1~7
50

1000

0~70

-65~150

Unit

V
V
V

mA

mW

˚C
˚C

ELECTRICAL CHARACTERISTICS

Symbol

VOH
VOL

IOZ
I I

ICC1 (AV)

High-level output voltage
Low-level output voltage

Off-state output current

Input current
Average supply current

from VCC, operating

Parameter

(Note 3,4,5)

(Ta=0~70˚C, VCC=5V±10%, VSS=0V, unless otherwise noted) (Note 2)

M5M44800C-5,-5S
M5M44800C-6,-6S
M5M44800C-7,-7S

Test conditions

IOH=-5mA
IOL=4.2mA
Q floating, 0V ≤ VOUT ≤ 5.5V
0V ≤ VIN ≤ +6.0V, Other inputs pins=0V

RAS, CAS cycling
tRC=tWC=min.
output open

Min Max

2.4
0

-10

-10

RAS= CAS =VIH, output open

ICC2

Supply current from VCC, stand-by

(Note 6)

RAS= CAS ≥ VCC -0.5V
output open

M5M44800C-5,-5S
M5M44800C-6,-6S
M5M44800C-7,-7S
M5M44800C-5,-5S
M5M44800C-6,-6S
M5M44800C-7,-7S
M5M44800C-5,-5S
M5M44800C-6,-6S
M5M44800C-7,-7S

RAS cycling, CAS= VIH
tRC=min.
output open

RAS=VIL, CAS cycling
tPC=min.
output open

CAS before RAS refresh cycling
tRC=min.
output open

ICC3 (AV)

ICC4(AV)

ICC6(AV)

Average supply current
from VCC, RAS only
refresh mode

(Note 3,5)

Average supply current
from VCC, Fast Page
Mode

Average supply current
from VCC, CAS before RAS
refresh mode

(Note 3,4,5)

(Note 3,5)

RAS cycling CAS ≤ 0.2V or CAS
before RAS refresh cycling

RAS ≤ 0.2V or ≥ VCC-0.2V
Average supply current from VCC,
Extended-Refresh mode

(Note 6)ICC8(AV) *

CAS ≤ 0.2V or ≥ VCC-0.2V

W ≤ 0.2V or ≥ VCC-0.2V

OE ≤ 0.2V or ≥ VCC-0.2V

A0~A9 ≤ 0.2V or ≥ VCC-0.2V, DQ=open

tRC=125µs, tRAS=tRASmin~1µs

ICC9(AV) *

Note 2: Current flowing into an IC is positive, out is negative.

Note 3: ICC1 (AV), ICC3 (AV), ICC4 (AV) and ICC6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
Note 4: ICC1 (AV) and ICC4 (AV) are dependent on output loading. Specified values are obtained with the output open.
Note 5: Column address can be changed once or less while RAS=VIL and CAS=VIH

3

M5M44800CJ,TP-5,-5S:Under development

Average supply current from VCC,
Self-Refresh mode

(Note 6)

RAS=CAS ≤ 0.2V
output open

Limits

Typ

Vcc

0.4
10
10

90
75
65

1.0

0.1 *
90
75

65
90
75
65
80
65
55

150

150

Unit

V

V
µA
µA

mA

2

mA

mA

mA

mA

µA

µA

MITSUBISHI LSIs

M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S

FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM

CAPACITANCE

Symbol Parameter Test conditions

CI (A)
CI (CLK)

CI / O

SWITCHING CHARACTERISTICS

(Ta=0~70˚C, VCC=5V±10%, VSS=0V, unless otherwise noted)

Input capacitance, address inputs
Input capacitance, clock inputs
Input/Output capacitance, data ports

VI=VSS
f=1MHz

VI=25mVrms

(Ta=0~70˚C, VCC = 5V±10%, VSS=0V, unless otherwise noted, see notes 6,13,14)

Limits

Min Max

Typ

5
7

7

Unit

pF
pF
pF

Limits

Symbol

tCAC
tRAC
tAA
tCPA
tOEA
tCLZ

tOFF
tOEZ

Note 6:An initial pause of 500µs is required after power-up followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh
cycles).
Note the RAS may be cycled during the initial pause. And 8 initialization cycles are required after prolonged periods (greater than 16.4ms) of RAS
inactivity before proper device operation is achieved.

Note 7:Measured with a load circuit equivalent to 2TTL loads and 100pF.
Note 8:Assumes that tRCD ≥ tRCD(max) and tASC ≥ tASC(max).
Note 9:Assumes that tRCD ≤ tRCD(max) and tRAD ≤ tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC will

increase by amount that tRCD exceeds the value shown.

nOR10:Assumes that tRAD ≥ tRAD(max) and tASC ≤ tASC(max).
Note11:Assumes that tCP ≤ tCP(max) and tASC ≥ tASC(max).
Note12:tOFF(max), tOEZ(max) defines the time at which the output achieves the high impedance state (IOUT ≤ ±10µA ) and is not reference to VOH(min) or

VOL(max).

Access time from CAS
Access time from RAS
Column address access time
Access time from CAS precharge
Access time from OE

Output low impedance time from CAS low
Output disable time after CAS high
Output disable time after OE high

Parameter

(Note 7,8)
(Note 7,9)

(Note 7,10)
(Note 7,11)

(Note 7)
(Note 7)

(Note 12)
(Note 12)

M5M44800C-5,-5S

Min Max

13
50
25
30

13
13

M5M44800C-6,-6S

Min Max

15
60

30
35

1513

55

15
15

M5M44800C-7,-7S

Min Max

20
70
35
40
20

5

20
20

Unit

ns

ns

ns

ns

ns

ns

ns

ns

4

M5M44800CJ,TP-5,-5S:Under development

MITSUBISHI LSIs

M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S

FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM

TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh, and Fast-Page Mode Cycles)

(Ta=0~70˚C, VCC = 5V±10%, VSS=0V, unless otherwise noted, see notes 6,13,14)

Symbol

tREF
tREF

tRP
tRCD
tCRP
tRPC
tCPN
tRAD
tASR
tASC
tRAH
tCAH
tDZC
tDZO
tCDD
tODD
tT

Note 13: The timing requirements are assumed tT=5ns.

Note 14: VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
Note 15: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is

controlled exclusively by tCAC or tAA.

Note 16: tRAD(max) is specified as a reference point only. If tRAD ≥ tRAD(max) and tASC ≤ tASC(max), access time is controlled exclusively by tAA.
Note 17: tASC(max) is specified as a reference point only. If tRCD ≥ tRCD(max) and tASC ≥ tASC(max), access time is controlled exclusively by tCAC.
Note 18: Either tDZC or tDZO must be satisfied.
Note 19: Either tCDD or tODD must be satisfied.
Note 20: tT is measured between VIH(min) and VIL(max).

Refresh cycle time
Refresh cycle time *
RAS high pulse width
Delay time, RAS low to CAS low

Delay time, CAS high to RAS low
Delay time, RAS high to CAS low
CAS high pulse width
Column address delay time from RAS low
Row address setup time before RAS low
Column address setup time before CAS low
Row address hold time after RAS low
Column address hold time after CAS low

Delay time, data to CAS low
Delay time, data to OE low

Delay time, CAS high to data
Delay time, OE high to data
Transition time

Parameter

(Note 15)

(Note 16)

(Note 17)

(Note 18)
(Note 18)
(Note 19)
(Note 19)
(Note 20)

M5M44800C-5,-5S M5M44800C-6,-6S

Min Max

16.4
128

30
18
5

10

13

13

37

0

25
0
0
8

0
0

1

7

50

Limits

Min Max

16.4
128

40
20

10
15

10
15

1513
1513

45
5
0

30
0

10

0

0
0

50

1

M5M44800C-7,-7S

Min Max

50
20

5

0
10
15

0

0
10
15

0

0
20

20

1

16.4
128

50

35

10

50

Unit

ms
ms

ns

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

ns
ns
ns

Read and Refresh Cycles

Symbol

tRC
tRAS

tCAS
tCSH
tRSH
tRCS

tRCH
tRRH

tRAL
tOCH

tORH

Note 21: Either tRCH or tRRH must be satisfied for a read cycle.

Read cycle time
RAS low pulse width

CAS low pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Read Setup time before CAS low
Read hold time after CAS high
Read hold time after RAS high
Column address to RAS hold time
CAS hold time after OE low
RAS hold time after OE low

Parameter

(Note 21)
(Note 21)

M5M44800C-5,-5S M5M44800C-6,-6S

Min Max

90

10000

50

10000

13
50
13

0
0

0
25
13 15
13

Limits

Min Max

110

60

10000

15

10000

60

15

0

0
0
30

15

M5M44800C-7,-7S

Min Max

130

10000

70

10000

20
70
20

0

0
0
35
20
20

Unit

ns
ns
ns
ns
ns

ns
ns
ns

ns
ns
ns

5

M5M44800CJ,TP-5,-5S:Under development

FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM

Write Cycle (Early Write and Delayed Write)

Symbol

tWC
tRAS
tCAS
tCSH
tRSH
tWCS
tWCH
tCWL
tRWL
tWP
tDS
tDH
tOEH

Write cycle time
RAS low pulse width

CAS low pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Write setup time before CAS low
Write hold time after CAS low
CAS hold time after W low

RAS hold time after W low

Write pulse width
Data setup time before CAS low or W low
Data hold time after CAS low or W low

OE hold time after W low

Parameter

MITSUBISHI LSIs

M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S

Limits

Unit

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

ns

(Note 23)

M5M44800C-5,-5S M5M44800C-6,-6S

Min

90

50

13

50

13

13

13

0

8

13

Max

10000
10000

0
8

8

Min
110
60
15

60
15

10
15
15

10

10
15

Max

10000
10000

0

0

M5M44800C-7,-7S

Min

Max

130

10000

70

10000

20
70
20

0

15
20
20

15

0
15
20

Read-Write and Read-Modify-Write Cycles

Symbol

tRWC
tRAS
tCAS
tCSH
tRSH
tRCS
tCWD
tRWD
tAWD
tCWL
tRWL ns
tWP
tDS
tDH
tOEH

Note 22: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT.

Note 23: tWCS, tCWD, tRWD and tAWD and, tCPWD are specified as reference points only. If tWCS ≥ tWCS(min) the cycle is an early write cycle and the DQ pins

will remain high impedance throughout the entire cycle. If tCWD ≥ tCWD(min), tRWD ≥ tRWD(min), tAWD ≥ tAWD(min) and tCPWD ≥ tCPWD(min) (for fast page
mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above
condition (delayed write) of the DQ (at access time and until CAS or OE goes back to VIH ) is indeterminate.

Read write/read modify write cycle time
RAS low pulse width

CAS low pulse width
CAS hold time after RAS low

RAS hold time after CAS low

Read setup time before CAS low
Delay time, CAS low to W low
Delay time, RAS low to W low

Delay time, address to W low
CAS hold time after W low
RAS hold time after W low
Write pulse width
Data setup time before CAS low or W low

Data hold time after CAS low or W low
OE hold time after W low

Parameter

(Note 22)

(Note 23)
(Note 23)
(Note 23)

M5M44800C-5,-5S M5M44800C-6,-6S

Min Max

126

86

10000

49

10000
86
49

0
31
68
43

13 15 20
13 15 20

13 15 20

Limits

Min Max
150

100

10000

55

10000

100

55
0

35
80
50

10 8 15

0 0 0

10 8 15

M5M44800C-7,-7S

Min Max

180
120

10000

70

10000

120

70
0

45
95
60

Unit

ns
ns
ns

ns
ns
ns
ns
ns
ns
ns

ns
ns
ns
ns

6

M5M44800CJ,TP-5,-5S:Under development

MITSUBISHI LSIs

M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S

FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM

Fast Page Mode Cycle (Read, Early Write, Read-Write, Read-Modify-Write Cycle) (Note 24)

Limits

Symbol

tPC
tPRWC
tRAS
tCP
tCPRH
tCPWD

Note 24: All previously specified timing requirements and switching characteristics are applicable to their respective Fast page mode cycle.

Note 25: tRAS(min) is specified as two cycles of CAS input are performed.
Note 26: tCP(max) is specified as a reference point only.

Fast page mode read/write cycle time
Fast page mode read write/read modify write cycle time

RAS low pulse width for read or write cycle
CAS high pulse width

RAS hold time after CAS precharge
Delay time, CAS precharge to W low

Parameter

(Note 25)
(Note 26)

(Note 23)

CAS before RAS Refresh Cycle, Extended Refresh Cycle * (Note 27)

Symbol

tCSR
tCHR

tCAS

Note 27: Eight or more CAS before RAS cycles instead of eight RAS cycles are necessary for proper operation of CAS before RAS refresh mode.

CAS setup time before RAS low
CAS hold time after RAS low
CAS low pulse width

Parameter

M5M44800C-5,-5S

Min Max
35

71 80
85

100000

8

12
30
48

M5M44800C-5,-5S

Min Max

5

10
20

M5M44800C-6,-6S

Min Max

40

100000

100

M5M44800C-6,-6S

10
35
55

Min Max
5

10
20

15

Limits

M5M44800C-7,-7S

Min Max

45
95

100000

115

M5M44800C-7,-7S

Min Max

10
40

65

5
15

25

15

Unit

ns
ns
ns

ns
ns
ns

Unit

ns
ns
ns

Self Refresh Cycle * (Note 28)

Symbol

tRASS
tRPS
tCHS

CBR self refresh RAS low pulse width
CBR self refresh RAS high precharge time
CBR self refresh CAS hold time

Parameter

M5M44800C-5,-5S

Min Max
100

90

-50 -50 -50

Limits

M5M44800C-6,-6S

Min Max
100
110

M5M44800C-7,-7S

Min Max
100
130

Unit

µs

ns
ns

7

M5M44800CJ,TP-5,-5S:Under development