Mitsubishi M5M44265CJ-6, M5M44265CJ-5S, M5M44265CJ-5, M5M44265CTP-7S, M5M44265CTP-7 Datasheet
...
Microcomputer memory, Refresh memory for CRT, Frame Buffer
memory for CRT
MITSUBISHI LSIs
This is a family of 262144-word by 16-bit dynamic RAMs with
Hyper Page mode fuction, fabricated with the high performance
CMOS process, and is ideal for the buffer memory systems of
personal computer graphics and HDD where high speed, low
power dissipation, and low costs are essential.
The use of double-layer metalization process technology and a
single-transistor dynamic storage stacked capacitor cell provide
high circuit density at reduced costs. Multiplexed address inputs
permit both a reduction in pins and an increase in system
densities. Self or extended refresh current is low enough for
battery back-up application.
This device has 2CAS and 1W terminals with a refresh cycle of
512 cycles every 8.2ms.
MITSUBISHI LSIs
M5M44265CJ,TP-5,-6,-7,
M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S
-5S,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
DESCRIPTION
FEATURES
Power
Cycle
dissipa-
time
tion
(typ.mW)
90 625
110
550
130
475
Type name
M5M44265CXX-5,-5S
M5M44265CXX-6,-6S
M5M44265CXX-7,-7S
XX=J,TP
RAS
time
CAS
access
time
(max.ns)
access
(max.ns)
50 13 25
60
7015203035
Address
access
(max.ns)
time
OE
access
time
(max.ns)
13
15
20
(min.ns)
Standard 40pin SOJ, 44 pin TSOP (II)
Single 5V±10% supply
Low stand-by power dissipation
CMOS Input level 5.5mW (Max)
CMOS Input level 550µW (Max)*
Operating power dissipation
M5M44265Cxx-5,-5S 688mW (Max)
M5M44265Cxx-6,-6S 605mW (Max)
M5M44265Cxx-7,-7S 523mW (Max)
Self refresh capability*
Self refresh current 150µA (Max)
Extended refresh capability
Extended refresh current 150µA (Max)
Hyper-page mode (512-column random access), Read-modifywrite, RAS-only refresh, CAS before RAS refresh, Hidden refresh
capabilities.
Early-write mode, OE and W to control output buffer impedance
512 refresh cycles every 8.2ms (A0~A8)
512 refresh cycles every 128ms (A0~A8)*
Byte or word control for Read/Write operation (2CAS, 1W type)
* : Applicable to self refresh version (M5M44265CJ,TP-5S,-6S,-7S
: option) only
APPLICATION
PIN CONFIGURATION (TOP VIEW)
(5V)VCC
(5V)VCC
(5V)VCC
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
NC
NC
W
RAS
NC
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Outline 40P0K (400mil SOJ)
(5V)VCC
(5V)VCC
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
1
2
3
4
5
6
7
8
9
10
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
44
43
42
41
40
39
38
37
36
35
VSS(0V)
DQ16
DQ15
DQ14
DQ13
VSS(0V)
DQ12
DQ11
DQ10
DQ9
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
VSS(0V)
VSS(0V)
DQ16
DQ15
DQ14
DQ13
VSS(0V)
DQ12
DQ11
DQ10
DQ9
PIN DESCRIPTION
Pin name
A0~A8
DQ1~DQ16
RAS
LCAS
UCAS
W
OE
VCC
VSS
1
Address inputs
Data inputs / outputs
Row address strobe input
Lower byte control
column address strobe input
Upper byte control
column address strobe input
Write control input
Output enable input
Power supply (+5V)
Ground (0V)
Function
NC
NC
RAS
NC
A0
A1
A2
A3
(5V)VCC
13
14
15
W
16
17
18
19
20
21
22
32
31
30
29
28
27
26
25
24
23
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
VSS(0V)
Outline 44P3W-R (400mil TSOP Nomal Bend)
NC: NO CONNECTION
M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S
modify-write operations the M5M44265CJ, TP provides a number
of
of other functions, e.g., RAS-only refresh and delayed-write. The
input conditions for each are shown in Table 1.
STROBE INPUT
EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
FUNCTION
In addition to Hyper page mode, normal read, write and read-
Table 1 Input conditions for each mode
Operation
Lower byte read
Upper byte read
Word read
Lower byte write
Upper byte write
Word write
RAS only refresh
Hidden refresh
CAS before RAS (Extended*) refresh
Self refresh*
Stand-by
Note : ACT : active, NAC : nonactive, DNC : don' t care, OPN : open
RAS LCAS OE
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
NAC
Inputs
UCAS
ACT
NAC
ACT
ACT
NAC
ACT
NAC
NAC
ACT
ACT
NAC
ACT
ACT
NAC
ACT ACTACT DOUT
ACT
ACT
DNC
ACT
ACT
DNC
W
NAC
NAC
NAC
ACT
ACT
ACT
DNC
NAC
DNC
DNC
DNC
DQ1~DQ8 DQ9~DQ16
ACT
ACT
ACT
NAC
NAC
NAC
DNC
DOUT
OPN
DOUT
DIN
DNC
DIN
OPN
DNC OPN
DNC OPN
DNC
OPN
MITSUBISHI LSIs
Input/Output
OPN
DOUT
DOUT
DNC
DIN
DIN
OPN
DOUT
OPN
OPN
OPN
BLOCK DIAGRAM
ROW ADDRESS
LOWER BYTE CONTROL
UPPER BYTE CONTROL
STROBE INPUT
COLUMN ADDRESS
STROBE INPUT
COLUMN ADDRESS
WRITE CONTROL
INPUT
ADDRESS INPUTS
RAS
LCAS
UCAS
W
A0
A1
A2
A3
A4
A5
A6
A7
A8
ROW
&
COLU-
MN
ADDRESS
BUFF-
ER
A0~A8
A0~
A8
ROW
DECO
DER
CLOCK GENERATOR
CIRCUIT
COLUMN DECODER
SENSE REFRESH
AMPLIFIER & I /O CONTROL
MEMORY CELL
(4194304 BITS)
LOWER
UPPER
(8)LOWER
DATA IN
BUFFER
(8)LOWER
DATA OUT
BUFFER
(8) UPPER
DATA IN
BUFFER
(8)UPPER
DATA OUT
BUFFER
VCC (5V)
VSS (0V)
DQ1
DQ2
LOWER DATA
INPUTS / OUTPUTS
DQ8
VCC (5V)
VSS (0V)
DQ9
DQ10
UPPER DATA
INPUTS / OUTPUTS
DQ16
VCC (5V)
VSS (0V)
2
OUTPUT ENABLE
OE
INPUT
EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
V I
VO
I O
Pd
Topr
Tstg
Supply voltage
Input voltage
Output voltage
Output current
Power dissipation
Operating temperature
Storage temperature
Parameter Conditions Ratings Unit
MITSUBISHI LSIs
M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S
-1~7
With respect to VSS
Ta=25 C
-1~7
-1~7
50
1000
0~70
-65~150
V
V
V
mA
mW
˚C
˚C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VSS
VIH
VIL
Note 1 : All voltage values are with respect to VSS.
* *
Supply voltage
Supply voltage
High-level input voltage, all inputs
Low-level input voltage, all inputs
: VIL(min) is -2.0V when pulse width is less than 25ns. (Pulse width is with respect to Vss.)
ELECTRICAL CHARACTERISTICS
Symbol
VOH
VOL
IOZ
I I
ICC1(AV)
ICC2
ICC3(AV)
ICC4(AV)
ICC6(AV)
ICC8(AV)*
ICC9(AV)*
Note 2: Current flowing into an IC is positive, out is negative.
Note 3: ICC1 (AV), ICC3 (AV), ICC4 (AV), and ICC6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
Note 4: ICC1 (AV) and ICC4 (AV) are dependent on output loading. Specified values are obtained with the output open.
3
Note 5: Column Address can be changed once or less while RAS=VIL and CAS=VIH.
High-level output voltage
Low-level output voltage
Off-state output current
Input current
Average supply current
from Vcc, operating
Supply current from VCC, stand-by
Average supply current
from Vcc, RAS only
refresh mode
Average supply current
from Vcc
Hyper page mode
Average supply current
from Vcc
CAS before RAS refresh
mode
Average supply current
from VCC
Extended-refresh mode
Average supply current from VCC
Self-refresh mode
Parameter
Parameter
(Note 3,4,5)
(Note 3,5)
(Note 3,4,5)
(Note 3,5)
(Ta=0~70˚C, VCC=5V±10%, VSS=0V, unless otherwise noted) (Note 2)
M5M44265C-5,-5S
M5M44265C-6,-6S
M5M44265C-7,-7S
M5M44265C-5,-5S
M5M44265C-6,-6S
M5M44265C-7,-7S
M5M44265C-5,-5S
M5M44265C-6,-6S
M5M44265C-7,-7S
M5M44265C-5,-5S
M5M44265C-6,-6S
M5M44265C-7,-7S
(Ta=0~70˚C, unless otherwise noted) (Note 1)
Limits
Nom
(Note 6)
(Note 6)
(Note 6)
Min
4.5
0
2.4
-0.5**
IOH=-2mA
IOL=2mA
Q floating 0V ≤ VOUT ≤ 5.5V
0V ≤ VIN ≤ +6.0V, Other inputs pins=0V
RAS, CAS cycling
tRC=tWC=min.
output open
RAS= CAS =VIH, output open
RAS= CAS ≥ VCC -0.5V
output open
RAS cycling, CAS=VIH
tRC=min.
output open
RAS=VIL, CAS cycling
tPC=min.
output open
CAS before RAS refresh cycling
tRC=min.
output open
RAS cycling CAS ≤ 0.2V or CAS
before RAS refresh cycling
RAS ≤ 0.2V or ≥ VCC-0.2V
CAS ≤ 0.2V or ≥ VCC-0.2V
W ≤ 0.2V or ≥ VCC-0.2V
OE ≤ 0.2V or ≥ VCC-0.2V
A0~A8 ≤ 0.2V or ≥ VCC-0.2V
DQ=open
tRC=250µs, tRAS=tRAS min~1µs
RAS=CAS ≤ 0.2V
output open
Max
5.0
0
5.5
0
6.0
0.8
Test conditions
Unit
V
V
V
V
Min Max
2.4
0
-10
-10
Limits
Typ
VCC
0.4
10
10
125
110
95
1.0
0.1*
125
110
95
125
110
95
115
100
85
150
150
Unit
V
V
µA
µA
mA
2
mA
mA
mA
mA
µA
µA
MITSUBISHI LSIs
M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
CAPACITANCE
Symbol
CI (A)
CI (CLK)
CI / O
(Ta=0~70˚C, VCC=5V±10%, VSS=0V, unless otherwise noted)
Parameter Test conditions
Input capacitance, address inputs
Input capacitance, clock inputs
Input/Output capacitance, data ports
VI=VSS
f=1MHz
VI=25mVrms
Limits
Min Max
Typ
5
7
7
Unit
pF
pF
pF
SWITCHING CHARACTERISTICS (Ta=0~70˚C, VCC=5V±10%, VSS=0V, unless otherwise noted, see notes 6,14,15)
Limits
Symbol
tCAC
tRAC
tAA
tCPA
tOEA
tOHC
tOHR
tCLZ
tOEZ
tWEZ
tOFF
tREZ
Note 6: An initial pause of 500µs is required after power-up followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh
cycles).
Note the RAS may be cycled during the initial pause. And 8 initialization cycles are required after prolonged periods (greater than 8.2ms) of RAS
inactivity before proper device operation is achieved.
7: Measured with a load circuit equivalent to 1TTL and 50pF.
The reference levels for measuring of output signals are 2.0V(VOH) and 0.8V(VOL).
8: Assumes that tRCD ≥ tRCD(max) and tASC ≥ tASC(max) and tCP ≥ tCP(max).
9: Assumes that tRCD ≤ tRCD(max) and tRAD ≤ tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC
will increase by amount that tRCD exceeds the value shown.
10: Assumes that tRAD ≥ tRAD(max) and tASC ≤ tASC(max).
11: Assumes that tCP ≤ tCP(max) and tASC ≥ tASC(max).
12: tOEZ (max), tWEZ(max), tOFF(max) and tREZ(max) defines the time at which the output achieves the high impedance state (IOUT ≤ ±10µA ) and is not
reference to VOH(min) or VOL(max).
13: Output is disabled after both RAS and CAS go to high.
Access time from CAS
Access time from RAS
Columu address access time
Access time from CAS precharge
Access time from OE
Output hold time from CAS
Output hold time from RAS
Output low impedance time from CAS low
Output disable time after OE high
Output disable time after WE high
Output disable time after CAS high
Output disable time after RAS high
Parameter
(Note 7,8)
(Note 7,9)
(Note 7,10)
(Note 7,11)
(Note 7)
(Note 13)
(Note 13)
(Note 7)
(Note 12)
(Note 12)
(Note 12,13)
(Note 12,13)
M5M44265C-5,-5S M5M44265C-6,-6S M5M44265C-7,-7S
Min Max
Min Max Min Max
13
50
25
28
13
15
60
30
33
15
20
70
35
38
20
5 55
5 55
5
13
13
13
13
5
15
15
15
15
5
20
20
20
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
MITSUBISHI LSIs
CAS low pulse width
M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh and Hyper-Page Mode Cycles)
(Ta=0~70˚C, VCC=5V±10%, VSS=0V, unless otherwise noted, see notes 14,15)
Limits
Symbol
tREF
tREF
tRP
tRCD
tCRP
tRPC
tCPN
tRAD
tASR
tASC
tRAH
tCAH
tDZC
tDZO
tRDD 13
tCDD
tODD
tT
Note 14: The timing requirements are assumed tT=2ns.
15: VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
16: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is
controlled exclusively by tCAC or tAA.
17: tRAD(max) is specified as a reference point only. If tRAD ≥ tRAD(max) and tASC ≤ tASC(max), access time is controlled exclusively by tAA.
18: tASC(max) is specified as a reference point only. If tRCD ≥ tRCD(max) and tASC ≥ tASC(max), access time is controlled exclusively by tCAC.
19: Either tDZC or tDZO must be satisfied.
20: Either tRDD or tCDD or tODD must be satisfied.
21: tT is measured between VIH(min) and VIL(max).
Refresh cycle time
Refresh cycle time*
RAS high pulse width
Delay time, RAS low to CAS low
Delay time, CAS high to RAS low
Delay time, RAS high to CAS low
CAS high pulse width
Column address delay time from RAS low
Row address setup time before RAS low
Column address setup time before CAS low
Row address hold time after RAS low
Column address hold time after CAS low
Delay time, data to OE low
Delay time, RAS high to data
Delay time, CAS high to data
Delay time, OE high to data
Transition time
Parameter
(Note 16)
(Note 17)
(Note 18)
(Note 19)Delay time, data to CAS low
(Note 19)
(Note 20)
(Note 20)
(Note 20)
(Note 21)
M5M44265C-5,-5S
Min Max
30
18
5
0
8
13
0
0
8
8
0
0
13
13
1
M5M44265C-6,-6S
8.2
128
32
25
10
50
M5M44265C-7,-7S
Min Max Min Max
8.2 8.2
40
20
5
10
15
10
10
15
15
15
128
38
0
30
0
13
0
0
0
1
50
50
20
5
13
15
10
10
20
20
20
128
42
0
35
0
0
13
0
0
50
1
Unit
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read and Refresh Cycles
Symbol
tRC
tRAS
tCAS
tCSH
tRSH
tRCS
tRCH
tRRH
tRAL
tCAL
tORH
tOCH
Note 22: Either tRCH or tRRH must be satisfied for a read cycle.
5
Read cycle time
RAS low pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Read setup time before CAS low
Read hold time after CAS high
Read hold time after RAS high
Column address to RAS hold time
Column address to CAS hold time
RAS hold time after OE low
CAS hold time after OE low
Parameter
(Note 22)
(Note 22)
Limits
M5M44265C-5,-5S M5M44265C-6,-6S M5M44265C-7,-7S
Min Max
90
10000
50
8
10000
40
13
0
0
0
25
13
13
Min Max Min Max
110
10000
60
10
10000
48
15
0
0
0
30
18 23
15
15
130
70
13
55
20
0
35
20
20
10000
10000
0
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns13
ns
ns
EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
CAS low pulse width
Write Cycle (Early Write and Delayed Write)
Symbol
tWC
tRAS
tCAS
tCSH
tRSH
tWCS
tWCH
tCWL
tRWL
tWP
tDS
tDH
Write cycle time
RAS low pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Write setup time before CAS low
Write hold time after CAS low
CAS hold time after W low
RAS hold time after W low
Write pulse width
Data setup time before CAS low or W low
Data hold time after CAS low or W low
Parameter
MITSUBISHI LSIs
M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S
Limits
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note 24)
M5M44265C-5,-5S M5M44265C-6,-6S M5M44265C-7,-7S
Min Max
90
10000
50
10000
8
40
13
0
8
8
8
8
0
8
Min Max Min Max
110
60
10
48
15
10
10
10
10
10
10000
10000
0
0
130
70
13
55
20
13
13
13
13
13
10000
10000
0
0
Read-Write and Read-Modify-Write Cycles
Limits
Symbol
tRWC
tRAS
tCAS
tCSH
tRSH
tRCS
tCWD
tRWD
tAWD
tOEH
Note 23: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT.
24: tWCS, tCWD, tRWD and tAWD and tCPWD are specified as reference points only. If tWCS ≥ tWCS(min) the cycle is an early write cycle and the DQ pins
will remain high impedance throughout the entire cycle. If tCWD ≥ tCWD(min), tRWD ≥ tRWD(min), tAWD ≥ tAWD(min) and tCPWD ≥ tCPWD(min)
(for Hyper page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address.
If neither of the above condition (delayed write) of the DQ (at access time and until CAS or OE goes back to VIH) is indeterminate.
Read write/read modify write cycle time
RAS low pulse width
CAS low pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Read setup time before CAS low
Delay time, CAS low to W low
Delay time, RAS low to W low
Delay time, address to W low
OE hold time after W low
Parameter
(Note 23)
(Note 24)
(Note 24)
(Note 24)
M5M44265C-5,-5S M5M44265C-6,-6S M5M44265C-7,-7S
Min Max
109
10000
75
38
70
38
0
28
65
40
Min Max Min Max
133
10000
89
1000010000
44
82
44
0
32
77
47
1513 20
161
107
57
99
57
42
92
57
10000
10000
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6
MITSUBISHI LSIs
M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Hyper Page Mode Cycle
(Read, Early Write, Read-Write, Read-Modify-Write Cycle, Read Write Mix Cycle, Hi-Z control by OE or W) (Note 25)
ParameterSymbol Unit
tHPC
tHPRWC
tDOH
tRAS
tCP
tCPRH
tCPWD
tCHOL
tOEPE
tWPE
tHCWD
tHAWD
tHPWD
tHCOD
tHAOD
tHPOD
Note 25: All previously specified timing requirements and switching characteristics are applicable to their respective Hyper page mode cycle.
26: tHPC(min) is specified in the case of read-only and early write-only in Hyper page mode.
27: tRAS(min) is specified as two cycles of CAS input are performed.
28: tCP(max) is specified as a reference point only.
Hyper page mode read/write cycle time
Hyper page mode read write / read modify write cycle time
Output hold time from CAS low
RAS low pulse width for read or write cycle
CAS high pulse width
RAS hold time after CAS precharge
Delay time, CAS precharge to W low
Hold time to maintain the data Hi-Z until CAS access
OE pulse width (Hi-Z control)
W pulse width (Hi-Z control)
Delay time, CAS low to W low after read
Delay time, Address to W low after read
Delay time, CAS precharge to W low after read
Delay time, CAS low to OE high after read
Delay time, Address to OE high after read
Delay time, CAS precharge to OE high after read
(Note 26)
(Note 27)
(Note 28)
(Note 24)
M5M44265C-5,-5S M5M44265C-6,-6S M5M44265C-7,-7S
Min
20
57
65
28
43
7
7
28
40
43
13
25
28
5
8
7
Max
100000
13
Limits
Min Max Min Max
25
66
5 5
77
100000
10
16
33
50
7
7
7
32
47
50
15
30
33
30
79
92
13
38
60
7
7
42
57
60
20
35
38
100000
7
16
CAS before RAS Refresh Cycle (Note 29)
Limits
Symbol
tCSR
tCHR
tCAS
Note 29: Eight or more CAS before RAS cycles instead of eight RAS cycles are necessary for proper operation of CAS before RAS refresh mode.
CAS setup time before RAS low
CAS low pulse width
Parameter
M5M44265C-5,-5S
Min Max
5
10CAS hold time after RAS low
17 17
M5M44265C-6,-6S
Min Max Min Max
5
10
M5M44265C-7,-7S
5
15
22
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
Self Refresh Cycle* (Note 30)
tRASS
tRPS
tCHS
7
CBR self refresh RAS low pulse width
CBR self refresh RAS high precharge time
CBR self refresh CAS hold time
Limits
ParameterSymbol
M5M44265C-5,-5S
Min Max
100
90
-50
M5M44265C-6,-6S
Min Max Min Max
110
-50
M5M44265C-7,-7S
100100
130
-50
Unit
µs
ns
ns
Timing Diagrams (Note 31)
Read Cycle
MITSUBISHI LSIs
M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
tRC
RAS
LCAS/UCAS
A0~A8
W
DQ1~DQ16
(INPUTS)
DQ1~DQ16
(OUTPUTS)
OE
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VIH
VIL
tCRP
tASR
ADDRESS
ROW
tRAH
tRAD
Hi-Z
tRCD
tRCS
tRAC
tASC
ADDRESS
tDZC
tRAS
COLUMN
tDZO
tCAH
tAA
tCLZ
tCAC
tCSH
tOEA
tOEA
tRAL
tRSH
tCAS
tCAL
Hi-Z
tORH
tOCH
tOHR
DATA VALID
tREZ
tRP
tRPC
tCRP
tASR
ROW
ADDRESS
tRRH
tRCH
tCDD
tWEZ
tOFF
tOHC
Hi-Z
tOEZ
tODD
Note 31
8
Indicates the don't care input.
VIH(min) ≤ VIN ≤ VIH(max) or VIL(min) ≤ VIN ≤ VIL(max)
Indicates the invalid output.
Byte Read Cycle
MITSUBISHI LSIs
M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
tRC
tRAS
tRP
RAS
LCAS
(or UCAS)
UCAS
(or LCAS)
A0~A8
W
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
tCRP
tASR
ADDRESS
ROW
tRAH
tRAD
tRCD
tRCS
tASC
ADDRESS
tCSH
COLUMN
tCAH
tRAL
tCAL
tRSH
tCAS
tRPC
tCRP
tCPN
tASR
ROW
ADDRESS
tRRH
tRCH
DQ1~DQ8
(or DQ9~DQ16)
(INPUTS)
DQ1~DQ8
(or DQ9~DQ16)
(OUTPUTS)
DQ9~DQ16
(or DQ1~DQ8)
(INPUTS)
DQ9~DQ16
(or DQ1~DQ8)
(OUTPUTS)
OE
VIH
VIL
VOH
VOL
VIH
VIL
VOH
VOL
VIH
VIL
Hi-Z
tDZC
tRAC
tDZO
tAA
tCLZ
tCAC
Hi-Z
tOEA
Hi-Z
tOCH
tORH
tOHR
DATA VALID
tCDD
tREZ
tWEZ
tOFF
tOHC
Hi-Z
tOEZ
tODD
9
Early Write Cycle
MITSUBISHI LSIs
M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
tWC
tRAS
tRP
RAS
LCAS/UCAS
A0~A8
W
DQ1~DQ16
(INPUTS)
DQ1~DQ16
(OUTPUTS)
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
tCRP
tASR
ADDRESS
ROW
tRAH
tRCD
tASC
tWCS
tDS
tCSH
tCAH
COLUMN
ADDRESS
DATA VALID
tWCH
tDH
Hi-Z
tRSH
tCAS
tRPC
tCRP
tASR
ROW
ADDRESS
10
OE
VIH
VIL
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