Mitsubishi M5M44260CTP-7S, M5M44260CTP-7, M5M44260CTP-6S, M5M44260CTP-6, M5M44260CTP-5S Datasheet

This is a family of 262144-word by 16-bit dynamic RAMs,
fabricated with the high performance CMOS process, and is ideal
for memory systems where high speed, low power dissipation, and
low costs are essential.
The use of double-layer metalization process technology and a
single-transistor dynamic storage stacked capacitor cell provide
high circuit density at reduced costs. Multiplexed address inputs
permit both a reduction in pins and an increase in system
densities. Self or extended refresh current is small enough for
battery back-up application.
This device has 2CAS and 1W terminals with a refresh cycle of
512 cycles every 8.2ms.

CMOS Input level 550µW (Max) *
Operating power dissipation
M5M44260Cxx-5,-5S 688mW (Max)
M5M44260Cxx-6,-6S 605mW (Max)
M5M44260Cxx-7,-7S 523mW (Max)
Self refresh capability *
Self refresh current 150µA (Max)
Extended refresh capability
Extended refresh current 150µA (Max)
Fast-page mode (512-column random access), Read-modify-write,
RAS-only refresh, CAS before RAS refresh, Hidden refresh
capabilities.
Early-write mode, LCAS / UCAS and OE to control output buffer
impedance
512 refresh cycles every 8.2ms (A0~A8)
512 refresh cycles every 128ms (A0~A8) *
Byte or word control for Read/Write operation (2CAS, 1W type)
* : Applicable to self refresh version (M5M44260CJ,TP-5S,-6S,-7S
: option) only

MITSUBISHI LSIs

MITSUBISHI LSIs

M5M44260CJ,TP-5,-6,-7,

M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S

-5S,-6S,-7S

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

DESCRIPTION

FEATURES

Type name

M5M44260CXX-5,-5S

M5M44260CXX-6,-6S
M5M44260CXX-7,-7S

XX=J,TP

RAS

time

CAS

access

time

(max.ns)

access

(max.ns)

50 13 25
60

7015203035

Address

access

(max.ns)

time

OE

access

time

(max.ns)

13
15
20

(min.ns)

Standard 40pin SOJ, 44 pin TSOP (II)
Single 5V±10% supply
Low stand-by power dissipation
CMOS Input level 5.5mW (Max)

Power

Cycle

dissipa-

time

tion

(typ.mW)

90 625
110

550

130

475

PIN CONFIGURATION (TOP VIEW)

(5V)VCC

(5V)VCC

(5V)VCC

DQ1
DQ2

DQ3
DQ4

DQ5
DQ6
DQ7
DQ8

NC
NC

W

RAS

NC

A0
A1

A2
A3

1
2
3
4

5
6
7
8

9
10
11
12

13
14

15
16

17
18

19
20

40
39
38
37
36
35
34
33
32
31
30
29
28

27
26
25
24
23
22
21

VSS(0V)
DQ16

DQ15
DQ14
DQ13

VSS(0V)
DQ12
DQ11
DQ10
DQ9
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4

VSS(0V)

APPLICATION

Microcomputer memory, Refresh memory for CRT

PIN DESCRIPTION

Pin name

A0~A8

DQ1~DQ16
RAS

LCAS
UCAS

W
OE

VCC

VSS

1

M5M44260CJ,TP-5,-5S : Under development

Address inputs
Data inputs / outputs
Row address strobe input

Lower byte control
column address strobe input

Upper byte control
column address strobe input

Write control input
Output enable input
Power supply (+5V)
Ground (0V)

Function

Outline 40P0K (400mil SOJ)

(5V)VCC

(5V)VCC

(5V)VCC

DQ1
DQ2
DQ3

DQ4

DQ5
DQ6

DQ7
DQ8

NC
NC

RAS

NC

A0
A1

A2
A3

1

2

3

4

5

6

7

8

9
10

13
14
15

W

16
17
18
19
20
21
22

44
43

42
41
40
39

38
37

36
35

32
31
30

29
28
27
26
25
24
23

VSS(0V)
DQ16
DQ15

DQ14
DQ13
VSS(0V)

DQ12
DQ11
DQ10
DQ9

NC
LCAS
UCAS
OE

A8
A7
A6
A5

A4
VSS(0V)

Outline 44P3W-R (400mil TSOP Nomal Bend)

NC: NO CONNECTION

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

In addition to normal read,write and read-modify-write operations
the M5M44260CJ, TP provides a number of other functions, e.g.,

conditions for each are shown in Table 1.

STROBE INPUT

FUNCTION

Table 1 Input conditions for each mode

Operation

Lower byte read
Upper byte read
Word read
Lower byte write
Upper byte write
Word write
RAS only refresh
Hidden refresh

CAS before RAS (Extended *) refresh

Self refresh *
Stand-by

Note : ACT : active, NAC : nonactive, DNC : don' t care, OPN : open

RAS
ACT

ACT
ACT
ACT

ACT
ACT

ACT
ACT
ACT

ACT
NAC

LCAS

ACT
NAC
ACT
ACT
NAC
ACT
NAC

UCAS

NAC
ACT
ACT
NAC
ACT
ACT

NAC
ACT ACTACT DOUT
ACT
ACT
DNC

ACT

ACT

DNC

MITSUBISHI LSIs

M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S

fast page mode, RAS-only refresh and delayed-write. The input

Inputs

W
NAC
NAC
NAC
ACT
ACT
ACT
DNC
DNC
DNC
DNC
DNC

OE
ACT
ACT
ACT
NAC
NAC
NAC
DNC

Row

address

APD
APD
APD
APD
APD
APD
APD

DNC

DNC OPN
DNC OPN

DNC

DNC
DNC
DNC

Column
address

APD
APD
APD
APD
APD
APD
DNC
DNC
DNC
DNC
DNC

Input/Output

DQ1~

DQ8

DOUT
OPN

DOUT

DIN

DNC

DIN

OPN

OPN

DQ9~

DQ16

OPN
DOUT
DOUT

DNC

DIN
DIN

OPN
DOUT

OPN
OPN

OPN

Refresh

YES
YES
YES
YES
YES
YES
YES
YES
YES
YES

No

Remark

Fast
page
mode
identical

BLOCK DIAGRAM

ROW ADDRESS

LOWER BYTE CONTROL

UPPER BYTE CONTROL

STROBE INPUT

COLUMN ADDRESS

STROBE INPUT

COLUMN ADDRESS

WRITE CONTROL

INPUT

ADDRESS INPUTS

RAS

LCAS
UCAS

W

A0
A1
A2
A3
A4
A5
A6
A7
A8

ROW &

COLUMN

ADDRESS

BUFFER

A0~A8

A0~
A8

ROW

DECODER

CLOCK GENERATOR

CIRCUIT

COLUMN DECODER

SENSE REFRESH

AMPLIFIER & I /O CONTROL

MEMORY CELL
(4194304 BITS)

LOWER

UPPER

(8)LOWER

DATA IN
BUFFER

(8)LOWER
DATA OUT

BUFFER

(8)UPPER

DATA IN
BUFFER

(8)UPPER
DATA OUT

BUFFER

VCC (5V)

VSS (0V)

DQ1
DQ2

DQ8

VCC (5V)

VSS (0V)

DQ9
DQ10

DQ16

VCC (5V)

VSS (0V)

LOWER DATA
INPUTS /
OUTPUTS

UPPER DATA
INPUTS /
OUTPUTS

2

M5M44260CJ,TP-5,-5S : Under development

OUTPUT ENABLE

OE

INPUT

ABSOLUTE MAXIMUM RATINGS

Symbol
VCC
V I
VO
I O
Pd
Topr
Tstg

Supply voltage
Input voltage

Output voltage
Output current
Power dissipation
Operating temperature
Storage temperature

Parameter

MITSUBISHI LSIs

M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

Conditions

With respect to VSS

Ta=25˚C

Ratings

-1~7

-1~7

-1~7
50

1000
0~70

-65~150

Unit

V
V

V

mA

mW

˚C
˚C

RECOMMENDED OPERATING CONDITIONS

Symbol

VCC
VSS

VIH
VIL

Note 1 : All voltage values are with respect to VSS.

* *

Supply voltage
Supply voltage
High-level input voltage, all inputs
Low-level input voltage, all inputs

: VIL(min) is -2.0V when pulse width is less than 25ns. (Pulse width is with respect to Vss.)

ELECTRICAL CHARACTERISTICS

Symbol

VOH
VOL
IOZ
I I

ICC1(AV)

ICC2

ICC3(AV)

ICC4(AV)

ICC6(AV)

High-level output voltage
Low-level output voltage
Off-state output current

Input current
Average supply current

from Vcc, operating

Supply current from VCC, stand-by

Average supply current
from Vcc, RAS only
refresh mode

Average supply current
from Vcc
Fast page mode

Average supply current
from Vcc
CAS before RAS refresh
mode

Parameter

Parameter

(Note 3,4,5)

(Note 3,5)

(Note 3,4,5)

(Note 3,5)

(Ta=0~70˚C , VCC=5V±10%, VSS=0V, unless otherwise noted) (Note 2)

M5M44260C-5,-5S
M5M44260C-6,-6S
M5M44260C-7,-7S

M5M44260C-5,-5S
M5M44260C-6,-6S
M5M44260C-7,-7S
M5M44260C-5,-5S
M5M44260C-6,-6S
M5M44260C-7,-7S

M5M44260C-5,-5S
M5M44260C-6,-6S
M5M44260C-7,-7S

(Ta=0~70˚C, unless otherwise noted) (Note 1)

Min

4.5
0

2.4

-0.5 * *

IOH=-5mA
IOL=4.2mA
Q floating 0V ≤ VOUT ≤ 5.5V
0V ≤ VIN ≤ +6.0V, Other inputs pins=0V

RAS, CAS cycling
tRC=tWC=min.
output open

RAS= CAS =VIH, output open

(Note 6)

RAS= CAS ≥ VCC -0.5V
output open

RAS cycling, CAS=VIH
tRC=min.
output open

RAS=VIL, CAS cycling
tPC=min.
output open

CAS before RAS refresh cycling
tRC=min.
output open

Limits

Nom

Max

5.0
0

5.5
0

6.0

0.8

Test conditions

Unit

V
V
V

V

Limits

Typ

Min Max

2.4
0

-10

-10

VCC

0.4
10
10

125

110

95

1.0

0.1 *
125
110

95
125
110

95

115
100

85

Unit

V
V

µA
µA

mA

2

mA

mA

mA

mA

RAS cycling CAS ≤ 0.2V or CAS
before RAS refresh cycling

ICC8(AV) *

ICC9(AV) *

Note 2: Current flowing into an IC is positive, out is negative.
3: ICC1 (AV), ICC3 (AV), ICC4 (AV), and ICC6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
4: ICC1 (AV) and ICC4 (AV) are dependent on output loading. Specified values are obtained with the output open.
5: Column Address can be changed once or less while RAS=VIL and CAS=VIH.

3

M5M44260CJ,TP-5,-5S : Under development

Average supply current
from VCC
Extended-refresh mode

Average supply current from VCC
Self-refresh mode

(Note 6)

(Note 6)

RAS ≤ 0.2V or ≥ VCC-0.2V
CAS ≤ 0.2V or ≥ VCC-0.2V
W ≤ 0.2V or ≥ VCC-0.2V
OE ≤ 0.2V or ≥ VCC-0.2V
A0~A8 ≤ 0.2V or ≥ VCC-0.2V,
DQ=open
tRC=250µs, tRAS=tRAS min~1µs

RAS=CAS ≤ 0.2V
output open

150

150

µA

µA

MITSUBISHI LSIs

M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

CAPACITANCE

Symbol

CI (A)
CI (CLK)
CI / O

SWITCHING CHARACTERISTICS

Symbol

tCAC
tRAC

tAA
tCPA
tOEA
tCLZ
tOFF
tOEZ

Note 6: An initial pause of 500 µs is required after power-up followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh
cycles).
Note the RAS may be cycled during the initial pause. And 8 initialization cycles are required after prolonged periods (greater than 8.2ms) of RAS
inactivity before proper device operation is achieved.
7: Measured with a load circuit equivalent to 2TTL loads and 100pF.
8: Assumes that tRCD ≥ tRCD(max) and tASC ≥ tASC(max).
9: Assumes that tRCD ≤ tRCD(max) and tRAD ≤ tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC
will increase by amount that tRCD exceeds the value shown.
10: Assumes that tRAD ≥ tRAD(max) and tASC ≤ tASC(max).
11: Assumes that tCP ≤ tCP(max) and tASC ≥ tASC(max).
12: tOFF(max) and tOEZ (max) defines the time at which the output achieves the high impedance state (IOUT ≤ ±10 µA ) and is not reference to VOH(min)
or VOL(max).

(Ta=0~70˚C , VCC=5V±10%, VSS=0V, unless otherwise noted)

Parameter Test conditions

Input capacitance, address inputs
Input capacitance, clock inputs

Input/Output capacitance, data ports

(Ta=0~70˚C, VCC=5V±10%, Vss=0V, unless otherwise noted, see notes 6,13,14)

Parameter

Access time from CAS
Access time from RAS
Columu address access time
Access time from CAS precharge
Access time from OE
Output low impedance time from CAS low
Output disable time after CAS high
Output disable time after OE high

VI=VSS
f=1MHz
VI=25mVrms

(Note 7,8)

(Note 7,9)
(Note 7,10)
(Note 7,11)

(Note 7)

(Note 7)
(Note 12)
(Note 12)

Limits

Min Max

M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S

Min Max

13
50

25
30
13

5

13
13

Limits

Min Max Min Max

5

15
60

30
35

15

15
15

Typ

5
7

7

20
70

35
40
20

5

20
20

Unit

pF
pF
pF

Unit

ns
ns

ns
ns
ns

ns
ns

ns

4

M5M44260CJ,TP-5,-5S : Under development

MITSUBISHI LSIs

CAS low pulse width

Refresh cycle time

M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh and Fast-Page Mode Cycles)

(Ta=0~70˚C, VCC=5V±10%, VSS=0V, unless otherwise noted, see notes 6,13,14)

Limits

Symbol

tREF
tREF Refresh cycle time *

tRP
tRCD

tCRP
tRPC
tCPN

tRAD
tASR
tASC

tRAH
tCAH
tDZC
tDZO

tCDD
tODD
tT

Note 13: The timing requirements are assumed tT =5ns.
14: VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
15: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is
controlled exclusively by tCAC or tAA.
16: tRAD(max) is specified as a reference point only. If tRAD ≥ tRAD(max) and tASC ≤ tASC(max), access time is controlled exclusively by tAA.
17: tASC(max) is specified as a reference point only. If tRCD ≥ tRCD(max) and tASC ≥ tASC(max), access time is controlled exclusively by tCAC.
18: Either tDZC or tDZO must be satisfied.
19: Either tCDD or tODD must be satisfied.
20: tT is measured between VIH(min) and VIL(max).

RAS high pulse width
Delay time, RAS low to CAS low
Delay time, CAS high to RAS low
Delay time, RAS high to CAS low
CAS high pulse width
Column address delay time from RAS low
Row address setup time before RAS low
Column address setup time before CAS low

Row address hold time after RAS low
Column address hold time after CAS low

Delay time, data to OE low

Delay time, CAS high to data
Delay time, OE high to data
Transition time

Parameter

(Note 15)

(Note 16)

(Note 17)

(Note 18)Delay time, data to CAS low
(Note 18)
(Note 19)

(Note 19)
(Note 20)

M5M44260C-5,-5S

Min Max

8.2

128
30
18
5

10
13

13

13
13

37

0

25

0

7

0
8

0
0

50

1

M5M44260C-6,-6S

Min Max Min Max

40
20

5

0
10
15

0

0
10
15

0

0
15
15

1

M5M44260C-7,-7S

8.2 8.2

128

45

30

10

50

128

50
20

5

0

10
15

0

0
10
15

0

0
20
20

1

50

35

10

50

Unit

ms

ms

ns
ns

ns
ns
ns
ns
ns
ns

ns
ns

ns
ns

ns
ns
ns

Read and Refresh Cycles

Symbol

tRC
tRAS
tCAS

tCSH
tRSH
tRCS

tRCH
tRRH
tRAL
tOCH
tORH

Note 21: Either tRCH or tRRH must be satisfied for a read cycle.

Read cycle time
RAS low pulse width

CAS hold time after RAS low
RAS hold time after CAS low
Read setup time before CAS low
Read hold time after CAS high
Read hold time after RAS high

Column address to RAS hold time
CAS hold time after OE low
RAS hold time after OE low

Parameter

(Note 21)
(Note 21)

Limits

M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S

Min Max

90

10000

50
13

10000
50
13

0

0
0
25
13
13

Min Max Min Max
110

60
15

60
15

0
30
15
15

10000
10000

0
0

130

70
20

70
20

0
35
20
20

10000
10000

0
0

Unit

ns
ns

ns
ns

ns
ns
ns

ns
ns
ns
ns

5

M5M44260CJ,TP-5,-5S : Under development

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

CAS low pulse width

Write Cycle (Early Write and Delayed Write)

Symbol

tWC
tRAS

tCAS
tCSH

tRSH
tWCS
tWCH
tCWL

tRWL
tWP
tDS
tDH

tOEH

Write cycle time
RAS low pulse width

CAS hold time after RAS low
RAS hold time after CAS low
Write setup time before CAS low

Write hold time after CAS low
CAS hold time after W low
RAS hold time after W low
Write pulse width

Data setup time before CAS low or W low
Data hold time after CAS low or W low
OE hold time after W low

Parameter

MITSUBISHI LSIs

M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S

Limits

Unit

ns
ns
ns

ns
ns

ns
ns
ns

ns
ns
ns

ns
ns

(Note 23)

M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S

Min Max

90

10000

50

10000

13
50
13

0

8

13
13

8

0

8
13

Min Max Min Max

110

60
15

60

15

10
15
15
10

10
15

10000
10000

0

0

130

70
20
70
20

15
20
20
15

15
20

10000
10000

0

0

Read-Write and Read-Modify-Write Cycles

Limits

Symbol

tRWC
tRAS
tCAS

tCSH
tRSH
tRCS

tCWD
tRWD
tAWD

tCWL
tRWL
tWP
tDS
tDH
tOEH

Note 22: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT.

23: tWCS, tCWD, tRWD and tAWD and tCPWD are specified as reference points only. If tWCS ≥ tWCS(min) the cycle is an early write cycle and the DQ pins
will remain high impedance throughout the entire cycle. If tCWD ≥ tCWD(min), tRWD ≥ tRWD(min), tAWD ≥ tAWD(min) and tCPWD ≥ tCPWD(min)
(for fast page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address.
If neither of the above condition (delayed write) of the DQ (at access time and until CAS or OE goes back to VIH) is indeterminate.

Read write/read modify write cycle time
RAS low pulse width
CAS low pulse width

CAS hold time after RAS low
RAS hold time after CAS low
Read setup time before CAS low
Delay time, CAS low to W low
Delay time, RAS low to W low
Delay time, address to W low
CAS hold time after W low
RAS hold time after W low
Write pulse width
Data setup time before CAS low or W low
Data hold time after CAS low or W low
OE hold time after W low

Parameter

(Note 22)

(Note 23)
(Note 23)

(Note 23)

M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S

Min Max
126

10000

86
49
86

49

0

31
68

43
13

13

8
0

8

Min Max Min Max

150

10000

100

1000010000

55

100

55

0

35
80

50
15

15
10

0

10
1513 20

180
120

70

120

70

45
95

60
20

20
15

15

10000
10000

0

0

Unit

ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns

6

M5M44260CJ,TP-5,-5S : Under development

MITSUBISHI LSIs

M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

Fast-Page Mode Cycle (Read, Early Write, Read -Write, Read-Modify-Write Cycle) (Note 24)

Symbol

tPC
tPRWC
tRAS
tCP
tCPRH
tCPWD

Note 24: All previously specified timing requirements and switching characteristics are applicable to their respective fast page mode cycle.
25: tRAS(min) is specified as two cycles of CAS input are performed.
26: tCP(max) is specified as a reference point only.

Fast page mode read/write cycle time
Fast page mode read write/read modify write cycle time
RAS low pulse width for read or write cycle
CAS high pulse width
RAS hold time after CAS precharge

Delay time, CAS precharge to W low

Parameter

(Note 25)
(Note 26)

(Note 23)

M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S

Min

Max
35
71
85

100000

8

12
30
48

CAS before RAS Refresh Cycle, Extended Refresh Cycle * (Note 27)

Symbol

tCSR
tCHR
tCAS

Note 27: Eight or more CAS before RAS cycles instead of eight RAS cycles are necessary for proper operation of CAS before RAS refresh mode.

CAS setup time before RAS low

CAS low pulse width

Parameter

M5M44260C-5,-5S

Min Max

5

10CAS hold time after RAS low
20 20

Limits

Min Max Min Max

40
80

100

100000

10

15

35
55

Limits

M5M44260C-6,-6S

Min Max Min Max

5

10

45
95

115

10
40

65

M5M44260C-7,-7S

5
15
25

100000

15

Unit

ns
ns
ns
ns
ns
ns

Unit

ns
ns
ns

Self Refresh Cycle * (Note 28)

tRASS
tRPS

tCHS

CBR self refresh RAS low pulse width
CBR self refresh RAS high precharge time
CBR self refresh CAS hold time

Limits

ParameterSymbol

M5M44260C-5,-5S

Min Max

100

90

-50

M5M44260C-6,-6S

Min Max Min Max

110

-50

M5M44260C-7,-7S

100100
130

-50

Unit

µs

ns
ns

7

M5M44260CJ,TP-5,-5S : Under development

Timing Diagrams (Note 29)
Read Cycle

MITSUBISHI LSIs

M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

tRC

RAS

LCAS/UCAS

A0~A8

W

DQ1~DQ16
(INPUTS)

DQ1~DQ16
(OUTPUTS)

OE

VIH
VIL

VIH
VIL

VIH
VIL

VIH
VIL

VIH
VIL

VOH

VOL

VIH
VIL

tCRP

tASR

ADDRESS

ROW

tRAH

tRAD

Hi-Z

tRCD

tRCS

tDZC

tASC

tRAC

tRAS

tCSH

COLUMN

ADDRESS

tDZO

tCAH

tAA

tCLZ

tCAC

tCAS

tRAL

tOEA

tRSH

tOCH

Hi-Z

DATA VALID

tORH

tOFF

tOEZ

tRCH

tRPC

tCDD

tODD

tRP

tCRP

tASR

ROW

ADDRESS

tRRH

Hi-Z

8

M5M44260CJ,TP-5,-5S : Under development

Note 29

Indicates the don't care input.
VIH(min) ≤ VIN ≤ VIH(max) or VIL(min) ≤ VIN ≤ VIL(max)

Indicates the invalid output.

Byte Read Cycle

MITSUBISHI LSIs

M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

tRC

RAS

UCAS
(or LCAS)

LCAS
(or UCAS)

A0~A8

W

VIH
VIL

VIH
VIL

VIH
VIL

VIH
VIL

VIH
VIL

tCRP

tASR

ADDRESS

ROW

tRAH

tRAD

tRCD

tRCS

tASC

ADDRESS

tRAS

tCSH

COLUMN

tCAH

tCAS

tRAL

tRSH

tCPN

tRCH

tRPC

tRRH

tRP

tCRP

tASR

ROW

ADDRESS

DQ1~DQ8
(or DQ9~DQ16)
(INPUTS)

DQ1~DQ8
(or DQ9~DQ16)
(OUTPUTS)

DQ9~DQ16
(or DQ1~DQ8)
(INPUTS)

DQ9~DQ16
(or DQ1~DQ8)
(OUTPUTS)

OE

VIH
VIL

VOH

VOL

VIH
VIL

VOH

VOL

VIH
VIL

Hi-Z

tDZC

tRAC

tDZO

tAA

tCLZ

tCAC

Hi-Z

tOEA

Hi-Z

tOCH

DATA VALID

tORH

tCDD

tOFF

Hi-Z

tOEZ

tODD

9

M5M44260CJ,TP-5,-5S : Under development