Mitsubishi M5M29GT161BWG, M5M29GT160BWG, M5M29GB161BWG, M5M29GB160BWG Datasheet

MITSUBISHI LSIs

M5M29GB/T161BWG

16,777,216-BIT (1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

DESCRIPTION

The MITSUBISHI Mobile FLASH M5M29GB/T161BWG are 3.3V-only high speed 16,777,216-bit CMOS boot block Flash Memories with
alternating BGO (Back Ground Operation) feature. The BGO feature of the device allows Program or Erase operations to be performed in
one bank while the device simultaneously allows Read operations to be performed on the other bank. This BGO feature is suitable for
mobile and personal computing, and communication products. The M5M29GB/T161BWG are fabricated by CMOS technology for the
peripheral circuits and DINOR(Divided bit line NOR) architecture for the memory cells, and are available in 6x8-balls CSP (0.75mm ball
pitch) .

FEATURES

Organization 1048,576 word x 16bit

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(M5M29GB/T161BWG)

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Supply voltage

Access time 90ns (Max.)

................................ VCC = 2.7~3.6V

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Power Dissipation
Read 54 mW (Max. at 5MHz)
(After Automatic Power saving) 0.33µW (typ.)
Program/Erase 126 mW (Max.)
Standby 0.33µW (typ.)
Deep power down mode 0.33µW (typ.)

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Auto program for Bank(I)
Program Time 4ms (typ.)
Program Unit
(Byte Program) 1word
(Page Program) 128word
Auto program for Bank(II)
Program Time 4ms (typ.)
Program Unit 128word
Auto Erase
Erase time 40 ms (typ.)
Erase Unit
Bank(I) Boot Block 16Kword x 1
Parameter Block 16Kword x 7
Bank(II) Main Block 32Kword x 28

Program/Erase cycles 100Kcycles

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Boot Block
M5M29GB161BWG Bottom Boot
M5M29GT161BWG Top Boot

........................

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Other Functions
Soft Ware Command Control
Selective Block Lock
Erase Suspend/Resume
Program Suspend/Resume
Status Register Read
Alternating Back Ground Program/Erase Operation
Between Bank(I) and Bank(II)

Package
7mm x 8.5mm CSP (Chip Scale Package)

- 6 x 8 balls, 0.75mm ball pitch

APPLICATION

Digital Cellular Phone
Telecommunication
Mobile Computing Machine
PDA (Personal Digital Assistance)
Car Navigation System
Video Game Machine

PIN CONFIGURATION (TOP VIEW)

6
5

4
3
2

1

INDEX

1

8.5mm

A13 A11

A10

A14

A15 A12

A16

D14

NC

GND

D15

D7

A8

WE#

A9

D5

D13

D6

WP2#

RP#

NC NC

D11

D12

D4

WP1#

A18

D2

D3

VCC

A19

D10

D8

D9

A3A6

CE#

D0

D1 OE#

A4A7

A2A5A17

A1

A0

GND

AB CDEFGH

M5M29GB/T161BWG

CSP(0.75mm ball pitch):48FJA

16-bit version

NC : NO CONNECTION

7.0mm

Sep.1999. Rev4.0

MITSUBISHI LSIs

M5M29GB/T161BWG

16,777,216-BIT (1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

BLOCK DIAGRAM

ADDRESS

INPUTS

CHIP ENABLE INPUT

OUTPUT ENABLE INPUT

WRITE ENABLE INPUT
WRITE PROTECT INPUT
WRITE PROTECT INPUT

RESET/POWER DOWN INPUT

A19
A18
A17

A16
A15

A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2

A1
A0

CE#
OE#
WE#
WP1#
WP2#

RP#

X-DECODER

Y-DECODER

STATUS / ID REGISTER

CUI WSM

128 WORD PAGE BUFFER

Main Block 32KW

Bank(II)

28

Main Block 32KW

Parameter Block7 16KW
Parameter Block6 16KW

Bank(I)

Parameter Block5 16KW
Parameter Block4 16KW
Parameter Block3 16KW
Parameter Block2 16KW
Parameter Block1 16KW
Boot Block 16KW

Y-GATE / SENSE AMP.

MULTIPLEXER

INPUT/OUTPUT

BUFFERS

DQ14DQ13DQ12 DQ2DQ1DQ0DQ3

DQ15

DATA INPUTS/OUTPUTS

VCC (3.3V)
GND (0V)

M5M29GB/T161BWG (16 bit version)

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Sep.1999. Rev4.0

MITSUBISHI LSIs

M5M29GB/T161BWG

16,777,216-BIT (1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

FUNCTION

The M5M29GB/T161BWG includes on-chip program/erase control
circuitry. The Write State Machine (WSM) controls block erase
and byte/page program operations. Operational modes are
selected by the commands written to the Command User Interface
(CUI). The Status Register indicates the status of the WSM and
when the WSM successfully completes the desired program or
block erase operation.
A Deep Powerdown mode is enabled when the RP# pin is at GND,
minimizing power consumption.

Read

The M5M29GB/T161BWG has three read modes, which accesses
to the memory array, the Device Identifier and the Status Register.
The appropriate read command are required to be written to the
CUI. Upon initial device powerup or after exit from deep
powerdown, the M5M29GB/T161BWG automatically resets to read
array mode. In the read array mode, low level input to CE# and
OE#, high level input to WE# and RP#, and address signals to the
address inputs (A19-A0:M5M29GB/T161BWG) output the data of
the addressed location to the data input/output
(D15-D0:M5M29GB/T161BWG).

Write

Writes to the CUI enables reading of memory array data, device
identifiers and reading and clearing of the Status Register. They
also enable block erase and program. The CUI is written by
bringing WE# to low level, while CE# is at low level and OE# is at
high level. Address and data are latched on the earlier rising edge
of WE# and CE#. Standard micro-processor write timings are
used.

Deep Power-Down

When RP# is at VIL, the device is in the deep powerdown
mode and its power consumption is substantially low. During
read modes, the memory is deselected and the data
input/output are in a high-impedance(High-Z) state. After
return from powerdown, the CUI is reset to Read Array , and
the Status Register is cleared to value 80H.
During block erase or program modes, RP# low will abort
either operation. Memory array data of the block being altered
become invalid.

Automatic Power-Saving (APS)

The Automatic Power-Saving minimizes the power
consumption during read mode. The device automatically
turns to this mode when any addresses or CE# isn't changed
more than 200ns after the last alternation. The power
consumption becomes the same as the stand-by mode. While
in this mode, the output data is latched and can be read out.
New data is read out correctly when addresses are changed.

Alternating Background Operation (BGO)

The M5M29GB/T161BWG allows to read array from one bank
while the other bank operates in software command write cycling
or the erasing / programming operation in the background. Read
array operation with the other bank in BGO is performed by
changing the bank address without any additional command.
When the bank address points the bank in software command
write cycling or the erasing / programming operation, the data is
read out from the status register. The access time with BGO is the
same as the normal read operation.

Output Disable

When OE# is at VIH, output from the devices is disabled. Data
input/output are in a high-impedance(High-Z) state.

Standby

When CE# is at VIH, the device is in the standby mode and its
power consumption is reduced. Data input/output are in a
high-impedance(High-Z) state. If the memory is deselected
during block erase or program, the internal control circuits
remain active and the device consume normal active power
until the operation completes.

3

Sep.1999. Rev4.0

MITSUBISHI LSIs

M5M29GB/T161BWG

16,777,216-BIT (1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

SOFTWARE COMMAND DEFINITIONS

The device operations are selected by writing specific software
command into the Command User Interface.

Read Array Command (FFH)
The device is in Read Array mode on initial device power up and
after exit from deep powerdown, or by writing FFH to the
Command User Interface. After starting the internal operation the
device is set to the read status register mode automatically.

Read Device Identifier Command (90H)
It can normally read device identifier codes when Read Device
Identifier Code Command(90H) is written to the command latch.
Following the command write, the manufacturer code and the
device code can be read from address 0000H and 0001H,
respectively.

Read Status Register Command (70H)
The Status Register is read after writing the Read Status Register
command of 70H to the Command User Interface. Also, after
starting the internal operation the device is set to the Read Status
Register mode automatically.
The contents of Status Register are latched on the later falling
edge of OE# or CE#. So CE# or OE# must be toggled every status
read.

Clear Status Register Command (50H)
The Erase Status, Program Status and Block Status bits are set to
"1"s by the Write State Machine and can only be reset by the Clear
Status Register command of 50H. These bits indicates various
failure conditions.

C)Single Data Load to Page Buffer (74H)
/ Page Buffer to Flash (0EH/D0H)

Single data load to the page buffer is performed by writing 74H
followed by a second write specifying the column address and
data. Distinct data up to 128word can be loaded to the page
buffer by this two-command sequence. On the other hand, all of
the loaded data to the page buffer is programed simultaneously
by writing Page Buffer to Flash command of 0EH followed by the
confirm command of D0H. After completion of programing the
data on the page buffer is cleared automatically.
This command is valid for only Bank(I) alike Word Program.

Clear Page Buffer Command (55H)
Loaded data to the page buffer is cleared by writing the Clear
Page Buffer command of 55H followed by the Confirm command
of D0H. This command is valid for clearing data loaded by Single
Data Load to Page Buffer command.

Suspend/Resume Command (B0H/D0H)
Writing the Suspend command of B0H during block erase
operation interrupts the block erase operation and allows read out
from another block of memory. Writing the Suspend command of
B0H during program operation interrupts the program operation
and allows read out from another block of memory. The Bank
address is required when writing the Suspend/Resume Command.
The device continues to output Status Register data when read,
after the Suspend command is written to it. Polling the WSM
Status and Suspend Status bits will determine when the erase
operation or program operation has been suspended. At this
point, writing of the Read Array command to the CUI enables
reading data from blocks other than that which is suspended.
When the Resume command of D0H is written to the CUI,
the WSM will continue with the erase or program processes.

Block Erase / Confirm Command (20H/D0H)
Automated block erase is initiated by writing the Block Erase
command of 20H followed by the Confirm command of D0H. An
address within the block to be erased is required. The WSM
executes iterative erase pulse application and erase verify
operation.

Program Commands

A)Word Program (40H)

Word program is executed by a two-command sequence. The
Word Program Setup command of 40H is written to the
Command Interface, followed by a second write specifying the
address and data to be written. The WSM controls the program
pulse application and verify operation. The Word Program
Command is Valid for only Bank(I).

B)Page Program for Data Blocks (41H)

Page Program for Bank(I) and Bank(II) allows fast programming of
128words of data. Writing of 41H initiates the page program
operation for the Data area. From 2nd cycle to 129th cycle , write
data must be serially inputted. Address A6-A0 have to be
incremented from 00H to 7FH. After completion of data loading, the
WSM controls the program pulse application and verify operation.

DATA PROTECTION

The M5M29GB/T161BWG provides selectable block locking of
memory blocks. Each block has an associated nonvolatile lock-bit
which determines the lock status of the block. In addition, the
M5M29GB/T161BWG have a master Write Protect pin (WP1# &
WP2#) which prevents any modifications to memory blocks whose
lock-bits are set to "0", when WP1# or WP2# is low. When WP1#
& WP2# are high , all blocks can be programmed or erased
regardless of the state of the lock-bits, and the lock-bits are
cleared to "1" by erase. See the BLOCK LOCKING table on P.9 for
details.

Power Supply Voltage

When the power supply voltage (Vcc) is less than V
Lock-Out voltage, the device is set to the Read-only mode.
Regarding DC electrical characteristics of V
A delay time of 2 us is required before any device operation is
initiated. The delay time is measured from the time Vcc reaches
Vccmin (2.7V).
During power up, RP#=GND is recommended. Falling in Busy
status is not recommended for possibility of damaging the device.

MEMORY ORGANIZATION

The M5M29GB/T161BWG has one 16Kword boot block, seven
16Kword parameter blocks, for Bank(I) and twenty-eight 32Kword
main blocks for Bank(II). A block is erased independently of other
blocks in the array.

LKO, see P.9

LKO, Low VCC

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Sep.1999. Rev4.0

Mitsubishi 16M Flash Memory Type name

M 5 M 29G T 160B WG

Operating Voltage :
29G : 2.7 - 3.6V
Standard / BGO Type

29W : 1.65 - 2.2V
Standard / BGO Type

Boot Block :
T : Top Boot
B : Bottom Boot

Density/Write Protect/
Word Organizetion:

160B : 16M WP1#, x8/x16
161B : 16M WP1# & WP2#, x16

MITSUBISHI LSIs

M5M29GB/T161BWG

16,777,216-BIT (1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

Package :
VP : 48pin TSOP(I) 12mm x 20mm (Nomal Pinout)
WG: CSP Ball Pitch 0.75mm,6x8 array, 7mm x 8.5mm

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Sep.1999. Rev4.0

MEMORY ORGANIZATION

MITSUBISHI LSIs

M5M29GB/T161BWG

16,777,216-BIT (1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

x16 ( Wordmode)

F8000H-FFFFFH

F0000H-F7FFFH

E8000H-EFFFFH

E0000H-E7FFFH

D8000H-DFFFFH

D0000H-D7FFFH

C8000H-CFFFFH

C0000H-C7FFFH

B8000H-BFFFFH

B0000H-B7FFFH

A8000H-AFFFFH

A0000H-A7FFFH

98000H-9FFFFH

90000H-97FFFH

88000H-8FFFFH

80000H-87FFFH

78000H-7FFFFH

70000H-77FFFH

68000H-6FFFFH

60000H-67FFFH

58000H-5FFFFH

50000H-57FFFH

48000H-4FFFFH

40000H-47FFFH

38000H-3FFFFH

30000H-37FFFH

28000H-2FFFFH

20000H-27FFFH

1C000H-1FFFFH

18000H-1BFFFH

14000H-17FFFH

10000H-13FFFH

0C000H-0FFFFH

08000H-0BFFFH

04000H-07FFFH

00000H-03FFFH

A19-A0
(M5M29GB161BWG)

32Kword MAIN BLOCK 35
32Kword MAIN BLOCK 34
32Kword MAIN BLOCK 33
32Kword MAIN BLOCK 32
32Kword MAIN BLOCK 31
32Kword MAIN BLOCK 30
32Kword MAIN BLOCK 29
32Kword MAIN BLOCK 28
32Kword MAIN BLOCK 27
32Kword MAIN BLOCK 26
32Kword MAIN BLOCK 25
32Kword MAIN BLOCK 24
32Kword MAIN BLOCK 23
32Kword MAIN BLOCK 22
32Kword MAIN BLOCK 21

32Kword MAIN BLOCK 20
32Kword MAIN BLOCK 19
32Kword MAIN BLOCK 18
32Kword MAIN BLOCK 17
32Kword MAIN BLOCK 16
32Kword MAIN BLOCK 15
32Kword MAIN BLOCK 14
32Kword MAIN BLOCK 13

32Kword MAIN BLOCK 12
32Kword MAIN BLOCK 11
32Kword MAIN BLOCK 10
32Kword MAIN BLOCK 9
32Kword MAIN BLOCK 8

16Kword PARAMETER BLOCK 7
16Kword PARAMETER BLOCK 6

16Kword PARAMETER BLOCK 5

16Kword PARAMETER BLOCK 4
16Kword PARAMETER BLOCK 3
16Kword PARAMETER BLOCK 2
16Kword PARAMETER BLOCK 1

16Kword BOOT BLOCK 0

M5M29GB161BWG Memory Map

BANK(II)

BANK(I)

x16 ( Wordmode)

FC000H-FFFFFH

F8000H-FBFFFH

F4000H-F7FFFH

F0000H-F3FFFH

EC000H-EFFFFH

E8000H-EBFFFH

E4000H-E7FFFH

E0000H-E3FFFH

D8000H-DFFFFH

D0000H-D7FFFH

C8000H-CFFFFH

C0000H-C7FFFH

B8000H-BFFFFH

B0000H-B7FFFH

A8000H-AFFFFH

A0000H-A7FFFH

98000H-9FFFFH

90000H-97FFFH

88000H-8FFFFH

80000H-87FFFH

78000H-7FFFFH

70000H-77FFFH

68000H-6FFFFH

60000H-67FFFH

58000H-5FFFFH

50000H-57FFFH

48000H-4FFFFH

40000H-47FFFH

38000H-3FFFFH

30000H-37FFFH

28000H-2FFFFH

20000H-27FFFH

18000H-1FFFFH

10000H-17FFFH

08000H-0FFFFH

00000H-07FFFH

19-A0

A
(M5M29GT161BWG)

16Kword BOOT BLOCK 35

16Kword PARAMETER BLOCK 34

16Kword PARAMETER BLOCK 33
16Kword PARAMETER BLOCK 32

16Kword PARAMETER BLOCK 31
16Kword PARAMETER BLOCK 30

16Kword PARAMETER BLOCK 29
16Kword PARAMETER BLOCK 28

32Kword MAIN BLOCK 27
32Kword MAIN BLOCK 26
32Kword MAIN BLOCK 25
32Kword MAIN BLOCK 24
32Kword MAIN BLOCK 23
32Kword MAIN BLOCK 22
32Kword MAIN BLOCK 21
32Kword MAIN BLOCK 20

32Kword MAIN BLOCK 19
32Kword MAIN BLOCK 18
32Kword MAIN BLOCK 17
32Kword MAIN BLOCK 16
32Kword MAIN BLOCK 15
32Kword MAIN BLOCK 14
32Kword MAIN BLOCK 13
32Kword MAIN BLOCK 12
32Kword MAIN BLOCK 11
32Kword MAIN BLOCK 10
32Kword MAIN BLOCK 9
32Kword MAIN BLOCK 8
32Kword MAIN BLOCK 7
32Kword MAIN BLOCK 6
32Kword MAIN BLOCK 5
32Kword MAIN BLOCK 4
32Kword MAIN BLOCK 3
32Kword MAIN BLOCK 2
32Kword MAIN BLOCK 1

32Kword MAIN BLOCK 0

M5M29GT161BWG Memory Map

BANK(I)

BANK(II)

6

Sep.1999. Rev4.0

BUS OPERATIONS

Bus Operations for Word-Wide Mode (M5M29GB/T161BWG)

MITSUBISHI LSIs

M5M29GB/T161BWG

16,777,216-BIT (1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

Mode

Array

Read

Output disable
Stand by

Write

Deep Power Down

1) X can be VIH or VIL for control pins.

Status Register
Lock Bit Status VIL VIL
Identifier Code

Program
Erase
Others

Pins

CE# OE# WE#

V

IL

VIL

VIL
VIL
VIH
VIL
VIL

IL VIH

V

X

VIL
VIL

VIL
VIH

V
VIH

VIH
VIH
VIH
VIH

1)

X

IH

X

VIH

X
V
VIL
V

X Hi-Z

DQ

RP#

IH

V
VIH
VIH
VIH
VIH
VIH

IL

IL

VIH
VIH
V
VIL

IH

Status Register Data

Lock Bit Data (DQ6)

Command/Data in

0-15

Data out

Identifier Code

Hi-Z
Hi-Z

Command
Command

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Sep.1999. Rev4.0