MITSUBISHI 7477 Technical data
查询7477 GROUP供应商查询7477 GROUP供应商
DESCRIPTION
The 7477/7478 group is the single-chip microcomputer designed
with CMOS silicon gate technology.
The single-chip microcomputer is useful for business equipment
and other consumer applications.
In addition to its simple instruction set, the ROM, RAM, and I/O
addresses are placed on the same memory map to enable easy
programming.
In addition, built-in PROM type microcomputers with built-in electrically writable PROM, and additional functions equivalent to the
mask ROM version are also available.
7477/7478 group products are shown noted below.
The 7477 and the 7478 differ in the number of I/O ports, package
outline, and clock generating circuit only.
Product
M37477M4-XXXSP/FP
M37477M8-XXXSP/FP
M37477E8SP/FP
M37477E8-XXXSP/FP
M37478M4-XXXSP/FP
M37478M8-XXXSP/FP
M37478E8SP/FP
M37478E8-XXXSP/FP
M37478E8SS
Mask ROM version
One Time PROM version
(Built-in PROM type microcomputers)
Mask ROM version
One Time PROM version
(Built-in PROM type microcomputers)
PROM version
(Built-in PROM type microcomputer)
FEATURES
●Basic machine-language instructions ......................................71
●Memory size
ROM.............................. 8192 bytes (M37477M4, M37478M4)
RAM ................................ 192 bytes (M37477M4, M37478M4)
●The minimum instruction execution time
......................................0.5µs (at 8MHz oscillation frequency)
●Power source voltage
.......... 2.7 to 4.5V (at 2.2VCC – 2.0MHz oscillation frequency)
............................. 4.5 to 5.5V (at 8MHz oscillation frequency)
●Power dissipation in normal mode
.................................... 35mW (at 8MHz oscillation frequency)
●Subroutine nesting
.................................96 levels max. (M37477M4, M37478M4)
●Interrupt ................................................... 13 sources, 11 vectors
●8-bit timers ................................................................................. 4
●Programmable I/O ports
(Ports P0, P1, P4) .......................................... 18 (7477 group)
●Input ports (Ports P2, P3) .................................... 8 (7477 group)
(Ports P2, P3, P5) ............................16 (7478 group)
●8-bit serial I/O ........................... 1 (UART or clock-synchronized)
●8-bit A-D converter ................................ 4 channels (7477 group)
Version
20 (7478 group)
8 channels (7478 group)
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN CONFIGURATION (TOP VIEW)
P17/SRDY
P16/SCLK
P15/TXD
P1
4/RXD
P1
3/T1
P12/T0
P11
P10
P23/IN3
P22/IN2
P21/IN1
P20/IN0
VREF
XIN
XOUT
VSS
1
2
3
4
5
M37477E8-XXXSP
6
7
8
9
10
11
12
13
14
15
16
Outline 32P4B
P17/SRDY
P16/SCLK
P15/TXD
P1
4/RXD
P1
3/T1
P12/T0
P11
P10
P23/IN3
P22/IN2
P21/IN1
P20/IN0
VREF
XIN
XOUT
VSS
1
2
3
4
5
M37477E8-XXXFP
6
7
8
9
10
11
12
13
14
15
16 17
Outline 32P2W-A
Note : The only differences between the 32P4B package prod-
uct and the 32P2W-A package product are package
shape and absolute maximum ratings.
APPLICATIONS
Audio-visual equipment, VCR, Tuner,
Office automation equipment
32
P07
31
P06
30
P05
29
P04
28
27
26
25
24
23
22
21
20
19
18
17
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
P03
P02
P01
P00
P41
P40
P33/CNTR1
P32/CNTR0
P31/INT1
P30/INT0
RESET
CC
V
P07
P06
P05
P04
P03
P02
P01
P00
P41
P40
P33/CNTR1
P32/CNTR0
P31/INT1
P30/INT0
RESET
CC
V
M37477M4-XXXSP
M37477M8-XXXSP
M37477M4-XXXFP
M37477M8-XXXFP
PIN CONFIGURATION (TOP VIEW)
P5
3
P17/
S
RDY
P16/S
CLK
P15/TXD
P1
4/RX
D
P1
3/T1
P12/T
0
P1
1
P1
0
P27/IN
7
P26/IN
6
P25/IN
5
P24/IN
4
P23/IN
3
P22/IN
2
P21/IN
1
P20/IN
0
V
REF
X
IN
X
OUT
V
SS
Outline 42P4B
1
2
3
4
5
6
7
M37478E8-XXXSP
M37478E8SS
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42S1B-A (Window)
42
P5
41
P0
40
P0
39
P0
38
P0
37
P0
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P0
P0
P0
P4
P4
P4
P4
P33/CNTR
P32/CNTR
P31/INT
P30/INT
RESET
P51/X
P50/X
V
CC
M37478M4-XXXSP
M37478M8-XXXSP
2
7
6
5
4
3
2
1
0
3
2
1
0
COUT
CIN
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
0
1
1
0
/INT
/CNTR
/INT
/CNTR
2
/IN
2
P2
2
P3
32
13
1
/IN
1
P2
1
P3
31
14
0
/IN
0
P2
0
P3
30
15
REF
V
NC
29
16
NC
28
RESET
27
NC
26
P51/X
P50/X
NC
V
CC
V
SS
AV
SS
NC
X
OUT
X
IN
NC
COUT
CIN
25
24
23
22
21
20
19
18
17
3
4
2
P0
P0
NC
P0
43
41
42
44
45
NC
NC
RDY
CLK
NC
46
5
47
6
48
7
49
2
50
51
SS
52
3
53
54
55
56
1
NC
M37478M4-XXXFP
M37478M8-XXXFP
M37478E8-XXXFP
4
3
2
0
1
D
X
/T
/T
2
3
/R
4
P1
P1
P1
P0
P0
P0
P5
V
P5
7
/
S
P1
1
P16/S
0
1
0
P15/TXD
40
5
1
P0
1
P1
0
P0
39
6
0
P1
3
P4
38
7
7
/IN
7
P2
2
P4
37
8
6
/IN
6
P2
36
9
1
P4
5
/IN
5
P2
0P33
P4
NC
35
34
10
11
3
4
/IN
/IN
4
3
P2
P2
33
12
Outline 56P6N-A
Note : The only differences between the 42P4B package product and the 56P6N-A package product are package shape, ab-
solute maximum ratings and the fact that the 56P6N-A package product has an AVSS pin.
2
decoder
signal
Control
Instruction
Instruction register(8)
control
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
25
26
27
28
P0
P0(8)
29
I/O port
30
31
32
M37477M4-XXXSP/FP BLOCK DIAGRAM
input
Reset
Clock
output
input
Clock
SS
V
CC
V
RESET
OUT
X
IN
X
Data bus
16
17
18
15
14
(8)
Timer 1
1)
(Note
8192
bytes
(P)ROM
(8)
L
PC
counter
Program
(8)
H
PC
counter
Program
2)
(Note
192
RAM
bytes
circuit
Clock generating
Timer 2(8)
(8)
Timer 3
S(8)
Stack
pointer
Y(8)
Index
register
X(8)
Index
register
status
register
Processor
A(8)
lator
Accumu-
unit
8-bit
Arithmetic
and logical
PS(8)
PWM
(8)
Timer 4
S I/O(8)
4
A-D converter
0
1
INT
INT
0
CNTR
1
CNTR
P1(8)
(4)
P2
P3(4)
(2)
P4
8
7
6
5
P1
4
I/O port
3
2
1
12
11
P2
10
Input port
9
3
REF
1
V
Reference voltage input
19
20
21
P3
22
Input port
23
P4
24
I/O port
2 : 384 bytes for M37477M8/E8-XXXSP/FP
Notes 1 : 16384 bytes for M37477M8/E8-XXXSP/FP
3
Control signal
Instruction decoder
Instruction register(8)
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
34
35
36
37
P0(8)
38
39
40
41
I/O port P0
Main clock
M37478M4-XXXSP BLOCK DIAGRAM
SS
V
CC
V
input
Reset
RESET
OUT
X
output
IN
X
input
Main clock
Data bus
21
22
25
20
19
Timer 1(8)
(Note 1)
8192
bytes
(P)ROM
(8)
L
PC
counter
Program
(8)
H
PC
counter
Program
(Note 2)
192
RAM
bytes
COUT
X
Sub-clock
circuit
CIN
Clock generating
X
Sub-clock
output
input
Timer 2(8)
Timer 3(8)
S(8)
Stack
pointer
Y(8)
Index
register
X(8)
Index
register
PS(8)
status
register
Processor
A(8)
lator
Accumu-
unit
8-bit
Arithmetic
and logical
PWM control
Timer 4(8)
S I/O(8)
8
A-D converter
0
INT
1
INT
0
CNTR
1
CNTR
CIN
X
COUT
X
P1(8)
P2(8)
P3(4)
P4(4)
P5(4)
9
8
7
6
5
4
I/O port P1
3
2
17
16
15
14
13
12
Input port P2
11
10
REF
18
V
Reference voltage input
26
27
28
29
Input port P3
30
31
32
33
I/O port P4
23
24
42
1
Input port P5
Notes 1 : 16384 bytes for M37478M8/E8-XXXSP, M37478E8SS
2 : 384 bytes for M37478M8/E8-XXXSP, M37478E8SS
4
Control signal
Instruction decoder
Instruction register(8)
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
39
40
41
42
P0(8)
43
46
47
48
I/O port P0
M37478M4-XXXFP BLOCK DIAGRAM
21
AVSS
VSS
22
23
VCC
input
Reset
RESET
OUT
X
output
Main clock
IN
18
X
input
Main clock
Data bus
51
28
19
Timer 1(8)
(Note 1)
8192
bytes
(P)ROM
L(8)
PC
counter
Program
H(8)
PC
counter
Program
(Note 2)
192
RAM
bytes
XCOUT
Sub-clock
circuit
CIN
Clock generating
X
Sub-clock
output
input
Timer 2(8)
Timer 3(8)
S(8)
Stack
pointer
Y(8)
Index
register
X(8)
Index
register
PS(8)
status
register
Processor
A(8)
lator
Accumu-
unit
8-bit
Arithmetic
and logical
PWM control
Timer 4(8)
S I/O(8)
8
A-D converter
INT0
INT1
CNTR0
CNTR1
XCIN
XCOUT
P1(8)
P2(8)
P3(4)
P4(4)
P5(4)
6
5
4
3
2
55
I/O port P1
54
53
14
13
12
11
10
9
Input port P2
8
7
REF
15
V
Reference voltage input
30
31
32
33
Input port P3
35
36
37
38
I/O port P4
25
26
49
52
Input port P5
Notes 1 : 16384 bytes for M37478M8/E8-XXXFP
2 : 384 bytes for M37478M8/E8-XXXFP
5
FUNCTIONS OF 7477/7478 GROUP
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Parameter
Basic machine-language instructions
Instruction execution time
Clock input oscillation frequency
M37477M4
Memory size
Input/Output port
Serial I/O
Timers
A-D converter
Subroutine nesting
Interrupt
Clock generating circuit
Power source circuit
Power dissipation
Input/Output characters
Operating temperature range
Device structure
Package
M37478M4
M37477M8/E8
M37478M8/E8
P0, P1
P2
P3, P5
P4
M37477M4, M37478M4
M37477M8/E8, M37478M8/E8
Input/Output voltage
Output current
M37477M4/M8/E8-XXXSP
M37477M4/M8/E8-XXXFP
M37478M4/M8/E8-XXXSP
M37478M4/M8/E8-XXXFP
M37478E8SS
ROM
RAM
(P)ROM
RAM
I/O
Input
Input
I/O
Functions
71
0.5µs (The minimum instructions, at 8 MHz oscillation frequency)
8 MHz (max.)
8192 bytes
192 bytes
16384 bytes
384 bytes
8-bit ✕ 2
8-bit ✕ 1 (4-bit ✕ 1 for the 7477 group)
4-bit ✕ 2 (Port P5 is not included in the 7477 group)
4-bit ✕ 1 (2-bit ✕ 1 for the 7477 group)
8-bit ✕ 1
8-bit timer ✕ 4
8-bit ✕ 1 (8 channels) (8-bit ✕ 1 (4 channels) for the 7477 group)
96 (max.)
192 (max.)
5 external interrupts, 7 internal interrupts, 1 software interrupt
Built-in circuit with internal feedback resistor (a ceramic or a quartz-
crystal oscillator)
2.7 to 4.5V (at 2.2VCC–2.0MHz oscillation frequency), 4.5 to 5.5V
(at 8MHz oscillation frequency)
35mW (at 8MHz oscillation frequency)
5V
–5 to 10mA (P0, P1, P4 : CMOS tri-states)
–20 to 85°C
CMOS silicon gate
32-pin shrink plastic molded DIP
32-pin plastic molded SOP
42-pin shrink plastic molded DIP
56-pin plastic molded QFP
42-pin ceramic DIP
6
PIN DESCRIPTION
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Pin Name Functions
VCC, VSS
AVSS
(Note 1)
RESET
XIN
XOUT
VREF
P00 – P07
P10 – P17
P20 – P27
(Note 2)
P30 – P33
P40 – P43
(Note 3)
P50 – P53
(Note 4)
Notes 1 : AV
2 : Only P20–P23 (IN0–IN3) 4-bit for the 7477 group.
3 : Only P40 and P41 2-bit for the 7477 group.
4 : This port is not included in the 7477 group.
Power source
Analog power
source
Reset input
Clock input
Clock output
Reference voltage
input
I/O port P0
I/O port P1
Input port P2
Input port P3
I/O port P4
Input port P5
SS for M37478M4/M8/E8-XXXFP.
Input/
Output
Input
Input
Output
Input
I/O
I/O
Input
Input
I/O
Input
Apply voltage of 2.7 to 5.5V to VCC, and 0V to VSS.
Ground level input pin for A-D converter.
Same voltage as VSS is applied.
To enter the reset state, the reset input pin must be kept at “L” for 2µs or more
(under normal VCC conditions).
These are I/O pins of internal clock generating circuit for main clock. To
control generating frequency, an external ceramic or a quartz crystal oscillator
is connected between the X
clock source should be connected the XIN pin and the XOUT pin should be left
open. Feedback resistor is connected between XIN and XOUT.
Reference voltage input pin for A-D converter.
Port P0 is an 8-bit I/O port. The output structure is CMOS output.
When this port is selected for input, pull-up transistor can be connected in
units of 1-bit and a key on wake up function is provided.
Port P1 is an 8-bit I/O port. The output structure is CMOS output.
When this port is selected for input, pull-up transistor can be connected in
units of 4-bit. P1
P14, P15, P16 and P17 are in common with serial I/O pins RXD, TXD, SCLK
____
and SRDY, respectively .
Port P2 is an 8-bit input port.
This port is in common with analog input pins IN0 to IN7.
Port P3 is a 4-bit input port. P30, P31 are in common with external interrupt
input pins INT0, INT1, and P32, P33 are in common with timer input pins
CNTR0, CNTR1.
Port P4 is a 4-bit I/O port. The output structure is CMOS output, When this
port is selected for input, pull-up transistor can be connected in units of 4-bit.
Port P5 is a 4-bit input port and pull-up transistor can be connected in units of
4-bit. P50, P51 are in common with input/output pins of clock for clock function
XCIN, XCOUT. When P50, P51 are used as XCIN, XCOUT, connect a ceramic or a
quartz crystal oscillator between XCIN and XCOUT. If an external clock input is
used, connect the clock input to the XCIN pin and open the XCOUT pin.
Feedback resistor is connected between XCIN and XCOUT pins.
2 and P13 are in common with timer output pins T0 and T1.
IN and XOUT pins. If an external clock is used, the
7
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
The 7477/7478 group uses the standard 740 family instruction set.
Refer to the table of 740 family addressing modes and machine instructions or the SERIES 740 <Software> User’s Manual for
details on the instruction set.
Machine-resident 740 family instructions are as follows:
The FST and SLW instruction cannot be used.
The MUL, DIV, WIT, and STP instruction can be used.
b7
CPU Mode Register
The CPU mode register is allocated at address 00FB16.
This register contains the stack page selection bit.
b0
CPU mode register (Address 00FB16)
These bits must always be set to “0”.
Stack page selection bit (Note 1)
0 : In page 0 area
1 : In page 1 area
Notes 1 : In the M37477M4-XXXSP/FP, M37478M4-XXXSP/FP, set this bit to “0”.
2 : In the 7477 group, set this bit to “0”.
Fig. 1 Structure of CPU mode register
0
, P51/X
CIN
, X
COUT
P5
0 : P5
1 : X
X
0 : Low
1 : High
Clock (XIN-X
0 : Oscillates
1 : Stops
Internal system clock selection bit (Note 2)
0 : X
1 : X
0
, P5
1
CIN
, X
COUT
COUT
drive capacity selection bit (Note 2)
OUT
IN-XOUT
CIN-XCOUT
selection bit (Note 2)
) stop bit (Note 2)
selected (normal mode)
selected (low-speed mode)
8
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MEMORY
• Special Function Register (SFR) Area
The special function register (SFR) area contains the registers
relating to functions such as I/O ports and timers.
• RAM
RAM is used for data storage as well as a stack area.
• ROM
ROM is used for storing user programs as well as the interrupt
vector area.
RAM (192 bytes)
for
M37477M4
M37477M8/E8
M37478M4
M37478M8/E8
RAM (192 bytes)
for
M37477M8/E8
M37478M8/E8
• Interrupt Vector Area
The interrupt vector area is for storing jump destination addresses used at reset or when an interrupt is generated.
• Zero Page
Zero page addressing mode is useful because it enables access
to this area with fewer instruction cycles.
• Special Page
Special page addressing mode is useful because it enables access to this area with fewer instruction cycles.
16
0000
Zero
page
00BF16
00FF16
010016
01BF16
SFR area
Fig. 2 Memory map
ROM (16K bytes)
for
M37477M8/E8
M37478M8/E8
ROM (8K bytes)
for
M37477M4
M37478M4
C00016
E00016
FF0016
FFE816
FFFF16
Not used
Special
page
Interrupt vector area
9
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
00C016
00C116
00C216
00C316
00C416
00C516
00C616
00C716
00C816
00C916
00CA16
00CB16
00CC16
00CD16
00CE16
00CF16
00D016
00D116
00D216
00D316
00D416
00D516
00D616
00D716
00D816
00D916
00DA16
00DB16
00DC16
00DD16
00DE16
00DF16
Port P0
Port P0 direction register
Port P1
Port P1 direction register
Port P2
Port P3
Port P4
Port P4 direction register
Port P5 (Note 1)
P0 pull-up control register
P1–P5 pull-up control register (Note 2)
Edge polarity selection register
Input latch register
A-D control register
A-D conversion register
00E016
00E116
00E216
00E316
00E416
00E516
00E616
00E716
00E816
00E916
00EA16
00EB16
00EC16
00ED16
00EE16
00EF16
00F016
00F116
00F216
00F316
00F416
00F516
00F616
00F716
00F816
00F916
00FA16
00FB16
00FC16
00FD16
00FE16
00FF16
Transmit/receive buffer register
Serial I/O status register
Serial I/O control register
UART control register
Baud rate generator
Timer 1
Timer 2
Timer 3
Timer 4
Timer FF register
Timer 12 mode register
Timer 34 mode register
Timer mode register 2
CPU mode register
Interrupt request register 1
Interrupt request register 2
Interrupt control register 1
Interrupt control register 2
Notes 1 : This address is not used in the 7477 group.
2 : This address is allocated P1–P4 pull-up control register for the 7477 group.
Fig. 3 SFR (Special Function Register) memory map
10
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INTERRUPTS
Interrupts can be caused by 13 different sources consisting of five
external, seven internal, and one software sources.
Interrupts are vectored interrupts with priorities shown in Table 1.
Reset is also included in the table because its operation is similar
to an interrupt.
When an interrupt is accepted, the registers are pushed, interrupt
disable flag I is set, and the program jumps to the address specified in the vector table. The interrupt request bit is cleared
automatically. The reset and BRK instruction interrupt can never
be disabled. Other interrupts are disabled when the interrupt disable flag is set.
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit. The interrupt request bits
are in interrupt request registers 1 and 2 and the interrupt enable
bits are in interrupt control registers 1 and 2. External interrupts
INT0 and INT1 can be asserted on either the falling or rising edge
as set in the edge polarity selection register. When “0” is set to this
register, the interrupt is activated on the falling edge; when “1” is
set to the register, the interrupt is activated on the rising edge.
When the device is put into power-down state by the STP instruction or the WIT instruction, if bit 5 in the edge polarity selection
register is “1”, the INT1 interrupt becomes a key on wake up interrupt. When a key on wake up interrupt is valid, an interrupt request
is generated by applying the “L” level to any pin in port P0. In this
case , the port used for interrupt must have been set for the input
mode.
If bit 5 in the edge polarity selection register is “0” when the device
is in power-down state, the INT1 interrupt is selected. Also, if bit 5
in the edge polarity selection register is set to “1” when the device
is not in a power-down state, neither key on wake up interrupt request nor INT1 interrupt request is generated.
The CNTR0/CNTR1 interrupts function in the same as INT0 and
INT1. The interrupt input pin can be specified for either CNTR0 or
CNTR1 pin by setting bit 4 in the edge polarity selection register.
Figure 4 shows the structure of the edge polarity selection register, interrupt request registers 1 and 2, and interrupt control
registers 1 and 2.
Interrupts other than the BRK instruction interrupt and reset are
accepted when the interrupt enable bit is “1”, interrupt request bit
is “1”, and the interrupt disable flag is “0”. The interrupt request bit
can be reset with a program, but not set. The interrupt enable bit
can be set and reset with a program.
Reset is treated as a non-maskable interrupt with the highest priority. Figure 5 shows interrupts control.
Table 1. Interrupt vector address and priority.
______
RESET
INT0 interrupt
INT1 interrupt or key on wake up interrupt
CNTR0 interrupt or CNTR1 interrupt
Timer 1 interrupt
Timer 2 interrupt
Timer 3 interrupt
Timer 4 interrupt
Serial I/O receive interrupt
Serial I/O transmit interrupt
A-D conversion completion interrupt
BRK instruction interrupt
Interrupt source
Priority
1
2
3
4
5
6
7
8
9
10
11
12
Vector addresses
FFFF16, FFFE16
FFFD16, FFFC16
FFFB16, FFFA16
FFF916, FFF816
FFF716, FFF616
FFF516, FFF416
FFF316, FFF216
FFF116, FFF016
FFEF16, FFEE16
FFED16, FFEC16
FFEB16, FFEA16
FFE916, FFE816
Remarks
Non-maskable
External interrupt (polarity programmable)
External interrupt (INT1 is polarity programmable)
External interrupt (polarity programmable)
Non-maskable software interrupt
11
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7 b0
b7 b0
Edge polarity selection register (EG)
(Address 00D4
INT0 edge selection bit
INT
1 edge selection bit
CNTR
0 edge selection bit
CNTR
1 edge selection bit
0 : Falling edge
1 : Rising edge
CNTR
0/CNTR1 interrupt selection bit
0 : CNTR
1 : CNTR
INT1 source selection bit (at power-down state)
0 : P3
1 : P0
Nothing is allocated (The value is undefined at reading)
Interrupt request register 1
(Address 00FC
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Timer 3 interrupt request bit
Timer 4 interrupt request bit
Nothing is allocated
(The value is undefined at reading)
Serial I/O receive interrupt request bit
Serial I/O transmit interrupt request bit
A-D conversion completion interrupt request bit
16)
0
1
1/INT1
0 – P07 “L” level (for key-on wake-up)
16)
b7 b0
Interrupt request register 2
(Address 00FD
INT0 interrupt request bit
INT
1 interrupt request bit
CNTR0 or CNTR1 interrupt request bit
0 : No interrupt request
1 : Interrupt requested
Nothing is allocated
(The value is undefined at reading)
16)
b7 b0
Interrupt control register 1
(Address 00FE
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
Timer 4 interrupt enable bit
Nothing is allocated
(The value is undefined at reading)
Serial I/O receive interrupt enable bit
Serial I/O transmit interrupt enable bit
A-D conversion completion interrupt enable bit
Fig. 4 Structure of registers related to interrupt
Interrupt request bit
Interrupt enable bit
Interrupt disable flag I
BRK instruction
Reset
16)
b7
b0
Interrupt control register 2
(Address 00FF
INT0 interrupt enable bit
INT
1 interrupt enable bit
CNTR0 or CNTR1 interrupt enable bit
0 : Interrupt disable
1 : Interrupt enabled
Nothing is allocated
(The value is undefined at reading)
16)
Interrupt request
Fig. 5 Interrupt control
12
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMER
The 7477/7478 group has four timers; timer 1, timer 2, timer 3,
and timer 4.
A block diagram of timer 1 through 4 is shown in Figure 6.
Timer 1 can be operated in the timer mode, event count mode, or
pulse output mode. Timer 1 starts counting when bit 0 in the timer
12 mode register (address 00F816) is set to “0”.
The count source can be selected from the f(XIN) divided by 16,
f(XCIN) divided by 16, f(XCIN), or event input from P32/CNTR0 pin.
Do not select f(XCIN) as the count source in the 7477 group. When
bit 1 and bit 2 in the timer 12 mode register are “0”, f(XIN) divided
by 16 or f(XCIN) divided by 16 is selected. Selection between
f(XIN) and f(XCIN) is done by bit 7 in the CPU mode register (address 00FB16). When bit 1 in the timer 12 mode register is “0” and
bit 2 is “1”, f(XCIN) is selected. And, when bit 1 in the timer 12
mode register is “1”, an event input from the CNTR0 pin is selected. Event inputs are selected depending on bit 2 in the edge
polarity selection register (address 00D416). When this bit is “0”,
the inverted value of CNTR0 input is selected; when the bit is “1”,
CNTR0 input is selected.
When bit 3 in the timer 12 mode register is set to “1”, the P12 pin
becomes timer output T0. When the direction register of P12 is set
for the output mode at this time, the timer 1 overflow divided by 2
is output from T0.
Please set the initial output value in the following procedure.
➀ Set “1” to bit 0 of the timer 12 mode register.
(Timer 1 count stop.)
➁ Set “1” to bit 0 of the timer mode register 2.
➂ Set the output value to bit 0 of the timer FF register.
➃ Set the count value to the timer 1.
➄ Set “0” to bit 0 of the timer 12 mode register.
(Timer 1 count start.)
Timer 2 can only be operated in the timer mode. Timer 2 starts
counting when bit 4 in the timer 12 mode register is set to “0”.
The count source can be selected from the divide by 16, divide by
64, divide by 128, or divide by 256 frequency of f(XIN) or f(XCIN),
and timer 1 overflow. Do not select f(XCIN) as the count source in
the 7477 group. When bit 5 in the timer 12 mode register is “0”,
any of the divide by 16, divide by 64, divide by 128, or divide by
256 frequency of f(XIN) or f(XCIN) is selected. The divide ratio is
selected according to bit 6 and bit 7 in the timer 12 mode register,
and selection between f(XIN) and f(XCIN) is made according to bit
7 in the CPU mode register. When bit 5 in the timer 12 mode register is “1”, timer 1 overflow is selected as the count source.
Timer 3 can be operated in the timer mode, event count mode, or
PWM mode. Timer 3 starts counting when bit 0 in the timer 34
mode register (address 00F916) is set to “0”.
The count source can be selected from the f(XIN) divided by 16,
f(XCIN) divided by 16, f(XCIN), timer 1 or timer 2 overflow, or an
event input from P33/CNTR1 pins according to the statuses of bit 1
and bit 2 in the timer 34 mode register, bit 6 in the timer mode register 2 (address 00FA16) and bit 7 in the CPU mode register. Do
not select f(XCIN) as the count source in the 7477 group. Note,
however, that if timer 1 overflow or timer 2 overflow is selected for
the count source of timer 3 when timer 1 overflow is selected for
the count source of timer 2, timer 1 overflow is always selected regardless of the status of bit 6 in the timer mode register 2. Event
inputs are selected depending on bit 3 in the edge polarity selection register. When this bit is “0”, the inverted value of CNTR1 input
is selected; when the bit is “1”, CNTR1 input is selected.
Timer 4 can be operated in the timer mode, event count mode,
pulse output mode, pulse width measuring mode, or PWM mode.
Timer 4 starts counting when bit 3 in the timer 34 mode register is
set to “0” when bit 6 in this register is “0”. When bit 6 is “1”, the
pulse width measuring mode is selected. The count source can be
selected from timer 3 overflow, f(XIN) divided by 16, f(XCIN) divided
by 16, f(XCIN), timer 1 or timer 2 overflow, or an event input from
P33/CNTR1 pin according to the statuses of bit 4 and bit 5 in the
timer 34 mode register, bit 6 in the timer mode register 2, and bit 7
in the CPU mode register. Do not select f(XCIN) as the count
source in the 7477 group. Note, however, that if timer 1 overflow or
timer 2 overflow is selected for the count source of timer 4 when
timer 1 overflow is selected for the count source of timer 2, timer 1
overflow is always selected regardless of the status of bit 6 in the
timer mode register 2. Event inputs are selected depending on bit
3 in the edge polarity selection register.
When this bit is “0”, the inverted value of CNTR1 input is selected;
when the bit is “1”, CNTR1 input is selected.
When bit 7 in the timer 34 mode register is set to “1”, the P13 pin
becomes timer output T1. When the direction register of P13 is set
for the output mode at this time, the timer 4 overflow divided by 2
is output from T1 when bit 7 in the timer mode register 2 is “0”.
Please set the initial output value in the following procedure.
➀ Set “1” to bit 3 of the timer 34 mode register.
(Timer 4 count stop.)
➁ Set “1” to bit 1 of the timer mode register 2.
➂ Set the output value to bit 1 of the timer FF register.
➃ Set the count value to the timer 4.
➄ Set “0” to bit 3 of the timer 34 mode register.
(Timer 4 count start.)
(1) Timer mode
Timer performs down count operations with the dividing ratio being
1/(n+1). Writing a value to the timer latch sets a value to the timer.
When the value to be set to the timer latch is nn16, the value to be
set to a timer is nn16, which is down counted at the falling edge of
the count source from nn16 to (nn16-1) to (nn16-2) to ...0116 to 0016
to FF16. At the falling edge of the count source immediately after
timer value has reached FF16, value (nn16-1) obtained by subtracting one from the timer latch value is set (reloaded) to the timer to
continue counting. At the rising edge of the count source immediately after the timer value has reached FF16, an overflow occurs
and an interrupt request is generated.
(2) Event count mode
Timer operates in the same way as in the timer mode except that
it counts input from the CNTR0 or CNTR1 pin.
(3) Pulse output mode
In this mode, duty 50% pulses are output from the T0 or T1 pin.
When the timer overflows, the polarity of the T0 or T1 pin output
level is inverted.
(4) Pulse width measuring mode
The 7477/7478 group can measure the “H” or “L” width of the
CNTR0 or CNTR1 input waveform by using the pulse width measuring mode of timer 4. The pulse width measuring mode is
selected by writing “1” to bit 6 in the timer 34 mode register. In the
pulse width measuring mode, the timer counts the count source
while the CNTR0 or CNTR1 input is “H” or “L”. Whether the CNTR0
input or CNTR1 input to be measured can be specified by the status of bit 4 in the edge polarity selection register; whether the “H”
13
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
width or “L” width to be measured can be specified by the status of
bit 2 (CNTR0) and bit 3 (CNTR1) in the edge polarity selection register.
(5) PWM mode
The PWM mode can be entered for timer 3 and timer 4 by setting
bit 7 in the timer mode register 2 to “1”. In the PWM mode, the P13
pin is set for timer output T1 to output PWM waveforms by setting
bit 7 in the timer 34 mode register to “1”. The direction register of
P13 must be set for the output mode before this can be done.
In the PWM mode, timer 3 is counting and timer 4 is idle while the
PWM waveform is “L”. When timer 3 overflows, the PWM waveform goes “H”. At this time, timer 3 stops counting simultaneously
and timer 4 starts counting. When timer 4 overflows, the PWM
waveform goes “L”, and timer 4 stops and timer 3 starts counting
again. Consequently, the “L” duration of the PWM waveform is determined by the value of timer 3; the “H” duration of the PWM
waveform is determined by the value of timer 4.
When a value is written to the timer in operation during the PWM
mode, the value is only written to the timer latch, and not written to
the timer. In this case, if the timer overflows, a value one less the
value in the timer latch is written to the timer. When any value is
written to an idle timer, the value is written to both the timer latch
and the timer.
In this mode, do not select timer 3 overflow as the count source for
timer 4.
INPUT LATCH FUNCTION
The 7477/7478 group can latch the P30/INT0, P31/INT1, P32/
CNTR0, and P33/CNTR1 pin level into the input latch register (address 00D616) when timer 4 overflows. The polarity of each pin
latched to the input latch register can be selected by using the
edge polarity selection register.
When bit 0 in the edge polarity selection register is “0”, the inverted value of the P30/INT0 pin level is latched; when the bit is
“1”, the P30/INT0 pin level is latched as it is.
When bit 1 in the edge polarity selection register is “0”, the inverted value of the P31/INT1 pin level is latched; when the bit is
“1”, the P31/INT1 pin level is latched as it is. When bit 2 in the
edge polarity selection register is “0”, the inverted value of the
P32/CNTR0 pin level is latched; when the bit is “1“, the P32/CNTR0
pin level is latched as it is. When bit 3 in the edge polarity selection register is “0”, the inverted value of the P33/CNTR1 pin level is
latched; when the bit is “1”, the P33/CNTR1 pin level is latched as
it is.
14
X
CIN
(Note)
MITSUBISHI MICROCOMPUTERS
7477/7478 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Data bus
1/2
P32/CNTR
P12/T
P32/CNTR
T12M
X
1/2
IN
0
Port latch
0
CM
T12M
7
EG
3
1/8
2
T12M
2
T12M
1
TM2
Timer 1 latch (8)
0
0
1/2
Timer 1 (8)
Timer 1
interrupt request
Timer 2 latch (8)
T12M
1/4
1/8
1/16
T12M
6
7
T12M
5
TM2
T12M
6
T34M
T34M
4
Timer 2 (8)
1
2
Timer 2
interrupt request
Timer 3 latch (8)
T34M
0
1
EG
3
T34M
4
T34M
5
Timer 3 (8)
Timer 3
interrupt request
Timer 4 latch (8)
Port latch
P13/T
1
T34M
( Select gate : At reset, shaded side is connected.)
Note : The 7477 group does not have X
Fig. 6 Block diagram of timer 1 through 4
EG
7
P33/CNTR
P32/CNTR
P31/INT
P30/INT
T34M
4
1
0
1
0
6
T34M
Timer 4 (8)
3
F/F
Timer 4
interrupt request
1/2
TM2
7
TM2
EG
EG
3
2
1
C
D3 Q3
EG
1
D2 Q2
D1 Q1
D0 Q0
EG
0
CIN
input.
15
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