MITSUBISHI 38K0 User Manual

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MITSUBISHI MICROCOMPUTERS

38K0 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

DESCRIPTION

The 38K0 group is the 8-bit microcomputer based on the 740 fam­ily core technology.
The 38K0 group has the USB function, an 8-bit bus interface, a
Serial I/O, three 8-bit timers, and an 8-channel 10-bit A-D con­verter, which are available for the PC peripheral I/O device.
The various microcomputers in the 38K0 group include variations
of internal memory size and packaging. For details, refer to the
section on part numbering.

FEATURES

Basic machine-language instructions....................................... 71

•

The minimum instruction execution time.......................... 0.25 µs

•

System clock✻: Reference frequency to internal circuit except

USB function

Memory size

•

ROM ................................................................ 16 K to 3 2 K bytes

RAM ............................................................... 1024 to 2048 bytes

Programmable input/output ports ............................................. 48

•

Software pull-up resistors

•

Interrupts .................................................. 15 sources, 15 vectors

•

USB function (USB version 1.1 specification) ........... 4 endpoints

•

External bus interface ....................................... 8-bit ✕ 1 channel

•

Timers ............................................................................. 8-bit ✕ 3

•

Watchdog timer ............................................................. 16-bit ✕ 1

•

Serial I/O ...................... 8-bit ✕ 1 (UART or Clock-synchronized)

•

A-D converter ................................................ 10-bit ✕ 8 channels

•

(at 8 MHz system clock✻)

(8-bit reading available)

LED direct drive port ................................................................... 4

•

Clock generating circuit

•

(connect to external ceramic resonator or quartz-crystal oscillator)
Power source voltage

•

System clock/Internal clock division mode

At 12 MHz/Through mode (φ = 12 MHz) ......................................

......................................................... 4.50 to 5.25 V (under planning)

At 12 MHz/2-divide mode(φ = 6 MHz) ..........................................

............................................. 4.00 to 5.25 V (under development)

At 8 MHz/Through mode (φ = 8 MHz) ................... 4.00 to 5.25 V

At 6 MHz/Through mode (φ = 6 MHz) ................... 4.00 to 5.25 V

At 6 MHz/Through mode (φ = 6 MHz) ..........................................

............................................. 3.00 to 4.00 V (under development)

Remarks: The mode under development will be available from

Aug./2002.

Power dissipation

•

At 5 V power source voltage.................................. 125 mW (typ.)

(at 8 MHz system clock, in through mode)

At 3.3 V power source voltage ................................ 45 mW (typ.)

(at 6 MHz system clock, in through mode)

Operating temperature range ....................................–20 to 85°C

•

Packages

•

FP ........................................ 64P6U-A (64-pin 14 ✕ 14 mm LQFP)

HP ........................................64P6Q-A (64-pin 10 ✕ 10 mm LQFP)

■Notes

1. The specifications of this product are subject to change be­cause it is under development. Inquire the use of Mitsubishi
Electric Corporation.

2. The flash memory version cannot be used for application em­bedded in the MCU card.

PIN CONFIGURATION (TOP VIEW)

P 40/ EXD R E Q / RXD

P 4

Fig. 1 Pin configuration of 38K0 group

3

2

1

6

5

7

5
P

24

S
S

V
C

N

5
P

14

T

R

E S E

5
P

03

E

C
C

V

4

5
P

93

1

01

F
R

V

E

1

/ EXD A C K / TXD

2

/ EXT C / S

P 4
P43/EXA1/S

P 33/ EXI N T

4

/ EXC S

P 3

5/EX

P3

P3

6/EX

7

/ EXA 0

P 3
P10/DQ0/AN
P1

1

/DQ1/AN

P 0
P 0

P 3
P 3
P 3

WR

C L K
RDY

RD

4

5

0

0

P

P

4

84

74

6

49

7

50
51
52
53
54

0

55

1
2

0
1

M 3 8 K 0 7 M 4 - X X X F P / H P

56
57
58
59
60
61
62
63
64

123456789

2

3

N

N

/

/

3

2

Q

Q

/

/

2

3

1

1

P

P

D

D

A

A

0

0

0

0

0

P

P

P

P

4

64

54

34

4

M 3 8 K 0 9 F 8 F P / H P

4

5

6

7

N

N

N

N

/

/

/

/

4

5

6

7

Q

Q

Q

Q

/

/

/

/

4

5

6

7

1

1

1

1

P

P

P

P

D

D

D

D

A

A

A

A

Package type : 64P6U-A/64P6Q-A

3

5
P

83

11

S
S

V

1

T
/

2

5

I N

P

73

21

N

I

X

/

1

5

C N T

I N

P

63

31

T
O

X

U

0

T
/

0

5
P

53

41

C
C

V

N

7

2
P

43

5

2

S
S

V
C

6

2
P

3

P 2

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

6

1

)

0

D
(

0

6
P

L E

5

P 2

4

P 2

3

P 2

2

P 2

1

P 2

0

D 0 ­D 0 +
T r O N
USBV

REF

DV

CC

P V

C C

P V

S S

3

( L E D3)

P 6
P 6

2

( L E D2)

P 61( L E D1)

1

MITSUBISHI MICROCOMPUTERS

C

N T

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0

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S

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2
V

C

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5 ( 8

)
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6

(

4

)

678

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4

(

4

)

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X T B U S ( 8

)

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)

123

4
5

5
5

6
5

7
5

8
5

9
6

0
6

1
6

2

0

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T

r O

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B

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2
2

3
2

4
2

6

5

P

0 ( 8

)

4

3
4

4
4

5
4

6
4

7
4

8
4

9
5

0

V

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1 ( 8

)

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7

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C

C

E

9

38K0 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

FUNCTIONAL BLOCK DIAGRAM (Package : 64P6U-A/64P6Q-A)

Fig. 2 Functional block diagram

2

PIN DESCRIPTION

Table 1. Pin description

MITSUBISHI MICROCOMPUTERS

38K0 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Pin

VCC, VSS
VCCE

CNVSS

CNVSS2
VREF

DVCC
PVCC, PVSS

RESET
XIN

XOUT

USBVREF

TrON

D0+, D0-

P00–P07

P10/DQ0/AN0–
P17/DQ7/AN

P20–P27

P30–P32
P33/ExINT

P34/ExCS
P35/ExWR
P36/ExRD
P37/ExA0

P40/ExDREQ/RxD
P41/ExDACK/TxD
P42/ExTC/S
P43/ExA1/S

P50/INT0
P51/CNTR0
P52/INT1
P53–P57
P60–P63

Power source
Analog power

source
CNVSS

CNVSS2
Analog reference

voltage input
Analog power

source
Reset input
Clock input

Clock output

USB reference
power source

USB reference
voltage output

USB upstream
I/O

I/O port P0

I/O port P1

7

I/O port P2

I/O port P3

I/O port P4

CLK

RDY

I/O port P5

I/O port P6

Name

Function

• Apply voltage of 3.0 V – 5.25 V to VCC, and 0 V to VSS.

• Power source pin for ports P1, P3, P4 and analog circuit. Connect this pin to VCC.

• This pin controls the operation mode of the chip. Connect this pin to VSS. In the flash memory

mode, this pin becoems VPP power source input pin.

• This pin controls the operation mode of the chip. Connect this pin to VSS.

• Reference voltage input pin for A-D converter.

• Power source pin for analog circuit.

• Connect the DVCC and PVCC pins to VCC, and the PVSS pin to VSS.

• Reset input pin for active “L”

• Input and output pins for the main clock generating circuit.

• Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set

the oscillation frequency.

•If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.

• Power source pin for USB port circuit.

In Vcc = 4.00 to 5.25 V use the built-in USB reference voltage circuit. In Vcc = 3.00 to 4.00 V apply

3.3 V power supply from the external because use of the built-in USB reference voltage circuit is
prohibited in this voltage range. In Vcc = 3.00 to 3.60 V connect this pin to VCC.

• Output pin to pull-up D0+ by 1.5 kΩ external resistor.

• USB upstream I/O port

• USB input level

• USB output level output structure

• 8-bit I/O port

• I/O direction register allows each pin to be individually

programmed as either input or output.

• CMOS compatible input level

• CMOS 3-state output structure

• Pull-up control is enabled.

• 8-bit I/O port

• I/O direction register allows each pin to be individually

programmed as either input or output.

• CMOS compatible input level

• CMOS 3-state output structure

• 8-bit I/O port

• I/O direction register allows each pin to be individually programmed as either input or output.

• CMOS compatible input level

• CMOS 3-state output structure

• 8-bit I/O port

• I/O direction register allows each pin to be individually

programmed as either input or output.

• CMOS compatible input level

• CMOS 3-state output structure

• 4-bit I/O port

• I/O direction register allows each pin to be individually

programmed as either input or output.

• CMOS compatible input level

• CMOS 3-state output structure

• 8-bit I/O port

• I/O direction register allows each pin to be individually

programmed as either input or output.

• CMOS compatible input level

• CMOS 3-state output structure

• 4-bit I/O port

• I/O direction register allows each pin to be individually programmed as either input or output.

• CMOS compatible input level

• CMOS 3-state output structure

• Output large current for LED drive is enabled.

Function except a port function

• Key input pins (key-on wake up interrupt)

• A-D converter input pins

• External bus interface function pins

• External bus interface function pins

• Serial I/O function pins

• External bus interface function pins

• Interrupt input pin

• Timer X funciton pin

• Interrupt input pin

3

PART NUMBERING

MITSUBISHI MICROCOMPUTERS

38K0 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

P r o d u c t

M 3 8 K0 7 M 4 - X X X FP

P a c k a g e t y p e

F P : 6 4 P 6 U - A p a c k a g e
H P : 6 4 P 6 Q - A p a c k a g e

R O M n u m b e r

O m i t t e d i n t h e f l a s h m e m o r y v e r s i o n .

– : Standard
Omitted in the flash memory version.

R O M / P R O M s i z e

1 : 4 0 9 6 b y t e s
2 : 8 1 9 2 b y t e s
3 : 1 2 2 8 8 b y t e s
4 : 1 6 3 8 4 b y t e s
5 : 2 0 4 8 0 b y t e s
6 : 2 4 5 7 6 b y t e s
7 : 2 8 6 7 2 b y t e s
8 : 3 2 7 6 8 b y t e s

T h e f i r s t 1 2 8 b y t e s a n d t h e l a s t 2 b y t e s o f R O M
a r e r e s e r v e d a r e a s ; t h e y c a n n o t b e u s e d a s a
u s e r ’ s R O M a r e a .
H o w e v e r , t h e y c a n b e p r o g r a m m e d o r e r a s e d i n
t h e f l a s h m e m o r y v e r s i o n , s o t h a t u s e r s c a n
u s e t h e m .

9 : 3 6 8 6 4 b y t e s
A : 4 0 9 6 0 b y t e s
B : 4 5 0 5 6 b y t e s
C : 4 9 1 5 2 b y t e s
D : 5 3 2 4 8 b y t e s
E : 5 7 3 4 4 b y t e s
F : 6 1 4 4 0 b y t e s

Fig. 3 Part numbering

Memory type

M : Mask ROM version
F : Flash memory version

R A M s i z e

0 : 1 9 2 b y t e s
1 : 2 5 6 b y t e s
2 : 3 8 4 b y t e s
3 : 5 1 2 b y t e s
4 : 6 4 0 b y t e s
5 : 7 6 8 b y t e s
6 : 8 9 6 b y t e s
7 : 1 0 2 4 b y t e s
8 : 1 5 3 6 b y t e s
9 : 2 0 4 8 b y t e s

4

MITSUBISHI MICROCOMPUTERS

38K0 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

GROUP EXPANSION

Mitsubishi plans to expand the 38K0 group as follows.

Memory Type

Support for mask ROM and flash memory versions.

Memory Size

Flash memory size .......................................................... 32 Kbytes

Mask ROM size ............................................................... 16 Kbytes

RAM size .......................................................... 1024 to 2048 bytes

Memory Expansion Plan

: U n d e r d e v e l o p m e n t

R O M s i z e

( b y t e s )

6 0 K

3 2 K

Packages

64P6U-A .................................. 0.8 mm-pitch plastic molded LQFP

64P6Q-A .................................. 0.5 mm-pitch plastic molded LQFP

100D0M ...........................0.65 mm-pitch metal seal PIGGY BACK

M 3 8 K 0 9 F 8

1 6 K

8 K

P r o d u c t s u n d e r d e v e l o p m e n t o r p l a n n i n g : t h e d e v e l o p m e n t s c h e d u l e a n d s p e c i f i c a t i o n m a y b e r e v i s e d
w i t h o u t n o t i c e . T h e d e v e l o p m e n t o f p l a n n i n g p r o d u c t s m a y b e s t o p p e d .

Fig. 4 Memory expansion plan

Currently products are listed below.

Table 2. List of products

Product

M38K07M4-XXXFP
M38K07M4-XXXHP
M38K09F8FP
M38K09F8HP
M38K09RFS

ROM size (bytes)

ROM size for User in ( )

16384

(16254)

32768

(32638)

2 5 65

—

1

21

RAM size (bytes)

1024

2048
2048

M 3 8 K 0 7 M 4

R A M s i z e ( b y t e s )

Package

64P6U-A
64P6Q-A
64P6U-A
64P6Q-A

100D0M

, 0 2

42

Mask ROM version

Flash memory version
Emulator MCU (for program evaluation)

, 0 4

8

Remarks

As of February 2002

5

MITSUBISHI MICROCOMPUTERS

38K0 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

FUNCTIONAL DESCRIPTION
CENTRAL PROCESSING UNIT (CPU)

The 38K0 group uses the standard 740 family instruction set. Re­fer to the table of 740 family addressing modes and machine
instructions or the 740 Family Software Manual for details on the
instruction set.
Machine-resident 740 family instructions are as follows:
The FST and SLW instruction cannot be used.
The STP, WIT, MUL, and DIV instruction can be used.
The CPU has the 6 registers. The register structure is shown in
Figure 5.

[Accumulator (A)]

The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.

[Index Register X (X)]

The index register X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of
register X and specifies the real address.

[Index Register Y (Y)]

The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.

[Stack Pointer (S)]

The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the
contents of the stack pointer. The high-order 8 bits of the stack
address are determined by the stack page selection bit. If the
stack page selection bit is “0” , the high-order 8 bits becomes
“0016”. If the stack page selection bit is “1”, the high-order 8 bits
becomes “0116”.
Figure 6 shows the store and the return movement into the stack.
If there are registers other than those described in Figure 5, the
users need to store them with the program.

[Program Counter (PC)]

The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PCL. It is used to indicate the address of the
next instruction to be executed.

b7

b0

A Accumulator

b7

b0

X Index register X

b7

b0

Y Index register Y

b7 b0

S Stack pointer

b7b15 b0

H

PC

L

Program counterPC

b7 b0

N V T B D I Z C Processor status register (PS)

Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag

Fig. 5 740 Family CPU register structure

6

e

I n t e r r u p t r e q u e s t

( N o t e )

O n - g o i n g R o u t i n

MITSUBISHI MICROCOMPUTERS

38K0 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

M (S) (PCH)

P u s h r e t u r n a d d r e s s
o n s t a c k

P O P re t u r n
a d d r e s s f r o m s t a c k

M ( S )( P CH)

S ) –
( S )

(

1

M ( S )( P CL)

(S) (S)– 1

S u b r o u t i n e

E x e c u t e R T S

S ) +

( S )

(

1

(PCL)M (S)

(S) (S) + 1

( P CH)M ( S )

E x e c u t e J S R

(S) (S) – 1

M ( S )( P CL)

S ) –
( S )

(

1

M (S) (PS)

(S) (S) – 1

I n t e r r u p t

S e r v i c e R o u t i n e

Execute RTI

(S) (S) + 1

( P S )M ( S )

(S) (S) + 1

(PCL)M (S)

(S) (S) + 1

(PCH)M (S)

P u s h r e t u r n a d d r e s s
o n s t a c k

P u s h c o n t e n t s o f p r o c e s s o r
s t a t u s r e g i s t e r o n s t a c k

I Flag is set from “0” to “1”
Fetch the jump vector

POP contents of
processor status
register from stack

P O P r e t u r n
a d d r e s s
f r o m s t a c k

N o t e: C o n d i t i o n f o r a c c e p t a n c e o f a n i n t e r r u p t I n t e r r u p t e n a b l e f l a g i s “ 1 ”

Fig. 6 Register push and pop at interrupt generation and subroutine call

Table 3 Push and pop instructions of accumulator or processor status register

Push instruction to stack

Accumulator
Processor status register

PHA
PHP

I n t e r r u p t d i s a b l e f l a g i s “ 0 ”

Pop instruction from stack

PLA
PLP

7

MITSUBISHI MICROCOMPUTERS

38K0 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

[Processor status register (PS)]

The processor status register is an 8-bit register consisting of 5
flags which indicate the status of the processor after an arithmetic
operation and 3 flags which decide MCU operation. Branch opera­tions can be performed by testing the Carry (C) flag , Zero (Z) flag,
Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z,
V, N flags are not valid.

•Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.

•Bit 1: Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.

•Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
Interrupts are disabled when the I flag is “1”.

•Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC

•Bit 4: Break flag (B)
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the processor
status register is always “0”. When the BRK instruction is used to
generate an interrupt, the processor status register is pushed
onto the stack with the break flag set to “1”.

•Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory. When the T flag is “1”, direct
arithmetic operations and direct data transfers are enabled
between memory locations.

•Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location
operated on by the BIT instruction is stored in the overflow flag.

•Bit 7: Negative flag (N)
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored
in the negative flag.

Table 4 Set and clear instructions of each bit of processor status register

Set instruction
Clear instruction

C flag

SEC
CLC

Z flag

–
–

I flag

SEI
CLI

D flag

SED
CLD

B flag

–
–

T flag

SET

CLT

V flag

–

CLV

N flag

–
–

8

[CPU Mode Register (CPUM)] 003B16

P

CPU

( C P U M

B

)

b

b

The CPU mode register contains the stack page selection bit and
the internal system clock selection bit.
The CPU mode register is allocated at address 003B16.

MITSUBISHI MICROCOMPUTERS

38K0 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

7

Fig. 7 Structure of CPU mode register

0

10

mode register

: a d d r e s s 0 0 3

rocessor mode bits

b1 b0

0 0 : Single-chip mode
01 :
1 0 : Not availab le
11 :

Stack page selection bit

0 : 0 page

1 : 1 page
Not used (returns “1” when read)
(Do not write “0” to this bit)
Not used (returns “0” when read)
(Do not write “1” to this bit)
System clock selection bit

0 : Main clock (X

SYN

1 : f
System clock division ratio selection bits

b7 b6

00 :

01 :

10 :

11 :

1 6

IN

)

φ

= f(system clock)/8 (8-divide mode)

φ

= f(system clock)/4 (4-divide mode)

φ

= f(system clock)/2 (2-divide mode)

φ

= f(system clock) (Through mode)

9

MITSUBISHI MICROCOMPUTERS

FF

RAM

R A M

A d d

6
2
8
4
0
6
2
8
4
0
6
2
8
4
0

F

F

ROM

ROM si

A d d

A d d

FF

FFDC

F F F E

FFFF

XXXX

YYYY

ZZZZ

RAM

R O M

S F R

N

d

I

a

R

ROM

Z

S

R

FFF

S F R

38K0 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MEMORY
Special Function Register (SFR) Area

The Special Function Register area in the zero page contains con­trol registers such as I/O ports and timers.

RAM

RAM is used for data storage and for stack area of subroutine
calls and interrupts.

ROM

The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs. In
the flash memory version, program and erase can be performed in
the reserved area.

area

s i z

( b y t e s )

192
256
384
512
640
768
896
1024
1536
2048

area

(bytes)

4 0 9

8 1 9
1 2 2 8
1 6 3 8
2 0 4 8
2 4 5 7
2 8 6 7
3 2 7 6
3 6 8 6
4 0 9 6
4 5 0 5
4 9 1 5
5 3 2 4
5 7 3 4
6 1 4 4

Fig. 8 Memory map diagram

r e s s

e

r e s

ze

X X X X

00
013F
01BF
023F
02BF
033F
03BF
043F
063F
083F

Y Y Y Y

0 0
E 0 0 0

D 0 0 0
C 0 0 0
B 0 0 0
A 0 0 0
9 0 0 0
8 0 0 0
7 0 0 0
6 0 0 0
5 0 0 0
4 0 0 0
3 0 0 0
2 0 0 0
1 0 0 0

1 6

16
16

16

16

16

16

16
16
16
16

r e s

s

1 6

1 6

0

1 6

1 6
1 6

1 6

1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6

Z Z Z Z

0 8
E 0 8 0

D 0 8 0
C 0 8 0
B 0 8 0
A 0 8 0
9 0 8 0
8 0 8 0
7 0 8 0
6 0 8 0
5 0 8 0
4 0 8 0
3 0 8 0
2 0 8 0
1 0 8 0

s

1 6

1 6

0

1 6
1 6
1 6
1 6

1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6

Interrupt Vector Area

The interrupt vector area contains reset and interrupt vectors.

Zero Page

The 256 bytes from addresses 000016 to 00FF16 are called the
zero page area. The internal RAM and the special function regis­ters (SFR) are allocated to this area.
The zero page addressing mode can be used to specify memory
and register addresses in the zero page area. Access to this area
with only 2 bytes is possible in the zero page addressing mode.

Special Page

The 256 bytes from addresses FF0016 to FFFF16 are called the
special page area. The special page addressing mode can be
used to specify memory addresses in the special page area. Ac­cess to this area with only 2 bytes is possible in the special page
addressing mode.

0000

0040

0100

0FE0
0

16

16

16

16

16
16

16

16

00

16

16

1 6

e s e r v e d R O M a r e

16

eserved

n t e r r u p t v e c t o r a r e

a r e

ot use

a r e

(128 by tes)

a

a

area

e r o p a g

e

p e c i a l p a g

e

a

10

MITSUBISHI MICROCOMPUTERS

A

B

C

D

E

F

A

B

C

D

E

F

A

B

C

D

E

F

A

B

C

D

E

F

P

)

P

)

P

)

P

)

P

)

P

)

P

)

P

D)

P

)

P

)

P

)

P

)

Serial I/O

(SIOSTS)

I

(ICON2)

T

CPU

(CPUM)

I

(IREQ1)

I

(IREQ2)

I

(ICON1)

P

(PRE12)

Ti

)

P

(PREX)

Ti

(TX)

Ti

)

Ti

(TM)

A-D

(ADCON)

A-D

(ADL)

P

)

P

D)

R

)

R

( N

)

U S B

l

i

)

U S B

)

USB add

(USBA0)

USB add

(USBA1)

E

)

E

)

Endpoi

(EPXXREG2)

E

)

E

)

E

)

Endpoi

(EPXXREG6)

E

)

R

( N

)

R

( N

)

R

( N

)

R

( N

)

R

( N

)

R

( N

)

R

( N

)

R

)

F

)

F

)

U S B

E XB

R

)

EXB ind

(EXBINDEX)

E X B

)

E X B

)

A-D

(ADH)

R

)

F E

F E

F E

F E

F E

F E A

Flash

(FMCR)

P L L

( P L L C O N )

P

(PULL5)

Endpoi

(EPXXREG8)

Endpoi

(EPXXREG9)

S

)

UART

(UARTCON)

B

)

P

l

i

)

R

( N

)

F E B

F E C

F E D

FEE

F E F

F F

F F

F F

F F

F F

F F A

FFB

F F C

F F D

FFE

F F F

R

)

R

( N

)

R

( N

)

R

( N

)

R

)

R

( N

)

R

)

R

( N

)

R

( N

)

R

( N

)

R

)

R

( N

)

R

( N

)

R

( N

)

R

( N

)

M I S R G

R

( N

)

R

( N

)

R

)

R

( N

)

R

( N

)

N

38K0 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

o r t P 0 ( P 0

0 0 0 0

1 6

o r t P 0 d i r e c t i o n r e g i s t e r ( P 0 D

0 0 0 1

1 6

o r t P 1 ( P 1

0 0 0 2

1 6

o r t P 1 d i r e c t i o n r e g i s t e r ( P 1 D

0 0 0 3

1 6

o r t P 2 ( P 2

0 0 0 4

1 6

o r t P 2 d i r e c t i o n r e g i s t e r ( P 2 D

0 0 0 5

1 6

o r t P 3 ( P 3

0 0 0 6

1 6

0 0 0 7

1 6

ort P3 direction register (P3

o r t P 4 ( P 4

0 0 0 8

1 6

0 0 0 9

1 6

0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0

0 0 1 0
0 0 1 1
0012
0013
0 0 1 4
0 0 1 5
0 0 1 6
0017
0018

0 0 1 9
0 0 1
001
0 0 1
001
001
0 0 1

ort P4 direction register (P4

o r t P 5 ( P 5

1 6

o r t P 5 d i r e c t i o n r e g i s t e r ( P 5 D

1 6
1 6

ort P6 (P6

o r t P 6 d i r e c t i o n r e g i s t e r ( P 6 D

1 6
1 6

eserved (Note

e s e r v e d

o t e

1 6
1 6
1 6
16
16
1 6
1 6
1 6
16
16
1 6
1 6
16
1 6
16
16
1 6

c o n t r o

s t e r ( U S B C O N
a d d r e s s e n a b l e r e g i s t e r ( U S B A E

ress 0 register
ress 1 register

r a m e n u m b e r r e g i s t e r L o w ( F N U M L
r a m e n u m b e r r e g i s t e r H i g h ( F N U M H

U S B i n t e r r u p t s o u r c e e n a b l e r e g i s t e r

i n t e r r u p t s o u r c e r e g i s t e
n d p o i n t i n d e x r e g i s t e r ( U S B I N D E X
n d p o i n t f i e l d r e g i s t e r 1 ( E P X X R E G 1

nt field register 2

n d p o i n t f i e l d r e g i s t e r 3 ( E P X X R E G 3
n d p o i n t f i e l d r e g i s t e r 4 ( E P X X R E G 4
n d p o i n t f i e l d r e g i s t e r 5 ( E P X X R E G 5

nt field register 6

n d p o i n t f i e l d r e g i s t e r 7 ( E P X X R E G 7

r e g

( U S B I C O N )

( U S B I R E Q )

r

0020

16

0021
0022
0023
0024
0025
0026
0027
0028
0029
0 0 2
0 0 2
002
002
0 0 2
0 0 2
0030
0031
0032
0033
0034
0035
0036
0037
0038
0039
0 0 3
003
003
003
003
0 0 3

rescaler 12

16

mer 1 (T1

16

mer 2 (T2

16

mer X mode register

16

rescaler X

16

mer X

16

ransmit/Receive buffer register

16
16
16
1 6
1 6
16
16
1 6
1 6
16
16
16
16
16
16
16
16
16
16
1 6
16
16
16
16
1 6

status register

e s e r v e d

o t e

e s e r v e d

o t e

e s e r v e d

o t e

e s e r v e d

o t e

e s e r v e d

o t e

e s e r v e d

o t e

e s e r v e d

o t e

eserved (Note

E X B i n t e r r u p t s o u r c e e n a b l e r e g i s t e r

i n t e r r u p t s o u r c e r e g i s t e

eserved (Note

ex register

f i e l d r e g i s t e r 1 ( E X B R E G 1
f i e l d r e g i s t e r 2 ( E X B R E G 2

control register
conversion register Low
conversion register High

Watchdo g timer control register (WDTCON)

eserved (Note

mode register
nterrupt request register 1
nterrupt request register 2
nterrupt co ntrol register 1

nterrupt co ntrol register 2

(TB/RB)

( E X B I C O N )

( E X B I R E Q )

r

e r i a l I / O c o n t r o l r e g i s t e r ( S I O C O N

0

1 6

0

0

1 6

0
0FE3

0FE4
0
0FE6

0

0FE8
0FE9

0
0

0
0
0

0

1
2

1 6

5

16

7

16

1 6

16

a u d r a t e g e n e r a t o r ( B R G

1 6
16

eserved (Note

e s e r v e d

o t e

16

e s e r v e d

o t e

e s e r v e d

o t e

1 6

eserved (Note

e s e r v e d

o t e

16

eserved (Note

e s e r v e d

o t e

1 6

e s e r v e d

o t e

1 6
1 6

e s e r v e d

o t e

eserved (Note

1 6

control register

nt field register 8
nt field register 9

o t e: D o n o t w r i t e a n y d a t a t o t h e s e a d d r e s s e s , b e c a u s e t h e s e a r e a s a r e r e s e r v e d

Fig. 9 Memory map of special function register (SFR)

o r t P 0 p u l l - u p c o n t r o

s t e r ( P U L L 0

0

1 6

0

e s e r v e d

o t e

0

1 6

1

0

1 6

2

0FF3

16

Interrupt edge selection regi s ter (INTEDGE)

e s e r v e d

o t e

0FF4

16

e s e r v e d

o t e

0

1 6

5

e s e r v e d

o t e

0FF6

16

e s e r v e d

o t e

0

1 6

7

c o n t r o l r e g i s t e r

0FF8

16

e s e r v e d

o t e

0FF9

16

e s e r v e d

o t e

0

1 6

0

16

0

1 6

e s e r v e d

o t e

0

1 6

0

16

e s e r v e d

o t e

0

1 6

ort P5 pull-up co ntrol register

eserved (Note

memory control register

r e g

.

11

MITSUBISHI MICROCOMPUTERS

38K0 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

I/O PORTS

The I/O ports have direction registers which determine the input/
output direction of each individual pin. Each bit in a direction reg­ister corresponds to one pin, and each pin can be set to be input
port or output port.
When “0” is written to the bit corresponding to a pin, that pin be­comes an input pin. When “1” is written to that bit, that pin be­comes an output pin.
If data is read from a pin set to output, the value of the port output
latch is read, not the value of the pin itself. Pins set to input are
floating. If a pin set to input is written to, only the port output latch
is written to and the pin remains floating.

Table 5 I/O ports functions

Pin

P00–P07

P10–P17

P20–P27

P30–P32
P33/ExINT

P34/ExCS
P35/ExWR
P36/ExRD
P37/ExA0

P40/RxD/
ExDREQ

P41/TxD/
ExDACK

P42/SCLK/
ExTC

P43/SRDY/
ExA1

P50/INT0
P52/INT1

P51/CNTR0
P53–P57
P60–P63

Note: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate poten-

tial, a current will flow from VCC to VSS through the input-stage gate.

Name

Port P0

Port P1

Port P2

Port P3

Port P4

Port P5

Port P6

Input/Output

Input/output,
individual bits

I/O Format

CMOS compatible
input level
CMOS 3-state output

CMOS compatible
input level
CMOS 3-state output
(Power source is
VCCE)

CMOS compatible
input level
CMOS 3-state output

CMOS/TTL compat­ible input level
CMOS 3-state output
(Power source is
VccE)

CMOS compatible
input level
CMOS 3-state output

Non-Port Function

Key-on wake up

A-D conversion input
External bus interface
funciton I/O

External bus interface
funciton output

External bus interface
funciton input

Serial I/O input
External bus interface
funciton output

Serial I/O output
External bus interface
funciton input

Serial I/O I/O
External bus interface
funciton input

Serial I/O output
External bus interface
funciton input

External interrupt input

Timer X function I/O

Related SFRs

Port P0 pull-up control
register

A-D control register
EXB control register

EXB control register

EXB control register

Serial I/O control
register
EXB control register

Serial I/O control
register
EXB control register

Serial I/O control
register
EXB control register

Serial I/O control
register
EXB control register

Port P5 pull-up control
register
Interrupt edge selection
register

Timer X mode register

Diagram No.

(1)

(2)

(3)

(4)
(5)

(6)

(7)

(8)

(9)

(10)

(11)

(12)
(13)
(14)

12

MITSUBISHI MICROCOMPUTERS

38K0 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

( 1 ) P o r t P 0

D a t a b u s

( 2 ) P o r t P 1

E x t e r n a l b u s i n t e r f a c e e n a b l e b i t

D i r e c t i o n r e g i s t e r

D a t a b u s

E X B d a t a o u t p u t

E X B d a t a i n p u t

P u l l - u p c o n t r o l b i t

D i r e c t i o n r e g i s t e r

P o r t l a t c h

K e y - o n w a k e - u p i n p u t

EXO E

P o r t l a t c h

O u t p u t b u f f e r

I n p u t b u f f e r

A - D c o n v e r s i o n i n p u t

VC

CE

A n a l o g i n p u t p i n s e l e c t i o n b i t

(4) Ports P30–P32

D i r e c t i o n r e g i s t e r

D a t a b u sP

o r t l a t c

h

( 5 ) P o r t P 33

E x t e r n a l b u s i n t e r f a c e e n a b l e b i t

D i r e c t i o n r e g i s t e r

D a t a b u s

P o r t l a t c h

EXI N T o u t p u t

( 6 ) P o r t s P 34, P 35, P 36, P 37

E x t e r n a l b u s i n t e r f a c e e n a b l e b i t

D i r e c t i o n r e g i s t e r

D a t a b u sP

o r t l a t c

h

C CE

V

VC

CE

VC

CE

( 3 ) P o r t P 2

D i r e c t i o n r e g i s t e r

D a t a b u s

P o r t l a t c h

Fig. 10 Port block diagram (1)

D ( P

0 ( P

R ( P
EXC S ( P 34)

E

XW

E

XR

36)

E

XA

37)

35)
E x t e r n a l b u s i n t e r f a c e e n a b l e b i t

13

MITSUBISHI MICROCOMPUTERS

k

38K0 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

(7) Port P4

E x t e r n a l b u s i n t e r f a c e e n a b l e b i t

Data bus

(8) Port P4

External bus interface enable bit

D a t a b u s

0

S e r i a l I / O e n a b l e b i t

R e c e i v e e n a b l e b i t

D i r e c t i o n r e g i s t e r

P o r t l a t c h

E

X

D r e q o u t p u t

1

S e r i a l I / O e n a b l e b i t

Receive enable bit

Direction register

P o r t l a t c h

Serial I/O output

EXDac

S e r i a l I / O i n p u t

V

C C

E

V

C C

E

E x t e r n a l b u s i n t e r f a c e e n a b l e b i t

( 1 1 ) P o r t s P 5

D a t a b u s

( 1 2 ) P o r t P 5

Data bus

0 ,

P 5

2

Direction register

Port latch

I N T

0

( P 50) , I N T

1

D i r e c t i o n r e g i s t e r

Port latch

Pulse output mode

Timer output

Pull-up control bit

1

( P 52) i n t e r r u p t i n p u t

CNTR0 interrupt input

(9) Port P4

Serial I/O synchronous clock selection bit

(10) Port P4

External bus interface enable bit

2

Serial I/O enable bit

Serial I/O mode selection bit

S e r i a l I / O e n a b l e b i t

E x t e r n a l b u s i n t e r f a c e e n a b l e b i t

Direction register

D a t a b u s

Serial I/O external clock input

Serial I/O mode selection bit

S e r i a l I / O e n a b l e b i t

S

RDY

output enable bit

Data bus

P o r t l a t c h

S e r i a l I / O c l o c k o u t p u t

EXTC

3

Direction register

P o r t l a t c h

(13) Ports P53–P5

VCCE

Serial I/O synchronous clock selection bit
External bus interface enable bit

V

C C

E

Data bus

( 1 4 ) P o r t P 6

Data bus

7

D i r e c t i o n r e g i s t e r

P o r t l a t c h

D i r e c t i o n r e g i s t e r

Port latch

Serial I/O output

EXA1

E x t e r n a l b u s i n t e r f a c e e n a b l e b i t

Fig. 11 Port block diagram (2)

14

MITSUBISHI MICROCOMPUTERS

P

l l

P

P

b

b

P

P

P

b

b

38K0 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

7

0

0 p u l l - u p c o n t r o l r e g i s t e

o r t

( P 0 P U L L : a d d r e s s 0 F F 0

- u p c o n t r o l b i

0

p u

0

r

1 6

)

t
0 : N o p u l l - u p
1 : P u l l - u p

P 0

1

p u l l - u p c o n t r o l b i t
0 : N o p u l l - u p
1 : P u l l - u p

P 0

2

p u l l - u p c o n t r o l b i t
0 : N o p u l l - u p
1 : P u l l - u p

P 0

3

p u l l - u p c o n t r o l b i t
0 : N o p u l l - u p
1 : P u l l - u p

P 0

4

p u l l - u p c o n t r o l b i t
0 : N o p u l l - u p
1 : P u l l - u p

P 0

5

p u l l - u p c o n t r o l b i t
0 : N o p u l l - u p
1 : P u l l - u p

P 0

6

p u l l - u p c o n t r o l b i t
0 : N o p u l l - u p
1 : P u l l - u p

P 0

7

p u l l - u p c o n t r o l b i t
0 : N o p u l l - u p
1 : P u l l - u p

7

0

5 p u l l - u p c o n t r o l r e g i s t e

o r t

( P 5 P U L L : a d d r e s s 0 F F 2

r

1 6

)

50 pull-up control bit

0 : No pull-up
1 : Pull-up

Nothing is arranged for this bit. This is a write disabled bit.
When this bit is read out, the contents are “0”.

P5

2

pull-up co ntrol bit
0 : No pull-up
1 : Pull-up

Nothing is arranged for these bits. These are write disabled
bits. When these bits are read out, the contents are “0”.

Fig. 12 Structure of port I/O-related registers

15

MITSUBISHI MICROCOMPUTERS

38K0 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

INTERRUPTS

Interrupts occur by fifteen sources: four external, ten internal, and

one software.

Interrupt Control

Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in­terrupt set by the BRK instruction. An interrupt occurs if the corre­sponding interrupt request and enable bits are “1” and the inter­rupt disable flag is “0”.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction cannot be disabled with any flag or bit. The I
flag disables all interrupts except the BRK instruction interrupt.
When several interrupts occur at the same time, the interrupts are
received according to priority.

Interrupt Operation

By acceptance of an interrupt, the following operations are auto­matically performed:

1. The contents of the program counter and the processor status
register are automatically pushed onto the stack.

2. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.

3. The interrupt jump destination address is read from the vector
table into the program counter.

■Notes on interrupts

When setting the followings, the interrupt request bit may be set to

“1”.

•When setting external interrupt active edge

Related register:

When not requiring for the interrupt occurrence synchronized with
these setting, take the following sequence.

➀Set the corresponding interrupt enable bit to “0” (disabled).
➁Set the interrupt edge select bit (active edge switch bit).
➂Set the corresponding interrupt request bit to “0” after 1 or more

instructions have been executed.

➃Set the corresponding interrupt enable bit to “1” (enabled).

Interrupt edge selection register (address
0FF316), Timer X mode register (address

002316)

Table 6 Interrupt vector addresses and priority

Interrupt Source

Reset (Note 2)
USB bus reset
USB SOF
USB device

External bus

INT0
Timer X
Timer 1
Timer 2
INT1

(Note 3)

Serial I/O
reception

Serial I/O
transmission

CNTR0
Key-on wake up
A-D conversion
BRK instruction

Notes 1: Vector addresses contain interrupt jump destination addresses.

2: Reset function in the same way as an interrupt with the highest priority.
3: Nothing is arranged in these vector addresses.
4: Fix bit 1 of interrupt control register 2 (address 003F

Priority

1
2
3
4

5

6
7
8
9

10

—

11

12

13
14
15
16

Vector Addresses (Note 1)

High

FFFD16

FFFB16
FFF916
FFF716

FFF516

FFF316
FFF116

FFEF16
FFED16
FFEB16

FFE916

FFE716

FFE516

FFE316

FFE116
FFDF16
FFDD16

Low
FFFC16
FFFA16

FFF816
FFF616

FFF416

FFF216

FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616

FFE416

FFE216
FFE016
FFDE16

FFDC16

16) to “0”.

Interrupt Request

Generating Conditions
At reset
At detection of USB bus reset signal (2.5 µs interval SE0)
At detection of USB SOF signal
At detection of resume signal (K state or SE0) or suspend signal (3

ms interval bus idle), or at completion of transaction
At completion of reception or transmission or at completion of DMA

transmission
At detection of either rising or falling edge of INT0 input
At timer X underflow
At timer 1 underflow
At timer 2 underflow
At detection of either rising or falling edge of INT1 input

(Note 4)

At completion of serial I/O data reception

At completion of serial I/O data transmission

At detection of either rising or falling edge of CNTR0 input
At falling of conjunction of input level for port P2 (at input mode)
At completion of A-D conversion
At BRK instruction execution

16

t
t

t

b

b

I

I N T

i

( I N T E D G E

)

I

U S B

I

d

(IREQ

C16)

( I C O N

E

)

I

INT

(IREQ

D16)

I

d

(ICON

F16)

F

b7b

b7b

b7b

b7b

U S B

INT

I n t e r r u p t r e q u e s t b i

I n t e r r u p t e n a b l e b i

Interrupt disable flag (I)

MITSUBISHI MICROCOMPUTERS

38K0 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Fig. 13 Interrupt control

7

✽ “0” can be set by software, but “1”

cannot be set .

0

n t e r r u p t e d g e s e l e c t i o n r e g i s t e

: a d d r e s s 0 F F

n t e r r u p t e d g e s e l e c t i o n b i

0

N o t u s e d ( r e t u r n “ 0 ” w h e n r e a d )
I N T

1

i n t e r r u p t e d g e s e l e c t i o n b i t

N o t u s e d ( r e t u r n “ 0 ” w h e n r e a d )

0

n t e r r u p t r e q u e s t r e g i s t e r

1 : address 003

b u s r e s e t i n t e r r u p t r e q u e s t b i
U S B S O F i n t e r r u p t r e q u e s t b i t

U S B d e v i c e i n t e r r u p t r e q u e s t b i t
E X B i n t e r r u p t r e q u e s t b i t
I N T

0

i n t e r r u p t r e q u e s t b i t
T i m e r X i n t e r r u p t r e q u e s t b i t
T i m e r 1 i n t e r r u p t r e q u e s t b i t
T i m e r 2 i n t e r r u p t r e q u e s t b i t

B R K i n s t r u c t i o n

R e s e

I n t e r r u p t r e q u e s t

r

1 6

3

t

a l l i n g e d g e a c t i v
0 :

1 : R i s i n g e d g e a c t i v e

1

e

n t e r r u p t r e q u e s t r e g i s t e r

0

2

2 : address 003

t

1

interrupt request bit
Nothing is arranged for this bit. This is a
write disabled bit. When this bit is read
out, the contents are “0”.
Serial I/O receive interrupt request bit
Serial I/O transmit int erru pt reques t bit
CNTR

0

interrupt request bit
Key- on wake- up interrupt requ est bit
A-D conversion interrupt request bit
Nothing is arranged for this bit. This is a
write disabled bit. When this bit is read
out, the contents are “0”.

0 : No interrupt re quest issue
1 : Interrupt request issued

0

n t e r r u p t c o n t r o l r e g i s t e r
1 : a d d r e s s 0 0 3

b u s r e s e t i n t e r r u p t e n a b l e b i
U S B S O F i n t e r r u p t e n a b l e b i t

U S B d e v i c e i n t e r r u p t e n a b l e b i t
E X B i n t e r r u p t e n a b l e b i t
I N T

0

i n t e r r u p t e n a b l e b i t
T i m e r X i n t e r r u p t e n a b l e b i t
T i m e r 1 i n t e r r u p t e n a b l e b i t
T i m e r 2 i n t e r r u p t e n a b l e b i t

✽ “ 0 ” c a n b e s e t b y s o f t w a r e , b u t “ 1 ”

c a n n o t b e s e t .

Fig. 14 Structure of interrupt-related registers

0

1

1 6

t

nterrupt co ntrol register 2

2 : address 003

1

interrupt enable bit
Fix this bit to “0”.
Serial I/O receive interrupt enable bit
Serial I/O transmit int erru pt enable bit
CNTR

0

interrupt enable bit
Key- on wake- up interrupt enabl e bit
A-D conversion interrupt enab le bit
Fix this bit to “0”.

0 : Interrupts disable
1 : Interrupts enabled

17

MITSUBISHI MICROCOMPUTERS

38K0 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Key Input Interrupt (Key-on Wake Up)

A Key-on wake up interrupt request is generated by applying a
falling edge to any pin of port P0 that have been set to input mode.
In other words, it is generated when AND of input level goes from

P o r t P X x

“ L ” l e v e l o u t p u t

P0

P0

P0

7

output

6

output

5

output

P U L L 0 r e g i s t e r
B i t 7 = “ 0 ”

✽

P U L L 0 r e g i s t e r
B i t 6 = “ 0 ”

✽

P U L L 0 r e g i s t e r
B i t 5 = “ 0 ”

✽

✽ ✽

✽ ✽

✽ ✽

P o r t P 0
d i r e c t i o n r e g i s t e r = “ 1 ”

P o r t P 0

7

l a t c h

6

Port P0
latch

P o r t P 0

5

l a t c h

“1” to “0”. An example of using a key input interrupt is shown in
Figure 15, where an interrupt request is generated by pressing
one of the keys consisted as an active-low key matrix which inputs
to ports P00–P03.

7

P o r t P 0

6

d i r e c t i o n r e g i s t e r = “ 1 ”

Port P0

5

direction register = “1”

K e y i n p u t i n t e r r u p t r e q u e s t

P 0

4

o u t p u t

P 0

3

P 0

2

P0

1

0

P 0

i n p u t

i n p u t

input

i n p u t

P U L L 0 r e g i s t e r
B i t 4 = “ 0 ”

✽

P U L L 0 r e g i s t e r
B i t 3 = “ 1 ”

✽

P U L L 0 r e g i s t e r
B i t 2 = “ 1 ”

✽

PULL 0 register
Bit 1 = “1”

✽

P U L L 0 r e g i s t e r
B i t 0 = “ 1 ”

✽

✽ ✽

✽ ✽

✽ ✽

✽ ✽

✽ ✽

P o r t P 0
l a t c h

P o r t P 0
l a t c h

P o r t P 0
l a t c h

P o r t P 0
l a t c h

P o r t P 0
l a t c h

Port P0

4

direction register = “1”

4

P o r t P 0

3

d i r e c t i o n r e g i s t e r = “ 0 ”

3

Port P0

2

direction register = “0”

2

Port P0

1

direction register = “0”

1

0

P o r t P 0
d i r e c t i o n r e g i s t e r = “ 0 ”

0

Port P0
Input reading circuit

Fig. 15 Connection example when using key input interrupt and port P0 block diagram

✽ P - c h a n n e l t r a n s i s t o r f o r p u l l - u p
✽ ✽ C M O S o u t p u t b u f f e r

18

MITSUBISHI MICROCOMPUTERS

T i

T i

b

b

38K0 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

TIMERS

The 38K0 group has three timers: timer X, timer 1, and timer 2.
The division ratio of each timer or prescaler is given by 1/(n + 1),
where n is the value in the corresponding timer or prescaler latch.
All timers are down count timers. When the timer reaches “0016”,
an underflow occurs at the next count pulse and the correspond­ing timer latch is reloaded into the timer and the count is contin­ued. When a timer underflows, the interrupt request bit corre­sponding to that timer is set to “1”.

7

Fig. 16 Structure of timer X mode register

0

m e r X m o d e r e g i s t e
( T M : a d d r e s s 0 0 2 3

i n t e r r u p t

m e r X o p e r a t i n g m o d e b i t

i n t e r r u p

a c t i v e e d g e s w i t c h b i

b 1 b 0
00 : T i m e r m o d e
01 : P u l s e o u t p u t m o d e
10 : E v e n t c o u n t e r m o d e
11 : P u l s e w i d t h m e a s u r e m e n t m o d e

0

C N T R

0 : F a l l i n g e d g e a c t i v e f o r C N T R

C o u n t a t r i s i n g e d g e i n e v e n t c o u n t e r m o d e

1 : R i s i n g e d g e a c t i v e f o r C N T R

C o u n t a t f a l l i n g e d g e i n e v e n t c o u n t e r m o d e

T i m e r X c o u n t s t o p b i t

0 : C o u n t s t a r t
1 : C o u n t s t o p

N o t u s e d ( r e t u r n “ 0 ” w h e n r e a d )

r

1 6)

s

t

0

0

t

Timer 1 and Timer 2

The count source of prescaler 12 is the system clock divided by

16. The output of prescaler 12 is counted by timer 1 and timer 2,
and a timer underflow periodically sets the interrupt request bit.

Timer X

Timer X can each select in one of four operating modes by setting
the timer X mode register.

(1) Timer Mode

The timer counts the count source selected by timer count source
selection bit.

(2) Pulse Output Mode

The timer counts the system clock divided by 16. Whenever the
contents of the timer reach “0016”, the signal output from the
CNTR0 pin is inverted. If the CNTR0 active edge selection bit is
“0”, output begins at “ H”.
If it is “1”, output starts at “L”. When using a timer in this mode, set
the corresponding port P51 direction register to output mode.

(3) Event Counter Mode

Operation in event counter mode is the same as in timer mode,
except that the timer counts signals input through the CNTR0 pin.
When the CNTR0 active edge selection bit is “0”, the rising edge of
the CNTR0 pin is counted.
When the CNTR0 active edge selection bit is “1”, the falling edge
of the CNTR0 pin is counted.

(4) Pulse Width Measurement Mode

If the CNTR0 active edge selection bit is “0”, the timer counts the
system clock divided by 16 while the CNTR0 pin is at “H”. If the
CNTR0 active edge selection bit is “1”, the timer counts it while the
CNTR0 pin is at “L”.

The count can be stopped by setting “1” to the timer X count stop
bit in any mode. The corresponding interrupt request bit is set
each time a timer underflows.

19

e a s u r e m e n t

D a t a b u s

MITSUBISHI MICROCOMPUTERS

38K0 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

P 5

1

/ C N T R

S y s t e m c l o c k

0

1

Port P5
direction
register

S y s t e m c l o c k

D i v i d e r

1 / 1 6

C N T R

0

a c t i v e

e d g e s e l e c t i o n b i t

“ 0 ”

“ 1 ”

P o r t P 5
l a t c h

P u l s e o u t p u t m o d e

D i v i d e r

1 / 1 6

P u l s e w i d t h

m

m o d e

CNTR
edge selection bit

1

Prescaler 12 latch (8)

E v e n t
c o u n t e r
m o d e

0

active

P r e s c a l e r 1 2 ( 8 )

Timer mode
Pulse output
mode

T i m e r X c o u n t s t o p b i t

P r e s c a l e r X l a t c h ( 8 )

“ 1 ”

Q
Q

“0”

Data bus

Prescaler X (8)

Toggle

flip-flop

T

R

Timer 1 latch (8)

Timer 1 (8)

Timer X latch (8)

Timer X (8)

Timer X latch write
Pulse output mode

Timer 2 latch (8)

Timer 2 (8)

T i m e r X i n t e r r u p t
r e q u e s t b i t

C N T R

0

i n t e r r u p t

r e q u e s t b i t

T i m e r 2 i n t e r r u p t
r e q u e s t b i t

Fig. 17 Timer block diagram

T i m e r 1 i n t e r r u p t
r e q u e s t b i t

20

MITSUBISHI MICROCOMPUTERS

P

EXT C

S

P

EXA

S

P

EXD R E Q

D

S

k

F/F

r

A d d

R

)

R

(RI)

S h i f

k

S

Add

B R G

D

Add

Shif

k

T

)

T

(TBE)

T

(TI)

T

Add

D

A d d

P

EXDACK/TxD

R

S

D

D0D1D2D3D4D5D

R B F

T B E

T B E

T

hif

k

Serial

TXD

S

RXD

W

O

(OE)

N

T h

D

D0D

D

D3D4D5D

38K0 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

SERIAL I/O

Serial I/O can be used as either clock synchronous or asynchro­nous (UART) serial I/O. A dedicated timer (baud rate generator) is
also provided for baud rate generation.

ata bus

r e s s 0 0 2

R e c e i v e b u f f e r r e g i s t e r

/ R x

0

/

4

2

/

/

4

C L K

c o u n t s o u r c e s e l e c t i o n b i

y s t e m c l o c

1 / 4

3

/

1

/

4

R D Y

F a l l i n g - e d g e d e t e c t o r

41/

R e c e i v e s h i f t r e g i s t e r

t c l o c

e r i a l I / O s y n c h r o n o u
c l o c k s e l e c t i o n b i t

F r e q u e n c y d i v i s i o n r a t i o 1 / ( n + 1 )

t

Transmit shift register

Transmit buffer regis ter

B a u d r a t e g e n e r a t o r

ata bus

6

1 6

ress 0FE2

t cloc

ress 0026

(1) Clock Synchronous Serial I/O Mode

Clock synchronous serial I/O mode can be selected by setting the
mode selection bit of the serial I/O control register (bit 6 of ad­dress 0FE016) to “1”.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the Trancemit/Receive buffer register.

S e r i a l I / O c o n t r o l r e g i s t e r

e c e i v e b u f f e r f u l l f l a g ( R B F

eceive interrupt re qu es t

Clock control circuit

s

1/4

16

Clock control circuit

ransmit interrupt source selection bit

ransmit buffer empty flag

Serial I/ O status regi s te

16

r e s s 0 F E

r a n s m i t s h i f t r e g i s t e r s h i f t c o m p l e t i o n f l a g ( T S C

ransmit interrupt request

ress 0027

1 6

0

16

Fig. 18 Block diagram of clock synchronous serial I/O

ransfer s
(1/2 to 1/2048 of the internal
clock, or an external clock)

e c e i v e e n a b l e s i g n a l
r i t e s i g n a l t o r e c e i v e / t r a n s m i t

b u f f e r r e g i s t e r ( a d d r e s s 0 0 2 6

t cloc

output

e r i a l i n p u t

R D Y

1 6

)

=

0

=

1

T S C = 0

o t e

e t r a n s m i t i n t e r r u p t ( T I ) c a n b e g e n e r a t e d e i t h e r w h e n t h e t r a n s m i t b u f f e r r e g i s t e r h a s e m p t i e d ( T B E = 1 ) o r a f t e r t h e t r a n s m i t

s

1 :

s h i f t o p e r a t i o n h a s e n d e d ( T S C = 1 ) , b y s e t t i n g t h e t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t ( T I C ) o f t h e s e r i a l I / O 1 c o n t r o l r e g i s t e r .

2 : I f d a t a i s w r i t t e n t o t h e t r a n s m i t b u f f e r r e g i s t e r w h e n T S C = 0 , t h e t r a n s m i t c l o c k i s g e n e r a t e d c o n t i n u o u s l y a n d s e r i a l d a t a i s

o u t p u t c o n t i n u o u s l y f r o m t h e T

3 : T h e r e c e i v e i n t e r r u p t ( R I ) i s s e t w h e n t h e r e c e i v e b u f f e r f u l l f l a g ( R B F ) b e c o m e s “ 1 ” .

X

D p i n .

1

Fig. 19 Operation of clock synchronous serial I/O function

6

2

6

7

7

=
T S C = 1

verrun error

detection

1

21

MITSUBISHI MICROCOMPUTERS

S

k

OE

PE

F E

D

R

Add

R

hif

R

)

R

)

B

F

)

Add

D

T

hif

Add

T

hif

hif

(TSC)

T

(TBE)

T

(TI)

A d d

S T d

SP d

UART

Add

Ch

A d d

B R G

t

T

bit

S

C l

C h

Serial I/O

P

EXT C

S

K

Serial I/O

P

EXD R E Q

D

P

EXDACK/TxD

T S C
R B F

T B E

TBE

RBF

RBF

S T

D0D

S P

D

0

D

S T

S P

TBE

S T

D0D

S P

D0D

S T

S P

T

l

b i

E

N

S

TXD

S

RXD

R

l

T

k

38K0 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

(2) Asynchronous Serial I/O (UART) Mode

Clock asynchronous serial I/O mode (UART) can be selected by
setting the serial I/O mode selection bit of the serial I/O control
register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer regis-

a t a b u

ress 0026

a r a c t e r l e n g t h s e l e c t i o n b i

/ R x

0

/

4

e t e c t o

r

7 b i t s
8 bits

e r i a l I / O s y n c h r o n o u s c l o c k s e l e c t i o n b i

/

2

/

4

C L

c o u n t s o u r c e s e l e c t i o n b i

y s t e m c l o c

1 / 4

41/

aracter length selection bit

16

eceive buffer register

t

eceive s

t register

etector

r e q u e n c y d i v i s i o n r a t i o 1 / ( n + 1

a u d r a t e g e n e r a t o

ress 0FE2

ST/SP/PA generator

ransmit s

Transmi t buffer register

ata bus

ter, but the two buffers have the same address in memory. Since
the shift register cannot be written to or read from directly, transmit
data is written to the transmit buffer, and receive data is read from
the receive buffer.
The transmit buffer can also hold the next data to be transmitted,
and the receive buffer register can hold a character while the next
character is being received.

s

t

r

16

1/16

t register

ress 0026

1 control register

e c e i v e b u f f e r f u l l f l a g ( R B F

r e s s 0 F E

e c e i v e i n t e r r u p t r e q u e s t ( R I

o c k c o n t r o l c i r c u i

t

ransmit interrupt source selection

16

status register

1/16

1 6

0

control register

ress 0FE1

ransmit s

t register s

ransmit interrupt request

ransmit buffer empty flag

r e s s 0 0 2

7

16

t completion flag

1 6

Fig. 20 Block diagram of UART serial I/O

r a n s m i t o r r e c e i v e c l o c

ransmit buffer write signa

=

0

=

0

T B E = 1

e r i a l o u t p u t

e c e i v e b u f f e r r e a d s i g n a

e r i a l i n p u t

r r o r f l a g d e t e c t i o n o c c u r s a t t h e s a m e t i m e t h a t t h e R B F f l a g b e c o m e s “ 1 ” ( a t 1 s t s t o p b i t , d u r i n g r e c e p t i o n )

o t e s

1 :
2 : T h e t r a n s m i t i n t e r r u p t ( T I ) c a n b e g e n e r a t e d t o o c c u r w h e n e i t h e r t h e T B E o r T S C f l a g b e c o m e s “ 1 ” , d e p e n d i n g o n t h e s e t t i n g o f t h e t r a n s m i t i n t e r r u p t

s o u r c e s e l e c t i o n b i t ( T I C ) o f t h e s e r i a l I / O 1 c o n t r o l r e g i s t e r .

3 : T h e r e c e i v e i n t e r r u p t ( R I ) i s s e t w h e n t h e R B F f l a g b e c o m e s “ 1 ” .
4 : A f t e r d a t a i s w r i t t e n t o t h e t r a n s m i t b u f f e r r e g i s t e r w h e n T S C = 1 , 0 . 5 t o 1 . 5 c y c l e s o f t h e d a t a s h i f t c y c l e i s n e c e s s a r y u n t i l c h a n g i n g t o T S C = 0 .

Fig. 21 Operation of UART serial I/O function

=0

1

t

1 s t a r t
7 o r 8 d a t a b i t s
1 o r 0 p a r i t y b i t
1 o r 2 s t o p b i t ( s )

1

=1

1

✽

G e n e r a t e d a t 2 n d b i t i n 2 - s t o p - b i t m o d e

=

=1

0

1

.

T S C = 1

✽

=1

22

[Serial I/O Control Register (SIOCON)] 0FE016

The serial I/O control register contains eight control bits for the se­rial I/O function.

[UART Control Register (UARTCON)] 0FE116

The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer.

[Serial I/O Status Register (SIOSTS)] 002716

The read-only serial I/O status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer reg­ister, and the receive buffer full flag is set. A write to the serial I/O
status register clears all the error flags OE, PE, FE, and SE (bit 3
to bit 6, respectively). Writing “0” to the serial I/O enable bit SIOE
(bit 7 of the serial I/O control register) also clears all the status
flags, including the error flags.
All bits of the serial I/O status register are initialized to “0” at reset,
but if the transmit enable bit (bit 4) of the serial I/O control register
has been set to “1”, the transmit shift register shift completion flag
(bit 2) and the transmit buffer empty flag (bit 0) become “1”.

MITSUBISHI MICROCOMPUTERS

38K0 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

[Transmit Buffer/Receive Buffer Register (TB/
RB)] 0026

The transmit buffer register and the receive buffer register are lo­cated at the same address. The transmit buffer register is write­only and the receive buffer register is read-only. If a character bit
length is 7 bits, the MSB of data stored in the receive buffer regis­ter is “0”.

16

[Baud Rate Generator (BRG)] 0FE216

The baud rate generator determines the baud rate for serial trans­fer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate genera­tor.

■Notes on serial I/O

When setting the transmit enable bit to “1”, the serial I/O transmit
interrupt request bit is automatically set to “1”. When not requiring
the interrupt occurrence synchronized with the transmission
enalbed, take the following sequence.

➀Set the serial I/O transmit interrupt enable bit to “0” (disabled).
➁Set the transmit enable bit to “1”.
➂Set the serial I/O transmit interrupt request bit to “0” after 1 or

more instructions have been executed.

➃Set the serial I/O transmit interrupt enable bit to “1” (enabled).

23

MITSUBISHI MICROCOMPUTERS

BRG

(CSS)

S

T

)

Serial I/O

U A R T

C h

)

38K0 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

b 7b

0

(SIOSTS : address 0027

r a n s m i t b u f f e r e m p t y f l a g ( T B E
0 : B u f f e r f u l l

1 : B u f f e r e m p t y
R e c e i v e b u f f e r f u l l f l a g ( R B F )

0 : B u f f e r e m p t y
1 : B u f f e r f u l l

T r a n s m i t s h i f t r e g i s t e r s h i f t c o m p l e t i o n f l a g ( T S C )
0 : T r a n s m i t s h i f t i n p r o g r e s s
1 : T r a n s m i t s h i f t c o m p l e t e d

O v e r r u n e r r o r f l a g ( O E )
0 : N o e r r o r
1 : O v e r r u n e r r o r

P a r i t y e r r o r f l a g ( P E )
0 : N o e r r o r
1 : P a r i t y e r r o r

F r a m i n g e r r o r f l a g ( F E )
0 : N o e r r o r
1 : F r a m i n g e r r o r

S u m m i n g e r r o r f l a g ( S E )
0 : ( O E ) U ( P E ) U ( F E ) = 0
1 : ( O E ) U ( P E ) U ( F E ) = 1

N o t u s e d ( r e t u r n s “ 1 ” w h e n r e a d )

b 7b

c o n t r o l r e g i s t e r

0

( U A R T C O N : a d d r e s s 0 F E 1

a r a c t e r l e n g t h s e l e c t i o n b i t ( C H A S
0 : 8 b i t s

1 : 7 b i t s
P a r i t y e n a b l e b i t ( P A R E )

0 : P a r i t y c h e c k i n g d i s a b l e d
1 : P a r i t y c h e c k i n g e n a b l e d

P a r i t y s e l e c t i o n b i t ( P A R S )
0 : E v e n p a r i t y
1 : O d d p a r i t y

S t o p b i t l e n g t h s e l e c t i o n b i t ( S T P S )
0 : 1 s t o p b i t
1 : 2 s t o p b i t s

N o t u s e d ( r e t u r n “ 0 ” w h e n r e a d )
( T h i s i s a w r i t e d i s a b l e d b i t . )

N o t u s e d ( r e t u r n “ 1 ” w h e n r e a d )

status register

b7 b0

16

)

1 6

)

e r i a l I / O c o n t r o l r e g i s t e
( S I O C O N : a d d r e s s 0 F E 0

count source selection bit
0: System clock
1: System clock/4

Serial I/O synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous serial

I/O is selected.
BRG output divided by 16 when UART is selected.

1: External clock input when clock synchronous serial I/O is

selected.
External clock input divided by 16 when UART is selected.

RDY

output enable bit (SRDY)

S

3

pin operates as ordinary I/O pin

0: P4
1: P4

3

pin operate s as S

Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed

Transmit enable bit ( TE)
0: Transmit disabled
1: Transmit enabled

Receive enable bit (RE)
0: Receive disabled
1: Receive enabled

Serial I/O mode selection bi t (SIOM)
0: Asynchronous serial I/O (UART)
1: Clock synchronous serial I/O

Serial I/O enable bit (SIOE)
0: Serial I/O disabled

0

(pins P4

1: Serial I/O enabled

0

(pins P4

r

1 6

)

RDY

output pin

–P43 operate as ordinary I/O pins)
–P43 can operate as serial I/O pins)

Fig. 22 Structure of serial I/O control registers

24

MITSUBISHI MICROCOMPUTERS

38K0 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

USB FUNCTION

38K0 Group is equipped with a USB function control circuit
(USBFCC) that enables effective interfacing with the host-PC.
This circuit is in compliance with USB Specification Version 2.0
Full-Speed Transfer Mode (12 Mbps, equivalent to Version 1.1).
This circuit also supports all four transfer-types specified in the
standard USB specification.
The USBFCC has four endpoints that can select its transfer type.
Although Endpoint 0 is fixed to Control Transfer, the Endpoints 1
to 3 can be set to Interrupt Transfer, Bulk Transfer, or Isochronous
Transfer.
A dedicated circuit automatically performs stage management for
Control Transfer and packet management for transactions, which
are necessary for matching of data transmit/receive timing, error
detection, and retry after error. This dedicated control circuit en­ables the user to develop a program or timing design very easily.
Each endpoint can be programmed for data transfer conditions so
that the endpoints are adaptive for all USB device class transfer
systems.
The data buffer of each endpoint can be assigned to any area in
the multi-channel RAM. This feature offers highly efficient memory
usage by avoiding re-buffering and enabling simple data modifica­tion.

The transmit/receive data is directly transferred to the data buffer
via the control circuit (direct RAM access type) without disturbing
the CPU operation. This mechanism enables the CPU to transfer
data smoothly with no drop in performance. In addition to this
buffer function, a double-buffer setting will keep a re-buffering stall
at a minimum and increase the overall data throughput (max. 64
bytes X 2 channels).
As other special signals control, the endpoints have detection
functions for the USB bus reset signal, resume signal, suspend
signal, and SOF signal, and also have a remote wake-up signal
transmit function.
When completing data transfer or receiving a special signal, the
endpoint generates the corresponding interrupt to the CPU (3 vec­tors/18 factors).
With all this essential yet comprehensive built-in hardware, your
system using the 38K2 group will be ready for any USB applica­tion that comes its way.

38K0 Group MCU

External MCU

Built-in Peripheral

Functions

External Bus Interface

(EXB)

Program ROM

Fig. 23 USB function overview

USB Data Transfer

The USB specification promises 12 Mbps data transfer in the full­speed mode, that is equivalent to 1.5 M bytes per second of data
transactions.
However, in USB data transfer, bit-stuffing may be executed de­pending on the bit patterns of the transfer data, possibly resulting
in 1-byte data (normally 8 bits) handled as up to 10 bits.
Because USB uses asynchronous transfers, the clock cycle of the
USB internal reference clock may change to adjust to the clock
phase. Therefore, the access timing of the USBFCC for the multi­channel RAM will change owing to the frequency of internal clock φ:
When the USBFCC is operating at φ =8 MHZ, access for a normal

CPU

Interrupt request

USBMulti-channel RAM

Data transmit/Receive path
[Direct RAM Access Type]

USB Bus

(USB-Host)

transfer is performed every 5 to 6 cycles and access for a bit-stuff­ing transfer is performed in up to 7 cycles.
If the EXB function is enabled in the above conditions, this func­tion generates a maximum wait of 1 clock cycle, so that the
access is performed every 4 to 8 cycles.
When operating at φ = 6MHZ, a normal access is performed every
4 cycles. If the clock-phase correction of the reference clock oc­curs, access is performed every 3 to 5 cycles.
If bit stuffing occurs at this clock rate, the access cycle will be ex­tended to up to 6 cycles. When the EXB function that generates a
maximum 1-wait cycle is used in this condition, the access cycle
will be 2 (min.) to 7 (max.) cycles.

25

USB Function Control Circuit (USBFCC)
Block Diagram

The following diagram shows the USBFCC block diagram. The cir­cuit comprises:
(1) Serial Interface Engine (SIE)
(2) Device Control Unit (DCU)
(3) Internal Memory Interface (MIF)
(4) CPU Interface (CIF)

U S B F u n c t i o n C o n t r o l C i r c u i t

MITSUBISHI MICROCOMPUTERS

38K0 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

D C U c o n t r o l

U
D

D C U s t a t u s

U
C

P

F
C

I

MIF control

C

F
M

I

M u l t i - C h a n n e l R A M

Fig. 24 USB Function Control Circuit (USBFCC) block diagram

(1) Serial Interface Engine (SIE)

The SIE performs the following USB lower-layer protocols (pack­ets, transactions):

•Sampling of receive data and clock, generation of transmit clock

•Serial-to-parallel conversion of transmit/receive data

•NRZI (Non Return Zero Invert) encode/decode

•Bit stuffing/unstuffing

•SYNC (Synchronization Pattern) detection, EOP (End of
Packet) detection

•USB address detection, endpoint detection

•CRC (Cyclic Redundancy Check) generation and checking

SIE control

r

S I E s t a t u s

E
S

I

D 0 +
D 0 -

U

S B T r a n s c e i v e

Transmit/Receive

data

(3) Memory Interface (MIF)

The MIF controls the flow of data transfer between the SIE and the
multi-channel RAM under the management of the DCU.

(4) CPU Interface (CIF)

The CIF performs the following functions:

•Mode setting via registers, DCU control signal generation, DCU
status signal reading

•Interrupt signal generation

•Internal bus interface control.

(2) Device Control Unit (DCU)

The DCU manages the following USB upper-layer protocols (ad­dress/endpoint and control-transfer sequence):

•Status control for each endpoint

•Control-transfer sequence control

•Memory interface status control

26

USB Port External Circuit Configuration

Full

Full

The operation mode of the USB port driver circuit can be config­ured by USB control register (address 001016).
Figure 25 shows the USB port external circuit block diagram.

D V

C C

R E F

V

R E F E

U S B R e f e r e n c e

V

R E F C O N

V o l t a g e C i r c u i t

0

E

1

V

3.3V output
Normal mode

MITSUBISHI MICROCOMPUTERS

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

VREFCON

01

Hiz Hiz

3.3V output
Low-power mode

USBVREF status

USBVREF

2 . 2 µF

38K0 Group

0 . 1 µF

T R O N C O N

TRONE

X

OUT

PLL

“1”

f

VCO

UCLKCON

“ 0 ”

f

U S B

USB

Module

USBE

USBDIFE

USBE

USBE

Fig. 25 USB port external circuit (D0+, D0-, USBVREF, TrON) block diagram

Speed

Speed

T R O N

1.5 kΩ

D 0 +

+

-

D 0 -

2 7 Ω

2 7 Ω

27

MITSUBISHI MICROCOMPUTERS

38K0 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Endpoint Buffer Area Setting

The buffer area used in data transfer can be assigned to any area
of the multi-channel RAM for each endpoint.

●Buffer area beginning address

The buffer area configuration register (address 0FED16) defines
the beginning address of the buffer area (every 32 bytes) for each
Endpoint. However, the only RAM area is configurable.

•00h [Address 000016], 01h [Address 002016]: Not configurable

•02h [Address 004016] to 1Fh [Address 03E016]: Configurable

●Interrupt-source dependant buffer area offset address

An offset value is added to the beginning address of each source,
which is specified by the interrupt source register (address
001D16), for each endpoint.
This section describes in detail the beginning address specified by
the buffer area set register as offset address 00h, according to
each endpoint.

(1) Endpoint 00

Endpoint 00 has two kinds of interrupt sources for accessing the
buffer. The respective address offsets are:

•BSRDY00 (SETUP Buffer Ready Interrupt): Offset address = 00h

•BRDY00 (OUT or IN Buffer Ready Interrupt):

Offset address = 08h

(2) Endpoint 01

The buffer area offset address for each interrupt source for of End­point 01 varies according to the contents of the EP01 set register
(address 001916).

•In single buffer mode (DBLB01 = “0”):
Endpoint 01 has only one interrupt source for accessing the
buffer.
B0RDY01 (Buffer 0 Ready Interrupt): Offset address = 00h

0000

0FED

16

0010 1010

= 15h

0000

Memory

0000

0020

0040

0060

02A0

03E0

16

SFR

16

16

16

RAM

16

16

0FED

16

00

Disabled to be used

01

02

03

15

1F

Fig. 26 Example setting of buffer area beginning address

•In double buffer mode (DBLB01 = “1”):
Endpoint 01 has two kinds of interrupt sources for accessing the
buffer.
B0RDY01 (Buffer 0 Ready Interrupt): Offset address = 00h
B1RDY01 (Buffer 1 Ready Interrupt):
The offset address varies according to the double buffer begin­ning address set bit (BSIZ01).

-Offset address = 08h when BSIZ01 = 00

-Offset address = 10h when BSIZ01 = 01

-Offset address = 40h when BSIZ01 = 10

-Offset address = 80h when BSIZ01 = 11

(3) Endpoints 02 and 03

Same as Endpoint 01.

Notes

The selected RAM area must be within addresses 004016 to
03FF16.
Make sure the buffer area beginning address is set in agreement
with the offset address and the number of transmit/receive data
bytes.
This is particularly important when in the double buffer mode or
when handling 64-byte data.

(a) When selecting Endpoint 00

Memory

16

02A0

Offset

00

h

(b) When selecting Single Buffer Mode

Memory

02A016

Offset

00h

BSRDY00

02A816

08h

B0RDY01

BRDY00

Fig. 27 Examples of interrupt source dependant buffer area offset address

(c) When selecting Double Buffer Mode

(when BSIZ01 = 11)

Memory

02A016

Offset

00h

B0RDY01

032016

80h

B1RDY01

28

USB Interrupt Function

USB Interrupt Control Circuit (USBINTCON) has 3 requests and
16 USB-device interrupt request sources. Each interrupt source
register enables the user to easily determine which interrupt has
occurred.
Table 7 shows the list of USB interrupt sources.

Table 7 USB interrupt sources

Interrupt request bit

(IREQ1: Address 003C16)

USB bus reset

USB SOF —

USB device EP00

USB interrupt bit

(USBIREQ: Address 001716)

—

EP01

EP02

EP03

SUS

RSM

At USB bus reset signal detection:
After enabling the USB module (USBE = “1”), an interrupt request occurs

when 2.5 µs SE0 state is detected in D0+/D0- port.
(Equivalent to 120-clock length when fUSB = 48 MHz)

At SOF packet receive:
After enabling the USB module (USBE = “1”), an interrupt request occurs

when SOF packet is detected in D0+/D0- port.
Its occurrence does not depend on frame-time or CRC value after SOF
packet is transferred.
(Normally, SOF packet detection occurs only when fUSB = 48 MHz)

At Endpoint 00 data transfer complete:

•Buffer ready (read/write enabled state)

•Control transfer completed

•Status stage transition

•SETUP buffer ready (read enabled state)

•Control transfer error

At Endpoint 01 data transfer complete:

•Buffer 0 ready (read/write enabled state)

•Buffer 1 ready (read/write enabled state)

•Transfer error

At Endpoint 02 data transfer complete:

•Buffer 0 ready (read/write enabled state)

•Buffer 1 ready (read/write enabled state)

•Transfer error

At Endpoint 03 data transfer complete:

•Buffer 0 ready (read/write enabled state)

•Buffer 1 ready (read/write enabled state)

•Transfer error

At suspend signal detection:
After enabling the USB module (USBE = “1”), an interrupt request occurs

when 3 ms J state is detected in D0+/D0- port.
(Equivalent to 144,000 clock-length when fUSB = 48MHz)

At resume signal detection:
After enabling the USB module (USBE = “1”) and resume interrupt (RSME

= “1”), an interrupt request occurs when a bus state change (J state to
SE0 or K state) is detected in D0- port.

MITSUBISHI MICROCOMPUTERS

38K0 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Interrupt source

29

MITSUBISHI MICROCOMPUTERS

38K0 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

[EPXXREG5]

[EP00REQ]

BRDY00
CTEND00
CTSTS00
BSYDY00

ERR00

[EP01REQ]

B0RDY01
B1RDY01

ERR01

[EP02REQ]

B0RDY02
B1RDY02

ERR02

[EP03REQ]

B0RDY03
B1RDY03

ERR03

[USBIREQ]

EP00

EP01

EP02

EP03

[USBICON]

EP00E

USB device
interrupt request

EP01E

EP02E

EP03E

Fig. 28 USB device interrupt control

SUSE

SUS

RSME

RSM

30