MITSUBISHI 38C8 User Manual

查询M38C80E1-XXXFP供应商查询M38C80E1-XXXFP供应商

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to

change.

MITSUBISHI MICROCOMPUTERS

38C8 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

DESCRIPTION

The 38C8 group is the 8-bit microcomputer based on the 740 family core technology. The 38C8 group has a LCD drive control circuit (bias control, time sharing control), a 10-bit A-D converter, and a Serial I/O as additional functions. The various microcomputers in the 38C8 group include variations of internal memory size and packaging. For details, refer to the section on part numbering.

FEATURES

●Basic machine-language instructions ....................................... 71

●The minimum instruction execution time ............................ 0.5 µs

(at 8 MHz oscillation frequency)

●Memory size

ROM ............................................................................ 60 K bytes

RAM ............................................................................ 2048 bytes

●Programmable input/output ports ............................................. 35

●Software pull-up resistors

.................................................................. Ports P0–P3, P41–P47

●Interrupts ...................................................15 sources, 15 vectors

(includes key input interrupt)

●Timers ............................................................8-bit ✕ 3, 16-bit ✕ 2

●Serial I/O ........................8-bit ✕ 1 (UART or Clock-synchronized)

●A-D converter (32 kHz operating available) ... 10-bit ✕ 8 channels

●LCD drive control circuit

Bias ................................................................................... 1/5, 1/7

Duty .............................................................................. 1/16, 1/32

Common output ............................................................... 16 or 32

Segment output ............................................................... 52 or 68

●Main clock generating circuit (RC oscillation selectable)

...................... (connect to external ceramic resonator or resistor)

●Sub-clock generating circuit

............................................. (connect to quartz-crystal oscilaltor)

●Power source voltage

In high-speed mode .................................................... 4.0 to 5.5 V

In middle-speed mode ................................................2.2 to 5.5 V

In low-speed mode ..................................................... 2.2 to 5.5 V

●Power dissipation

In high-speed mode ........................................................... 30 mW

(at 8 MHz oscillation frequency, at 5 V power source voltage)

In low-speed mode .............................................................60 µW

(at 32 kHz oscillation frequency, at 3 V power source voltage, at WIT state, at voltage multiplier operating, LCD drive waveform generating state)

●Operating temperature range ................................... – 20 to 85°C

APPLICATIONS

Dot-matrix-type displays

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to

change.

PIN CONFIGURATION (TOP VIEW)

5

6

7

9

0

1

G3 S

E

0 61

G3 S

E

0 51

G3 S

E

0 41

8

G3

E

S

0 31

2

G3

G4

S

E

S

E

S

E

1

2

0

1

0

1

0

S E G3 S E G3 S E G3 S E G3 S E G2 S E G2 S E G2 S E G2 S E G2 S E G2 S E G2 S E G2 S E G2 S E G2 S E G1 S E G1 S E G1 S E G1 S E G1 S E G1 S E G1 S E G1 S E G1 S E G1

S E G9

S E G8 S E G7/ C O M2 S E G6/ C O M2 S E G5/ C O M2 S E G4/ C O M2 S E G3/ C O M1 S E G2/ C O M1 S E G1/ C O M1 SEG0/COM16

COM7 COM6

4

G3

E

S

E

1

0 81

0 71

1 0 9

3

1 1 0

2

1 1 1

1

1 1 2

0

1 1 3

9

1 1 4

8

1 1 5

7

116

6

117

5

118

4

119

3

120

2

121

1

122

0

123

9

1 2 4

8

1 2 5

7

1 2 6

6

1 2 7

5

128

4

129

3

130

2

131

1

132

0

133 134 135

3

1 3 6

2

1 3 7

1

1 3 8

0

1 3 9

9

1 4 0

8

1 4 1

7

1 4 2 1 4 3 1 4 4

123456789

0

1

2

3

G4 S

E

9

99

4

G4 S

E

89

5

G4 S

E

79

6

G4 S

E

69

7

G4 S

E

59

8

G4 S

E

49

9

G4 S

E

39

E

29

G5 S

E

19

G5 S

E

08

G5 S

E

98

3

G5

E

S

88

M 3 8 C 8 9 M F - X X X F P

1

01

11

21

31

41

51

61

71

81

92

02

12

4

G5 S

E

78

22

MITSUBISHI MICROCOMPUTERS

38C8 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

1

0

8

9

7

6

5

M2

4/

G6 S

E

C O

77

13

23

M2

5/

G6 S

E

C O

67

33

M2

6/

G6

E

S

C O

57

43

4

M2

7/ 6

G S

O

47

53

5

4

M1

C

O

3

6

7 2

C O M1

7 1

C O M1

7 0

C O M1

6 9

C O M1

6 8

C O M9

6 7

C O M8

N

6 6

P 30/ AI

6 5

P31/AIN1

6 4

P32/AIN2

N

6 3

P 33/ AI NC

6 2

XIN

6 1 6 0 5 9 5 8 5 7 5 6 55 54 5 3 5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7

N C VSS XOUT OSCSEL

VC

C

NC XCIN

O U

XC NC

R E S E T P10/AIN4

P11/AIN5 P12/AIN6

N

P 13/ AI P14 P 15 P 16 P 17

P 00 P01 P 02 P 03 P04 P05

5

G5 S

E

68

32

6

G5 S

E

58

42

7

G5 S

E

48

52

8

G5

E

S

38

62

9

G5 S

E

C O

28

72

M3

0/

G6 S

E

C O

18

82

M3

1/

G6 S

E

C O

07

93

M2

2/

G6

E

S

C O

97

03

M2

3/

G6 S

E

C O

87

3 2 1 0

0

3

T

7

C

O M5C

O

M4

O M3C

C

O

C

O M0C

O

M1

M2

Fig. 1 M38C89MF-XXXFP pin configuration

2

1

VL

L

C3C2C1

VL

V

5

4

3

2

)

N

S

C N

27P

VS

I

VL

S

( N C

VS

Package type : 144P6Q-A

26

P

25P

24P

23P

22

P

21P

K

Y

20P

SR 47/

L

P

D

-

TXD

RXD

SC

45/

44/

46/

P

R1/

43/

B E E P

C N T

P

7

+

T

0

06

T0

P

40/

T1/

P

I N

R0/

41/

A D

I N

P

42/ P

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to

change.

1

0

M

C

O

C

O

MITSUBISHI MICROCOMPUTERS

38C8 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

7

6

5

1

0

9

0

1

2

6

7

8

1

M

/

4

5

2

3

M

C

O

C

O

C

O

1

25436

4 41

/

6

7

0

1

2

M

G

E

S

E

S

E

S

E

C

O

C O

0

2

1

4 11

4

1

4 31

4

3

1

2

M

/

0

1

3

4

5

6

7

G

S

E

S

E

S

E

S

E

C O

9

1

3 81

3 71

3 61

3 51

1

3

3 41

8

G S

E

3 31

9

G S

E

3 21

1

G S

E

3 11

2

1

G

S

E

0

3

7

6

5

G

E

S

E

S

E

S

E

4

8

9

3

2

M

/

0

1

2

8

9

6

5

G

C O

S

E

S

E

S

E

S

E

4

1

8

28

38

98

08

r D L

c

C

o n t r o l l e

4

8

2

M

/

3

6

G C O

E

S

87

5

4

3

2

1

4

5

6

7

1

6

M

G

C

O

C O

S

E

S

E

S

E

37

47

57

67

77

0

1

M C

O

27

9

1

8

M

C

O

C

O

C

O

C

O

C

O

7 6

6

86

97

07

17

5 V

L

4 V

L

3

9 8 7

V

L

2

0 1

V

L

1

1 1

V

L

21

3

1

C

31

2 C

1

41

C

N

5

I

L V

S

8 1

VS

S

s

9 5

VS

D

a t a b u

C

6

C

V

t

T

15 5

R

E S E

R

e s e t i n p u

t

T

3 5

O U

XC

S

u b - c l o c k o

u t p u

t

N

4 5

I

XC

S

u b - c l o c k i

n p u

T

t

8 5

O

U

X

C

l o c k o

u t p u

t

N

1 6

XI

C

l o c k i

n p u

)

M R

A

(

L

C D R A M

1 7 6 b y t e

)

T

i m e r X ( 1 6

r

M

T

i m e

)

T

i m e r Y ( 1 6

)

i m e r 2 ( 8 )T

i m e r 3 ( 8

)T

T

i m e r 1 ( 8

1

C N T R0, C N T R

R

O

L

C

A

X

Y

S

P

U C

P

t

H

C P

)

A

- D c o n v e r t e r ( 1 0

φ

)

C

l o c k g e n e r a t i n g c i r c u i

S

e r i a l I / O ( 8

K e y - o n w a k e - u p

6 52

2

4

) P

2 ( 8

) P

1 ( 8

) P

0 ( 8

) P

3 ( 4

) P

4 ( 7

1

32 26 12

I

/ O p o r t P

02 2

9 1

0 95

1

8 74 64 54

I

/ O p o r t P

44 4

3 4

2 14

4

0

04 94 83

3 7

3

I

/ O p o r t P

6 3

5 3

3

6 6

5 6

4 2 36

I

/ O p o r t P

7 2

8 2

4

9 2

0 13 23

3

I

/ O p o r t P

3 3

4 3

I N T0, I N T

FUNCTIONAL BLOCK DIAGRAM (Package: 144P6Q-A)

Fig. 2 Functional block diagram

3

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to

change.

PIN DESCRIPTION

Table 1 Pin description

MITSUBISHI MICROCOMPUTERS

38C8 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

VCC, VSS RESET XIN

XOUT

OSCSEL

XCIN XCOUT

VLIN

VL1 – VL5

COM0 – COM32

SEG0/COM16– SEG7/COM23,

SEG60COM31– SEG67/COM

SEG8–SEG59 P00–P07 P14–P17 P10/AIN4–

P13/AIN7 P20–P27 P30/AIN0 –

P33/AIN3

P40/INT0

P41/INT1/ADT

P42/CNTR0/ BEEP+, P43/CNTR1/ BEEP-

P44/RxD, P45/TxD, P46/SCLK, P47/SRDY

C1, C2, C3

VSS (NC), NC

24

Name

Power source Reset input Clock input

Clock output

RC oscillation select

Sub-clock input Sub-clock output

Power source input for LCD

LCD power source

Common output

Segment output/ Common output

Segment output I/O port P0 I/O port P1

I/O port P2 I/O port P3

Input port P4

I/O port P4

Voltage multiplier

Function

• Apply voltage of 4.0–5.5 V to VCC, and 0 V to VSS. (at high-speed mode)

• Reset input pin for active “L.”

• Input and output pins for the main clock generating circuit.

• Feedback resistor is built in between XIN pin and XOUT pin.

• Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set the

oscillation frequency.

• If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.

• This pin determines the oscillation between XIN and XOUT. The oscillation method can be selected from

either by an oscillator or by a resistor.

• Input and output pins for sub-clock generating circuit. (Connect a quartz-crystal oscillator between the XCIN and XCOUT pins to set the oscillation frequency . The clock generated the externals cannot be input directly.)

• Reference voltage input pin for LCD.

• The input voltage to this pin is boosted threefold by voltage multiplier.

• LCD drive power source pins.

• LCD common output pins.

• LCD segment/common output pins.

• LCD segment output pins.

• 8-bit I/O port.

• CMOS compatible input level.

• CMOS 3-state output structure.

• 4-bit I/O port.

• CMOS compatible input level.

• CMOS 3-state output structure.

• 1-bit input port.

• CMOS compatible input level.

• 7-bit I/O port.

• CMOS compatible input level.

• CMOS 3-state output structure.

• I/O direction register allows each pin to be individually

programmed as either input or output.

• External capacitor connect pins for a voltage multiplier of LCD.

• Non-function pins.

• Leave the VSS (NC) pin open.

Function except a port function

• A-D converter analog input pin

• Key-on wake-up interrupt input pin

• A-D converter analog input pin

• External interrupt pin

• A-D trigger input pin

•Timer function I/O pin

• Serial I/O I/O pin

4

PRELIMINARY

M

M F

X X X F P

P

R O M / P R O M

The fi

ROM

M

RAM si

Pack

R O M

b

Notice: This is not a final specification.

Some parametric limits are subject to

change.

P ART NUMBERING

r o d u c

t

3 8 C

89

MITSUBISHI MICROCOMPUTERS

38C8 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

–

age type

FP: 144P6Q-A package

n u m b e

O m i t t e d i n O n e T i m e P R O M v e r s i o n .

s i z

1 : 4 0 9 6 b y t e s 2 : 8 1 9 2 b y t e s 3 : 1 2 2 8 8 b y t e s 4 : 1 6 3 8 4 b y t e s 5 : 2 0 4 8 0 b y t e s 6 : 2 4 5 7 6 b y t e s 7 : 2 8 6 7 2 b y t e s 8 : 3 2 7 6 8 b y t e s

are reserved areas; they cannot be used.

e m o r y t y p

M : M a s k R O M v e r s i o n E : O n e T i m e P R O M v e r s i o n

r

e

y t e 9 : 3 6 8 6 4

A : 4 0 9 6 0 b y t e s B : 4 5 0 5 6 b y t e s C : 4 9 1 5 2 b y t e s D : 5 3 2 4 8 b y t e s E : 5 7 3 4 4 b y t e s F : 6 1 4 4 0 b y t e s

rst 128 bytes and the last 2 bytes of

e

s

Fig. 3 Part numbering

ze

0: 192 bytes 1: 256 bytes 2: 384 bytes 3: 512 bytes 4: 640 bytes 5: 768 bytes 6: 896 bytes 7: 1024 bytes 8: 1536 bytes 9: 2048 bytes

5

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to

change.

MITSUBISHI MICROCOMPUTERS

38C8 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

GROUP EXPANSION

Mitsubishi plans to expand the 38C8 group as follows.

Memory Type

Support for mask ROM and One Time PROM versions

Memory Size

ROM/PROM size ............................................................ 60 K bytes

RAM size........................................................................ 2048 bytes

Memory Expansion Plan

R O M s i z e ( b y t e s )

6 0 K

56K

4 8 K

4 0 K

3 2 K

28K

24K

20K

Packages

144P6Q-A ...................................0.5 mm-pitch plastic molded QFP

U n d e r d e v e l o p m e n t

M38C89MF/EF

16K

1 2 K

8K

4K

2 5 63 8 45 1 2 640 7 6 88 9 6

192

P r o d u c t s u n d e r d e v e l o p m e n t o r p l a n n i n g : t h e d e v e l o p m e n t s c h e d u l e a n d s p e c i f i c a t i o n m a y b e r e v i s e d w i t h o u t n o t i c e . T h e d e v e l o p m e n t o f p l a n n i n g p r o d u c t s m a y b e s t o p p e d .

Fig. 4 Memory expansion plan

Currently planning products are listed below.

Table 2 Support products

Product name

M38C89MF-XXXFP M38C89EFFP

(P) ROM size (bytes)

ROM size for User in ( )

61440 (61310) 61440 (61310)

R A M s i z e ( b y t e s )

RAM size

(bytes)

2048 2048

1,024

Package

144P6Q-A 144P6Q-A

1 , 5 3 62

Remarks

Mask ROM version One Time PROM version

, 0 4

8

As of Dec. 2000

6

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to

change.

MITSUBISHI MICROCOMPUTERS

38C8 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU)

The 38C8 group uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 family instructions are as follows: The FST and SLW instruction cannot be used. The STP, WIT, MUL, and DIV instruction can be used.

[Accumulator (A)]

The accumulator is an 8-bit register. Data operations such as data transfer, etc., are executed mainly through the accumulator.

[Index Register X (X)]

The index register X is an 8-bit register. In the index addressing modes, the value of the OPERAND is added to the contents of register X and specifies the real address.

[Index Register Y (Y)]

The index register Y is an 8-bit register. In partial instruction, the value of the OPERAND is added to the contents of register Y and specifies the real address.

b7

[Stack Pointer (S)]

The stack pointer is an 8-bit register used during subroutine calls and interrupts. This register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack page selection bit is “0” , the high-order 8 bits becomes “0016”. If the stack page selection bit is “1”, the high-order 8 bits becomes “0116”. The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure 6. Store registers other than those described in Figure 6 with program when the user needs them during interrupts or subroutine calls.

[Program Counter (PC)]

The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed.

b0

A Accumulator

b7

b0

X Index register X

b7

b0

Y Index register Y

b7 b0

S Stack pointer

b7b15 b0

L Program counterPCH

PC

b7 b0

N V T B D I Z C Processor status register (PS)

Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag Index X mode flag Overflow flag Negative flag

Fig. 5 740 Family CPU register structure

7

PRELIMINARY

e

Notice: This is not a final specification.

Some parametric limits are subject to

change.

O n - g o i n g R o u t i n

MITSUBISHI MICROCOMPUTERS

38C8 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

P u s h r e t u r n a d d r e s s o n s t a c k

POP return address from stack

Interrupt request

M ( S )( P CH)

S ) – ( S )

M ( S )( P CL)

(S) (S)– 1

Subroutine

E x e c u t e R T S

S ) + ( S )

( P CL)M ( S )

(S) (S) + 1

( P CH)M ( S )

(Note)

(

M (S) (PCH)

E x e c u t e J S R

1

S ) – ( S )

(

1

M ( S )( P CL)

S ) –

( S )

(

1

M ( S )( P S )

S ) – ( S )

(

1

Interrupt

Service Routine

Execute RTI

S ) +

( S )

(

1

(PS) M (S)

S ) + ( S )

(

1

(PCL)M (S)

S ) + ( S )

(

1

Push return address on stack

Push contents of processor status register on stack

I Flag is set from “0” to “1” Fetch the jump vector

POP contents of processor status register from stack

POP return address from stack

Note: Condition for acceptance of an interrupt Interrupt enable flag is “1”

Fig. 6 Register push and pop at interrupt generation and subroutine call

Table 3 Push and pop instructions of accumulator or processor status register

Push instruction to stack

Accumulator Processor status register

I n t e r r u p t d i s a b l e f l a g i s “ 0 ”

PHA PHP

(PCH)M (S)

Pop instruction from stack

PLA PLP

8

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to

change.

MITSUBISHI MICROCOMPUTERS

38C8 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

[Processor status register (PS)]

The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag , Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid.

•Bit 0: Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction.

•Bit 1: Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is “0”, and cleared if the result is anything other than “0”.

•Bit 2: Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is “1”.

•Bit 3: Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is “0”; decimal arithmetic is executed when it is “1”. Decimal correction is automatic in decimal mode. Only the ADC

•Bit 4: Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always “0”. When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to “1”.

•Bit 5: Index X mode flag (T) When the T flag is “0”, arithmetic operations are performed between accumulator and memory. When the T flag is “1”, direct arithmetic operations and direct data transfers are enabled between memory locations.

•Bit 6: Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag.

•Bit 7: Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag.

Table 4 Set and clear instructions of each bit of processor status register

Set instruction Clear instruction

C flag

SEC CLC

Z flag

– –

I flag

SEI CLI

D flag

SED CLD

B flag

– –

T flag

SET CLT

V flag

–

CLV

N flag

– –

9

PRELIMINARY

N

P

CPU

( C P U M

B

)

b

Notice: This is not a final specification.

Some parametric limits are subject to

change.

[CPU Mode Register (CPUM)] 003B16

The CPU mode register contains the stack page selection bit and the internal system clock selection bit. The CPU mode register is allocated at address 003B16.

MITSUBISHI MICROCOMPUTERS

38C8 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

7

Fig. 7 Structure of CPU mode register

0

mode register

( C M ) : a d d r e s s 0 0 3

rocessor mode bits b1 b0 0 0 : Single-chip mode 0 1 : 1 0 : 1 1 : Stack page selection bit

0 : 0 page

1 : 1 page Not used (returns “1” when read) (Do not write “0” to this bit) Sub-clock (X

0 : Stopped

1 : Oscillating Main clock (X

0 : Oscillating

1 : Stopped Main clock division ratio selection bit

0 : f(X

1 : f(XIN)/8 (middle-s peed mode) Internal system clock selection bit

0 : X

1 : XCIN–XCOUT selected (low-s peed mode)

o t a v a i l a b l

CIN–XCOUT) stop bit

IN–XOUT) stop bit

IN)/2 (high-speed m ode)

IN–XOUT selected (m iddle-/high-speed mode)

1 6

e

10

PRELIMINARY

F F

R A M

A d d

F

R O M

Add

F F

F F D C

F F F E

FFFF16X X X X

YYYY16ZZZZ

RAM

ROM

S F R

N

d

I

a

R

Z

S

R

ROM

Notice: This is not a final specification.

Some parametric limits are subject to

change.

MITSUBISHI MICROCOMPUTERS

38C8 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MEMORY Special Function Register (SFR) Area

The Special Function Register area in the zero page contains control

Zero Page

Access to this area with only 2 bytes is possible in the zero page addressing mode.

registers such as I/O ports and timers.

Special Page

RAM

RAM is used for data storage and for stack area of subroutine calls and interrupts.

Access to this area with only 2 bytes is possible in the special page addressing mode.

ROM

The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs.

Interrupt Vector Area

The interrupt vector area contains reset and interrupt vectors.

a r e

a

s i z

( b y t e s )

192 256 384 512 640 768 896 1024 1536 2048

a r e

s i z

( b y t e s )

4 0 9 6

8 1 9 2 1 2 2 8 8 1 6 3 8 4 2 0 4 8 0 2 4 5 7 6 2 8 6 7 2 3 2 7 6 8 3 6 8 6 4 4 0 9 6 0 4 5 0 5 6 4 9 1 5 2 5 3 2 4 8 5 7 3 4 4 6 1 4 4 0

r e s s

e

X X X X

0 0 0 1 3 F 0 1 B F 0 2 3 F 0 2 B F 0 3 3 F 0 3 B F 0 4 3 F 0 6 3 F 0 8 3 F

1 6 1 6 1 6

1 6 1 6

1 6 1 6 1 6 1 6

a

e

YYYY

0 0 E 0 0 0

D 0 0 0 C 0 0 0 B 0 0 0 A 0 0 0 9 0 0 0 8 0 0 0 7 0 0 0 6 0 0 0 5 0 0 0 4 0 0 0 3 0 0 0 20 0 0 10 0 0

ress

0

16

1 6

1 6 1 6 1 6 1 6 1 6

1 6 1 6 1 6 1 6 1 6 1 6 1 6 1 6 1 6

ZZZZ

080 E080 D080 C080 B080 A080 9080 8080 7080 6080 5080 4080 3080 2080 1080

ress

16

16 16 16 16

16 16 16 16 16 16 16 16 16 16

0000

0040

0130

0 3 4 0

0 4 3 0

0840

0

16

LCD display RA M area

16

1 6

L C D d i s p l a y R A M a r e a

1 6

16

e s e r v e d R O M a r e

16

1 6

0

1 6

nterrupt vector are

1 6

eserved

a r e

ot use

( 1 2 8 b y t e s )

a

e r o p a g

e

✽

a

p e c i a l p a g

e

area

✽ The stard address of the LCD display area can be switched either zero page (addresses 004016–00EF16) or 3 page (addresses

0340

16

Fig. 8 Memory map diagram

–03EF16) by software. Immediately after reset released, 3 page is selected.

11

PRELIMINARY

T

(TB/RB)

A

B

C

D

E

F

A

B

C

D

E

F

A

B

C

D

E

F

A

B

C

D

E

F

P

)

P

)

P

)

P

)

P

)

P

)

P

)

P

)

P

D)

S

)

Serial I/O

(SIOCON)

UART

(UARTCON)

I

)

Ti

(TXM)

I

(INTEDGE)

CPU

(CPUM)

I

(IREQ1)

I

(IREQ2)

I

(ICON1)

Ti

(TXL)

P U L L

)

P U L L

)

L C D

)

A

)

A-D

(ADL)

A-D

(high

(ADH)

P

)

B

)

T i

)

T i

)

T i

)

T i

)

T i

)

T i

)

T i

)

T i

)

L C D

)

L C D

)

Notice: This is not a final specification.

Some parametric limits are subject to

change.

0 0 0 0

1 6

ort P0 (P0

o r t P 0 d i r e c t i o n r e g i s t e r ( P 0 D

0 0 0 1

1 6

o r t P 1 ( P 1

0 0 0 2

1 6

o r t P 1 d i r e c t i o n r e g i s t e r ( P 1 D

0 0 0 3

1 6

0 0 0 4

1 6

ort P2 (P2

o r t P 2 d i r e c t i o n r e g i s t e r ( P 2 D

0 0 0 5

1 6

o r t P 3 ( P 3

0 0 0 6

1 6

o r t P 3 d i r e c t i o n r e g i s t e r ( P 3 D

0 0 0 7

1 6

o r t P 4 ( P 4

0 0 0 8

1 6

0009

16

ort P4 direction register (P4

000

16

0 0 0

1 6

0 0 0

1 6

0 0 0

1 6

0 0 0

1 6

0 0 0

1 6

0010

16

0 0 1 1

1 6

0012

16

0013

16

0 0 1 4

1 6

0 0 1 5

1 6

r e g i s t e r A ( P U L L A

0 0 1 6

1 6

r e g i s t e r B ( P U L L B

0 0 1 7

1 6

0 0 1 8

1 6

ransmit/Receive buffer register

e r i a l I / O s t a t u s r e g i s t e r ( S I O S T S

0019

16

001 001 001 001 001 001

16 16

a u d r a t e g e n e r a t o r ( B R G

16 16 16 16

control register

0020 0021 0022 0023 0024 0025 0026 0027 0028

0029 0 0 2 0 0 2 002 002 002 002

0030

0031

0032

0033

0034

0035

0036

0037

0038

0039 0 0 3 0 0 3 0 0 3 0 0 3 0 0 3 003

MITSUBISHI MICROCOMPUTERS

38C8 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

16

mer X (low-order)

m e r X ( h i g h - o r d e r ) ( T X H

16

m e r Y ( l o w - o r d e r ) ( T Y L

16

m e r Y ( h i g h - o r d e r ) ( T Y H

16

m e r 1 ( T 1

16

m e r 2 ( T 2

16

m e r 3 ( T 3

16 16

mer X mode register

m e r Y m o d e r e g i s t e r ( T Y M

16

m e r 1 2 3 m o d e r e g i s t e r ( T 1 2 3 M

16 1 6 1 6 16 16 16 16 16

- D c o n t r o l r e g i s t e r ( A D C O N

16 16

conversion register (low-order)

16

conversion register

16 16 16

c o n t r o l r e g i s t e r 1 ( L C 1

16

c o n t r o l r e g i s t e r 2 ( L C 2

16

m o d e r e g i s t e r ( L M

16 1 6

nterrupt edge selection register

1 6

mode register

1 6

nterrupt request register 1

1 6

nterrupt request register 2

1 6

nterrupt control register 1

n t e r r u p t c o n t r o l r e g i s t e r 2 ( I C O N 2

16

-order)

Fig. 9 Memory map of special function register (SFR)

12

PRELIMINARY

P 00– P 03 p u l l - u p P 04– P 07 p u l l - u p P 1

0

– P 13 p u l l - u p

P 14– P 17 p u l l - u p P 20– P 23 p u l l - u p P 24– P 27 p u l l - u p P 3

0

– P 33 p u l l - u p

N o t u s e d ( r e t u r n “ 0 ” w h e n r e a d )

N o t e : T h e c o n t e n t s o f P U L L r e g i s t e r A a n d P U L L r e g i s t e r B d o

n o t a f f e c t p o r t s p r o g r a m m e d a s t h e o u t p u t p o r t .

Notice: This is not a final specification.

Some parametric limits are subject to

change.

MITSUBISHI MICROCOMPUTERS

38C8 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

I/O PORTS [Direction Registers]

The I/O ports P0–P3 and P41–P47 have direction registers which determine the input/output direction of each individual pin. Each bit in a direction register corresponds to one pin, each pin can be set to be input port or output port. When “0” is written to the bit corresponding to a pin, that pin becomes an input pin. When “1” is written to that bit, that pin becomes an output pin. If data is read from a pin set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating.

Pull-up Control

By setting the PULL register A (address 001616) or the PULL register B (address 001716), ports P0 to P4 except for port P40 can control pull-up with a program. However, the contents of PULL register A and PULL register B do not affect ports programmed as the output ports.

b7 b0

b 7b0

PULL register A (PULLA: address 0016

PULL register B (PULLB: address 0017

N o t u s e d ( r e t u r n “ 0 ” w h e n r e a d ) P 41 p u l l - u p P 4

2

p u l l - u p P 43 p u l l - u p P 4

4

p u l l - u p P 45 p u l l - u p P 46 p u l l - u p P 4

7

p u l l - u p

16

0: No pull-up 1: Pull-up

)

Fig. 10 Structure of PULL register A and PULL register B

13

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to

change.

Table 5 List of I/O port function

Pin P00–P07 P10/AN4–

P13/AN7 P14–P17 P20–P27

P30/AN0– P33/AN3

P40/INT0

P41/INT1 P42/CNTR0/

BEEP+ P43/CNTR1/

BEEPP44/RxD P45/TxD P46/SCLK P47/SRDY COM0–COM7,

COM8–COM SEG0/COM16–

SEG7/COM23, SEG60/COM31–

SEG67/COM SEG8–SEG

24

59

Name Port P0 Port P1

Port P2

Port P3

Port P4

Common

15

Segment/ Common

Segment

Input/Output

Input/Output,

individual bits

Input/Output,

individual bits

Input/Output,

individual bits

Input

Input/Output,

individual bits

Output

I/O format

CMOS 3-state output

CMOS compatible input level CMOS 3-state output

CMOS 3-state output

CMOS compatible input level

CMOS compatible input level CMOS 3-state output

LCD common output

LCD segment output LCD common ouput

LCD segment output

MITSUBISHI MICROCOMPUTERS

38C8 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Non-port function

Key input (key-on wake-up) interrupt input

A-D converter input

External interrupt input

Timer X function I/O

Timer Y function input

Serial I/O funtion I/O

Related SFRs PULL register A PULL register A

A-D control register PULL register A PULL register A

Interrupt control register 2

PULL register A A-D control register

PULL register B Interrupt edge select

register PULL register B

Timer X mode register PULL register B

Timer Y mode register PULL register B Serial I/O control register Serial I/O status register UART control register LCD mode register

Ref. No.

(1) (2)

(1) (1)

(2)

(3)

(1) (4)

(5)

(6) (7) (8) (9)

14

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to

change.

MITSUBISHI MICROCOMPUTERS

38C8 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

( 1 ) P o r t s P 0 , P 14– P 17, P 2 , P 4

D i r e c t i o n

r e g i s t e r

D a t a b u s

P o r t l a t c h

K e y - o n w a k e - u p i n t e r r u p t i n p u t

1

i n t e r r u p t i n p u t , A D T

I N T

1

P u l l - u p c o n t r o l

E x c e p t P 0 , P 1

(3) Port P4

INT0 interrupt input

0

D a t a b u s

( 2 ) P o r ts P 10– P 13, P 3

D i r e c t i o n

r e g i s t e r

Data bus

Port latch

P u l l - u p c o n t r o l

A-D converter input

A n a l o g i n p u t p i n s e l e c t i o n b i t

( 4 ) P o r t P 4

D a t a b u s

2

D i r e c t i o n

r e g i s t e r

P o r t l a t c h

B u z z e r o u t p u t m o d e

T i m e r o u t p u t

Fig. 11 Port block diagram (1)

P u l l - u p c o n t r o l

C N T R0 i n t e r r u p t i n p u t

( 5 ) P o r t P 4

Data bus

Buzzer output mode

3

Direction

register

P o r t l a t c h

Timer output

CNTR

Pull-up control

1

interrupt input

15

PRELIMINARY

t t t

s

t

t t

Notice: This is not a final specification.

Some parametric limits are subject to

change.

MITSUBISHI MICROCOMPUTERS

38C8 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

( 6 ) P o r t P 4

D a t a b u s

(8) Port P4

S e r i a l I / O s y n c h r o n o u

4

S e r i a l I / O e n a b l e b i

R e c e i v e e n a l b l e b i

D i r e c t i o n

r e g i s t e r

P o r t l a t c h

6

c l o c k s e l e c t i o n b i

S e r i a l I / O e n a b l e b i t

Serial I/O mode selection bi

Serial I/O enable bi

Direction

register

Pull-up control

S e r i a l I / O i n p u t

Pull-up control

( 7 ) P o r t P 4

P45/TxD P-channel output disable bit

D a t a b u s

(9) Port P4

S e r i a l I / O m o d e s e l e c t i o n b i

5

S e r i a l I / O e n a b l e b i

T r a n s m i t e n a b l e b i

Direction

register

P o r t l a t c h

Serial I/O output

7

S e r i a l I / O e n a b l e b i

S

R D Y

o u t p u t e n a b l e b i

Direction

register

Pull-up control

P u l l - u p c o n t r o l

Port latchData bus

Serial I/O clock output

Fig. 12 Port block diagram (2)

Serial I/O clock input

Data bus

Serial I/O ready output

P o r t l a t c h

16