MITSUBISHI 38C2 Technical data

F

)

S

)

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

MITSUBISHI MICROCOMPUTERS

38C2 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

DESCRIPTION

The 38C2 group is the 8-bit microcomputer based on the 740 family core technology. The 38C2 group has an LCD drive control circuit, a 10-channel A-D converter, and a Serial I/O as additional functions. The various microcomputers in the 38C2 group include variations of internal memory size and packaging. For details, refer to the section on part numbering.

FEATURES

●Basic machine-language instructions ....................................... 71

●The minimum instruction execution time .......................... 0.25 µs

(at 8MHz oscillation frequency)

●Memory size

ROM ................................................................ 16 K to 60 K bytes

RAM ................................................................. 640 to 2048 bytes

●Programmable input/output ports ............................................. 51

(common to SEG: 24)

●Interrupts................................................... 18 sources, 16 vectors

●Timers ............................................................8-bit ✕ 4, 16-bit ✕ 2

●A-D converter................................................. 10-bit ✕ 8 channels

●Serial I/O ........................8-bit ✕ 2 (UART or Clock-synchronized)

●PWM .................. 10-bit ✕ 2, 16-bit ✕ 1 (common to IGBT output)

PIN CONFIGURA TION (T OP VIEW)

●LCD drive control circuit

Bias ................................................................................... 1/2, 1/3

Duty ........................................................................... 1/2, 1/3, 1/4

Common output .......................................................................... 4

Segment output ........................................................................ 24

●Two clock generating circuits (connect to external ceramic resonator or quartz-crystal oscillator)

●Watchdog timer............................................................... 8-bit ✕ 1

● LED direct drive port .................................................................. 8

(average current: 15 mA, peak current: 30 mA, total current: 90 mA)

●Power source voltage

In through mode.......................................................... 4.0 to 5.5 V

(at 8 MHz oscillation frequency)

In frequency/2 mode ................................................... 1.8 to 5.5 V

(at 4 MHz oscillation frequency, A-D operation excluded)

In low-speed mode ..................................................... 1.8 to 5.5 V

(at 32 kHz oscillation frequency)

●Power dissipation

In through mode................................................................. 26 mW

(at 8 MHz oscillation frequency, VCC = 5 V)

In low-speed mode .............................................................21 µW

(at 32 kHz oscillation frequency, VCC = 3 V)

●Operating temperature range ................................... – 20 to 85°C

( K W7) / P 03/ S E G3 ( K W6) / P 02/ S E G2 ( K W5) / P 01/ S E G1 ( K W4) / P 00/ S E G0

D Y

( K W3) / P 57/ SR

L K

( K W2) / P 56/ SC

1 1

( K W1) / P 55/ TXD1 ( K W0) / P 54/ RXD1

O U

P W P 53/ T4

T/

O U

P W P 52/ T3

M1

T/

M0 P51/INT1 P 50/ I N T0

AVS

VRE P 47/ R T P1/ A N7 P 46/ R T P0/ A N6

Fig. 1 M38C2XMX-XXXFP pin configuration

6

7

8

9

G1

20/

21/

22/

23/

S E

P

)

T

C

R1

D7

VC

XO

R0/

60/ P

C N T

37/ P

( L E

C N T

4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 59 60 61 6 2 6 3 6 4

0

1

4

G6

G7

G8

G5

G /

4

06/

07/

10/

05/

0

S E

P

4 84 74 6

S E

P

4 5444 34 24 1403 93 83 7363 53 43 3

2

G9

G1

11/

12/

13/

14/

S E

P

S E

P

M 3 8 C 2 X M X - X X X F P

12345

N4

N5

44/

45/

P

A

67891 011121 31 4151 6

S

T

N1

N0

N3

N2

VS

1/

0/

43/

42/

C

R

E S E

P

A

N

P

A

OO 41/

P

U T

A

O U

OO 40/

P

A

U T

T

XC 62/

P

I

3

4

5

G1

17/

15/

16/

S E

P

S

N

VS

XI

XC 61/

P

U

Package type : 64P6N-A/64P6Q-A

3 2 3 1 30 29 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 19 1 8 1 7

P24/SEG20 P25/SEG21 P26/SEG22/VL1 P27/SEG23/VL2 VL3 COM0 COM1 COM2 C O M3

D Y

( L E P 30/ SR

2/

P31/SCLK2/(LED1

P 32/ TXD2/ ( L E D2

P33/RXD2/(LED3)

P 34/ I N T2/ ( L E D4

O U

( L E P 35/ TX

T/

O U

( L E P 36/ T2

T/φ/

D0

)

D5

)

D6

)

PRELIMINARY

T

i m e

r

T

i m e r X ( 1 6 b i t s

)

P

W M ( 1 6 b i t s

)

I

G B T o u t p u

t

T

i m e r Y ( 1 6 b i t s

)

T

i m e r 1 ( 8 b i t s

)

T

i

m

e

r

2

(

8

b

i

t

s

)

T

i

m

e

r

3

(

8

b

i

t

s

)

P

W

M

0

(

1

0

b

i

t

s

)

T

i

m

e

r

4

(

8

b

i

t

s

)

P

W

M

1

(

1

0

b

i

t

s

)

P

o r t P 0 ( 8

)

P

o

r

t

P

1

(

8

)

8

P

o r t P 2 ( 8

)

8

I

n t e r n a l p e r i p h e r a l f u n c t i o

n

A

- D c o n v e r s i o

n

1

0 - b i t

✕

8 - c h a n n e

l

S

e r i a l I /

O

S

e r i a l I / O 1

(

U A R T o r C l o c k s y n c h r o n o u s

)

S

e r i a l I / O

2

(

U A R T o r C l o c k s y n c h r o n o u s

)

L

C D d r i v e c o n t r o l c i r c u i

t

4

C O M

✕

2 4 S E

G

S

y s t e m c l o c k

φ g

e n e r a t i o

n

X

I

N

–

X

O

U

T

(

M a i n c l o c k

)

X

C

I

N

–

X

C

O U

T

(

S u b - c l o c k

)

e

m

o

r

y

R

O

M

R

A M f o r L C D d i s p l a

y

(

1 2 b y t e s

)

R

A

M P

U

c

o

r

e

W

a t c h d o g t i m e

r

8

P

o r t P 4 ( 8

)

P

o

r

t

P

5

(

8

)

P

o r t P 6 ( 3

)

P

o r t P 3 ( 8

)

8

Notice: This is not a final specification.

Some parametric limits are subject to change.

MITSUBISHI MICROCOMPUTERS

38C2 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

FUNCTIONAL BLOCK DIAGRAM

Fig. 2 Functional block diagram

2

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

PIN DESCRIPTION

Table 1 Pin description (1)

VCC, VSS VREF

AVSS RESET XIN

XOUT

VL3

COM0 – COM3

P00/SEG0 – P03/SEG3 P04/SEG4 – P07/SEG7 P10/SEG8 – P17/SEG15 P20/SEG16 – P25/SEG21 P26/SEG22/VL1 P27/SEG23/VL2 P30/SRDY2 P31/SCLK2 P32/TxD2 P33/RxD2 P34/INT2 P35/TXOUT P36/T2OUT/φ P37/CNTR0 P40/OOUT0/AN0 P41/OOUT1/AN1 P42/AN2– P45/AN5 P46/RTP0/AN6 P47/RTP1/AN7 P50/INT0 P51/INT1 P52/T3OUT/PWM0 P53/T4OUT/PWM1 P54/RxD1 P55/TxD1 P56/SCLK1 P57/SRDY1

Power source Analog reference voltage Analog power source Reset input Clock input

Clock output

LCD power source Common output

I/O port P0

I/O port P1

I/O port P2

I/O port P3

I/O port P4

I/O port P5

MITSUBISHI MICROCOMPUTERS

38C2 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

FunctionPin Name

• Apply voltage of 1.8 V to 5.5 V to VCC, and 0 V to VSS.

•Reference voltage input pin for A-D converter.

•GND input pin for A-D converter. Connect to VSS.

•Reset input pin for active “L.”

•Input and output pins for the main clock generating circuit.

•Feedback resistor is built in between XIN pin and XOUT pin.

•Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to

set the oscillation frequency. When an external clock is used, connect the clock source to XIN, and leave XOUT pin open.

• Input 0 ≤ VL1 ≤ VL2 ≤ VL3 ≤ VCC voltage.

•Input 0 – VL3 voltage to LCD.

•LCD common output pins.

•COM2 and COM3 are not used at 1/2 duty ratio.

•COM3 is not used at 1/3 duty ratio.

• 8-bit I/O port.

• CMOS compatible input level.

•CMOS 3-state output structure.

•I/O direction register allows each port to be individually

programmed as either input or output.

• Pull-up control is enabled.

Function except a port function

• LCD segment output pins

• Serial I/O2 function pins

• External interrupt pin

• Timer X, Timer 2 output pins

• Timer X function pin

• AD converter input

pins

• External interrupt pins

• Timer 3, Timer 4 output pins

• PWM output pins

• Serial I/O1 function pins

• Key input interrupt input pins

• Key input interrupt

pins

• LCD power source input pins

• Oscillation external output pins

• Real time port function pins

3

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

PIN DESCRIPTION

Table 2 Pin description (2)

P60/CNTR1 P61/XCIN P62/XCOUT

CNVSS

I/O port P6

CNVSS

MITSUBISHI MICROCOMPUTERS

38C2 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

FunctionPin Name

•3-bit I/O port.

•CMOS compatible input level.

•CMOS 3-state output structure.

•I/O direction register allows each pin to be individually

programmed as either input or output.

•Pull-up control is enabled.

•VPP power input pin in the flash mode. When MCU is operating, connect to VSS.

Function except a port function

• Timer Y function pin

• I/O pins for sub-clock generating circuit.

Connect oscillators to them.

4

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

PART NUMBERING

MITSUBISHI MICROCOMPUTERS

38C2 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

M38C2 9 M C – XXX HPProduct

Package type

: 64P6N-A package

FP

: 64P6Q-A package

HP

ROM number Omitted in Flash memory version.

Characteristics – : Standard

D : Extended operating temperature version

ROM/PROM size 1

: 4096 bytes : 8192 bytes

2

: 12288 bytes

3 4

: 16384 bytes : 20480 bytes

5

: 24576 bytes

6 7

: 28672 bytes : 32768 bytes

8

The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used.

Memory type MF : Mask ROM version

: Flash memory version

RAM size 0

: 192 bytes : 256 bytes

1

: 384 bytes

2 3

: 512 bytes : 640 bytes

4

: 768 bytes

5 6

: 896 bytes : 1024 bytes

7

: 1536 bytes

8 9

: 2048 bytes

: 36864 bytes

9

: 40960 bytes

A

: 45056 bytes

B

: 49152 bytes

C

: 53248 bytes

D

: 57344 bytes

E

: 61440 bytes

F

Fig. 3 Part numbering

5

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

MITSUBISHI MICROCOMPUTERS

38C2 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

GROUP EXPANSION

Mitsubishi plans to expand the 38C2 group as follows.

Memory T ype

Support for mask ROM, Flash-memory versions

Memory Size

ROM/flash memory size...................................... 16 K to 60 K bytes

RAM size............................................................. 640 to 2048 bytes

Memory Expansion Plan

ROM size (bytes)

60K 56K 48K 40K 32K 28K 24K

Under development

M38C24M6

Packages

64P6Q-A ..................................... 0.5 mm-pitch plastic molded QFP

64P6N-A ..................................... 0.8 mm-pitch plastic molded QFP

Under development

M38C29FF

Under development

M38C29MC

20K 16K 12K

8K 4K

256 384 512 640 768 896

192

Products under development or planning : the development schedule and specification may be revised without notice.

Fig. 4 Memory expansion plan

Currently supported products are listed below.

Table 3 Support products

Product name

M38C29MC-XXXFP M38C29MC-XXXHP M38C24M6-XXXFP M38C24M6-XXXHP M38C24M4-XXXFP M38C24M4-XXXHP M38C29FFFP M38C29FFHP

ROM size (bytes)

ROM size for User in ( )

49152 (49022)

24576 (24446)

16384 (16254)

61440 (61310)

Under development

M38C24M4

RAM size (bytes)

RAM size

(bytes)

2048

640

2048

Package 64P6N-A

64P6Q-A 64P6N-A 64P6Q-A 64P6N-A 64P6Q-A 64P6N-A 64P6Q-A

1024

Remarks

Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version Flash memory version Flash memory version

1536

2048

As of May 2000

6

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

MITSUBISHI MICROCOMPUTERS

38C2 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

FUNCTIONAL DESCRIPTION Central Processing Unit (CPU)

The 38C2 group uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 Family instructions are as follows:

The FST and SLW instructions cannot be used. The STP, WIT, MUL, and DIV instructions can be used.

[Accumulator (A)]

The accumulator is an 8-bit register. Data operations such as data transfer, etc., are executed mainly through the accumulator.

[Index Register X (X)]

The index register X is an 8-bit register. In the index addressing modes, the value of the OPERAND is added to the contents of register X and specifies the real address.

[Index Register Y (Y)]

The index register Y is an 8-bit register. In partial instruction, the value of the OPERAND is added to the contents of register Y and specifies the real address.

[Stack Pointer (S)]

The stack pointer is an 8-bit register used during subroutine calls and interrupts. This register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack page selection bit is “0” , the high-order 8 bits becomes “0016”. If the stack page selection bit is “1”, the high-order 8 bits becomes “0116”. The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure 6. Store registers other than those described in Figure 6 with program when the user needs them during interrupts or subroutine calls.

[Program Counter (PC)]

The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed.

b7

b0

A Accumulator

b7

b0

X Index register X

b7

b0

Y Index register Y

b7 b0

S Stack pointer

b7b15 b0

H

PC

L

Program counterPC

b7 b0

N V T B D I Z C Processor status register (PS)

Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag Index X mode flag Overflow flag Negative flag

Fig. 5 740 Family CPU register structure

7

PRELIMINARY

e

Notice: This is not a final specification.

Some parametric limits are subject to change.

O n - g o i n g R o u t i n

MITSUBISHI MICROCOMPUTERS

38C2 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

P u s h r e t u r n a d d r e s s o n s t a c k

P O P re t u r n a d d r e s s f r o m s t a c k

I n t e r r u p t r e q u e s t

M ( S )( P CH)

S ) – ( S )

M ( S )( P CL)

S ) – ( S )

S u b r o u t i n e

E x e c u t e R T S

S ) + ( S )

( P CL)M ( S )

S ) + ( S )

( P CH)M ( S )

( N o t e )

(

1

(

M ( S )( P CH)

E x e c u t e J S R

1

S ) – ( S )

(

M ( S )( P CL)

S ) –

( S )

(

M ( S )( P S )

S ) –

( S )

(

I n t e r r u p t

S e r v i c e R o u t i n e

E x e c u t e R T I

S ) + ( S )

(

( P S )M ( S )

S ) + ( S )

(

( P CL)M ( S )

S ) + ( S )

(

1

P u s h r e t u r n a d d r e s s o n s t a c k

1

P u s h c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r o n s t a c k

1

I F l a g i s s e t f r o m “ 0 ” t o “ 1 ” F e t c h t h e j u m p v e c t o r

1

P O P c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r f r o m s t a c k

1

P O P r e t u r n a d d r e s s

1

f r o m s t a c k

N o t e: C o n d i t i o n f o r a c c e p t a n c e o f a n i n t e r r u p t I n t e r r u p t e n a b l e f l a g i s “ 1 ”

Fig. 6 Register push and pop at interrupt generation and subroutine call

Table 4 Push and pop instructions of accumulator or processor status register

Push instruction to stack Accumulator Processor status register

I n t e r r u p t d i s a b l e f l a g i s “ 0 ”

PHA PHP

( P CH)M ( S )

Pop instruction from stack

PLA PLP

8

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

MITSUBISHI MICROCOMPUTERS

38C2 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

[Processor Status Register (PS)]

The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag , Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid.

• Bit 0: Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction.

• Bit 1: Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is “0”, and cleared if the result is anything other than “0”.

• Bit 2: Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is “1”.

• Bit 3: Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is “0”; decimal arithmetic is executed when it is “1”. Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can be used for decimal arithmetic.

• Bit 4: Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always “0”. When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to “1”.

• Bit 5: Index X mode flag (T) When the T flag is “0”, arithmetic operations are performed between accumulator and memory. When the T flag is “1”, direct arith- metic operations and direct data transfers are enabled between memory locations.

• Bit 6: Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag.

• Bit 7: Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag.

Table 5 Set and clear instructions of each bit of processor status register

Set instruction Clear instruction

C flag

SEC CLC

Z flag

– –

I flag

SEI CLI

D flag

SED CLD

B flag

– –

T flag

SET CLT

V flag

–

CLV

N flag

– –

9

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

[CPU Mode Register (CPUM)] 003B16

The CPU mode register contains the stack page selection bit and the control bit for the internal system clock. The CPU mode register is allocated at address 003B16.

MITSUBISHI MICROCOMPUTERS

38C2 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

b7 b0

Fig. 7 Structure of CPU mode register

CPU mode register (CPUM (CM) : address 003B

Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : 1 0 : 1 1 :

Stack page selection bit 0 : RAM in the zero page is used as stack area

Not available

16

)

1 : RAM in page 1 is used as stack area Not used (returns “1” when read)

(Do not write “0” to this bit.) Main clock (X

b5 b4 0 0 : X 0 1 : X 1 0 : X 1 1 : X

System clock control bits b7 b6 0 0 : X 0 1 : X 1 0 : X 1 1 : X

IN–XOUT

) d

ivision ratio selection bits

IN

/8 (frequency/8 mode)

IN

/4 (frequency/4 mode)

IN

/2 (frequency/2 mode)

IN

(through mode)

IN

stop, X

CIN

IN

oscillating, X

IN

oscillating, X

IN

oscillating, X

oscillating, system clock = X

CIN CIN CIN

stop, system clock = X oscillating, system clock = X oscillating, system clock = X

CIN IN

10

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

MITSUBISHI MICROCOMPUTERS

38C2 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MEMORY Special Function Register (SFR) Area

The Special Function Register area in the zero page contains control registers such as I/O ports and timers.

RAM

RAM is used for data storage and for stack area of subroutine calls and interrupts.

ROM

The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs.

Interrupt Vector Area

The interrupt vector area contains reset and interrupt vectors.

R A M a r e a

R A M s i z e

( b y t e s )

1 9 2 2 5 6 3 8 4 5 1 2 6 4 0 7 6 8

8 9 6 1 0 2 4 1 5 3 6 2 0 4 8

ROM area

R O M s i z e

( b y t e s )

4 0 9 6 8 1 9 2

1 2 2 8 8 1 6 3 8 4 2 0 4 8 0 2 4 5 7 6 2 8 6 7 2 3 2 7 6 8 3 6 8 6 4 4 0 9 6 0 4 5 0 5 6 4 9 1 5 2 5 3 2 4 8 5 7 3 4 4 6 1 4 4 0

A d d r e s s

X X X X

1 6

0 0 F F

1 6

0 1 3 F

1 6

0 1 B F

1 6

0 2 3 F

1 6

0 2 B F

1 6

0 3 3 F

1 6

0 3 B F

1 6

0 4 3 F

1 6

0 6 3 F

1 6

0 8 3 F

1 6

Address

YYYY

16

F 0 0 0

1 6

E 0 0 0

1 6

D 0 0 0

1 6

C 0 0 0

1 6

B 0 0 0

1 6

A 0 0 0

1 6

9 0 0 0

1 6

8 0 0 0

1 6

7 0 0 0

1 6

6 0 0 0

1 6

5 0 0 0

1 6

4 0 0 0

1 6

3 0 0 0

1 6

2 0 0 0

1 6

1 0 0 0

1 6

Address

ZZZZ

16

F 0 8 0

1 6

E 0 8 0

1 6

D 0 8 0

1 6

C 0 8 0

1 6

B 0 8 0

1 6

A 0 8 0

1 6

9 0 8 0

1 6

8 0 8 0

1 6

7 0 8 0

1 6

6 0 8 0

1 6

5 0 8 0

1 6

4 0 8 0

1 6

3 0 8 0

1 6

2 0 8 0

1 6

1 0 8 0

1 6

RAM

ROM

Zero Page

Access to this area with only 2 bytes is possible in the zero page addressing mode.

Special Page

Access to this area with only 2 bytes is possible in the special page addressing mode.

0 0 0 0

0 0 4 0 0 0 4 C

0100

XXXX

0 8 4 0 0 F E 0

1 0 00

Y Y Y Y

Z Z Z Z

F F 0 0

F F D C

F F F E F F F F

1 6

16

1 6

1 6 1 6

1 6

1 6 1 6

1 6

S F R a r e a

L C D d i s p l a y R A M a r e a

R e s e r v e d a r e a

N o t u s e d S F R a r e a

R e s e r v e d R O M a r e a

( 1 2 8 b y t e s )

Interrupt vector area

R e s e r v e d R O M a r e a

Zero page

S p e c i a l p a g e

Fig. 8 Memory map diagram

11

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

MITSUBISHI MICROCOMPUTERS

38C2 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Port P0 (P0)

0000

16

Port P0 direction register (P0D)

0001

16

Port P1 (P1)

0002

16

Port P1 direction register (P1D)

0003

16

Port P2 (P2)

0004

16

Port P2 direction register (P2D)

0005

16

Port P3 (P3)

0006

16

Port P3 direction register (P3D)

0007

16

Port P4 (P4)

0008

16

Port P4 direction register (P4D)

0009

16

Port P5 (P5)

000A

16

Port P5 direction register (P5D)

000B

16

Port P6 (P6)

000C

16

Port P6 direction register (P6D)

000D

16

000E

16

000F

16

0010

16

0011

16

0012

16

0013

16

0014

16

0015

16

0016

16

0017

16

Clock output control register (CKOUT)

0018

16

A-D control register (ADCON)

0019

16

A-D conversion register (low-order) (ADL)

001A

16

A-D conversion register (high-order) (ADH)

001B

16

Transmit/receive buffer register 1 (TB1/RB1)

001C

16

Serial I/O1 status register (SIO1STS)

001D

16

Transmit/receive buffer register 2 (TB2/RB2)

001E

16

Serial I/O2 status register (SIO2STS)

001F

16

0020

16

Timer 1 (T1) Timer 2 (T2)

0021

16

Timer 3 (T3)

0022

16

Timer 4 (T4)

0023

16

0024

16

PWM01 register (PWM01)

0025

16

Timer 12 mode register (T12M)

0026

16

Timer 34 mode register (T34M)

0027

16

Compare register (low-order) (COMPL)

0028

16

0029

16

Compare register (high-order) (COMPH)

002A

16

Timer X (low-order) (TXL)

002B

16

Timer X (high-order) (TXH)

002C

16

Timer X (extension) (TXEX)

002D

16

Timer Y (low-order) (TYL)

002E

16

Timer Y (high-order) (TYH)

002F

16

Timer X mode register (TXM)

0030

16

Timer Y mode register (TYM)

0031

16

0032

16

0033

16

0034

16

0035

16

0036

16

Watchdog timer control register (WDTCON)

0037

16

LCD power control register (VLCON)

0038

16

LCD mode register (LM)

0039

16

Interrupt edge selection register (INTEDGE)

003A

16

003B

16

CPU mode register (CPUM) Interrupt request register 1 (IREQ1)

003C

16

Interrupt request register 2 (IREQ2)

003D

16

003E

16

Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2)

003F

16

Serial I/O1 control register (SIO1CON)

0FE0

16

UART1 control register (UART1CON)

0FE1

16

Baudrate generator 1 (BRG1)

0FE2

16

Serial I/O2 control register (SIO2CON)

0FE3

16

UART2 control register (UART2CON)

0FE4

16

Baudrate generator 2 (BRG2)

0FE5

16

0FE6

16

0FE7

16

0FE8

16

0FE9

16

0FEA

16

0FEB

16

0FEC

16

0FED

16

0FEE

16

0FEF

16

Fig. 9 Memory map of special function register (SFR)

12

0FF0

16

Oscillation output control register (OSCOUT)

0FF1

16

PULL register (PULL)

0FF2

16

Key input control register (KIC)

0FF3

16

Timer 1234 mode register (T1234M)

0FF4

16

Timer X control register (TXCON)

Timer 12 frequency division selection register (PRE12)

0FF5

16

Timer 34 frequency division selection register (PRE34)

0FF6

16

Timer XY frequency division selection register (PREXY)

0FF7

16

0FF8

16

Segment output disable register 0 (SEG0)

0FF9

16

Segment output disable register 1 (SEG1)

0FFA

16

Segment output disable register 2 (SEG2)

0FFB

16

Timer Y mode register 2 (TYM2)

0FFC

16

0FFD

16

0FFE

16

Flash memory control register (FMCR)

0FFF

16

Reserved area

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

MITSUBISHI MICROCOMPUTERS

38C2 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

I/O PORTS Direction Registers

The I/O ports P0–P6 have direction registers which determine the input/output direction of each individual pin. Each bit in a direction register corresponds to one pin, each pin can be set to be input port or output port. When “0” is written to the bit of the direction register , the corresponding pin becomes an input pin. As for ports P0–P2, when “1” is written to the bit of the direction register and the segment output disable register, the corresponding pin becomes an output pin. As for ports P3–P6, when “1” is written to the bit of the direction register, the corresponding pin becomes an output pin. If data is read from a pin set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating.

Pull-up Control

Each individual bit of ports P0–P2 can be pulled up with a program by setting direction registers and segment output disable registers 0 to 2 (addresses 0FF816 to 0FFA16). The pin is pulled up by setting “0” to the direction register and “1” to the segment output disable register. By setting the PULL register (address 0FF116), ports P3–P6 can control pull-up with a program. However, the contents of PULL register do not affect ports programmed as the output ports.

b7 b0

PULL register (PULL : address 0FF1

P30–P33 pull-up P3

4

–P37 pull-up

0

–P43 pull-up

P4 P4

4

–P47 pull-up

P5

0

–P53 pull-up

P5

4

–P57 pull-up

0

–P62 pull-up

P6 Not used (return “0” when read)

Segment output disable register 0 (SEG0 : address 0FF8

P00 pull-up P0

1

pull-up

P0

2

pull-up

3

pull-up

P0 P0

4

pull-up

5

pull-up

P0 P0

6

pull-up

7

pull-up

P0

Segment output disable register 1 (SEG1 : address 0FF9

P10 pull-up P1

1

pull-up

P1

2

pull-up

P1

3

pull-up

4

pull-up

P1 P1

5

pull-up

P1

6

pull-up

P1

7

pull-up

16

)

16

)

16

)

0: No pull-up 1: Pull-up

S e g m e n t o u t p u t

d i s a b l e r e g i s t e r

D i r e c t i o n r e g i s t e r

“ 0 ”

“ 1 ”

“ 0 ”“

I n p u t p o r t

N o p u l l - u p

S e g m e n t

o u t p u t

I n p u t p o r t P u l l - u p

P o r t o u t p u t

Fig. 10 Structure of ports P0 to P2

b7 b0

1

”

I n i t i a l s t a t e

Note: The PULL register and segment output disable register

affect only ports programmed as the input ports.

Segment output disable register 2 (SEG2 : address 0FFA

P2

0

pull-up

P2

1

pull-up

P2

2

pull-up

P2

3

pull-up

4

pull-up

P2 P2

5

pull-up

P2

6

pull-up

P2

7

pull-up

16

)

0: No pull-up 1: Pull-up

Fig. 11 Structure of PULL register and segment output disable register

13

MITSUBISHI MICROCOMPUTERS

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

Table 6 List of I/O port function

Pin P00/SEG0 – P03/SEG3

P04/SEG4 – P07/SEG7 P10/SEG8 – P17/SEG15

P20/SEG16 – P25/SEG21 P26/SEG22/VL1 P27/SEG23/VL2 P30/SRDY2 P31/SCLK2 P32/TxD2 P33/RxD2 P34/INT2

P35/TXOUT P36/T2OUT/φ

P37/CNTR0

P40/OOUT0/AN0 P41/OOUT1/AN1

P42/AN2– P45/AN5 P46/RTP0/AN6 P47/RTP1/AN7

P50/INT0 P51/INT1

P52/T3OUT/PWM0 P53/T4OUT/PWM1

P54/RxD1 P55/TxD1 P56/SCLK1 P57/SRDY1 P60/CNTR1

P61/XCIN P62/XCOUT COM0–COM3

Notes 1: For details of how to use double/triple function ports as function I/O ports, refer to the applicable sections.

2: Make sure that the input level at each pin is either 0 V or V

When an input level is at an intermediate potential, a current will flow from V

Name

Port P0

Port P1

Port P2

Port P3

Port P4

Port P5

Port P6

Common

Input/Output Input/Output, individual bits

Input/Output, individual bits

Output

I/O format CMOS compatible input level CMOS 3-state output

CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output

CMOS compatible input level CMOS 3-state output

LCD common output

CC during execution of the STP instruction.

LCD segment output

Serial I/O2 function I/O

External interrupt input

Timer X output Timer 2 output

Timer X function input

A-D conversion input

External interrupt input

Timer 3 output Timer 4 output PWM output Serial I/O1 function I/O

Timer Y function input

Sub-clock oscillation circuit

CC to VSS through the input-stage gate.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Non-port function

Key input (key-on wakeup) interrupt input

LCD power input

Oscillation external output

Real time port function output

Key input (key-on wakeup) interrupt input

38C2 Group

Related SFRs Segment output disable register 1

Segment output disable register 2

Segment output disable register 3

PULL register Serial I/O2 control register Serial I/O2 status register UART2 control register PULL register Interrupt edge selection register PULL register Timer X mode register Timer 12 mode register PULL register Timer X mode register PULL register A-D control register

PULL register A-D control register Timer Y mode register PULL register Interrupt edge selection register PULL register Timer 12 mode register

PULL register Serial I/O1 control register Serial I/O1 status register UART1 control register PULL register Timer Y mode register PULL register CPU mode register LCD mode register

Ref. No.

(1)

(2)

(3) (4) (5) (6) (7)

(8) (9)

(7)

(11)

(10)

(11)

(7)

(9)

(12) (13) (14) (15)

(7)

(16) (17) (18)

14

PRELIMINARY

t t

Notice: This is not a final specification.

Some parametric limits are subject to change.

( 1 ) P o r t s P 00– P 0

S e g m e n t o u t p u t d i s a b l e b i t

3

V

MITSUBISHI MICROCOMPUTERS

38C2 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

( 2 ) P o r t s P 04– P 07, P 1 , P 2

V

L 2

/ V

L 2

/ V

L 3

S e g m e n t o u t p u t d i s a b l e b i t

L 3

S e g m e n t d a t a

S e g m e n t o u t p u t d i s a b l e b i t

D i r e c t i o n r e g i s t e r

D a t a b u s

K e y - o n w a k e u p i n t e r r u p t i n p u t

(3) Port P3

Serial I/O mode selection bit

0

Serial I/O enable bit

RDY

output enable b it

S

D i r e c t i o n r e g i s t e r

P o r t l a t c h

V

L 1

/ V

S S

K e y i n p u t c o n t r o l

P u l l - u p c o n t r o l

S e g m e n t d a t a

Segment output disable bit

D i r e c t i o n r e g i s t e r

D a t a b u s

( 4 ) P o r t P 3

Serial I/O synchronous

1

clock selection bit

Serial I/O enable bit

Serial I/O mode selection bi

Serial I/O enable bi

Direction register

P o r t l a t c h

V

L 1

/ V

S S

L C D p o w e r i n p u t ( V

o n l y f o r P 26, P 2

L 1

, V

L 2

)

7

P u l l - u p c o n t r o l

Data bus

Serial I/O ready output

(5) Port P3

Data bus

P o r t l a t c h

2

P 3

2

/ T x D2 P - c h a n n e l

S e r i a l I / O e n a b l e b i t

o u t p u t d i s a b l e b i t

T r a n s m i t e n a b l e b i t

D i r e c t i o n r e g i s t e r

P o r t l a t c h

Serial I/O output

Fig. 12 Port block diagram (1)

P u l l - u p c o n t r o l

Data bus

(6) Port P3

Data bus

Port latch

S e r i a l I / O c l o c k o u t p u t

3

S e r i a l I / O e n a b l e b i t

R e c e i v e e n a b l e b i t

Direction register

P o r t l a t c h

S e r i a l I / O c l o c k i n p u t

P u l l - u p c o n t r o l

S e r i a l I / O i n p u t

15

PRELIMINARY

t t

Notice: This is not a final specification.

Some parametric limits are subject to change.

MITSUBISHI MICROCOMPUTERS

38C2 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

( 7 ) P o r t s P 34, P 37, P 50, P 51, P 6

Direction register

Data bus

C N T R0, C N T R1 i n t e r r u p t i n p u t

( 9 ) P o r t s P 36, P 52, P 5

D a t a b u s

T i m e r o u t p u t / S y s t e m c l o c k φ o u t p u t

( 1 1 ) P o r t s P 40, P 41, P 46, P 4

Port latch

0

– I N T2 i n t e r r u p t i n p u t

I N T

3

D i r e c t i o n r e g i s t e r

P o r t l a t c h

P o r t / T i m e r o u t p u t s e l e c t i o n

T i m e r o u t p u t / P W M o u t p u t

7

Direction register

0

P u l l - u p c o n t r o l

Pull-up control

P u l l - u p c o n t r o l

(8) Port P3

Data bus

5

D i r e c t i o n r e g i s t e r

P u l s e o u t p u t m o d e

T i m e r X o u t p u t

(10) Ports P42–P4

D a t a b u s

(12) Port P5

4

Serial I/O enable bi

Receive enable bi

Direction register

Pull-up control

Port latch

5

Pull-up control

D i r e c t i o n r e g i s t e r

P o r t l a t c h

A-D conversion input

A n a l o g i n p u t p i n s e l e c t i o n b i t

Pull-up control

Data bus

O s c i l l a t i o n o u t p u t c o n t r o l b i t /

( 1 3 ) P o r t P 5

D a t a b u s

K e y - o n w a k e u p i n t e r r u p t i n p u t

P o r t l a t c h

R e a l t i m e c o n t r o l b i t

O s c i l l a t i o n o u t p u t /

D a t a f o r r e a l t i m e p o r t

5

/ T x D1 P - c h a n n e l

P 5

S e r i a l I / O e n a b l e b i t

o u t p u t d i s a b l e b i t

T r a n s m i t e n a b l e b i t

Direction register

Port latch

S e r i a l I / O o u t p u t

Fig. 13 Port block diagram (2)

A - D c o n v e r s i o n i n p u t

Analog input pin selection bit

Pull-up control

K e y i n p u t c o n t r o l

D a t a b u s

Key-on wakeup interrupt input

(14) Port P5

S e r i a l I / O s y n c h r o n o u s c l o c k

S e r i a l I / O e n a b l e b i t

S e r i a l I / O m o d e s e l e c t i o n b i t

Data bus

6

s e l e c t i o n b i t

S e r i a l I / O e n a b l e b i t

Direction register

Port latch

Serial I/O clock output

K e y - o n w a k e u p i n t e r r u p t i n p u t

Port latch

Serial I/O input

K e y i n p u t c o n t r o l

Pull-up control

Serial I/O clock input

K e y i n p u t c o n t r o l

16

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

MITSUBISHI MICROCOMPUTERS

38C2 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

( 1 5 ) P o r t P 5

S e r i a l I / O m o d e s e l e c t i o n b i t

Data bus

K e y - o n w a k e u p i n t e r r u p t i n p u t

(17) Port P6

D a t a b u s

7

S e r i a l I / O e n a b l e b i t

R D Y

o u t p u t e n a b l e b i t

S

S e r i a l I / O r e a d y o u t p u t

2

X c o s c i l l a t i o n e n a b l e d

D i r e c t i o n r e g i s t e r

P o r t l a t c h

X c o s c i l l a t i o n e n a b l e d + P u l l - u p c o n t r o l

P o r t l a t c h

P u l l - u p c o n t r o l

Key input control

( 1 6 ) P o r t P 6

Data bus Port latch

( 1 7 ) C O M0– C O M

1

X c o s c i l l a t i o n e n a b l e d Direction register

3

V

L3

V

L2

V

L1

Xc oscillation enabled + Pull-up control

Sub-clock generation circuit input

Gate input signal of each gate depends on the duty ratio and bias values.

Fig. 14 Port block diagram (3)

Port P6

Oscillator

1

Xc oscillation enabled

V

SS

17

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

MITSUBISHI MICROCOMPUTERS

38C2 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

INTERRUPTS

Interrupts occur by nineteen sources: six external, twelve internal, and one software.

Interrupt Control

Each interrupt except the BRK instruction interrupt have both an interrupt request bit and an interrupt enable bit, and is controlled by the interrupt disable flag. An interrupt occurs if the corresponding interrupt request and enable bits are “1” and the interrupt disable flag is “0”. Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The BRK instruction interrupt and reset cannot be disabled with any flag or bit. The I flag disables all interrupts except the BRK instruction interrupt and reset. If several interrupts requests occurs at the same time the interrupt with highest priority is accepted first.

Table 7 Interrupt vector addresses and priority

Interrupt Source

Reset (Note 2) INT0

INT1

INT2

Key input (key-on wakeup)

Serial I/O1 receive Serial I/O1 transmit

Serial I/O2 receive Serial I/O2 transmit

Timer X Timer 1 Timer 2 Timer 3 Timer 4 CNTR0

Timer Y CNTR1

A-D conversion

BRK instruction

Notes 1: Vector addresses contain interrupt jump destination addresses.

2: Reset function in the same way as an interrupt with the highest priority.

Priority

Vector Addresses (Note 1)

High

1

FFFD16

2

FFFB16

3

FFF916

4

FFF716

5

FFF516

6

FFF316

7

FFF116

8

FFEF16

9

FFED16 10 11 12 13 14

15

16

17

FFEB16

FFE916 FFE716 FFE516 FFE316

FFE116

FFDF16

FFDD16

Low FFFC16 FFFA16

FFF816

FFF616

FFF416 FFF216

FFF016 FFEE16

FFEC16

FFEA16 FFE816 FFE616 FFE416 FFE216

FFE016

FFDE16

FFDC16

At reset At detection of either rising or falling

edge of INT0 input At detection of either rising or falling

edge of INT1 input At detection of either rising or falling

edge of INT2 input At falling of ports P00–P03, P54–P57

input logical level AND At completion of serial I/O1 data receive At completion of serial I/O1 transmit

shift or transmit buffer is empty At completion of serial I/O2 data receive At completion of serial I/O2 transmit

shift or transmit buffer is empty At timer X underflow At timer 1 underflow At timer 2 underflow At timer 3 underflow At timer 4 underflow At detection of either rising or falling

edge of CNTR0 input At timer Y underflow At detection of either rising or falling

edge of CNTR1 input At completion of A-D conversion

At BRK instruction execution

Interrupt Operation

By acceptance of an interrupt, the following operations are automatically performed:

1.The processing being executed is stopped.

2.The contents of the program counter and processor status register are automatically pushed onto the stack.

3.The interrupt disable flag is set and the corresponding interrupt request bit is cleared.

4.The interrupt jump destination address is read from the vector table into the program counter.

■ Notes on Interrupts

When the active edge of an external interrupt (INT0 – INT2, CNTR0 or CNTR1) is set or an interrupt source where several interrupt source is assigned to the same vector address is switched, the corresponding interrupt request bit may also be set. Therefore, take following sequence:

(1) Disable the interrupt. (2) Set the interrupt edge selection register (Timer X control reg-

ister for CNTR0, Timer Y mode register for CNTR1). (3) Clear the set interrupt request bit to “0.” (4) Enable the interrupt.

Interrupt Request

Generating Conditions

Non-maskable External interrupt (active edge selectable)

External interrupt (active edge selectable)

Valid when INT2 interrupt is selected External interrupt (active edge selectable)

Valid when key input interrupt is selected External interrupt (falling valid)

Valid only when serial I/O1 is selected Valid only when serial I/O1 is selected

Valid only when serial I/O2 is selected Valid only when serial I/O2 is selected

Valid only when timer 1 interrupt is selected Valid only when timer 2 interrupt is selected

External interrupt (active edge selectable)

Valid when A-D conversion interrupt is selected

Non-maskable software interrupt

Remarks

18

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

Interrupt request bit

Interrupt enable bit

Interrupt disable flag (I)

MITSUBISHI MICROCOMPUTERS

38C2 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Fig. 15 Interrupt control

b7 b0

BRK instruction

Interrupt edge selection register

16

(INTEDGE : address 003A

)

INT0 interrupt edge selection bit

1

interrupt edge selection bit

INT INT

2

interrupt edge selection bit

2

/Key input interrupt switch bit

INT Timer Y/CNTR

1

interrupt switch bit Not used (return “0” when read) (Do not write to “1”)

Interrupt request register 1

16

(IREQ1 : address 003C

)

INT0 interrupt request bit

1

interrupt request bit

INT INT

2

interrupt request bit Key input interrupt request bit Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit Serial I/O2 receive interrupt request bit Serial I/O2 transmit interrupt request bit Timer X interrupt request bit

Reset

0 : Falling edge active 1 : Rising edge active

0 : INT2 interrupt 1 : Key input interrupt

0 : Timer Y interrupt 1 : CNTR

1

interrupt

b7 b0

Interrupt request

Interrupt request register 2 (IREQ2 : address 003D

Timer 1 interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit Timer 4 interrupt request bit CNTR Timer Y interrupt request bit CNTR AD conversion interrupt request bit Not used (returns “0” when read)

0 : No interrupt request issued 1 : Interrupt request issued

16

)

0

interrupt request bit

1

interrupt request bit

b7 b0

Interrupt control register 1

(ICON1 : address 003E

INT0 interrupt enable bit

1

interrupt enable bit

INT INT

2

interrupt enable bit Key input interrupt enable bit Serial I/O1 receive interrupt enable bit Serial I/O1 transmit interrupt enable bit Serial I/O2 receive interrupt enable bit Serial I/O2 transmit interrupt enable bit Timer X interrupt enable bit

Fig. 16 Structure of interrupt-related registers

b7 b0

16

)

Interrupt control register 2

(ICON2 : address 003F

16

)

Timer 1 interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit Timer 4 interrupt enable bit CNTR

0

interrupt enable bit Timer Y interrupt enable bit CNTR

1

interrupt enable bit AD conversion interrupt enable bit Not used (returns “0” when read) (Do not write to “1”.)

0 : Interrupts disabled 1 : Interrupts enabled

19