MITSUBISHI 3819 User Manual

MITSUBISHI MICROCOMPUTERS

3819 Group

SINGLE-CHIP 8-BIT MICROCOMPUTER

DESCRIPTION

The 3819 group is a 8-bit microcomputer based on the 740 family
core technology.
The 3819 group has a flourescent display automatic display circuit
and an 16-channel 8-bit A-D converter as additional functions.
The various microcomputers in the 3819 group include variations
of internal memory size and packaging. For details, refer to the
section on part numbering.
For details on availability of microcomputers in the 3819 group, re­fer to the section on group expansion.

FEATURES

●Basic machine-language instructions ...................................... 71

● The minimum instruction execution time ......................... 0.48 µs

(at 8.4 MHz oscillation frequency)

● Memory size .................................................................................

ROM.............................................4K to 60 K bytes

RAM ........................................... 192 to 2048 bytes

● Programmable input/output ports ............................................ 54

● High-breakdown-voltage output ports ...................................... 52

● Interrupts ................................................. 20 sources, 16 vectors

●Timers.............................................................................8-bit ✕ 6

●Serial I/O (Serial I/O1 has an automatic transfer function)

...................................................... 8-bit ✕ 3(clock-synchronized)

● PWM output circuit ...............8-bit ✕ 1(also functions as timer 6)

● A-D converter ............................................... 8-bit ✕ 16 channels

● D-A converter ................................................. 8-bit ✕ 1 channels

● Zero cross detection input............................................ 1 channel

● Fluorescent display function

Segments ........................................................................16 to 42

Digits.................................................................................. 6 to 16

●2 Clock generating circuit

Clock (XIN-XOUT) ................................. Internal feedback resistor

Sub-clock (XCIN-XCOUT) .........Without internal feedback resistor

(connect to external ceramic resonator or quartz-crystal oscil­lator)

●Power source voltage

In high-speed mode .................................................. 4.0 to 5.5 V

(at 8.4 MHz oscillation frequency and high-speed selected)

In middle-speed mode............................................... 2.8 to 5.5 V

(at 8.4 MHz oscillation frequency)

In low-speed mode .................................................... 2.8 to 5.5 V

(at 32 kHz oscillation frequency)

●Power dissipation

In high-speed mode ..........................................................35 mW

(at 8.4 MHz oscillation frequency)

In low-speed mode ............................................................ 6 0 µ W

(at 3 V power source voltage and 32 kHz oscillation frequency )

●Operating temperature range ....................................–10 to 85°C

APPLICATION

Musical Instruments, household appliance, etc.

PIN CONFIGURATION (TOP VIEW)

19

18

17

16

/SEG

/SEG

/SEG

/SEG

3

2

1

0

P9

P9

P9

P9

77

78

79

80

AV

81

15

82

14

83

13

84

12

85

11

86

10

87

9

88

8

89

7

90

6

91

V

CC

92

5

93

4

94

3

95

2

96

1

97

0

98

V

EE

99

SS

100

V

REF

1

7

/AN

7

P7

2

6

/AN

6

P7

3

5

/AN

5

P7

4

4

/AN

4

P7

P87/SEG
P86/SEG
P85/SEG
P84/SEG
P83/SEG
P82/SEG

P81/SEG

P80/SEG
PA7/SEG
PA6/SEG

PA5/SEG
PA4/SEG
PA3/SEG
PA2/SEG
PA1/SEG
PA0/SEG

4

2

5

1

0

3

/DIG

/DIG

/DIG

/DIG

/DIG

20

/SEG

4

P9

76

21

/SEG

5

P9

75

22

/SEG

6

P9

74

23

/SEG

7

P9

73

24

/SEG

0

P3

72

25

/SEG

1

P3

71

26

/SEG

2

P3

70

27

/SEG

3

P3

69

28

/SEG

4

P3

68

29

/SEG

5

P3

67

30

/SEG

6

P3

66

31

/SEG

7

P3

65

32

/SEG

0

P0

64

33

/SEG

1

P0

63

34

/SEG

2

P0

62

/DIG

35

/SEG

3

P0

61

36

/SEG

4

P0

60

37

/SEG

5

P0

59

58

M38197MA-XXXFP

9

8

7

6

5

3

/AN

3

P7

2

/AN

2

P7

1

/AN

1

P7

0

/AN

0

P7

3

PB

10

/DA

2

PB

11

15

/AN

RDY3

/S

7

P5

12

14

/AN

CLK3

/S

6

P5

13

13

/AN

OUT3

/S

5

P5

14

12

/AN

IN3

/S

4

P5

15

11

/AN

RDY2

/S

3

P5

16

10

/AN

CLK2

/S

2

P5

17

9

/AN

OUT2

/S

1

P5

18

8

/AN

IN2

/S

0

P5

20

19

CLK12

/CS/S

RDY1

/S

7

CLK11

/S

6

P6

21

OUT1

/S

5

P6

23

22

IN1

/S

4

P6

P6

Package type : 100P6S-A

100-pin plastic-molded QFP

7

6

/DIG

/DIG

38

39

/SEG

/SEG

6

7

P0

P0

57

24

1

0

/CNTR

/CNTR

3

2

P6

P6

9

8

/DIG

/DIG

41

40

/SEG

/SEG

1

0

P1

P1

55

56

26

25

0

P6

/PWM

1

P6

10

/DIG

2

P1

54

27

OUT

/T3

7

P4

11

/DIG

3

P1

53

28

OUT

/T1

6

P4

12

/DIG

4

P1

52

29

/ZCR

1

/INT

5

P4

13

/DIG

5

P1

51

30

4

/INT

4

P4

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31

P16/DIG
P17/DIG
P20/DIG
P21/DIG
P22/DIG
P23/DIG
P2

4

P2

5

P2

6

P2

7

V

SS

X

OUT

X

IN

PB0/X
PB1/X
RESET
P40/INT
P4

1

P42/INT
P43/INT

COUT
CIN

14
15
16
17
18
19

0

2
3

MITSUBISHI MICROCOMPUTERS

Interrupt interval

determination

circuit

ROM

CPU

P7 (8)

I/O port P7

12345678

P8 (8)

I/O port P8

81 828384 85 8687 88

A-D

converter (8)

P9 (8)

Output port P9

7374 7576 77 7879 80

PA (8)

I/O port PA

8990 92 93 949596 97

PB (4)

I/O port PB

9103637

P6 (8)

I/O port P6

1920 21 22 2324 25 2699

100

AV

SS

VREF

P5 (8)

I/O port P5

11 12 13 14 1516 17 18

P4 (8)

I/O port P4(6)

Input port P4(2)

27 28 29 30 3132 33 34

P3 (8)

Output port P3

65 66 67 68 6970 7172

S I/O3(8)

S I/O2(8)S I/O1(8)

16

P2 (8)

Output port P2(4)

I/O port P2(4)

48 47 46 4544 43 42 41

P1 (8)

Output port P1

56 55 5453 52 515049

P0 (8)

Output port P0

64 63 62 6160 59 58 57

D-A

converter (8)

PS

PCL

S

Y

X

A

PCH

RAM

Data

bus

Timer 1 (8)

Timer 2 (8)

Timer 3 (8)

Timer 4 (8)

Timer 5 (8)

Timer 6 (8)

T1

OUT

SI/O

automatic

transfer

controller

FLD

automatic

display

controller

SI/O

automatic

transfer RAM

32 bytes

FLD

automatic

display RAM

96 bytes

Clock generating

circuit

X

COUT

Sub-clock

output

XCIN

Sub-clock

input

Clock

output

X

OUT

Clock

input

X

IN

92

VEE

40

(0 V)

V

SS

91

(5 V)

V

CC

35

Reset input

RESET

39

38

XCOUT

XCIN

Zero cross

detection circuit

INT

0

INT

1

/ZCR

INT

2

T3OUT

PWM

CNTR

0

CNTR1

Local data

bus

INT

3

, INT

4

3819 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

FUNCTIONAL BLOCK DIAGRAM (Package : 100P6S-A)

2

PIN DESCRIPTION

MITSUBISHI MICROCOMPUTERS

3819 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Pin Name Function

VCC, VSS
VEE

VREF

AV SS
RESET

XIN

XOUT

P00/SEG32/
DIG0–P07/
SEG39/DIG7

P10/SEG40/
DIG8–P17/
DIG15

P20/DIG16–
P23/DIG19

P24–P27

P30/SEG24–
P37/SEG31

P40/INT0,
P45/INT1/
ZCR

P42/INT2–
P44/INT4

P41
P46/T1OUT,

P47/T3OUT

Power source
Pull-down

Power source
Analog reference

voltage
Analog power source

Reset input

Clock input

Clock output

Output port P0

Output port P1

Output port P2

I/O port P2

Output port P3

Input port P4

I/O port P4

•Apply voltage of 4.0 to 5.5 V to VCC, and 0 V to VSS.

•Applies voltage supplied to pull-down resistors of ports P0, P1, P20–P23, P3, and P9.

•Reference voltage input pin for A-D converter and D-A converter

•GND input pin for A-D converter and D-A converter

•Connect AVSS to VSS.

•Reset input pin for active “L”

•Input and output pins for the main clock generating circuit

•Feedback resistor is built in between XIN pin and XOUT pin.

•Connect a ceramic resonator or a quartz-crystal oscillator between the XIN pin and XOUT pin to
set oscillation frequency.

•If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin
open.

•This clock is used as the oscillating source of system clock.

•8-bit output port

•This port builds in pull-down resistor between
port P0 and the VEE pin.

•At reset this port is set to VEE level.

•The high-breakdown-voltage P-channel
open-drain

•8-bit output port with the same function as
port P0

•4-bit output port with the same function as
port P0

•4-bit I/O port

•I/O direction register allows each pin to be individually programmed as either input or output.

•At reset this port is set to input mode.

•TTL input level

•CMOS 3-state output

•8-bit output port with the same function as
port P0

•2-bit input port

•CMOS compatible input level

•6-bit CMOS I/O port with the same function
as ports P24–P27

•CMOS compatible input level

•CMOS 3-state output

Function except a port function

FLD automatic display pins

FLD automatic display pins

FLD automatic display pins

FLD automatic display pins

External interrupt input pins
A zero cross detection circuit input pin (P45)

Timer output pins

3

PIN DESCRIPTION (Continued)

MITSUBISHI MICROCOMPUTERS

3819 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Pin Name Function

P50/SIN2/AN8,
P51/SOUT2/AN9,
P52/SCLK2/AN10,
P53/SRDY2/AN11

P54/SIN3/AN12,
P55/SOUT3/AN13,
P56/SCLK3/AN14,
P57/SRDY3/AN15

P60
P61/PWM
P62/CNTR0,

P63/CNTR1
P64/SIN1,

P65/SOUT1,
P66/SCLK11,
P67/SRDY1/CS/
SCLK12

P70/AN0–
P77/AN7

P80/SEG8–
P87/SEG15

P90/SEG16–
P97/SEG23

PA0/SEG0–
PA7/SEG7

I/O port P5

I/O port P6

I/O port P7

I/O port P8

Output port P9

I/O port PA

•8-bit CMOS I/O port with the same function
as ports P24–P27

•CMOS compatible input level

•CMOS 3-state output

•8-bit CMOS I/O port with the same function
as ports P24–P47

•CMOS compatible input level

•CMOS 3-state output

•8-bit CMOS I/O port with the same function
as ports P24–P27

•CMOS compatible input level

•CMOS 3-state output

•8-bit I/O port with the same function as ports

P24–P27

•CMOS compatible input level

•The high-breakdown-voltage P-channel

open-drain

•8-bit output port with the same function as

port P0

•8-bit I/O port with the same function as ports

P24–P27

•CMOS compatible input level

•The high-breakdown voltage P-channel open-

drain

Function except a port function

Serial I/O2 function pins
A-D conversion input pins

Serial I/O3 function pins
A-D conversion input pins

PWM output pin (Timer output pin)
Timer input pins

Serial I/O1 function pins

A-D conversion input pins

FLD automatic display pins

PB0/XCOUT,
PB1/XCIN

PB2/DA
PB3

I/O port PB

•4-bit CMOS I/O port with the same function
as ports P24–P27

•CMOS compatible input level

•CMOS 3-state output

I/O pins for sub-clock generating circuit (con­nect a ceramic resonator or a quarts-crystal
oscillator)

D-A conversion output pin

4

PART NUMBERING

MITSUBISHI MICROCOMPUTERS

3819 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Product M3819 FPM

A XXX7

Package type
FP : 100P6S-A package
FS : 100D0 package

ROM number
Omitted in some types.

ROM/PROM size

: 4096 bytes

1

: 8192 bytes

2

: 12288 bytes

3

: 16384 bytes

4

: 20480 bytes

5

: 24576 bytes

6

: 28672 bytes

7

: 32768 bytes

8

: 36864 bytes

9

: 40960 bytes

A

: 45056 bytes

B

: 49152 bytes

C

: 53248 bytes

D

: 57344 bytes

E

: 61440 bytes

F

The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used.
Memory type

M

: Mask ROM version

E

: EPROM or One Time PROM version

RAM size
0 : 192 bytes
1 : 256 bytes
2 : 384 bytes
3 : 512 bytes
4 : 640 bytes
5 : 768 bytes
6 : 896 bytes
7 : 1024 bytes
8 : 1536 bytes
9 : 2048 bytes

5

MITSUBISHI MICROCOMPUTERS

3819 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

GROUP EXPANSION

Mitsubishi plans to expand the 3819 group as follows:
(1) Support for mask ROM, One Time PROM, and EPROM ver-

sions

ROM/PROM capacity .................................. 40 K to 60 K bytes

RAM capacity.............................................. 1024 to 2048 bytes

Memory Expansion Plan

60K
56K
52K
48K
44K
40K
36K
32K
28K
24K
20K
16K
12K

8K
4K

ROM size (bytes)

Mass product

(2) Packages

100P6S-A........................... 0.65 mm-pitch plastic molded QFP

100D0........................... Ceramic LCC(built-in EPROM version)

Under development

M38199MF/EF

Mass product

M38198MC/EC

M38197MA

256 512 768 1,024

RAM size (bytes)

Products under development : the development schedule and specifications may be revised without notice.

1,536 2,048

Currently supported products are listed below. As of May 1996

M38197MA-XXXFP
M38197MA-XXXKP
M38198MC-XXXKP
M38199MF-XXXKP
M38198MC-XXXFP
M38198EC-XXXFP
M38198ECFP
M38198ECFS
M38199MF-XXXFP
M38199EF-XXXFP
M38199EFFP
M38199EFFS

(P) ROM size (bytes)

ROM size for User in ( )

40960

(40830)

49152

(49022)

61440

(61310)

RAM size (bytes) RemarksPackageProduct

Mask ROM version
Mask ROM version
Mask ROM version

1024

100P6S-A

100P6P-E

Mask ROM version
Mask ROM version

1536

100P6S-A

100D0

One Time PROM version
One Time PROM version (blank)
EPROM version
Mask ROM version

2048

100P6S-A

100D0

One Time PROM version
One Time PROM version (blank)
EPROM version

6

MITSUBISHI MICROCOMPUTERS

3819 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)

The 3819 group uses the standard 740 family instruction set. Re­fer to the table of 740 family addressing modes and machine
instructions or the 740 Family Software Manual for details on the
instruction set.
Machine-resident 740 family instructions are as follows:
The FST, SLW instruction cannot be used.
The MUL, DIV, WIT and STP instruction can be used.

b7

b0

CPU mode register
(CPUM (CM) : address 003B

CPU Mode Register

The CPU mode register is allocated at address 003B16. The CPU
mode register contains the stack page selection bit and the inter­nal system clock selection bit.

16

)

Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1 :
1 0 : Not available
1 1 :

Stack page selection bit
0 : RAM in the zero page is used as stack area
1 : RAM in page 1 is used as stack area

X

COUT

drivability selection bit
0 : Low drive
1 : High drive

Port X

C

switch bit
0 : I/O port function
1 : X

CIN-XCOUT

oscillating function

Main clock (X
0 : Oscillating
1 : Stopped

Main clock division ratio selection bit
0 : f(X
1 : f(X

Internal system clock selection bit
0 : X
1 : X

IN-XOUT

) stop bit

IN

)/2 (high-speed mode)

IN

)/8 (middle-speed mode)

IN-XOUT

selected (middle/high-speed mode)

CIN-XCOUT

selected (low-speed mode)

Fig. BA-1 Structure of CPU mode register

7

MITSUBISHI MICROCOMPUTERS

3819 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Memory
Special function register (SFR) area

The special function register (SFR) area in the zero page contains
control registers such as I/O ports and timers.

RAM

RAM is used for data storage and for stack area of subroutine
calls and interrupts.

ROM

The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the reset is user area for storing programs.

Interrupt vector area

The interrupt vector area contains reset and interrupt vectors.

RAM area

RAM capacity

(bytes)

192
256
384
512
640
768

896
1024
1536
2048

ROM area

ROM capacity

(bytes)

4096

8192
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440

Address XXXX

00FF

16

013F

16

01BF

16

023F

16

02BF

16

033F

16

03BF

16

043F

16

063F

16

083F

16

Address YYYY

F000

16

E000

16

D000

16

C000

16

B000

16

A000

16

9000

16

8000

16

7000

16

6000

16

5000

16

4000

16

3000

16

2000

16

1000

16

16

16

Address ZZZZ

F080

16

E080

16

D080

16

C080

16

B080

16

A080

16

9080

16

8080

16

7080

16

6080

16

5080

16

4080

16

3080

16

2080

16

1080

16

16

Zero page

The 256 bytes from addresses 000016 to 00FF16 are called the
zero page area. The internal RAM and the special function regis­ters (SFR) are allocated to this area.
The zero page addressing mode can be used to specify memory
and register addresses in the zero page area. Access to this area
with only 2 bytes is possible in the zero page addressing mode.

Special page

The 256 bytes from addresses FF0016 to FFFF16 are called the
special page area. The special page addressing mode can be
used to specify memory addresses in the special page area. Ac­cess to this area with only 2 bytes is possible in the special page
addressing mode.

16

0000

RAM

RO
M

0040

010016

XXXX

044016

0F00

0F1F16

0F80

0FDF16

YYYY

ZZZZ

FF00

FFDC

FFFE
FFFF

SFR area

16

16

Reserved area

Not used

16

RAM area for serial I/O automatic transfer

Not used

16

RAM area for FLD automatic display

Not used

16

Reserved ROM area

(common ROM area,128 bytes)

16

16

16

Interrupt vector area

16

16

Reserved ROM area

Zero
page

Special
page

Fig. CA-1 Memory map

8

0000
0001

0002
0003

0004
0005

0006
0007

0008
0009

000A
000B

000C
000D

000E
000F

0010
0011

0012
0013

0014
0015

0016
0017

0018
0019

001A
001B

001C
001D

001E
001F

16

Port P0 (P0)

16
16

Port P1 (P1)

16
16

Port P2 (P2)

16

Port P2 direction register (P2D)

16

Port P3 (P3)

16
16

Port P4 (P4)

16

Port P4 direction register (P4D)
Port P5 (P5)

16

Port P5 direction register (P5D)

16

Port P6 (P6)

16

Port P6 direction register (P6D)

16

Port P7 (P7)

16

Port P7 direction register (P7D)

16

Port P8 (P8)

16

Port P8 direction register (P8D)

16
16

Port P9 (P9)

16
16

Port PA (PA)

16

Port PA direction register (PAD)
Port PB (PB)

16
16

Port PB direction register (PBD)

Serial I/O automatic transfer data pointer (SIODP)

16
16

Serial I/O1 control register (SIO1CON)

16

Serial I/O automatic transfer control register (SIOAC)

16

Serial I/O1 register (SIO1)

Serial I/O automatic transfer interval register (SIOAI)

16
16

Serial I/O2 control register (SIO2CON)

16

Serial I/O3 control register (SIO3CON)

16

Serial I/O2 register (SIO2)

0020
0021

0022
0023

0024
0025

0026
0027

0028
0029

002A
002B

002C
002D

002E
002F

0030
0031

0032
0033

0034
0035

0036
0037

0038
0039

003A
003B

003C
003D

003E
003F

MITSUBISHI MICROCOMPUTERS

3819 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

16

Timer 1 (T1)
Timer 2 (T2)

16

Timer 3 (T3)

16

Timer 4 (T4)

16

Timer 5 (T5)

16

Timer 6 (T6)

16

Serial I/O3 register (SIO3)

16

Timer 6 PWM register (T6PWM)

16

Timer 12 mode register (T12M)

16

Timer 34 mode register (T34M)

16

16

Timer 56 mode register (T56M)

16

D-A conversion register (DA)

16

AD-DA control register (ADCON)

16

A-D conversion register (AD)

16
16

Interrupt interval determination register (IID)

16

Interrupt interval determination control register (IIDCON)

16
16

Port P0 segment/digit switch register (P0SDR)
Port P2 digit/port switch register (P2DPR)

16

Port P8 segment/port switch register (P8SPR)

16
16

Port PA segment/port switch register (PASPR)

16

FLDC mode register 1 (FLDM1)
FLDC mode register 2 (FLDM2)

16
16

FLD data pointer (FLDDP)
Zero cross detection control register (ZCRCON)

16

Interrupt edge selection register (INTEDGE)

16

CPU mode register (CPUM)

16

Interrupt request register 1 (IREQ1)

16

Interrupt request register 2 (IREQ2)

16

Interrupt control register 1 (ICON1)

16
16

Interrupt control register 2 (ICON2)

Fig. CA-2 Memory map of special function register (SFR)

9

MITSUBISHI MICROCOMPUTERS

3819 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

I/O PORTS
Direction Registers

The 3819 group has 54 programmable I/O pins arranged in 8 I/O
ports (ports P24–P27, P41–P44, P46, P47, P5–P8, PA, and PB).
The I/O ports have direction registers which determine the input/
output direction of each individual pin. Each bit in a direction reg­ister corresponds to one pin, each pin can be set to be input or
output.
When “0” is written to the bit corresponding to a pin, that pin be­comes an input pin. When “1” is written to that bit, that pin
becomes an output pin.
If data is read from a pin which is set for output, the value of the
port latch is read, not the value of the pin itself. A pin which is set
for input the value of the pin itself is read because the pin is in
floating state. If a pin set for input is written to, only the port latch
is written to and the pin remains floating.

Pin Name Input/Output I/O Format Non-Port Function Related SFRS

P00/SEG32/
DIG0–
P07/SEG39/
DIG7

P10/SEG40/
DIG8–
P17/DIG15

P20/DIG16–
P23/DIG19

P24–P27

P30/SEG24–
P37/SEG31

P40/INT0
P45/INT1/
ZCR

P42/INT2–
P44/INT4
P41

P46/T1OUT,
P47/T3OUT

Port P0

Port P1

Port P2

Port P3

Port P4

Output

Output

Output

Input/output,
individual bits

Output

Input

Input/output,
individual bits

High-breakdown­voltage P-channel
open-drain output
with pull-down
resistor
High-breakdown­voltage P-channel
open-drain output
with pull-down
resistor
High-breakdown­voltage P-channel
open-drain output
with pull-down
resistor
TTL level input
CMOS 3-state output
High-breakdown­voltage P-channel
open-drain output
with pull-down
resistor

CMOS compatible
input level

CMOS compatible
input level

CMOS 3-state output

High-Breakdown-Voltage Output Ports

The 3819 group microprocessors have 7 ports with high-break­down-voltage pins (ports P0, P1, P20–P23, P3, P8, P9, PA). The
high-breakdown-voltage ports have P-channel open-drain output
with VCC –40 V of breakdown voltage.
Each pin in ports P0, P1, P20–P23, P3, and P9 has an internal
pull-down resistor connected to VEE. Ports P8 and PA have no in­ternal pull-down resistors, so that connect an external resistor to
each port. At reset, the P-channel output transistor of each port
latch is turned off, so it becomes VEE level (“L”) by the pull-down
resistor.
Writing “1” (weak drivability) to bit 7 of the FLDC mode register 1
(address 003616) shows the rising transition of the output transis­tors for reducing transient noise. At reset, bit 7 of the FLDC mode
register 1 is set to “0” (strong drivability).

FLDC mode register 1

FLD automatic dis­play function

FLD automatic dis­play function

FLD automatic dis­play function

FLD automatic dis­play function

External interrupt
input

Zero cross detec­tion circuit input
(P45)

Timer output

FLDC mode register 2
Port P0
segment/digit
switch register

FLDC mode register 1
FLDC mode register 2

FLDC mode register 1
FLDC mode register 2
Port P2 digit/port

switch register

FLDC mode register 1
FLDC mode register 2

Interrupt edge
selection register

Zero cross detection
control register

Timer 12 mode register
Timer 34 mode register

Diagram

No.

(1)

(1)
(2)

(3)

(4)

(5)

(6)

(7)
(4)
(8)

10

MITSUBISHI MICROCOMPUTERS

3819 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Pin Name Input/Output I/O Format Non-Port Function Related SFRS

P50/SIN2/
AN8
P51/SOUT2/
AN9,
P52/SCLK2/
AN10
P53/SRDY2/
AN11
P54/SIN3/
AN12
P55/SOUT3/
AN13,
P56/SCLK3/
AN14
P57/SRDY3/
AN15
P60

P61/PWM
P62/CNTR0,

P63/CNTR1
P64/SIN1
P65/SOUT1,
P66/SCLK11
P67/SRDY1/
CS/SCLK12

P70/AN0–
P77/AN7

P80/SEG8–
P87/SEG15

P90/SEG16–
P97/SEG23

PA0/SEG0–
PA7/SEG7

PB0/XCOUT,
PB1/XCIN

PB2/DA
PB3

Note : Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate poten-

tial, a current will flow from V

Port P5

Port P6

Port P7

Port P8

Port P9

Port PA

Port PB

Input/output,
individual bits

Output

Input/output,
individual bits

Input/output,
individual bits

CC to VSS through the input-stage gate.

CMOS compatible
input level

CMOS 3-state output

CMOS compatible
input level

CMOS 3-state output

CMOS compatible
input level

CMOS 3-state output
CMOS compatible

input level
High-breakdown-

voltage P-channel
open-drain output
with pull-down
resistor

High-breakdown­voltage P-channel
open-drain output
with pull-down
resistor

CMOS compatible
input level

High-breakdown­voltage P-channel
open-drain output

CMOS compatible
input level

CMOS 3-state output

Serial I/O2 func­tion I/O

A-D conversion in­put

Serial I/O3 func­tion I/O

A-D conversion in­put

PWM (timer) out­put

Timer input

Serial I/O1 func­tion I/O

A-D conversion in­put

FLD automatic
display function

I/O for sub-clock
generating circuit

D-A conversion
output

Serial I/O2 control
register

AD/DA control regis­ter

Serial I/O3 control
register

AD/DA control regis­ter

Timer 56 mode regis­ter

Interrupt edge selec­tion register

Serial I/O1 control
register

Serial I/O automatic
transfer control regis­ter

AD/DA control regis­ter

FLDC mode register
Segment/port switch
register

FLDC mode register

FLDC mode register
Segment/port switch
register

CPU mode register
AD/DA control regis-

ter

Diagram

No.

(9)

(10)

(11)

(9)

(10)

(11)

(4)
(8)

(7)
(9)

(10)

(11)

(12)

(13)

(5)

(13)

(14)
(15)

(16)

(4)

11

MITSUBISHI MICROCOMPUTERS

3819 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

(1) Ports P0, P10, P1

(2) Ports P12–P1

(3) Ports P20–P2

7

3

1

Blanking signal
for key-scan

Data bus

Local data bus

Data bus

Shift signal from previous stage

S/D switch register

Dimmer signal

Port latch

Shift signal to next stage

Shift signal from previous stage

Dimmer signal

(Note)

Port latch

Shift signal to next stage

Shift signal from previous stage

D/P switch register

(Note)

✽

V

EE

✽

V

EE

(4) Ports P24–P27, P41, P60, PB

✽ : High-breakdown-voltage P-channel transistor
Note: The dimmer signal sets the Toff timing.

Fig. UA-2 Port block diagram (1)

Data bus

Blanking signal
for key-scan

Data bus

Shift signal to next stage

3

Direction
register

Port latch

Dimmer signal

Port latch

(Note)

✽

V

EE

12

(5) Ports P3, P9

Local data bus

Data bus

MITSUBISHI MICROCOMPUTERS

3819 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Dimmer signal

(Note)

Port latch

✽

V

EE

(6) Ports P40, P4

(7) Ports P4

5

2

–P44, P62, P6

(8) Ports P46, P47, P6

Data bus

0

, INT1 interrupt input

INT

Zero cross
detection
circuit
input

5

)

(only P4

3

Direction
register

Data bus

1

Port latch

2

–INT4 interrupt input

INT

0

,CNTR1 input

CNTR

Timer 1 output selection bit
Timer 3 output selection bit
Timer 6 output selection bit

Direction
register

✽ : High-breakdown-voltage P-channel transistor
Note: The dimmer signal sets the Toff timing.

Fig. UA-3 Port block diagram (2)

Data bus

Port latch

Timer 1 output
Timer 3 output
Timer 6 output

13

MITSUBISHI MICROCOMPUTERS

3819 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

(9) Ports P50, P54, P6

(10) Ports P51, P52, P55, P56, P65, P6

(11) Ports P53, P57, P6

4

Data bus

Data bus

7

Direction
register

Port latch

6

P-channel output disable signal

Output OFF control signal

Serial I/O port selection bit

Direction
register

Port latch

OUT

or S

CLK

S

S

RDY

output enable bit

Direction
register

Serial I/O input

A-D conversion input

Analog input pin selection bit

Serial clock input

(only P52, P56, P66)

A-D conversion input

Analog input pin selection bit

(12) Port P7

Fig. UA-4 Port block diagram (3)

Data bus

Port latchData bus

Serial ready output

CLK

or S

A-D conversion input

Direction
register

Port latch

A-D conversion input

CS input

(only P67)

Analog input pin selection bit

Analog input pin selection bit

14

MITSUBISHI MICROCOMPUTERS

3819 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

(13) Ports P8, PA

(14) Port PB0

Local
data bus

Data bus

Data bus

S/P switch register

Directionregister

Port latch

C switch

Port X
bit

Direction
register

Port latch

Dimmer signal

(Note)

Port PB

rea

d

Oscillation circuit

1

Port XC switch bit

✽

(15) Port PB1

(16) Port PB2

✽ : High-breakdown-voltage P-channel transistor
Note: The dimmer signal sets the Toff timing.

Data bus

Data bus

C switch

Port X
bit

Direction
register

Port latch

Sub-clock generating circuit input

Direction
register

Port latch

D-A conversion output

D-A output enable bit

Fig. UA-5 Port block diagram (4)

15

MITSUBISHI MICROCOMPUTERS

3819 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

INTERRUPTS

Interrupts occur by 20 sources: 5 external, 14 internal, and 1 soft­ware.

Interrupt Control

Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in­terrupt set by the BRK instruction. An interrupt occurs if the
corresponding interrupt request and enable bits are “1” and the in­terrupt disable flag is “0”.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction cannot be disabled with any flag or bit.
The I (interrupt disable) flag disables all interrupts except the BRK
instruction interrupt.

Table 1. Interrupt vector addresses and priority

Interrupt Source Priority

Reset (Note 2) Non-maskable
INT0

INT1/ZCR

INT2
Remote control/

counter overflow
Serial I/O1
Serial I/O

automatic transfer
Serial I/O2

Serial I/O3
Timer 1

Timer 2
Timer 3
Timer 4
Timer 5
Timer 6

INT3

INT4

A-D conversion

FLD blanking

FLD digit

BRK instruction

Notes 1 : Vector addresses contain interrupt jump destination addresses.

2 : Reset function in the same way as an interrupt with the highest priority.

1

2

3

4

5

6

7
8

9
10
11
12
13

14

15

16

17

Vector Addresses (Note 1)

High

FFFD16
FFFB16

FFF916

FFF716

FFF516

FFF316

FFF116
FFEF16

FFED16
FFEB16
FFE916
FFE716
FFE516

FFE316

FFE116

FFDF16

FFDD16

Low

FFFC16

FFFA16

FFF816

FFF616

FFF416

FFF216

FFF016

FFEE16
FFEC16
FFEA16

FFE816
FFE616
FFE416

FFE216

FFE016

FFDE16

FFDC16

Interrupt Operation

When an interrupt is received, the contents of the program counter
and processor status register are automatically stored into the
stack. The interrupt disable flag is set to inhibit other interrupts
from interfering. The corresponding interrupt request bit is cleared
and the interrupt jump destination address is read from the vector
table into the program counter.

Notes on Use

When the active edge of an external interrupt (INT0 to INT4) is
changed or when switching interrupt sources in the same vector
address, the corresponding interrupt request bit may also be set.
Therefore, please take following sequence;
(1) Disable the external interrupt which is selected.
(2) Change the active edge.
(3) Clear the interrupt request bit which is selected to “0”.
(4) Enable the external interrupt which is selected.

Interrupt Request

Generating Conditions

At reset
At detection of either rising or

falling edge of INT0 input
At detection of either rising or

falling edge of INT1/ZCR input
At detection of either rising or

falling edge of INT2 input

At 8-bit counter overflow

At completion of data transfer
At completion of the last data

transfer
At completion of data transfer

At completion of data transfer
At timer 1 underflow

At timer 2 underflow
At timer 3 underflow
At timer 4 underflow
At timer 5 underflow
At timer 6 underflow
At detection of either rising or

falling edge of INT3 input

At detection of either rising or
falling edge of INT4 input

At completion of A-D conver­sion

At falling edge of the last digit
immediately before blanking
period starts

At rising edge of each digit

At BRK instruction execution

External interrupt (active edge
selectable)

External interrupt (active edge
selectable)

External interrupt (active edge
selectable)

Valid when interrupt interval
determination is operating

Valid when serial I/O ordinary
mode is selected

Valid when serial I/O automatic
transfer mode is selected

Valid when serial I/O2 is se­lected

Valid when serial I/O3 is se­lected

STP release timer underflow

External interrupt (active edge
selectable)

Valid when INT4 interrupt is
selected
External interrupt (active
edge selectable)

Valid when A-D conversion in­terrupt is selected

Valid when FLD blanking in­terrupt is selected

Valid when FLD digit interrupt
is selected

Non-maskable software inter­rupt

Remarks

16

Interrupt request bit

Interrupt enable bit

Interrupt disable flag (I)

MITSUBISHI MICROCOMPUTERS

3819 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Fig. DD-1 Interrupt control

b7

b7

b0

Interrupt edge selection register
(INTEDGE : address 003A

0

interrupt edge selection bit

INT
INT

1

/ZCR interrupt edge selection bit

2

interrupt edge selection bit

INT
INT

3

interrupt edge selection bit

4

interrupt edge selection bit

INT

INT

4

/AD conversion interrupt switch bit

CNTR

0

pin active edge switch bit

CNTR

1

pin active edge switch bit

b0

Interrupt request register 1
(IREQ1 : address 003C

0

interrupt request bit

INT
INT

1

/ZCR interrupt request bit

2

interrupt request bit

INT
Remote control/counter overflow
interrupt request bit
Serial I/O1 interrupt request bit
Serial I/O automatic transfer
interrupt request bit
Serial I/O2 interrupt request bit
Serial I/O3 interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit

16

16

)

BRK instruction

)

Reset

0 : Falling edge active
1 : Rising edge active

4

interrupt

0 : INT
1 : A-D conversion interrupt

0 : Rising edge count
1 : Falling edge count

b7

0 : No interrupt request issued
1 : Interrupt request issued

Interrupt request

b0

Interrupt request register 2
(IREQ2 : address 003D

Timer 3 interrupt request bit
Timer 4 interrupt request bit
Timer 5 interrupt request bit
Timer 6 interrupt request bit
INT

3

interrupt request bit

INT

4

interrupt request bit
AD conversion interrupt request bit
FLD blanking interrupt request bit
FLD digit interrupt request bit
Not used (returns “0” when read)

16

)

b7

b0

Interrupt control register 1
(ICON1 : address 003E

0

interrupt enable bit

INT

1

/ZCR interrupt enable bit

INT
INT

2

interrupt enable bit
Remote control/counter overflow
interrupt enable bit
Serial I/O1 interrupt enable bit
Serial I/O automatic transfer
interrupt enable bit
Serial I/O2 interrupt enable bit
Serial I/O3 interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit

Fig. DD-2 Structure of interrupt-related registers

b7

16

)

b0

Interrupt control register 2
(ICON2 : address 003F

16

)

Timer 3 interrupt enable bit
Timer 4 interrupt enable bit
Timer 5 interrupt enable bit
Timer 6 interrupt enable bit
INT

3

interrupt enable bit

4

interrupt enable bit

INT
AD conversion interrupt enable bit
FLD blanking interrupt enable bit
FLD digit interrupt enable bit
Not used (returns “0” when read)

(do not write “1” to this bit)

0 : Interrupts disabled
1 : Interrupts enabled

17

TIMERS

The 3819 group has 6 built-in timers: timer 1, timer 2, timer 3,
timer 4, timer 5, and timer 6.
Each timer has the 8-bit timer latch. The timers count down.
Once a timer reaches 0016, at the next count pulse the contents of
each timer latch is loaded into the corresponding timer, and sets
the corresponding interrupt request bit to “1”.
The count can be stopped by setting the stop bit of each timer to
“1”. The internal clock φ can be set to either the high-speed mode
or low-speed mode with the CPU mode register. At the same time,
timer internal count source is switched to either f(XIN) or f(XCIN).

Timer 1 and Timer 2

The count sources of timer 1 and timer 2 can be selected by set­ting the timer 12 mode register. A rectangular waveform of timer 1
underflow signal divided by 2 is output from the P46/T1OUT pin.
The waveform polarity changes each time timer 1 overflows. The
active edge of the external clock CNTR0 can be switched with the
bit 6 of the interrupt edge selection register.
At reset or when executing the STP instruction, all bits of the timer
12 mode register are cleared to “0”, timer 1 is set to “FF16”, and
timer 2 is set to “0116”.

MITSUBISHI MICROCOMPUTERS

3819 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Timer 3 and Timer 4

The count sources of timer 3 and timer 4 can be selected by set­ting the timer 34 mode register. A rectangular waveform of timer 3
underflow signal divided by 2 is output from the P47/T3OUT pin.
The waveform polarity changes each time timer 3 overflows.
The active edge of the external clock CNTR1 can be switched with
the bit 7 of the interrupt edge selection register.

Timer 5 and Timer 6

The count sources of timer 5 and timer 6 can be selected by set­ting the timer 56 mode register.
A rectangular waveform of timer 6 underflow signal divided by 2 is
output from the P61/PWM pin. The waveform polarity changes
each time timer 6 overflows.

Timer 6 PWM Mode

Timer 6 can output a rectangular waveform with duty cycle n/(n +
m) from the P61/PWM pin by setting the timer 56 mode register
(refer to fig. FB-3). The n is the value set in timer 6 latch (address

002516) and m is the value in the timer 6 PWM register (address

002716). If n is “0”, the PWM output is “L”, if m is “0”, the PWM out­put is “H”(n=0 is prior than m=0). In the PWM mode, interrupts
occur at the rising edge of the PWM output.

18