Microchip Technology Inc PIC12C671-04-P, PIC12C671-04-SM, PIC12C672-04I-P, PIC12C672-04I-SM, PIC12C672-10-P Datasheet

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

1997 Microchip Technology Inc.

Preliminary

DS30561A-page 1

Devices included in this Data Sheet:

PIC12C671 and PIC12C672 are 8-bit microcontrollers with 8-bit A/D Converter packaged in 8-lead packages. They are based on the 14-bit PIC16/17 architecture.

High-Performance RISC CPU:

• Only 35 single word instructions to learn

• All instructions are single cycle (1 µ s) except for program branches which are two-cycle

• Operating speed: DC - 10 MHz clock input

DC - 1 µ s instruction cycle

• 14-bit wide instructions

• 8-bit wide data path

• Interrupt capability

• Special function hardware registers

• Eight-level deep hardware stack

• Direct, indirect and relative addressing modes for data and instructions

• Internal 4 MHz oscillator with programmable calibration

• Selectable clockout

• In-circuit serial programming

• 4-channel 8-bit analog-to-digital converter

Peripheral Features:

• 8-bit real time clock/counter (TMR0) with 8-bit programmable prescaler

• Power-On Reset (POR)

• Power-up Timer (PWRT) and Oscillator Start-up Timer (OSC)

• Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation

• Programmable code-protection

• Power saving SLEEP mode

• Interrupt on pin change (GP0, GP1, GP3)

• Internal pull-ups on I/O pins (GP0, GP1, GP3)

Device EPROM RAM

PIC12C671 1024 x 14 128 x 8 PIC12C672 2048 x 14 128 x 8

• Selectable oscillator options:

- INTRC: Precision internal 4 MHz oscillator

- EXTRC: External low-cost RC oscillator

- XT: Standard crystal/resonator

- HS: High speed crystal/resonator

- LP: Power saving, low frequency crystal

• Internal pull-up on MCLR

CMOS Tec hnology:

• Low power, high speed CMOS EPROM technology

• Fully static design

• Wide operating voltage range:

- Commercial: 2.5V to 5.5V

- Industrial: 2.5V to 5.5V

- Extended: 4.5V to 5.5V

• Low power consumption

- < 2 mA @ 5V, 4 MHz

- 15 µ A typical @ 3V, 32 KHz

- < 1 µ A typical standby current

Pin Diagram

PDIP, SOIC

PIC12C671

PIC12C672

GP5/OSC1/CLKIN

GP4/OSC2/AN3/

GP3/MCLR

/VPP

VDD

VSS GP0/AN0 GP1/AN1/V

REF

GP2/T0CKI/ AN2/INT

CLKOUT

8-Pin, 8-Bit CMOS Microcontroller with A/D Converter

PIC12C67X

DS30561A-page 2

Preliminary



1997 Microchip Technology Inc.

Table of Contents

1.0 General Description............................................................................................................................................3

2.0 PIC12C67X Device Varieties .............................................................................................................................5

3.0 Architectural Overview .......................................................................................................................................7

4.0 Memory Organization.......................................................................................................................................11

5.0 I/O Ports...........................................................................................................................................................23

6.0 Timer0 Module .................................................................................................................................................25

7.0 Analog-to-Digital Converter (A/D) Module........................................................................................................31

8.0 Special Features of the CPU............................................................................................................................39

9.0 Instruction Set Summary..................................................................................................................................55

10.0 Development Support.......................................................................................................................................69

11.0 Electrical Characteristics for PIC12C67X ........................................................................................................73

12.0 DC and AC Characteristics - PIC12C67X........................................................................................................89

13.0 Packaging Information......................................................................................................................................93

Appendix A: Compatibility .............................................................................................................................................97

Index............................................................................................................................................................................101

PIC12C67X Product Identification System..................................................................................................................109

To Our Valued Customers

We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional amount of time to ensure that these documents are correct. However, we realize that we may have missed a few things. If you ﬁnd any information that is missing or appears in error, please use the reader response form in the back of this data sheet to inform us. We appreciate your assistance in making this a better document.



1997 Microchip Technology Inc.

Preliminary

DS30561A-page 3

PIC12C67X

1.0 GENERAL DESCRIPTION

The PIC12C67X device is a low-cost, high-performance, CMOS, fully-static, 8-bit microcontroller with integrated analog-to-digital (A/D) converter, in the PIC12CXXX Microcontroller family.

All PIC16/17 microcontrollers employ an advanced RISC architecture. The PIC12C67X microcontrollers have enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with the separate 8-bit wide data. The two stage instruction pipeline allows all instructions to execute in a single cycle, except for program branches which require two cycles. A total of 35 instructions (reduced instruction set) are available . Additionally , a large register set giv es some of the architectural innovations used to achie ve a very high performance.

PIC12C67X microcontrollers typically achieve a 2:1 code compression and a 4:1 speed improvement over other 8-bit microcontrollers in their class.

The PIC12C67X devices ha v e 128 bytes of RAM and 6 I/O

pins. In addition a timer/counter is available. Also a 4-channel high-speed 8-bit A/D is provided. The 8-bit resolution is ideally suited for applications requiring low-cost analog interface, e.g. thermostat control, pressure sensing, etc.

The PIC12C67X device has special features to reduce external components, thus reducing cost, enhancing system reliability and reducing power consumption. The PIC12C67X products are equipped with special features that reduce system cost and power requirements. The Power-On Reset (POR), Power-up Timer (PWRT), and Oscillator Start-up Timer (OST) eliminate the need for external reset circuitry . There are fiv e oscillator conﬁgurations to choose from, including INTRC precision internal oscillator mode and the power-saving LP (Low Po wer) oscillator. Power saving SLEEP mode, Watchdog Timer and code protection features improve system cost, power and reliability.The SLEEP (powerdown) feature provides a po wer sa ving mode. The user can wake up the chip from SLEEP through several external and internal interrupts and resets.

A highly reliable Watchdog Timer with its own on-chip RC oscillator provides protection against software lockup.

A UV erasable windowed package version is ideal for code development while the cost-effective One-TimeProgrammable (OTP) version is suitable for production in any volume. The customer can take full advantage of Microchip’s price leadership in OTP microcontrollers while beneﬁting from the OTP’s ﬂexibility.

The PIC12C67X device ﬁts perfectly in applications ranging from security and remote sensors to appliance control and automotive. The EPROM technology makes customization of application programs (transmitter codes, motor speeds, receiver frequencies, etc.) extremely fast and convenient. The small footprint packages make this microcontroller series perfect for all applications with space limitations. Low cost, low power, high perf ormance, ease of use and I/O ﬂe xibility make the PIC12C67X very versatile even in areas where no microcontroller use has been considered before (e.g. timer functions, communications and coprocessor applications).

1.1 F

amily and Upward Compatibility

The PIC12C67X products are compatible with other members of the PIC16CXXX family.

1.2 De

velopment Support

The PIC12C67X device is supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a low-cost development programmer and a full-featured programmer. A “C” compiler and fuzzy logic support tools are also available.

PIC12C67X

DS30561A-page 4

Preliminary



1997 Microchip Technology Inc.

TABLE 1-1: PIC12CXXX FAMILY OF DEVICES

PIC12C508

PIC12C509 PIC12C671 PIC12C672

Clock

Maximum Frequency of Operation (MHz)

4 4 10 10

Memory

EPROM Program Memory 512 x 12 1024 x 12 1024 x 14 2048 x 14 Data Memory (bytes) 25 41 128 128

Peripherals

Timer Module(s) TMR0 TMR0 TMR0 TMR0 A/D Converter (8-bit) Channels — — 4 4

Features

Wake-up from SLEEP on pin change

Yes Yes Yes Yes

Interrupt Sources — — 4 4 I/O Pins 5 5 5 5 Input Pins 1 1 1 1 Internal Pull-ups Yes Yes Yes Yes Voltage Range (Volts) 2.5-5.5 2.5-5.5 2.5-5.5 2.5-5.5 In-Circuit Serial Programming Yes Yes Yes Yes Number of Instructions 33 33 35 35 Packages 8-pin DIP, JW,

SOIC

8-pin DIP, JW, SOIC

All PIC12CXXX devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC12CXXX devices use serial programming with data pin GP0 and clock pin GP1.



1997 Microchip Technology Inc.

Preliminary

DS30561A-page 5

PIC12C67X

2.0 PIC12C67X DEVICE VARIETIES

A variety of frequency ranges and packaging options are available . Depending on application and production requirements, the proper device option can be selected using the information in the PIC12C67X Product Identiﬁcation System section at the end of this data sheet. When placing orders, please use that page of the data sheet to specify the correct part number.

For the PIC12C67X, there are two device “types” as indicated in the device number:

1. C , as in PIC12 C 671. These devices have

EPROM type memory and operate over the standard voltage range.

2. LC , as in PIC12 LC 671. These devices have

EPROM type memory and operate over an extended voltage range.

2.1 UV Erasab

le Devices

The UV erasable version, offered in windowed package, is optimal for prototype dev elopment and pilot programs.

The UV erasable version can be erased and reprogrammed to any of the conﬁguration modes. Microchip's PICSTART



Plus and PRO MATE



programmers both support the PIC12C67X. Third party programmers also are available; refer to the Microchip Third Party Guide for a list of sources.

2.2 One-Time-Pr

ogrammable (OTP)

Devices

The availability of OTP devices is especially useful for customers who need the ﬂexibility for frequent code updates and small volume applications.

The OTP devices, packaged in plastic packages, permit the user to program them once. In addition to the program memory, the conﬁguration bits must also be programmed.

CAUTION: Calibration values must be read before erasing.

2.3 Q

uick-Turnaround-Production (QTP)

Devices

Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but with all EPROM locations and conﬁguration options already programmed by the factory. Certain code and prototype veriﬁcation procedures apply before production shipments are available. Please contact your local Microchip Technology sales ofﬁce for more details.

2.4 Serializ

ed Quick-Turnaround

Production (SQTP

)

Devices

Microchip offers a unique programming service where a few user-deﬁned locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random, or sequential.

Serial programming allows each device to have a unique number which can serve as an entry-code, password, or ID number.

PIC12C67X

DS30561A-page 6

Preliminary



1997 Microchip Technology Inc.

NOTES:



1997 Microchip Technology Inc.

Preliminary

DS30561A-page 7

PIC12C67X

3.0 ARCHITECTURAL OVERVIEW

The high performance of the PIC12C67X family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC12C67X uses a Harvard architecture, in which program and data are accessed from separate memories using separate buses. This improves bandwidth over traditional von Neumann architecture in which program and data are fetched from the same memory using the same bus. Separating program and data buses also allow instructions to be sized differently than the 8-bit wide data word. Instruction opcodes are 14bits wide making it possible to have all single word instructions. A 14-bit wide program memory access bus fetches a 14-bit instruction in a single cycle. A twostage pipeline overlaps fetch and execution of instructions (Example 3-1). Consequently, all instructions (35) execute in a single cycle (1 µ s @ 4 MHz) except for program branches.

The table below lists program memory (EPROM) and data memory (RAM) for each PIC12C67X device.

Device

Program

Memory

Data Memory

PIC12C671 1K x 14 128 x 8 PIC12C672 2K x 14 128 x 8

The PIC12C67X can directly or indirectly address its register ﬁles or data memory. All special function registers, including the program counter, are mapped in the data memory. The PIC12C67X has an orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of ‘special optimal situations’ make programming with the PIC12C67X simple yet efﬁcient. In addition, the learning curve is reduced signiﬁcantly.

PIC12C67X devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between the data in the working register and any register ﬁle.

The ALU is 8-bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the working register (W register). The other operand is a ﬁle register or an immediate constant. In single operand instructions, the operand is either the W register or a ﬁle register.

The W register is an 8-bit working register used f or ALU operations. It is not an addressable register.

Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a borro

w bit and a digit borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.

PIC12C67X

DS30561A-page 8

Preliminary



1997 Microchip Technology Inc.

FIGURE 3-1: PIC12C67X BLOCK DIAGRAM

Power-up

Timer

Oscillator

Start-up Timer

EPROM

Program Memory

Data Bus

Program

Bus

Instruction reg

Program Counter

RAM

File

Registers

Direct Addr

RAM Addr

(1)

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

W reg

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

MCLR

VDD, VSS

Timer0

GPIO

GP4/OSC2/AN3/CLKOUT

GP3/MCLR/Vpp

GP2/T0CKI/AN2/INT

GP1/AN1/VREF

GP0/AN0

GP5/OSC1/CLKIN

8 Level Stack

(13 bit)

128 bytes

Note 1: Higher order bits are from the STATUS register.

A/D

Watchdog

Timer

Power-on

Reset

Device

PIC12C671 PIC12C672

Program Memory Data Memory (RAM)

1K x 14 2K x 14

128 x 8 128 x 8

4 MHz Clock

Internal



1997 Microchip Technology Inc.

Preliminary

DS30561A-page 9

PIC12C67X

TABLE 3-1: PIC12C67X PINOUT DESCRIPTION

Name

DIP

Pin #

SOIC

Pin #

I/O/P Type

Buffer

Type

Description

GP0/AN0 7 7 I/O TTL/ST Bi-directional I/O port/serial programming data/analog

input 0. Can be software programmed for internal weak pull-up and interrupt on pin change. This b uff er is a Schmitt Trigger input when used in serial programming mode.

GP1/AN1/V

REF

6 6 I/O TTL/ST Bi-directional I/O port/serial programming clock/analog

input 1/voltage reference. Can be software programmed for internal weak pull-up and interrupt on pin change. This buffer is a Schmitt Trigger input when used in serial programming mode.

GP2/T0CKI/AN2/INT 5 5 I/O ST Bi-directional I/O port/analog input 2. Can be conﬁg-

ured as T0CKI or external interrupt.

GP3/MCLR

4 4 I TTL Input port/master clear (reset) input/programming volt-

age input. When conﬁgured as MCLR

, this pin is an

active low reset to the device. Voltage on MCLR

must not exceed V

during normal device operation. Can be software programmed for internal weak pull-up and interrupt on pin change. Weak pull-up always on if conﬁgured as MCLR

GP4/OSC2/AN3/ CLKOUT

3 3 I/O TTL Bi-directional I/O port/oscillator crystal output/analog

input 3. Connections to crystal or resonator in crystal oscillator mode (XT and LP modes only , GPIO in other modes). In EXTRC and INTRC modes, the pin output can be conﬁgured to CLKOUT which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate.

GP5/OSC1/CLKIN 2 2 I/O TTL/ST Bidirectional IO port oscillator crystal input/external

clock source input (GPIO in INTRC mode only, OSC1 in all other oscillator modes). Schmitt trigger in EXTRC mode only.

1 1 P — Positive supply for logic and I/O pins

8 8 P — Ground reference for logic and I/O pins

Legend: I = input, O = output, I/O = input/output, P = power, — = not used, TTL = TTL input, ST = Schmitt Trigger input

PIC12C67X

DS30561A-page 10

Preliminary



1997 Microchip Technology Inc.

FIGURE 3-2: CLOCK/INSTRUCTION CYCLE

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

Q2 Q3 Q4

OSC1

Q1 Q2 Q3

Q4 PC

OSC2/CLKOUT

(EXTRC and

PC PC+1 PC+2

Fetch INST (PC)

Execute INST (PC-1) Fetch INST (PC+1)

Execute INST (PC) Fetch INST (PC+2)

Execute INST (PC+1)

Internal phase clock

INTRC modes)

instructions are single cycle, except for any program branches. These take two cycles since the fetch

truction is “ﬂushed” from the pipeline while the new instruction is being fetched and then executed.

Tcy0 Tcy1 Tcy2 Tcy3 Tcy4 Tcy5

1. MOVLW 55h

Fetch 1 Execute 1

2. MOVWF GPIO

Fetch 2 Execute 2

3. CALL SUB_1

Fetch 3 Execute 3

4. BSF GPIO, BIT3 (Forced NOP)

Fetch 4 Flush

5. Instruction @ address SUB_1

Fetch SUB_1 Execute SUB_1

3.1 Cloc

king Scheme/Instruction Cycle

The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution ﬂow is shown in Figure 3-2.

3.2 Instruction Flo

w/Pipelining

An “Instruction Cycle” consists of four Q cycles (Q1, Q2, Q3 and Q4). The instr uction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g. GOTO ) then two cycles are required to complete the instruction (Example 3-1).

A fetch cycle begins with the program counter (PC) incrementing in Q1.

In the execution cycle, the fetched instruction is latched into the “Instruction Register" (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).



1997 Microchip Technology Inc.

Preliminary

DS30561A-page 11

PIC12C67X

4.0 MEMORY ORGANIZATION

4.1 Pr

ogram Memory Organization

The PIC12C67X has a 13-bit program counter capable of addressing an 8K x 14 program memory space.

For the PIC12C671 the ﬁrst 1K x 14 (0000h-03FFh) is implemented.

For the PIC12C672, the ﬁrst 2K x 14 (0000h-07FFh) is implemented. Accessing a location above the physically implemented address will cause a wraparound. The reset vector is at 0000h and the interrupt vector is at 0004h.

FIGURE 4-1: PIC12C67X PROGRAM

MEMORY MAP AND STACK

PC<12:0>

0000h

0004h 0005h

07FFh

1FFFh

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-chip Program

Memory

CALL, RETURN RETFIE, RETLW

0800h

0400h

03FFh

Peripheral

(PIC12C672 only)

4.2 Data Memor

y Organization

The data memory is partitioned into two Banks which contain the General Purpose Registers and the Special Function Registers. Bit RP0 is the bank select bit.

RP0 (STATUS<5>) = 1 → Bank 1 RP0 (STATUS<5>) = 0 → Bank 0 Each Bank extends up to 7Fh (128 bytes). The lower

locations of each Bank are reserved for the Special Function Registers. Abo ve the Special Function Registers are General Purpose Registers implemented as static RAM. Both Bank 0 and Bank 1 contain special function registers. Some "high use" special function registers from Bank 0 are mirrored in Bank 1 for code reduction and quicker access.

Also note that F0h through FFh on the PIC12C67X is mapped into Bank 0 registers 70h-7Fh.

4.2.1 GENERAL PURPOSE REGISTER FILE The register ﬁle can be accessed either directly , or indi-

rectly through the File Select Register FSR (Section 4.5).

PIC12C67X

DS30561A-page 12 Preliminary  1997 Microchip Technology Inc.

FIGURE 4-2: PIC12C67X REGISTER FILE

MAP

INDF

(1)

TMR0

PCL

STATUS

FSR

GPIO

PCLATH INTCON

PIR1

ADRES

ADCON0

INDF

(1)

OPTION

PCL

STATUS

FSR

TRIS

PCLATH INTCON

PIE1

PCON

ADCON1

00h 01h 02h 03h 04h 05h 06h 07h 08h

09h 0Ah 0Bh 0Ch 0Dh 0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h 1Ah 1Bh 1Ch 1Dh 1Eh

1Fh

80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh

20h

A0h

General Purpose Register

7Fh

FFh

Bank 0 Bank 1

File

Address

BFh C0h

Unimplemented data memory locations, read

as '0'.

Note 1: Not a physical register.

File

Address

OSCCAL

F0h

EFh

Mapped

in Bank 0

70h

4.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by

the CPU and Peripheral Modules for controlling the desired operation of the device. These registers are implemented as static RAM.

The special function registers can be classiﬁed into two sets (core and peripheral). Those registers associated with the “core” functions are described in this section, and those related to the operation of the peripheral features are described in the section of that peripheral feature.

 1997 Microchip Technology Inc. Preliminary DS30561A-page 13

PIC12C67X

TABLE 4-1: PIC12C67X SPECIAL FUNCTION REGISTER SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

Power-on

Reset

Value on

all other

Resets

(3)

Bank 0

00h

(1)

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 02h

(1)

PCL Program Counter's (PC) Least Signiﬁcant Byte 0000 0000 0000 0000 03h

(1)

STATUS IRP

(4)

RP1

(4)

RP0 TO PD Z DC C 0001 1xxx 000q quuu

04h

(1)

FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 05h GPIO — — GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx --uu uuuu 06h — Unimplemented — — 07h — Unimplemented — — 08h — Unimplemented — — 09h — Unimplemented — — 0Ah

(1,2)

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 0Bh

(1)

INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 000x 0000 000u 0Ch PIR1 — ADIF — — — — — — -0-- ---- -0-- ---- 0Dh — Unimplemented — — 0Eh — Unimplemented — — 0Fh — Unimplemented — — 10h — Unimplemented — — 11h — Unimplemented — — 12h — Unimplemented — — 13h — Unimplemented — — 14h — Unimplemented — — 15h — Unimplemented — — 16h — Unimplemented — — 17h — Unimplemented — — 18h — Unimplemented — — 19h — Unimplemented — — 1Ah — Unimplemented — — 1Bh — Unimplemented — — 1Ch — Unimplemented — — 1Dh — Unimplemented — — 1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu 1Fh ADCON0 ADCS1 ADCS0 r CHS1 CHS0 GO/DONE r ADON 0000 0000 0000 0000

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0', r = reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: These registers can be addressed from either bank.

2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose

contents are transferred to the upper byte of the program counter. 3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 4: The IRP and RP1 bits are reserved on the PIC12C67X, always maintain these bits clear.

PIC12C67X

DS30561A-page 14 Preliminary  1997 Microchip Technology Inc.

Bank 1

80h

(1)

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 81h OPTION GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 82h

(1)

PCL Program Counter's (PC) Least Signiﬁcant Byte 0000 0000 0000 0000 83h

(1)

STATUS IRP

(4)

RP1

(4)

RP0 TO PD Z DC C 0001 1xxx 000q quuu

84h

(1)

FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 85h TRIS — — GPIO Data Direction Register --11 1111 --11 1111 86h — Unimplemented — — 87h — Unimplemented — — 88h — Unimplemented — — 89h — Unimplemented — — 8Ah

(1,2)

PCLATH — — — Write Buffer for the upper 5 bits of the PC ---0 0000 ---0 0000 8Bh

(1)

INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 000x 0000 000x 8Ch PIE1 — ADIE — — — — — — -0-- ---- -0-- ---- 8Dh — Unimplemented — — 8Eh PCON — — — — — — POR — ---- --0- ---- --u- 8Fh OSCCAL CAL3 CAL2 CAL1 CAL0 CALFST CALSLW — — 0111 00-- uuuu uu-- 90h — Unimplemented — — 91h — Unimplemented — — 92h — Unimplemented — — 93h — Unimplemented — — 94h — Unimplemented — — 95h — Unimplemented — — 96h — Unimplemented — — 97h — Unimplemented — — 98h — Unimplemented — — 99h — Unimplemented — — 9Ah — Unimplemented — — 9Bh — Unimplemented — — 9Ch — Unimplemented — — 9Dh — Unimplemented — — 9Eh — Unimplemented — — 9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000

TABLE 4-1: PIC12C67X SPECIAL FUNCTION REGISTER SUMMARY (CONT.)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

Power-on

Reset

Value on

all other

Resets

(3)

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0', r = reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: These registers can be addressed from either bank.

2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose

 1997 Microchip Technology Inc. Preliminary DS30561A-page 15

PIC12C67X

4.2.2.1 STATUS REGISTER The STATUS register, shown in Figure 4-3, contains

the arithmetic status of the ALU, the RESET status and the bank select bits for data memory.

The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the T

O and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended.

For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the ST ATUS register as 000u u1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect the Z, C or DC bits from the STA TUS register . For other instructions, not affecting any status bits, see the "Instruction Set Summary."

Note 1: Bits IRP and RP1 (STATUS<7:6>) are not

used by the PIC12C67X and should be maintained clear. Use of these bits as general purpose R/W bits is NOT recommended, since this may affect upward compatibility with future products.

Note 2: The C and DC bits operate as a borro

w and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.

FIGURE 4-3: STATUS REGISTER (ADDRESS 03h, 83h)

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO PD Z DC C R = Readable bit

W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: IRP: Register Bank Select bit (used for indirect addressing)

1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh) The IRP bit is reserved, always maintain this bit clear.

bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)

11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh)

Each bank is 128 bytes. The RP1 bit is reserved, always maintain this bit clear.

bit 4: T

O: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred

bit 3: PD

: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction

bit 2: Z: Zero bit

1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero

bit 1: DC: Digit carry/borro

w bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(for borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result

bit 0: C: Carry/borro

w bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) 1 = A carry-out from the most signiﬁcant bit of the result occurred 0 = No carry-out from the most signiﬁcant bit of the result occurred Note: For borro

w the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF , RLF) instructions, this bit is loaded with either the high or low order bit of the source register.

PIC12C67X

DS30561A-page 16 Preliminary  1997 Microchip Technology Inc.

4.2.2.2 OPTION REGISTER The OPTION register is a readable and writable regis-

ter which contains various control bits to conﬁgure the TMR0/WDT prescaler, the External INT Interrupt, TMR0, and the weak pull-ups on GPIO.

Note: To achieve a 1:1 prescaler assignment for

the TMR0 register, assign the prescaler to the Watchdog Timer by setting bit PSA (OPTION<3>).

FIGURE 4-4: OPTION REGISTER (ADDRESS 81h)

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

GPPU

INTEDG T0CS T0SE PSA PS2 PS1 PS0 R = Readable bit

W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: GPPU: Weak pullup enable

1 = Weak pullups disabled 0 = Weak pullups enabled (GP0, GP1, GP3)

bit 6: INTEDG: Interrupt edge

1 = Interrupt on rising edge of GP2/INT pin 0 = Interrupt on falling edge of GP2/INT pin

bit 5: T0CS: TMR0 Clock Source Select bit

1 = Transition on GP2/T0CKI/AN2 pin 0 = Internal instruction cycle clock (CLKOUT)

bit 4: T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on GP2/T0CKI/AN2 pin 0 = Increment on low-to-high transition on GP2/T0CKI/AN2 pin

bit 3: PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module

bit 2-0: PS2:PS0: Prescaler Rate Select bits

000 001 010 011 100 101 110 111

1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256

1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128

Bit Value TMR0 Rate WDT Rate

 1997 Microchip Technology Inc. Preliminary DS30561A-page 17

PIC12C67X

4.2.2.3 INTCON REGISTER The INTCON Register is a readable and writable regis-

ter which contains various enable and ﬂag bits for the TMR0 register overﬂow, GPIO Port change and External GP2/INT Pin interrupts.

Note: Interrupt ﬂag bits get set when an interrupt

condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>).

FIGURE 4-5: INTCON REGISTER (ADDRESS 0Bh, 8Bh)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE PEIE T0IE INTE GPIE T0IF INTF GPIF R = Readable bit

W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: GIE: Global Interrupt Enable bit

1 = Enables all un-masked interrupts 0 = Disables all interrupts

bit 6: PEIE: Peripheral Interrupt Enable bit

1 = Enables all un-masked peripheral interrupts 0 = Disables all peripheral interrupts

bit 5: T0IE: TMR0 Overﬂow Interrupt Enable bit

1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt

bit 4: INTE: INT External Interrupt Enable bit

1 = Enables the external interrupt on GP2/INT pin 0 = Disables the external interrupt on GP2/INT pin

bit 3: GPIE: GPIO Interrupt on Change Enable bit

1 = Enables the GPIO Interrupt on Change 0 = Disables the GPIO Interrupt on Change

bit 2: T0IF: TMR0 Overﬂow Interrupt Flag bit

1 = TMR0 register has overﬂowed (must be cleared in software) 0 = TMR0 register did not overﬂow

bit 1: INTF: INT External Interrupt Flag bit

1 = The external interrupt on GP2/INT pin occurred (must be cleared in software) 0 = The external interrupt on GP2/INT pin did not occur

bit 0: GPIF: GPIO Interrupt on Change Flag bit

1 = GP0, GP1, or GP3 pins changed state (must be cleared in software) 0 = Neither GP0, GP1, nor GP3 pins have changed state

PIC12C67X

DS30561A-page 18 Preliminary  1997 Microchip Technology Inc.

4.2.2.4 PIE1 REGISTER This register contains the individual enable bits for the

Peripheral interrupts.

Note: Bit PEIE (INTCON<6>) must be set to

enable any peripheral interrupt.

FIGURE 4-6: PIE1 REGISTER (ADDRESS 8Ch)

U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0

— ADIE — — — — — — R = Readable bit

W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: Unimplemented: Read as '0' bit 6: ADIE: A/D Converter Interrupt Enable bit

1 = Enables the A/D interrupt 0 = Disables the A/D interrupt

bit 5-0: Unimplemented: Read as '0'

 1997 Microchip Technology Inc. Preliminary DS30561A-page 19

PIC12C67X

4.2.2.5 PIR1 REGISTER This register contains the individual ﬂag bits for the

Peripheral interrupts.

Note: Interrupt ﬂag bits get set when an interrupt

condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt ﬂag bits are clear prior to enabling an interrupt.

FIGURE 4-7: PIR1 REGISTER (ADDRESS 0Ch)

U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0

— ADIF — — — — — — R = Readable bit

W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: Unimplemented: Read as '0' bit 6: ADIF: A/D Converter Interrupt Flag bit

1 = An A/D conversion completed 0 = The A/D conversion is not complete

bit 5-0: Unimplemented: Read as '0'

PIC12C67X

DS30561A-page 20 Preliminary  1997 Microchip Technology Inc.

4.2.2.6 PCON REGISTER The Power Control (PCON) register contains a ﬂag bit

to allow differentiation between a Power-on Reset (POR), an external MCLR

Reset, and WDT Reset.

FIGURE 4-8: PCON REGISTER (ADDRESS 8Eh)

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0

— — — — — — POR — R = Readable bit

W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7-2: Unimplemented: Read as '0' bit 1: POR

: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0: Unimplemented: Read as '0'

 1997 Microchip Technology Inc. Preliminary DS30561A-page 21

PIC12C67X

4.2.2.7 OSCCAL REGISTER The Oscillator Calibration (OSCCAL) register is used to

calibrate the internal 4 MHz oscillator. It contains four bits for ﬁne calibration and two other bits to either increase or decrease frequency.

FIGURE 4-9: OSCCAL REGISTER (ADDRESS 8Fh)

R/W-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 U-0 U-0 CAL3 CAL2 CAL1 CAL0 CALFST CALSLW — — R = Readable bit

W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7-4: CAL<3:0>: Fine calibration bit 3: CALFST: Calibration Fast

1 = Increase frequency 0 = No change

bit 2: CALSLW: Calibration Slow

1 = Decrease frequency 0 = No change

bit 1-0: Unimplemented: Read as '0'

Note: If CALFST = 1 and CALSLW = 1, CALFST has precedence.

PIC12C67X

DS30561A-page 22 Preliminary  1997 Microchip Technology Inc.

4.3 PCL and PCLATH

The program counter (PC) is 13-bits wide. The lo w byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any reset, the PC is cleared. Figure 4-10 shows the two situations for the loading of the PC. The upper example in the ﬁgure shows how the PC is loaded on a write to PCL (PCLA TH<4:0> → PCH). The lower example in the ﬁgure shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> → PCH).

FIGURE 4-10: LOADING OF PC IN

DIFFERENT SITUATIONS

4.3.1 COMPUTED GOTO A computed GOTO is accomplished by adding an off-

set to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the tab le location crosses a PCL memory boundary (each 256 byte block). Refer to the application note

“Implementing a Table Read"

(AN556).

12 8 7 0

PCLA TH<4:0>

PCLA TH

Instr

uction with

ALU result

GOTO, CALL

Opcode <10:0>

12 11 10 0

PCLATH<4:3>

PCH PCL

8 7

PCLATH

PCH PCL

PCL as Destination

4.3.2 STACK The PIC12C67X family has an 8 level deep x 13-bit

wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLA TH is not affected by a PUSH or POP operation.

The stack operates as a circular buff er . This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the ﬁrst push. The tenth push overwrites the second push (and so on).

4.4 Program Memory Paging

The PIC12C67X ignores both paging bits PCLATH<4:3>, which are used to access program memory when more than one page is available. The use of PCLATH<4:3> as general purpose read/write bits for the PIC12C67X is not recommended since this may affect upward compatibility with future products.

Note 1: There are no status bits to indicate stack

overﬂow or stack underﬂow conditions.

Note 2: There are no instructions/mnemonics

called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW, and RETFIE instructions, or the vectoring to an interrupt address.

 1997 Microchip Technology Inc. Preliminary DS30561A-page 23

PIC12C67X

4.5 Indirect Addressing, INDF and FSR Registers

The INDF register is not a physical register . Addressing the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses the register pointed to by the File Select Register, FSR. Reading the INDF register itself indirectly (FSR = '0') will read 00h. Writing to the INDF register indirectly results in a no-operation (although status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 4-11. However, IRP is not used in the PIC12C67X.

A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 4-1.

EXAMPLE 4-1: INDIRECT ADDRESSING

movlw 0x20 ;initialize pointer movwf FSR ;to RAM NEXT clrf INDF ;clear INDF register incf FSR,F ;inc pointer btfss FSR,4 ;all done? goto NEXT ;no clear next CONTINUE : ;yes continue

FIGURE 4-11: DIRECT/INDIRECT ADDRESSING

For register ﬁle map detail see Figure 4-2. Note 1: The RP1 and IRP bits are reserved, always maintain these bits clear.

Data Memory

Indirect AddressingDirect Addressing

bank select location select

(1)

RP1 RP0 6

from opcode

IRP

(1)

FSR register

bank select

location select

00 01 10 11

00h

7Fh

00h

7Fh

Bank 0 Bank 1 Bank 2 Bank 3

not used

PIC12C67X

DS30561A-page 24 Preliminary  1997 Microchip Technology Inc.

NOTES:

 1997 Microchip Technology Inc. Preliminary DS30561A-page 25

PIC12C67X

5.0 I/O PORT

As with any other register, the I/O register can be written and read under program control. However, read instructions (e.g., MOVF GPIO,W) always read the I/O pins independent of the pin’s input/output modes. On RESET, all I/O por ts are deﬁned as input (inputs are at hi-impedance) since the I/O control registers are all set.

5.1 GPIO

GPIO is an 8-bit I/O register. Only the low order 6 bits are used (GP5:GP0). Bits 7 and 6 are unimplemented and read as '0's. Please note that GP3 is an input only pin. The conﬁguration word can set several I/O’s to alternate functions. When acting as alternate functions the pins will read as ‘0’ during por t read. Pins GP0, GP1, and GP3 can be conﬁgured with weak pull-ups and also with interrupt on change. The interrupt on change and weak pull-up functions are not pin selectable. If pin 4 is conﬁgured as MCLR

, the weak pull-up is always on. Interrupt on change for this pin is not set and GP3 will read as '0'. Interrupt on change is enabled by setting INTCON<3>. Note that external oscillator use overrides the GPIO functions on GP4 and GP5.

5.2 TRIS Register

This register controls the data direction for GPIO. A '1' from a TRIS register bit puts the corresponding output driver in a hi-impedance mode. A '0' puts the contents of the output data latch on the selected pins, enabling the output buffer. The exceptions are GP3 which is input only and its TRIS bit will always read as '1'.

Upon reset, the TRIS register is all '1's, making all pins inputs.

Note: A read of the por ts reads the pins, not the

output data latches. That is, if an output driver on a pin is enabled and driven high, but the external system is holding it low, a read of the port will indicate that the pin is low.

5.3 I/O Interfacing

The equivalent circuit for an I/O port pin is shown in Figure 5-2. All port pins, except GP3 which is input only, may be used for both input and output operations. For input operations these por ts are nonlatching. Any input must be present until read by an input instruction (e.g., MOVF GPIO,W). The outputs are latched and remain unchanged until the output latch is rewritten. To use a port pin as output, the corresponding direction control bit in TRIS must be cleared (= 0). For use as an input, the corresponding TRIS bit must be set. Any I/O pin (except GP3) can be programmed individually as input or output.

FIGURE 5-1: EQUIVALENT CIRCUIT

FOR A SINGLE I/O PIN

Note: On a Power-on Reset, GP0, GP1, GP2,

GP4 are conﬁgured as analog inputs and read as '0'.

Note 1: I/O pins have protection diodes to VDD and VSS.

Data Bus

WR Port

TRIS ‘f’

Data

TRIS

RD Port

VSS

VDD

I/O pin

(1)

W Reg

Latch

Reset

GP3 is input only with no data latch and no output drivers.

TABLE 5-1: SUMMARY OF PORT REGISTERS

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

Power-on

Reset

Value on

all other

Resets

85h TRIS — — GPIO Data Direction Register --11 1111 --11 1111 81h OPTION GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 03h STATUS

IRP

(1)

RP1

(1)

RP0 TO PD Z DC C 0001 1xxx 000q quuu

05h GPIO — — GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx --uu uuuu Legend: Shaded cells not used by Port Registers, read as ‘0’, — = unimplemented, read as '0', x = unknown, u = unchanged,

q = see tables in Section 7.7 for possible values.

Note 1: The IRP and RP1 bits are reserved on the PIC12C67X, always maintain these bits clear.

PIC12C67X

DS30561A-page 26 Preliminary  1997 Microchip Technology Inc.

5.4 I/O Programming Considerations

5.4.1 BI-DIRECTIONAL I/O PORTS Any instruction which writes, operates internally as a

read followed by a write operation. The BCF and BSF instructions, for example, read the register into the CPU, ex ecute the bit operation and write the result back to the register. Caution must be used when these instructions are applied to a port with both inputs and outputs deﬁned. For example, a BSF operation on bit5 of GPIO will cause all eight bits of GPIO to be read into the CPU. Then the BSF operation takes place on bit5 and GPIO is written to the output latches. If another bit of GPIO is used as a bi-directional I/O pin (e.g., bit0) and it is deﬁned as an input at this time, the input signal present on the pin itself would be read into the CPU and rewritten to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the input mode, no problem occurs. However, if bit0 is switched to an output, the content of the data latch may now be unknown.

Reading the port register, reads the values of the port pins. Writing to the port register writes the value to the port latch. When using read-modify-write instructions (ex. BCF, BSF , etc.) on a port, the value of the port pins is read, the desired operation is done to this value, and this value is then written to the port latch.

Example 5-1 shows the effect of two sequential readmodify-write instructions on an I/O port.

EXAMPLE 5-1: READ-MODIFY-WRITE

INSTRUCTIONS ON AN I/O PORT

;Initial GPIO Settings ; GPIO<5:3> Inputs ; GPIO<2:0> Outputs ; ; GPIO latch GPIO pins ; ---------- --------- BCF GPIO, 5 ;--01 -ppp --11 pppp BCF GPIO, 4 ;--10 -ppp --11 pppp MOVLW 007h ; TRIS GPIO ;--10 -ppp --11 pppp ; ;Note that the user may have expected the pin ;values to be --00 pppp. The 2nd BCF caused ;GP5 to be latched as the pin value (High).

A pin actively outputting a Low or High should not be driven from external devices at the same time in order to change the level on this pin (“wired-or”, “wired-and”). The resulting high output currents may damage the chip.

FIGURE 5-2: SUCCESSIVE I/O OPERATION

PC PC + 1 PC + 2

PC + 3

Q1 Q2

Instruction

fetched

GP5:GP0

MOVWF GPIO

NOP

Port pin sampled here

NOP

MOVF GPIO,W

Instruction

executed

MOVWF GPIO

(Write to

GPIO)

NOP

MOVF GPIO,W

This example shows a write to GPIO followed by a read from GPIO.

Data setup time = (0.25 TCY – TPD) where: TCY = instruction cycle.

TPD = propagation delay

Therefore, at higher clock frequencies, a write followed by a read may be problematic.

(Read

GPIO)

Port pin written here

 1997 Microchip Technology Inc. Preliminary DS30561A-page 27

PIC12C67X

6.0 TIMER0 MODULE

The Timer0 module timer/counter has the following f eatures:

• 8-bit timer/counter

• Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select

• Interrupt on overﬂow from FFh to 00h

• Edge select for external clock Figure 6-1 is a simpliﬁed block diagram of the Timer0

module. Timer mode is selected by clearing bit T0CS

(OPTION<5>). In timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles (Figure 6-2 and Figure 6-3). The user can work around this by writing an adjusted value to the TMR0 register.

Counter mode is selected by setting bit T0CS (OPTION<5>). In counter mode, Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit T0SE (OPTION<4>). Clear ing

bit T0SE selects the r ising edge. Restrictions on the external clock input are discussed in detail in Section 6.2.

The prescaler is mutually exclusively shared between the Timer0 module and the Watchdog Timer. The prescaler assignment is controlled in software by control bit PSA (OPTION<3>). Clearing bit PSA will assign the prescaler to the Timer0 module. The prescaler is not readable or writable. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable. Section 6.3 details the operation of the prescaler.

6.1 Timer0 Interrupt

The TMR0 interrupt is generated when the TMR0 register overﬂows from FFh to 00h. This overﬂow sets bit T0IF (INTCON<2>). The interr upt can be masked by clearing bit T0IE (INTCON<5>). Bit T0IF must be cleared in software by the Timer0 module interrupt service routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from SLEEP since the timer is shut off during SLEEP. See Figure 64 for Timer0 interrupt timing.

FIGURE 6-1: TIMER0 BLOCK DIAGRAM

FIGURE 6-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE

Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION<5:0>).

2: The prescaler is shared with Watchdog Timer (refer to Figure 6-6 for detailed block diagram).

GP2/T0CKI/

T0SE

AN2

T0CS

FOSC/4

Programmable

Prescaler

Sync with

Internal

clocks

TMR0

PSout

(2 cycle delay)

PSout

Data bus

PSA

PS2, PS1, PS0

Set interrupt

ﬂag bit T0IF on overﬂow

PC-1

Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC (Program Counter)

Instruction

Fetch

TMR0

PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6

T0+1 T0+2 NT0 NT0 NT0 NT0+1 NT0+2

MOVWF TMR0

MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

Write TMR0 executed

Read TMR0 reads NT0

Read TMR0 reads NT0 + 1

Read TMR0 reads NT0 + 2

Instruction Executed

PIC12C67X

DS30561A-page 28 Preliminary  1997 Microchip Technology Inc.

FIGURE 6-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2

FIGURE 6-4: TIMER0 INTERRUPT TIMING

PC-1

Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC (Program Counter)

Instruction Fetch

TMR0

PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6

T0 NT0+1

MOVWF TMR0

MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

Write TMR0 executed

Read TMR0 reads NT0

Read TMR0 reads NT0 + 1

T0+1

NT0

Instruction Execute

Q2Q1 Q3 Q4Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

OSC1

CLKOUT(3)

Timer0

T0IF bit (INTCON<2>)

FEh

GIE bit (INTCON<7>)

INSTR

UCTION

Instruction fetched

PC +1 PC +1 0004h 0005h

Instruction executed

Inst (PC)

Inst (PC-1)

Inst (PC+1)

Inst (PC)

Inst (0004h) Inst (0005h)

Inst (0004h)Dummy cycle Dummy cycle

FFh 00h 01h 02h

Note 1: Interrupt ﬂag bit T0IF is sampled here (every Q1).

2: Interrupt latency = 4Tcy where Tcy = instruction cycle time. 3: CLKOUT is available only in RC oscillator mode.

LOW

 1997 Microchip Technology Inc. Preliminary DS30561A-page 29

PIC12C67X

6.2 Using Timer0 with an External Clock

When an external clock input is used for Timer0, it must meet certain requirements. The requirements ensure the external clock can be synchronized with the internal phase clock (T

OSC). Also, there is a delay in the actual

incrementing of Timer0 after synchronization.

6.2.1 EXTERNAL CLOCK SYNCHRONIZATION When no prescaler is used, the external clock input is

the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks (Figure 6-5). Therefore, it is necessary for T0CKI to be high for at least 2Tosc (and a small RC delay of 20 ns) and low for at least 2Tosc (and a small RC delay of 20 ns). Refer to the electrical speciﬁcation of the desired device.

When a prescaler is used, the external clock input is divided by the asynchronous ripple-counter type pres-

caler so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple-counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4Tosc (and a small RC delay of 40 ns) divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the minimum pulse width requirement of 10 ns. Refer to par ameters 40, 41 and 42 in the electrical speciﬁcation of the desired device.

6.2.2 TMR0 INCREMENT DELAY Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the external clock edge occurs to the time the Timer0 module is actually incremented. Figure 6-5 shows the delay from the external clock edge to the timer incrementing.

FIGURE 6-5: TIMER0 TIMING WITH EXTERNAL CLOCK

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

External Clock Input or Prescaler output

(2)

External Clock/Prescaler Output after sampling

Increment Timer0 (Q4)

Timer0

T0 T0 + 1 T0 + 2

Small pulse misses sampling

Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).

Therefore, the error in measuring the interval between two edges on Timer0 input = ±4Tosc max. 2: External clock if no prescaler selected, Prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs.

(3)

(1)

PIC12C67X

DS30561A-page 30 Preliminary  1997 Microchip Technology Inc.

6.3 Prescaler

An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer, respectively (Figure 6-6). For simplicity, this counter is being referred to as “prescaler” throughout this data sheet. Note that there is only one prescaler available which is m utually e xclusiv ely shared between the Timer0 module and the Watchdog Timer. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the Watchdog Timer, and vice-versa.

The PSA and PS2:PS0 bits (OPTION<3:0>) determine the prescaler assignment and prescale ratio.

When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g. CLRF 1, MOVWF 1,

BSF 1,x....etc.) will clear the prescaler. When assigned

to WDT , a CLRWDT instruction will clear the prescaler along with the Watchdog Timer. The prescaler is not readable or writable.

FIGURE 6-6: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

GP2/T0CKI/

T0SE

AN2

M U

CLKOUT (=Fosc/4)

SYNC

Cycles

TMR0 reg

8-bit Prescaler

8 - to - 1MUX

M U

M U X

Watchdog

Timer

PSA

WDT

Time-out

PS2:PS0

Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION<5:0>).

PSA

WDT Enable bit

M U

Data Bus

Set ﬂag bit T0IF

on Overﬂow

PSA

T0CS

 1997 Microchip Technology Inc. Preliminary DS30561A-page 31

PIC12C67X

6.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software con-

trol, i.e., it can be changed “on the ﬂy” during program execution.

EXAMPLE 6-1: CHANGING PRESCALER

(TIMER0→WDT)

BCF STATUS, RP0 ;Bank 0 CLRF TMR0 ;Clear TMR0 & Prescaler BSF STATUS, RP0 ;Bank 1 CLRWDT ;Clears WDT MOVLW b'xxxx1xxx' ;Select new prescale MOVWF OPTION_REG ;value & WDT BCF STATUS, RP0 ;Bank 0

Note: To avoid an unintended device RESET, the

following instruction sequence (shown in Example 6-1) must be executed when changing the prescaler assignment from Timer0 to the WDT. This sequence must be followed even if the WDT is disabled.

To change prescaler from the WDT to the Timer0 module use the sequence shown in Example 6-2.

EXAMPLE 6-2: CHANGING PRESCALER

(WDT→TIMER0)

CLRWDT ;Clear WDT and ;prescaler BSF STATUS, RP0 ;Bank 1 MOVLW b'xxxx0xxx' ;Select TMR0, new ;prescale value and MOVWF OPTION_REG ;clock source BCF STATUS, RP0 ;Bank 0

TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER0

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR

Value on all other

Resets

01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 0Bh/8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 000x 0000 000u 81h OPTION GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 85h TRIS — — TRIS5 TRIS4 TRIS3 TRIS2 TRIS1 TRIS0 --11 1111 --11 1111

Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.

PIC12C67X

DS30561A-page 32 Preliminary  1997 Microchip Technology Inc.

NOTES:

 1997 Microchip Technology Inc. Preliminary DS30561A-page 33

PIC12C67X

FIGURE 7-1: ADCON0 REGISTER (ADDRESS 1Fh)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ADCS1 ADCS0

r CHS1 CHS0 GO/DONE r ADON R =Readable bit

W =Writable bit U =Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits

00 = F

OSC/2

01 = F

OSC/8

10 = F

OSC/32

11 = F

RC (clock derived from an RC oscillation)

bit 5: Reserved bit 4-3: CHS1:CHS0: Analog Channel Select bits

00 = channel 0, (GP0/AN0) 01 = channel 1, (GP1/AN1) 10 = channel 2, (GP2/AN2) 11 = channel 3, (GP4/AN3)

bit 2: GO/DONE

: A/D Conversion Status bit

If ADON = 1 1 = A/D conversion in progress (setting this bit starts the A/D conversion) 0 = A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D conver-

sion is complete) bit 1: Reserved bit 0: ADON: A/D On bit

1 = A/D converter module is operating

0 = A/D converter module is shutoff and consumes no operating current

7.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE

The analog-to-digital (A/D) converter module has four analog inputs.

The A/D allows conversion of an analog input signal to a corresponding 8-bit digital number (refer to Application Note AN546 for use of A/D Converter). The output of the sample and hold is the input into the converter, which generates the result via successive approximation. The analog reference voltage is software selectable to either the device’ s positiv e supply v oltage (V

DD)

or the voltage lev el on the GP1/AN1/V

REF pin. The A/D

converter has a unique feature of being able to operate while the device is in SLEEP mode.

The A/D module has three registers. These registers are:

• A/D Result Register (ADRES)

• A/D Control Register 0 (ADCON0)

• A/D Control Register 1 (ADCON1)

The ADCON0 register, shown in Figure 7-1, controls the operation of the A/D module. The ADCON1 register, shown in Figure 7-2, conﬁgures the functions of the port pins. The port pins can be conﬁgured as analog inputs (GP1 can also be a voltage reference) or as digital I/O.

Note: If the port pins are conﬁgured as analog

inputs (reset condition), reading the port (MOVF GP,W) results in reading '0's.

PIC12C67X

DS30561A-page 34 Preliminary  1997 Microchip Technology Inc.

FIGURE 7-2: ADCON1 REGISTER (ADDRESS 9Fh)

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — PCFG2 PCFG1 PCFG0 R =Readable bit

W =Writable bit U =Unimplemented

bit, read as ‘0’

- n =Value at POR reset

bit7 bit0

bit 7-2: Unimplemented: Read as '0' bit 1-0: PCFG2:PCFG0: A/D Port Conﬁguration Control bits

A = Analog input D = Digital I/O

Note 1: Value on reset. Note: Any instruction that reads a pin conﬁgured as an analog input will read a '0'.

PCFG2:PCFG0 GP4 GP2 GP1 GP0 V

REF

000

(1)

A A A A VDD

001 A A VREF A GP1 010 D A A A V

011 D A VREF A GP1 100 D D A A V

101 D D VREF A GP1 110 D D D A V

111 D D D D —

 1997 Microchip Technology Inc. Preliminary DS30561A-page 35

PIC12C67X

The ADRES register contains the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRES register, the GO/DONE bit (ADCON0<2>) is cleared, and A/D interrupt ﬂag bit ADIF (PIE1<6>) is set. The block diagrams of the A/D module are shown in Figure 7-3.

After the A/D module has been conﬁgured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine sample time, see Section 7.1. After this acquisition time has elapsed the A/D conversion can be started. The following steps should be followed for doing an A/D conversion:

1. Conﬁgure the A/D module:

• Conﬁgure analog pins / voltage reference / and digital I/O (ADCON1)

• Select A/D input channel (ADCON0)

• Select A/D conversion clock (ADCON0)

• Turn on A/D module (ADCON0)

2. Conﬁgure A/D interrupt (if desired):

• Clear ADIF bit

• Set ADIE bit

• Set GIE bit

3. Wait the required acquisition time.

4. Start conversion:

• Set GO/DONE

bit (ADCON0)

5. Wait for A/D conversion to complete, by either:

• Polling for the GO/DONE

bit to be cleared

• Waiting for the A/D interrupt

6. Read A/D Result register (ADRES), clear bit ADIF if required.

7. For next conversion, go to step 1 or step 2 as required. The A/D conversion time per bit is deﬁned as T

AD. A minimum wait of 2TAD is

required before next acquisition starts.

FIGURE 7-3: A/D BLOCK DIAGRAM

(Input voltage)

VIN

VREF

(Reference

voltage)

PCFG2:PCFG0

CHS1:CHS0

000 or 010 or 100 or

001 or

GP4/AN3

GP0/AN0

GP2/AN2

GP1/AN1/V

REF

A/D

Converter

011 or 101

110 or

PIC12C67X

DS30561A-page 36 Preliminary  1997 Microchip Technology Inc.

7.1 A/D Sampling Requirements

For the A/D converter to meet its speciﬁed accuracy, the charge holding capacitor (C

HOLD) must be allowed

to fully charge to the input channel voltage level. The analog input model is shown in Figure 7-4. The source impedance (R

S) and the internal sampling switch (RSS)

impedance directly affect the time required to charge the capacitor C

HOLD. The sampling switch (RSS)

impedance varies over the device voltage (V

DD), see

Figure 7-4. The maximum recommended imped- ance for analog sources is 10 kΩ. After the analog input channel is selected (changed) this acquisition must be done before the conversion can be started.

To calculate the minimum acquisition time, Equation 71 may be used. This equation assumes that 1/2 LSb error is used (512 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its speciﬁed resolution.

EQUATION 7-1: A/D MINIMUM CHARGING

TIME

VHOLD = (VREF - (VREF/512)) • (1 - e

(-Tc/CHOLD(RIC + RSS + RS))

) or Tc = -(51.2 pF)(1 kΩ + RSS + RS) ln(1/511)

Example 7-1 shows the calculation of the minimum required acquisition time T

ACQ. This calculation is

based on the following system assumptions. Rs = 10 k

Ω

1/2 LSb error V

DD = 5V → Rss = 7 kΩ

Temp (system max.) = 50°C V

HOLD = 0 @ t = 0

EXAMPLE 7-1: CALCULATING THE

MINIMUM REQUIRED SAMPLE TIME

TACQ = Ampliﬁer Settling Time +

Holding Capacitor Charging Time + Temperature Coefﬁcient

ACQ = 5 µs + Tc + [(Temp - 25°C)(0.05 µs/°C)]

C = -CHOLD (RIC + RSS + RS) ln(1/512)

-51.2 pF (1 kΩ + 7 kΩ + 10 kΩ) ln(0.0020)

-51.2 pF (18 kΩ) ln(0.0020)

-0.921 µs (-6.2146)

5.724 µs

ACQ = 5 µs + 5.724 µs + [(50°C - 25°C)(0.05 µs/°C)]

10.724 µs + 1.25 µs

11.974 µs

Note 1: The reference voltage (VREF) has no

effect on the equation, since it cancels itself out.

Note 2: The charge holding capacitor (C

HOLD) is

not discharged after each conversion.

Note 3: The maximum recommended impedance

for analog sources is 10 kΩ. This is required to meet the pin leakage speciﬁcation.

Note 4: After a conversion has completed, a

2.0 T

AD delay must complete before

acquisition can begin again. During this time the holding capacitor is not connected to the selected A/D input channel.

FIGURE 7-4: ANALOG INPUT MODEL

CPIN

RAx

5 pF

VT = 0.6V

T = 0.6V

I leakage

IC ≤ 1k

Sampling Switch

CHOLD = DAC capacitance

Sampling Switch

5V 4V 3V 2V

5 6 7 8 9 10 11

( kΩ )

VDD

= 51.2 pF

± 500 nA

Legend CPIN

VT I leakage

RIC SS C

HOLD

= input capacitance = threshold voltage

= leakage current at the pin due to

= interconnect resistance = sampling switch = sample/hold capacitance (from DAC)

various junctions

 1997 Microchip Technology Inc. Preliminary DS30561A-page 37

PIC12C67X

7.2 Selecting the A/D Conversion Clock

The A/D conversion time per bit is deﬁned as TAD. The A/D conversion requires 9.5 T

AD per 8-bit conversion.

The source of the A/D conversion clock is software selected. The four possible options for T

AD are:

• 2T

OSC

• 8TOSC

• 32TOSC

• Precision internal 4 MHz oscillator

For correct A/D conversions, the A/D conversion clock (T

AD) must be selected to ensure a minimum TAD time

of 1.6 µs. Table 7-1 shows the resultant T

AD times derived from

the device operating frequencies and the A/D clock source selected.

7.3 Configuring Analog Port Pins

The ADCON1 and TRIS registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (V

OH or VOL) will be converted.

The A/D operation is independent of the state of the CHS2:CHS0 bits and the TRIS bits.

Note 1: When reading the port register, all pins

conﬁgured as analog input channel will read as cleared (a low level). Pins conﬁgured as digital inputs, will convert an analog input. Analog levels on a digitally conﬁgured input will not affect the conversion accuracy.

Note 2: Analog lev els on any pin that is deﬁned as

a digital input (including the AN3:AN0 pins), may cause the input buffer to consume current that is out of the devices speciﬁcation.

TABLE 7-1: TAD vs. DEVICE OPERATING FREQUENCIES

AD Clock Source (TAD)

Device Frequency

Operation ADCS1:ADCS0 4 MHz 1.25 MHz 333.33 kHz

OSC 00

500 ns

(2)

1.6 µs 6 µs

OSC 01 2.0 µs 6.4 µs

24 µs

(3)

32TOSC 10 8.0 µs

25.6 µs

(3)

96 µs

(3)

Internal ADC RC Oscillator

(5)

2 - 6 µs

(1,4)

2 - 6 µs

(1,4)

2 - 6 µs

(1)

Note 1: The RC source has a typical TAD time of 4 µs.

2: These values violate the minimum required T

AD time.

3: For faster conversion times, the selection of another clock source is recommended. 4: While in RC mode, with device frequency above 1 MHz, conversion accuracy is out of speciﬁcation. 5: For extended voltage devices (LC), please refer to Electrical Speciﬁcations section.

PIC12C67X

DS30561A-page 38 Preliminary  1997 Microchip Technology Inc.

7.4 A/D Conversions

Example 7-2 show how to perform an A/D conversion. The GP pins are conﬁgured as analog inputs. The analog reference (V

REF) is the device VDD. The A/D inter-

rupt is enabled, and the A/D conversion clock is F

RC.

The conversion is performed on the GP0 channel.

Note: The GO/DONE bit should NOT be set in

the same instruction that turns on the A/D.

Clearing the GO/DONE bit during a conversion will abort the current conversion. The ADRES register will NOT be updated with the partially completed A/D conversion sample. That is, the ADRES register will continue to contain the value of the last completed conversion (or the last value written to the ADRES register). After the A/D conversion is aborted, a 2T

AD wait

is required before the next acquisition is started. After this 2T

AD wait, an acquisition is automatically star ted

on the selected channel.

EXAMPLE 7-2: DOING AN A/D CONVERSION

BSF STATUS, RP0 ; Select Page 1 CLRF ADCON1 ; Configure A/D inputs BSF PIE1, ADIE ; Enable A/D interrupts BCF STATUS, RP0 ; Select Page 0 MOVLW 0xC1 ; RC Clock, A/D is on, Channel 0 is selected MOVWF ADCON0 ; BCF PIR1, ADIF ; Clear A/D interrupt flag bit BSF INTCON, PEIE ; Enable peripheral interrupts BSF INTCON, GIE ; Enable all interrupts ; ; Ensure that the required sampling time for the selected input channel has elapsed. ; Then the conversion may be started. ; BSF ADCON0, GO ; Start A/D Conversion : ; The ADIF bit will be set and the GO/DONE bit : ; is cleared upon completion of the A/D Conversion.

 1997 Microchip Technology Inc. Preliminary DS30561A-page 39

PIC12C67X

7.5 A/D Operation During Sleep

The A/D module can operate during SLEEP mode. This requires that the A/D clock source be set to RC (ADCS1:ADCS0 = 11). When the RC clock source is selected, the A/D module waits one instruction cycle before starting the conversion. This allows the SLEEP instruction to be executed, which eliminates all digital switching noise from the conv ersion. When the conversion is completed the GO/DONE

bit will be cleared, and the result loaded into the ADRES register. If the A/D interrupt is enabled, the device will wake-up from SLEEP. If the A/D interrupt is not enabled, the A/D module will then be turned off, although the ADON bit will remain set.

When the A/D clock source is another clock option (not RC), a SLEEP instruction will cause the present conversion to be aborted and the A/D module to be turned off, though the ADON bit will remain set.

Turning off the A/D places the A/D module in its lowest current consumption state.

7.6 A/D Accuracy/Error

The overall accuracy of the A/D is less than ± 1 LSb for V

DD = 5V ± 10% and the analog VREF = VDD. This over-

all accuracy includes offset error, full scale error, and integral error. The A/D converter is guaranteed to be monotonic. The resolution and accuracy may be less when either the analog reference (V

DD) is less than

5.0V or when the analog reference (V

REF) is less than

DD.

The maximum pin leakage current is ± 5 µA. In systems where the device frequency is low, use of

the A/D RC clock is preferred. At moderate to high frequencies, T

AD should be derived from the device oscil-

lator. T

AD must not violate the minimum and should be

≤ 8 µs for preferred operation. This is because T

AD,

when derived from T

OSC, is kept away from on-chip

phase clock transitions. This reduces, to a large extent, the effects of digital switching noise . This is not possible with the RC derived clock. The loss of accuracy due to digital switching noise can be signiﬁcant if many I/O pins are active.

In systems where the device will enter SLEEP mode after the start of the A/D conversion, the RC clock source selection is required. In this mode, the digital noise from the modules in SLEEP are stopped. This method gives high accuracy.

Note: For the A/D module to operate in SLEEP,

the A/D clock source must be set to RC (ADCS1:ADCS0 = 11). To perform an A/D conversion in SLEEP, the GO/DONE

bit must be set, followed b y the SLEEP instruction.

7.7 Effects of a RESET

A device reset forces all registers to their reset state. This forces the A/D module to be turned off, and any conversion is aborted. The value that is in the ADRES register is not modiﬁed for a Power-on Reset. The ADRES register will contain unknown data after a Power-on Reset.

7.8 Connection Considerations

If the input voltage exceeds the rail v alues (VSS or VDD) by greater than 0.2V, then the accuracy of the conversion is out of speciﬁcation.

An external RC ﬁlter is sometimes added for anti-aliasing of the input signal. The R component should be selected to ensure that the total source impedance is kept under the 10 kΩ recommended speciﬁcation. Any external components connected (via hi-impedance) to an analog input pin (capacitor, zener diode , etc.) should have very little leakage current at the pin.

7.9 Transfer Function

The ideal transfer function of the A/D conv erter is as follows: the first transition occurs when the analog input voltage (V

AIN) is 1 LSb (or Analog VREF / 256)

(Figure 7-5).

FIGURE 7-5: A/D TRANSFER FUNCTION

Note: For the PIC12C67X, care must be taken

when using the GP4 pin in A/D conversions due to its proximity to the OSC1 pin.

Digital code output

FFh FEh

04h 03h 02h 01h 00h

0.5 LSb

1 LSb

2 LSb

3 LSb

4 LSb

255 LSb

256 LSb

(full scale)

Analog input voltage

PIC12C67X

DS30561A-page 40 Preliminary  1997 Microchip Technology Inc.

FIGURE 7-6: FLOWCHART OF A/D OPERATION

TABLE 7-2: SUMMARY OF A/D REGISTERS

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

Power-on

Reset

Value on

all other

Resets

(1)

0Bh/8Bh

INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 000x 0000 000u

0Ch

PIR1 — ADIF — — — — — — -0-- ---- -0-- ----

8Ch

PIE1 — ADIE — — — — — — -0-- ---- -0-- ----

1Eh

ADRES A/D Result Register xxxx xxxx uuuu uuuu

1Fh

ADCON0 ADCS1 ADCS0 r CHS1 CHS0 GO/DONE r ADON 0000 0000 0000 0000

9Fh

ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000

05h GPIO — — GP5 GP4 GP3 GP2 GP1 GP0

--xx xxxx --uu uuuu

85h TRIS — — TRIS5 TRIS4 TRIS3 TRIS2 TRIS1 TRIS0

--11 1111 --11 1111

Legend: x = unknown, u = unchanged, - = unimplemented read as '0', r = reserved. Shaded cells are not used for A/D conv ersion. Note 1: These registers can be addressed from either bank.

Acquire

ADON = 0

ADON = 0?

GO = 0?

A/D Clock

GO = 0

ADIF = 0

Abort Conversion

SLEEP

Power-down A/D

Wait 2 T

Wake-up

Yes

Finish Conversion

GO = 0

ADIF = 1

Device in

Yes

Finish Conversion

GO = 0

ADIF = 1

Wait 2 TAD

Stay in Sleep

Selected Channel

= RC?

SLEEP

Yes

Instruction?

Start of A/D

Conversion Delayed

1 Instruction Cycle

From Sleep?

Power-down A/D

Yes

Wait 2 TAD

Finish Conversion

GO = 0

ADIF = 1

SLEEP?

 1997 Microchip Technology Inc. Preliminary DS30561A-page 41

PIC12C67X

8.0 SPECIAL FEATURES OF THE CPU

What sets a microcontroller apar t from other processors are special circuits to deal with the needs of realtime applications. The PIC12C67X family has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving oper ating modes and offer code protection. These are:

• Oscillator selection

• Reset

- Power-on Reset (POR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

• Interrupts

• Watchdog Timer (WDT)

• SLEEP

• Code protection

• ID locations

• In-circuit serial programming

The PIC12C67X has a Watchdog Timer which can be shut off only through conﬁguration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep

the chip in reset until the crystal oscillator is stable. The other is the Pow er-up Timer (PWRT), which provides a ﬁxed delay of 72 ms (nominal) on power-up only, designed to keep the part in reset while the power supply stabilizes. With these two timers on-chip, most applications need no external reset circuitry.

SLEEP mode is designed to offer a very low current power-down mode. The user can wake-up from SLEEP through external reset, Watchdog Timer Wake-up, or through an interrupt. Several oscillator options are also made available to allow the part to ﬁt the application. The EXTRC oscillator option saves system cost while the LP crystal option saves power. A set of conﬁguration bits are used to select various options.

8.1 Conﬁguration Bits

The conﬁguration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device conﬁgurations. These bits are mapped in program memory location 2007h.

The user will note that address 2007h is beyond the user program memory space. In fact, it belongs to the special test/conﬁguration memory space (2000h3FFFh), which can be accessed only during programming.

FIGURE 8-1: CONFIGURATION WORD

CP1 CP0 CP1 CP0 CP1 CP0 MCLRE CP1 CP0 PWRTE WDTE FOSC2 FOSC1 FOSC0

bit13 bit0

bit 13-8 CP1:CP0: Code Protection bits

(1)

6-5: 11 = Code protection off

10 = Locations 400h through 7FFh code protected (do not use for PIC12C671) 01 = Locations 200h through 7FFh code protected 00 = All memory is code protected

bit 7: MCLRE: Master Clear Reset Enable bit

1 = Master Clear Enabled 0 = Master Clear Disabled

bit 4: PWRTE: Power-up Timer Enable bit

1 = PWRT disabled 0 = PWRT enabled

bit 3: WDTE: Watchdog Timer Enable bit

1 = WDT enabled 0 = WDT disabled

bit 2-0: FOSC2:FOSC0: Oscillator Selection bits

111 = EXTRC, Clockout on OSC2 110 = EXTRC, OSC2 is I/O 101 = INTRC, Clockout on OSC2 100 = INTRC, OSC2 is I/O 011 = Invalid Selection 010 = HS Oscillator 001 = XT Oscillator 000 = LP Oscillator

Note 1: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.

PIC12C67X

DS30561A-page 42 Preliminary  1997 Microchip Technology Inc.

8.2 Oscillator Conﬁgurations

8.2.1 OSCILLATOR TYPES The PIC12C67X can be operated in seven different

oscillator modes. The user can program three conﬁguration bits (FOSC2:FOSC0) to select one of these seven modes:

• LP: Low Power Crystal

• HS: High Speed Crystal Resonator

• XT: Crystal/Resonator

• INTRC*: Internal 4 MHz Oscillator

• EXTRC*: External Resistor/Capacitor *Can be conﬁgured to support CLKOUT

8.2.2 CRYSTAL OSCILLATOR / CERAMIC RESONATORS

In XT, HS or LP modes, a cr ystal or ceramic resonator is connected to the GP5/OSC1/CLKIN and GP4/OSC2 pins to establish oscillation (Figure 8-2). The PIC12C67X oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers speciﬁcations. When in XT, HS or LP modes, the device can have an external clock source drive the GP5/OSC1/CLKIN pin (Figure 8-3).

FIGURE 8-2: CRYSTAL OPERATION

(OR CERAMIC RESONATOR) (XT, HS OR LP OSC CONFIGURATION)

FIGURE 8-3: EXTERNAL CLOCK INPUT

OPERATION (XT, HS OR LP OSC CONFIGURATION)

Note 1: See Capacitor Selection tables for

recommended values of C1 and C2.

2: A series resistor (RS) may be required for

AT strip cut crystals.

3: RF varies with the crystal chosen

(approx. value = 10 MΩ).

(1)

XTAL

OSC2

OSC1

(3)

SLEEP

To internal

logic

(2)

PIC12C67X

Clock from ext. system

OSC1

OSC2

PIC12C67X

Open

TABLE 8-1: CAPACITOR SELECTION

FOR CERAMIC RESONATORS

- PIC12C67X

TABLE 8-2: CAPACITOR SELECTION

FOR CRYSTAL OSCILLATOR

- PIC12C67X

Osc

Type

Resonator

Freq

Cap. RangeC1Cap. Range

XT 455 kHz

2.0 MHz

4.0 MHz

22-100 pF

15-68 pF 15-68 pF

22-100 pF

15-68 pF 15-68 pF

HS 4.0 MHz

8.0 MHz

10.0 MHz

15-68 pF 10-68 pF 10-22 pF

These values are for design guidance only. Since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components.

Osc

Type

Resonator

Freq

Cap.Range

Cap. Range

LP 32 kHz

(1)

100 kHz 200 kHz

15 pF 15-30 pF 15-30 pF

15 pF 30-47 pF 15-82 pF

XT 100 kHz

200 kHz 455 kHz

1 MHz 2 MHz 4 MHz

15-30 pF 15-30 pF 15-30 pF 15-30 pF 15-30 pF 15-47 pF

200-300 pF 100-200 pF

15-100 pF

15-30 pF 15-30 pF 15-47 pF

HS 4 MHz

8 MHz

10 MHz

15-30 pF 15-30 pF 15-30 pF

Note 1: For V

DD > 4.5V, C1 = C2 ≈ 30 pF is

recommended. These values are for design guidance only. Rs may be required in HS mode as well as XT mode to avoid overdriving crystals with low drive lev el speciﬁcation. Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components.

 1997 Microchip Technology Inc. Preliminary DS30561A-page 43

PIC12C67X

8.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT

Either a prepackaged oscillator or a simple oscillator circuit with TTL gates can be used as an external crystal oscillator circuit. Prepackaged oscillators provide a wide operating range and better stability. A well-designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used: one with parallel resonance, or one with series resonance.

Figure 8-4 shows implementation of a parallel resonant oscillator circuit. The circuit is designed to use the fundamental frequency of the crystal. The 74AS04 inverter performs the 180-degree phase shift that a parallel oscillator requires. The 4.7 kΩ resistor provides the negative feedback for stability. The 10 kΩ potentiometers bias the 74AS04 in the linear region. This circuit could be used for external oscillator designs.

FIGURE 8-4: EXTERNAL PARALLEL

RESONANT CRYSTAL OSCILLATOR CIRCUIT

Figure 8-5 shows a series resonant oscillator circuit. This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a 180degree phase shift in a series resonant oscillator circuit. The 330 Ω resistors provide the negative feedback to bias the inverters in their linear region.

FIGURE 8-5: EXTERNAL SERIES

RESONANT CRYSTAL OSCILLATOR CIRCUIT

20 pF

+5V

20 pF

10k

4.7k

10k

74AS04

XTAL

10k

74AS04

PIC12C67X

CLKIN

To Other Devices

330

74AS04

PIC12C67X CLKIN

To Other Devices

XTAL

330

74AS04

0.1 µF

8.2.4 EXTERNAL RC OSCILLATOR For timing insensitive applications, the RC device

option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (Rext) and capacitor (Cext) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low Cext values. The user also needs to take into account variation due to tolerance of external R and C components used.

Figure 8-6 shows how the R/C combination is connected to the PIC12C67X. For Rext values below

2.2 kΩ, the oscillator operation may become unstable, or stop completely. For very high Rext values (e.g., 1 MΩ) the oscillator becomes sensitive to noise, humidity and leakage. Thus, we recommend keeping Rext between 3 kΩ and 100 kΩ.

Although the oscillator will operate with no external capacitor (Cext = 0 pF), we recommend using values above 20 pF for noise and stability reasons. With no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as PCB trace capacitance or package lead frame capacitance.

The Electrical Speciﬁcations sections show RC frequency variation from part to part due to normal process variation. The variation is larger for larger R (since leakage current variation will affect RC frequency more for large R) and for smaller C (since variation of input capacitance will affect RC frequency more).

Also, see the Electrical Speciﬁcations sections for variation of oscillator frequency due to V

DD for given

Rext/Cext values as well as frequency variation due to operating temperature for given R, C, and V

DD values.

FIGURE 8-6: EXTERNAL RC OSCILLATOR

MODE

VDD

Rext

Cext V

OSC1

Internal clock

PIC12C67X

OSC2/CLKOUT

FOSC/4

PIC12C67X

DS30561A-page 44 Preliminary  1997 Microchip Technology Inc.

8.2.5 INTERNAL 4 MHz RC OSCILLATOR The internal RC oscillator provides a ﬁxed 4 MHz (nom-

inal) system clock at V

DD = 5V and 25°C, see "Electrical

Speciﬁcations" section for information on variation ov er voltage and temperature.

In addition, a calibration instruction is programmed into the last address of the program memor y which contains the calibration value for the internal RC oscillator. This value is programmed as a RETLW XX instruction where XX is the calibration value. In order to retr ieve the calibration value, issue a CALL YY instruction where YY is the last location in program memory (03FFh for the PIC12C671, 07FFh for the PIC12C672). Control will be returned to the user’s program with the calibration value loaded into the W register. The program should then perform a MOVWF OSCCAL instruction to load the value into the internal RC oscillator trim register.

OSCCAL, when written to with the calibration value, will “trim” the internal oscillator to remove process variation from the oscillator frequency. Bits <7:4>, CAL3-CAL0 are used for ﬁne calibration while bit 3, CALFST, and bit 2, CALSLW are used for more coarse adjustment. Adjusting CAL3-0 from 0000 to 1111 yields a higher clock speed. Set CALFST = 1 for greater increase in frequency or set CALSLW = 1 for greater decrease in frequency. Note that bits 1 and 0 of OSCCAL are unimplemented and should be written as 0 when modifying OSCCAL for compatibility with future devices.

8.2.6 CLKOUT The PIC12C67X can be conﬁgured to provide a clock

out signal CLKOUT on pin 3 when the conﬁguration word address (2007h) is programmed with FOSC2, FOSC1, FOSC0 equal to 101 for INTRC or 111 for EXTRC. The oscillator frequency, divided by 4 can be used for test purposes or to synchronize other logic.

Note: Please note that erasing the device will

also erase the pre-programmed internal calibration value for the internal oscillator. The calibration value must be saved prior to erasing the part.

8.3 Reset

The PIC12C67X differentiates between various kinds of reset:

• Power-on Reset (POR)

• MCLR

reset during normal operation

• MCLR

reset during SLEEP

• WDT Reset (normal operation) Some registers are not affected in any reset condition;

their status is unknown on POR and unchanged in any other reset. Most other registers are reset to a “reset state” on Power-on Reset (POR), on the MCLR

and

WDT Reset, on MCLR

reset during SLEEP. They are not affected by a WDT Wak e-up , which is viewed as the resumption of normal operation. The T

O and PD bits are set or cleared differently in different reset situations as indicated in Table 8-4. These bits are used in software to determine the nature of the reset. See Table 85 for a full description of reset states of all registers.

A simpliﬁed block diagram of the on-chip reset circuit is shown in Figure 8-7.

The PIC12C67X has a MCLR

noise ﬁlter in the MCLR

reset path. The ﬁlter will detect and ignore small pulses. It should be noted that a WDT Reset

does not drive MCLR

pin low.

 1997 Microchip Technology Inc. Preliminary DS30561A-page 45

PIC12C67X

FIGURE 8-7: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

Weak

Pull-up

GP3/MCLR/VPP Pin

OSC1/

WDT

Module

DD rise

detect

OST/PWRT

On-chip

(1)

RC OSC

WDT Time-out

Power-on Reset

OST

PWRT

Chip_Reset

10-bit Ripple-counter

Enable OST

Enable PWRT

SLEEP

See Table 8-3 for time-out situations.

Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.

CLKIN

10-bit Ripple-counter

MCLRE

INTERNAL MCLR

PIC12C67X

DS30561A-page 46 Preliminary  1997 Microchip Technology Inc.

8.4 Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)

8.4.1 POWER-ON RESET (POR)

A Power-on Reset pulse is generated on-chip when V

DD rise is detected (in the range of 1.5V - 2.1V). To

take advantage of the POR, just tie the MCLR

directly (or through a resistor) to V

DD. This will eliminate

external RC components usually needed to create a Power-on Reset. A maximum rise time for V

DD is spec-

iﬁed. See Electrical Speciﬁcations for details. When the device starts normal operation (exits the

reset condition), device operating parameters (voltage , frequency, temperature, ...) must be met to ensure operation. If these conditions are not met, the device must be held in reset until the operating conditions are met.

For additional information, refer to Application Note AN607, "

Power-up Trouble Shooting

8.4.2 POWER-UP TIMER (PWRT)

The Power-up Timer provides a ﬁxed 72 ms nominal time-out on power-up only, from the POR. The Powerup Timer operates on an internal RC oscillator. The chip is kept in reset as long as the PWRT is active . The PWRT’ s time dela y allo ws V

DD to rise to an acceptable

level. A conﬁguration bit is provided to enable/disable the PWRT.

The power-up time delay will vary from chip to chip due to V

DD, temperature, and process variation. See DC

parameters for details.

8.4.3 OSCILLATOR START-UP TIMER (OST) The Oscillator Start-up Timer (OST) provides 1024

oscillator cycle (from OSC1 input) delay after the PWRT delay is ov er. This ensures that the crystal oscillator or resonator has started and stabilized.

The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset or wake-up from SLEEP.

8.4.4 TIME-OUT SEQUENCE On power-up the time-out sequence is as follows: First

PWRT time-out is inv oked after the POR time delay has expired. Then OST is activated. The total time-out will vary based on oscillator conﬁguration and the status of the PWRT. For example, in RC mode with the PWRT disabled, there will be no time-out at all. Figure 8-8, Figure 8-9, and Figure 8-10 depict time-out sequences on power-up.

Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire . Then bringing MCLR

high will begin execution immediately (Figure 8-9). This is useful for testing purposes or to synchronize more than one PIC12C67X device operating in parallel.

Table 8-5 shows the reset conditions for all the registers.

8.4.5 POWER CONTROL/STATUS REGISTER

(PCON)

The power control/status register, PCON (address 8Eh) has one bit. See Figure 4-8 for register.

Bit1 is POR

(Power-on Reset). It is cleared on a Poweron Reset and is unaffected otherwise. The user set this bit following a Power-on Reset. On subsequent resets if POR is ‘0’, it will indicate that a Power-on Reset must have occurred.

TABLE 8-3: TIME-OUT IN VARIOUS SITUATIONS

TABLE 8-4: STATUS BITS AND THEIR SIGNIFICANCE

Oscillator Conﬁguration Power-up Wake-up from SLEEP

PWR

TE = 0 PWRTE = 1

XT, HS, LP 72 ms + 1024T

OSC 1024TOSC 1024TOSC

INTRC, EXTRC 72 ms — —

POR

TO PD

0 1 1 Power-on Reset 0 0 x Illegal, T

O is set on POR

0 x 0 Illegal, PD is set on POR 1 0 1 WDT Reset 1 0 0 WDT Wake-up 1 u u MCLR

Reset during normal operation

1 1 0 MCLR

Reset during SLEEP or interrupt wake-up from SLEEP

 1997 Microchip Technology Inc. Preliminary DS30561A-page 47

PIC12C67X

TABLE 8-5: RESET CONDITION FOR SPECIAL REGISTERS

TABLE 8-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS

Condition

Program

Counter

STATUS

PCON

Power-on Reset 000h 0001 1xxx ---- --0- MCLR Reset during normal operation 000h 0001 1uuu ---- --u- MCLR

Reset during SLEEP 000h 0001 0uuu ---- --u- WDT Reset during normal operation 000h 0000 1uuu ---- --u- WDT Wake-up from SLEEP PC + 1 uuu0 0uuu ---- --u- Interrupt wake-up from SLEEP PC + 1

(1)

uuu1 0uuu ---- --u-

Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'. Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector

(0004h).

Resets

WDT Reset

Wake-up via

WDT or Interrupt

W xxxx xxxx uuuu uuuu uuuu uuuu INDF 0000 0000 0000 0000 0000 0000 TMR0 xxxx xxxx uuuu uuuu uuuu uuuu PCL 0000 0000 0000 0000 PC + 1

(2)

STATUS 0001 1xxx 000q quuu

(3)

uuuq quuu

(3)

FSR xxxx xxxx uuuu uuuu uuuu uuuu GPIO --xx xxxx --uu uuuu --uu uuuu PCLATH ---0 0000 ---0 0000 ---u uuuu INTCON 0000 000x 0000 000u uuuu uuuu

(1)

PIR1 -0-- ---- -0-- ---- -u-- ----

(1)

ADCON0 0000 0000 0000 0000 uuuu uuuu OPTION 1111 1111 1111 1111 uuuu uuuu TRIS --11 1111 --11 1111 --uu uuuu PIE1 -0-- 0000 -0-- 0000 -u-- uuuu PCON ---- --0- ---- --u- ---- --u- OSCCAL 0111 00-- uuuu uu-- uuuu uu-- ADCON1 ---- -000 ---- -000 ---- -uuu

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition Note 1: One or more bits in INTCON and PIR1 will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector

(0004h).

3: See Table 8-5 for reset value for speciﬁc condition.

PIC12C67X

DS30561A-page 48 Preliminary  1997 Microchip Technology Inc.

FIGURE 8-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1

FIGURE 8-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

FIGURE 8-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR

TIED TO VDD)

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWR

T TIME-OUT

OST TIME-OUT

INTERNAL RESET

VDD

MCLR

INTERNAL POR

PWR

T TIME-OUT

OST TIME-OUT

INTERNAL RESET

TPWRT

TOST

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWR

T TIME-OUT

OST TIME-OUT

INTERNAL RESET

 1997 Microchip Technology Inc. Preliminary DS30561A-page 49

PIC12C67X

FIGURE 8-11: EXTERNAL POWER-ON

RESET CIRCUIT (FOR SLOW VDD POWER-UP)

Note 1: External Power-on Reset circuit is required

only if V

DD power-up slope is too slow . The

diode D helps discharge the capacitor quickly when V

DD powers down.

2: R < 40 kΩ is recommended to make sure

that voltage drop across R does not violate the device’s electrical speciﬁcation.

3: R1 = 100Ω to 1 kΩ will limit any current

ﬂowing into MCLR from external capacitor C in the event of MCLR

/VPP pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS).

MCLR

PIC12C67X

FIGURE 8-12: EXTERNAL BROWN-OUT

PROTECTION CIRCUIT 1

FIGURE 8-13: EXTERNAL BROWN-OUT

PROTECTION CIRCUIT 2

Note 1: This circuit will activate reset when VDD

goes below (Vz + 0.7V) where Vz = Zener voltage.

2: Internal brown-out detection should be

disabled when using this circuit.

3: Resistors should be adjusted for the char-

acteristics of the transistor.

VDD

33k

10k

4.3k

MCLR

PIC12C67X

Note 1: This brown-out circuit is less expensive ,

albeit less accurate. Transistor Q1 turns off when V

DD is below a certain level

such that:

2: Internal brown-out detection should be

disabled when using this circuit.

3: Resistors should be adjusted for the

characteristics of the transistor.

DD •

R1 + R2

= 0.7V

VDD

4.3k

VDD

MCLR

PIC12C67X

DS30561A-page 50 Preliminary  1997 Microchip Technology Inc.

8.5 Interrupts

There are four sources of interrupt:

The interrupt control register (INTCON) records individual interrupt requests in ﬂag bits. It also has individual and global interrupt enable bits.

A global interrupt enable bit, GIE (INTCON<7>) enables (if set) all un-masked interrupts or disables (if cleared) all interrupts. When bit GIE is enabled, and an interrupt’s ﬂag bit and mask bit are set, the interrupt will vector immediately. Individual interrupts can be disabled through their corresponding enable bits in various registers. Individual interrupt bits are set regardless of the status of the GIE bit. The GIE bit is cleared on reset.

Interrupt Sources

TMR0 overﬂow interrupt External interrupt GP2/INT pin GPIO Port change interrupts (pins GP0, GP1, GP3) A/D Interrupt

Note: Individual interrupt ﬂag bits are set regard-

less of the status of their corresponding mask bit or the GIE bit.

The “return from interrupt” instruction, RETFIE, exits the interrupt routine as well as sets the GIE bit, which re-enables interrupts.

The GP2/INT, GPIO port change interrupt and the TMR0 overﬂow interrupt ﬂags are contained in the INTCON register.

The peripheral interrupt ﬂag ADIF, is contained in the special function register PIR1. The corresponding interrupt enable bit is contained in special function register PIE1, and the peripheral interrupt enable bit is contained in special function register INTCON.

When an interrupt is responded to, the GIE bit is cleared to disable any further interrupt, the return address is pushed onto the stack and the PC is loaded with 0004h. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt ﬂag bits. The interr upt ﬂag bit(s) must be cleared in software before re-enabling interrupts to avoid recursive interrupts.

For external interrupt events, such as GPIO change interrupt, the interrupt latency will be three or four instruction cycles. The e xact latency depends when the interrupt event occurs (Figure 8-15). The latency is the same for one or two cycle instructions. Individual interrupt ﬂag bits are set regardless of the status of their corresponding mask bit or the GIE bit.

FIGURE 8-14: INTERRUPT LOGIC

GPIF GPIE

T0IF T0IE

GIE

Wakeup (If in SLEEP mode)

Interrupt to CPU

PEIE

ADIF ADIE

INTF

INTE

 1997 Microchip Technology Inc. Preliminary DS30561A-page 51

PIC12C67X

FIGURE 8-15: INT PIN INTERRUPT TIMING

Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

OSC1

CLKOUT

INT pin

INTF ﬂag (INTCON<1>)

GIE bit (INTCON<7>)

INSTR

UCTION FLOW

Instruction fetched

Instruction executed

Interrupt Latency

PC+1

0004h

0005h

Inst (0004h)

Inst (0005h)

Dummy Cycle

Inst (PC)

Inst (PC+1)

Inst (PC-1)

Inst (0004h)

Dummy Cycle

Inst (PC)

—

Note

1: INTF ﬂag is sampled here (every Q1). 2: Interrupt latency = 3-4 Tcy where Tcy = instruction cycle time.

Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT is available only in INTRC and EXTRC oscillator modes. 4: For minimum width of INT pulse, refer to AC specs. 5: INTF is enabled to be set anytime during the Q4-Q1 cycles.

PIC12C67X

DS30561A-page 52 Preliminary  1997 Microchip Technology Inc.

8.5.1 TMR0 INTERRUPT An overﬂow (FFh → 00h) in the TMR0 register will set

ﬂag bit T0IF (INTCON<2>). The interrupt can be enabled/disabled by setting/clearing enable bit T0IE (INTCON<5>). (Section 6.0)

8.5.2 INT INTERRUPT External interrupt on GP2/INT pin is edge triggered:

either rising if bit INTEDG (OPTION<6>) is set, or falling, if the INTEDG bit is clear. When a valid edge appears on the GP2/INT pin, ﬂag bit INTF (INTCON<1>) is set. This interr upt can be disabled by clearing enable bit INTE (INTCON<4>). Flag bit INTF must be cleared in software in the interrupt service routine before re-enabling this interrupt. The INT interrupt can wake-up the processor from SLEEP, if bit INTE was set prior to going into SLEEP. The status of global interrupt enable bit GIE decides whether or not the processor branches to the interrupt vector following wake-up. See Section 8.8 for details on SLEEP mode.

8.5.3 GPIO INTCON CHANGE An input change on GP3, GP1 or GP0 sets ﬂag bit

GPIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit GPIE (INTCON<3>). (Section 5.2)

8.6 Context Saving During Interrupts

During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save ke y registers during an interrupt i.e., W register and STATUS register. This will have to be implemented in software.

Example 8-1 store and restore the STA TUS and W registers. The register, W_TEMP, must be deﬁned in both banks and must be deﬁned at the same offset from the bank base address (i.e., if W_TEMP is deﬁned at 0x20 in bank 0, it must also be deﬁned at 0xA0 in bank 1).

The example: a) Stores the W register.

b) Stores the STATUS register in bank 0. c) Executes the ISR code. d) Restores the STATUS register (and bank select

bit).

e) Restores the W register.

EXAMPLE 8-1: SAVING STATUS AND W REGISTERS IN RAM

MOVWF W_TEMP ;Copy W to TEMP register, could be bank one or zero SWAPF STATUS,W ;Swap status to be saved into W BCF STATUS,RP0 ;Change to bank zero, regardless of current bank MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register : :(ISR) : SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W ;(sets bank to original state) MOVWF STATUS ;Move W into STATUS register SWAPF W_TEMP,F ;Swap W_TEMP SWAPF W_TEMP,W ;Swap W_TEMP into W

 1997 Microchip Technology Inc. Preliminary DS30561A-page 53

PIC12C67X

8.7 Watchdog Timer (WDT)

The Watchdog Timer is as a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. That means that the WDT will run, even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins of the device has been stopped, for example, by execution of a SLEEP instruction. During normal operation, a WDT time-out generates a device RESET (Watchdog Timer Reset). If the device is in SLEEP mode, a WDT time-out causes the device to wake-up and continue with normal operation (Watchdog Timer Wake-up). The WDT can be permanently disabled by clearing conﬁguration bit WDTE (Section 8.1).

8.7.1 WDT PERIOD The WDT has a nominal time-out period of 18 ms, (with

no prescaler). The time-out periods vary with temperature, V

and process variations from part to part (see DC specs). If longer time-out periods are desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT under software control by writing to the OPTION register. Thus, time-out periods up to

2.3 seconds can be realized.

The CLRWDT and SLEEP instructions clear the WDT and the postscaler, if assigned to the WDT, and prevent it from timing out early and generating a premature device RESET condition.

The T

O bit in the STATUS register will be cleared upon

a Watchdog Timer time-out.

8.7.2 WDT PROGRAMMING CONSIDERATIONS It should also be taken into account that under worst

case conditions (V

DD = Min., Temperature = Max., and

max. WDT prescaler) it may take several seconds before a WDT time-out occurs.

Note: When the prescaler is assigned to the

WDT, always execute a CLRWDT instruction before changing the prescale value, otherwise a WDT reset may occur.

FIGURE 8-16: WATCHDOG TIMER BLOCK DIAGRAM

FIGURE 8-17: SUMMARY OF WATCHDOG TIMER REGISTERS

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

2007h

Conﬁg. bits

(1)

MCLRE CP1 CP0 PWRTE WDTE FOSC2 FOSC1 FOSC0

81h OPTION

GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Figure 8-1 for operation of these bits. Not all CP0 and CP1 bits are shown.

From TMR0 Clock Source (Figure 6-6)

To TMR0 (Figure 6-6)

Postscaler

WDT Timer

WDT

Enable Bit

0 1

M U X

PSA

8 - to - 1 MUX

PS2:PS0

MUX

PSA

WDT

Time-out

Note: PSA and PS2:PS0 are bits in the OPTION register.

PIC12C67X

DS30561A-page 54 Preliminary  1997 Microchip Technology Inc.

8.8 Power-down Mode (SLEEP)

Power-down mode is entered by executing a SLEEP instruction.

If enabled, the Watchdog Timer will be cleared but keeps running, the PD

bit (STATUS<3>) is cleared, the

O (STATUS<4>) bit is set, and the oscillator dr iver is turned off. The I/O por ts maintain the status they had, before the SLEEP instruction was executed (driving high, low, or hi-impedance).

For lowest current consumption in this mode, place all I/O pins at either V

DD, or VSS, ensure no external cir-

cuitry is drawing current from the I/O pin, power-down the A/D, disable external clocks. Pull all I/O pins, that are hi-impedance inputs, high or low externally to av oid switching currents caused by ﬂoating inputs. The T0CKI input if enabled should also be at V

DD or VSS for

lowest current consumption. The contribution from onchip pull-ups on GPIO should be considered.

The MCLR

pin if enabled must be at a logic high level

IHMC).

8.8.1 WAKE-UP FROM SLEEP The device can wake up from SLEEP through one of

the following events:

1. External reset input on MCLR

pin.

2. Watchdog Timer Wake-up (if WDT was

enabled).

3. GP2/INT interrupt, interrupt GPIO por t change,

or some Peripheral Interrupts.

External MCLR

Reset will cause a device reset. All other events are considered a continuation of program execution and cause a "wake-up". The T

O and PD bits in the STATUS register can be used to determine the cause of device reset. The PD

bit, which is set on

power-up, is cleared when SLEEP is in vok ed. The T

O bit is cleared if a WDT time-out occurred (and caused wake-up).

The following peripheral interrupt can wake the device from SLEEP:

1. A/D conversion (when A/D clock source is RC).

Other peripherals can not generate interrupts since during SLEEP, no on-chip Q clocks are present.

When the SLEEP instruction is being executed, the ne xt instruction (PC + 1) is pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instr uction and then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction.

8.8.2 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit and interrupt ﬂag bit set, one of the following will occur:

• If the interrupt occurs before the the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore , the WDT and WDT postscaler will not be cleared, the T

O bit will not

be set and PD

bits will not be cleared.

• If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake up from sleep . The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT postscaler will be cleared, the T

O bit will be set and the PD bit will

be cleared.

Even if the ﬂag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD

bit. If the PD bit is set, the SLEEP instruction was

executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruc-

tion should be executed before a SLEEP instruction.

 1997 Microchip Technology Inc. Preliminary DS30561A-page 55

PIC12C67X

FIGURE 8-18: WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKOUT(4)

GPIO pin

GPIF ﬂag (INTCON<0>)

GIE bit (INTCON<7>)

INSTR

UCTION FLOW

Instruction fetched

Instruction executed

PC PC+1 PC+2

Inst(PC) = SLEEP

Inst(PC - 1)

Inst(PC + 1)

SLEEP

Processor in

SLEEP

Interrupt Latency

(Note 2)

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h)

Inst(0005h)

Inst(0004h)

Dummy cycle

PC + 2 0004h 0005h

Dummy cycle

TOST(2)

PC+2

Note 1: XT, HS or LP oscillator mode assumed.

2: T

OST = 1024TOSC (drawing not to scale) This delay will not be there for INTRC and EXTRC osc mode.

3: GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line. 4: CLKOUT is not available in XT, HS or LP osc modes, but shown here for timing reference.

8.9 Program Veriﬁcation/Code Protection

If the code protection bit(s) have not been programmed, the on-chip program memory can be read out for veriﬁcation purposes.

8.10 ID Locations

Four memory locations (2000h - 2003h) are designated as ID locations where the user can store checksum or other code-identiﬁcation numbers. These locations are not accessible during normal execution but are readable and writable during program/verify. It is recommended that only the 4 least signiﬁcant bits of the ID location are used.

8.11 In-Circuit Serial Programming

PIC12C67X microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent ﬁrmware or a custom ﬁrmware to be programmed.

The device is placed into a program/verify mode by holding the GP1 and GP0 pins low while raising the MCLR

(VPP) pin from VIL to VIHH (see programming speciﬁcation). GP1 (clock) becomes the programming clock and GP0 (data) becomes the programming data. Both GP0 and GP1 are Schmitt Trigger inputs in this mode.

Note: Microchip does not recommend code pro-

tecting windowed devices.

After reset, to place the device into programming/verify mode, the program counter (PC) is at location 00h. A 6bit command is then supplied to the device. Depending on the command, 14-bits of program data are then supplied to or from the device, depending if the command was a load or a read. For complete details of serial programming, please refer to the PIC12C67X Programming Speciﬁcations.

FIGURE 8-19: TYPICAL IN-CIRCUIT SERIAL

PROGRAMMING CONNECTION

External Connector Signals

To Normal Connections

PIC12C67X

VSS MCLR/VPP

GP1

GP0

+5V

VPP

CLK

Data I/O

VDD

PIC12C67X

DS30561A-page 56 Preliminary  1997 Microchip Technology Inc.

NOTES:

 1997 Microchip Technology Inc. Preliminary DS30561A-page 57

PIC12C67X

9.0 INSTRUCTION SET SUMMARY

Each PIC12C67X instruction is a 14-bit word divided into an OPCODE which speciﬁes the instruction type and one or more operands which further specify the operation of the instruction. The PIC12C67X instruction set summary in Table 9-2 lists byte-oriented, bit- oriented, and literal and control operations. Table 9- 1 shows the opcode ﬁeld descriptions.

For byte-oriented instructions, 'f' represents a ﬁle register designator and 'd' represents a destination designator. The ﬁle register designator speciﬁes which ﬁle register is to be used by the instruction.

The destination designator speciﬁes where the result of the operation is to be placed. If 'd' is zero, the result is placed in the W register . If 'd' is one , the result is placed in the ﬁle register speciﬁed in the instruction.

For bit-oriented instructions, 'b' represents a bit ﬁeld designator which selects the number of the bit affected by the operation, while 'f' represents the number of the ﬁle in which the bit is located.

For literal and control operations, 'k' represents an eight or eleven bit constant or literal value.

TABLE 9-1: OPCODE FIELD

DESCRIPTIONS

Field Description

f Register ﬁle address (0x00 to 0x7F) W Working register (accumulator) b Bit address within an 8-bit ﬁle register k Literal ﬁeld, constant data or label x Don't care location (= 0 or 1)

The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools.

d Destination select; d = 0: store result in W,

d = 1: store result in ﬁle register f. Default is d = 1

label Label name

TOS Top of Stack

PC Program Counter

PCLATH

Program Counter High Latch

GIE Global Interrupt Enable bit WDT Watchdog Timer/Counter

TO Time-out bit PD Power-down bit

dest Destination either the W register or the speciﬁed

[ ] Options

( )

Contents

→

Assigned to

< >

∈

In the set of

talics

User deﬁned term (font is courier)

The instruction set is highly orthogonal and is grouped into three basic categories:

• Byte-oriented operations

• Bit-oriented operations

• Literal and control operations All instructions are executed within one single instruc-

tion cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 µs. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 µs.

Table 9-2 lists the instructions recognized by the MPASM assembler.

Figure 9-1 shows the three general formats that the instructions can have.

All examples use the following format to represent a hexadecimal number:

0xhh

where h signiﬁes a hexadecimal digit.

FIGURE 9-1: GENERAL FORMAT FOR

INSTRUCTIONS

Note: To maintain upward compatibility with

future PIC12C67X products, do not use the OPTION and TRIS instructions.

Byte-oriented ﬁle register operations

13 8 7 6 0

d = 0 for destination W

OPCODE d f (FILE #)

d = 1 for destination f f = 7-bit ﬁle register address

Bit-oriented ﬁle register operations

13 10 9 7 6 0

OPCODE b (BIT #) f (FILE #)

b = 3-bit bit address f = 7-bit ﬁle register address

Literal and control operations

13 8 7 0

OPCODE k (literal)

k = 8-bit immediate value

13 11 10 0

OPCODE k (literal)

k = 11-bit immediate value

General

CALL and GOTO instructions only

PIC12C67X

DS30561A-page 58 Preliminary  1997 Microchip Technology Inc.

9.1 Special Function Registers as Source/Destination

The PIC12C67X’s orthogonal instruction set allows read and write of all ﬁle registers, including special function registers. There are some special situations the user should be aware of:

9.1.1 STATUS AS DESTINATION

If an instruction writes to ST ATUS, the Z, C and DC bits may be set or cleared as a result of the instruction and overwrite the original data bits written. For example, executing CLRF STATUS will clear register ST ATUS, and then set the Z bit leaving 0000 0100b in the register.

9.1.2 TRIS AS DESTINATION

Bit 3 of the TRIS register always reads as a '1' since GP3 is an input only pin. This f act can affect some readmodify-write operations on the TRIS register.

9.1.3 PCL AS SOURCE OR DESTINATION Read, write or read-modify-write on PCL may have the

following results: Read PC: PCL → dest Write PCL: PCLATH → PCH;

8-bit destination value → PCL

Read-Modify-Write: PCL→ ALU operand

PCLATH → PCH; 8-bit result → PCL

Where PCH = program counter high byte (not an addressable register), PCLATH = Program counter high holding latch, dest = destination, WREG or f.

9.1.4 BIT MANIPULATION All bit manipulation instructions are done by ﬁrst read-

ing the entire register, operating on the selected bit and writing the result back (read-modify-write). The user should keep this in mind when operating on special function registers, such as ports.

 1997 Microchip Technology Inc. Preliminary DS30561A-page 59

PIC12C67X

TABLE 9-2: INSTRUCTION SET SUMMARY

Mnemonic, Operands

Description Cycles 14-Bit Opcode Status

Affected

Notes

MSb LSb

BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF

ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF

f, d f, d f

f, d f, d f, d f, d f, d f, d f, d f

f, d f, d f, d f, d f, d

Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f

1 1 1 1 1 1

1(2)

1 1 1 1 1 1 1 1 1

00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110

dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff

ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff

C,DC,Z Z Z Z Z Z

Z Z

C C C,DC,Z

1,2 1,2 2

1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2

1,2 1,2 1,2 1,2 1,2

BIT-ORIENTED FILE REGISTER OPERATIONS BCF

BSF BTFSC BTFSS

f, b f, b f, b f, b

Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set

1 1 (2) 1 (2)

01 01 01 01

00bb 01bb 10bb 11bb

bfff bfff bfff bfff

ffff ffff ffff ffff

1,2 1,2 3 3

LITERAL AND CONTROL OPERATIONS ADDLW

ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW

k k k

k k

Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into standby mode Subtract W from literal Exclusive OR literal with W

11 11 10 00 10 11 11 00 11 00 00 11 11

111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010

kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk

kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk

C,DC,Z Z

O,PD

TO,PD C,DC,Z Z

Note 1: When an I/O register is modiﬁed as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present

on the pins themselves. For example, if the data latch is '1' for a pin conﬁgured as input and is driven low by an external device, the data will be written back with a '0'.

2: If this instruction is executed on the TMR0 register (and, where applicable , d = 1), the prescaler will be cleared if assigned

to the Timer0 Module.

3: If Program Counter (PC) is modiﬁed or a conditional test is true, the instruction requires two cycles. The second cycle is

executed as a NOP.

PIC12C67X

DS30561A-page 60 Preliminary  1997 Microchip Technology Inc.

9.2 Instruction Descriptions

ADDLW Add Literal and W

Syntax: [

label

] ADDLW k Operands: 0 ≤ k ≤ 255 Operation: (W) + k → (W) Status Affected: C, DC, Z Encoding:

11 111x kkkk kkkk

Description:

The contents of the W register are added to the eight bit literal 'k' and the result is placed in the W register

. Words: 1 Cycles: 1 Example

ADDLW 0x15

Before Instruction

W = 0x10

After Instruction

W = 0x25

ADDWF Add W and f

Syntax: [

label

] ADDWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: (W) + (f) → (dest) Status Affected: C, DC, Z Encoding:

00 0111 dfff ffff

Description:

Add the contents of the W register

with register 'f'. If 'd' is 0 the result is

stored in the W register. If 'd' is 1 the

result is stored back in register 'f'

. Words: 1 Cycles: 1 Example

ADDWF FSR, 0

Before Instruction

W = 0x17 FSR = 0xC2

After Instruction

W = 0xD9 FSR = 0xC2

ANDLW And Literal with W

Syntax: [

label

] ANDLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .AND. (k) → (W) Status Affected: Z Encoding:

11 1001 kkkk kkkk

Description:

The contents of W register are AND’ed with the eight bit literal 'k'. The result is placed in the W register

. Words: 1 Cycles: 1 Example

ANDLW 0x5F

Before Instruction

W = 0xA3

After Instruction

W = 0x03

ANDWF AND W with f

Syntax: [

label

] ANDWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: (W) .AND. (f) → (dest) Status Affected: Z Encoding:

00 0101 dfff ffff

Description:

AND the W register with register 'f'. If

'd' is 0 the result is stored in the W

back in register 'f'

. Words: 1 Cycles: 1 Example

ANDWF FSR, 1

Before Instruction

W = 0x17 FSR = 0xC2

After Instruction

W = 0x17 FSR = 0x02

 1997 Microchip Technology Inc. Preliminary DS30561A-page 61

PIC12C67X

BCF Bit Clear f

Syntax: [

label

] BCF f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7 Operation: 0 → (f<b>) Status Affected: None Encoding:

01 00bb bfff ffff

Description: Bit 'b' in register 'f' is cleared. Words: 1 Cycles: 1 Example

BCF FLAG_REG, 7

Before Instruction

FLAG_REG = 0xC7

After Instruction

FLAG_REG = 0x47

BSF Bit Set f

Syntax: [

label

] BSF f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7 Operation: 1 → (f<b>) Status Affected: None Encoding:

01 01bb bfff ffff

Description:

Bit 'b' in register 'f' is set.

Words: 1 Cycles: 1 Example

BSF FLAG_REG, 7

Before Instruction

FLAG_REG = 0x0A

After Instruction

FLAG_REG = 0x8A

BTFSC Bit Test, Skip if Clear

Syntax: [

label

] BTFSC f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7 Operation: skip if (f<b>) = 0 Status Affected: None Encoding:

01 10bb bfff ffff

Description:

If bit 'b' in register 'f' is '0' then the next

instruction is skipped.

If bit 'b' is '0' then the next instruction

fetched during the current instruction

execution is discarded, and a NOP is

executed instead, making this a 2 cycle

instruction

. Words: 1 Cycles: 1(2) Example

HERE FALSE TRUE

BTFSC GOTO

•

FLAG,1 PROCESS_CODE

Before Instruction

PC = address HERE

After Instruction

if FLAG<1> = 0, PC = address TRUE if FLAG<1>=1, PC = address FALSE

PIC12C67X

DS30561A-page 62 Preliminary  1997 Microchip Technology Inc.

BTFSS Bit Test f, Skip if Set

Syntax: [

label

] BTFSS f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b < 7 Operation: skip if (f<b>) = 1 Status Affected: None Encoding:

01 11bb bfff ffff

Description:

If bit 'b' in register 'f' is '1' then the next

instruction is skipped.

If bit 'b' is '1', then the next instruction

fetched during the current instruction

execution, is discarded and a NOP is

executed instead, making this a 2 cycle

instruction.

Words: 1 Cycles: 1(2) Example

HERE FALSE TRUE

BTFSC GOTO

•

FLAG,1 PROCESS_CODE

Before Instruction

PC = address HERE

After Instruction

if FLAG<1> = 0, PC = address FALSE if FLAG<1> = 1, PC = address TRUE

CALL Call Subroutine

Syntax: [

label

] CALL k Operands: 0 ≤ k ≤ 2047 Operation: (PC)+ 1→ TOS,

k → PC<10:0>,

(PCLATH<4:3>) → PC<12:11> Status Affected: None Encoding:

10 0kkk kkkk kkkk

Description:

Call Subroutine. First, return address

(PC+1) is pushed onto the stack. The

eleven bit immediate address is loaded

into PC bits <10:0>. The upper bits of

the PC are loaded from PCLATH.

CALL is a two cycle instruction.

Words: 1 Cycles: 2 Example

HERE CALL THERE

Before Instruction

PC = Address HERE

After Instruction

PC = Address THERE TOS= Address HERE+1

CLRF Clear f

Syntax: [

label

] CLRF f Operands: 0 ≤ f ≤ 127 Operation: 00h → (f)

1 → Z Status Affected: Z Encoding:

00 0001 1fff ffff

Description:

The contents of register 'f' are cleared

and the Z bit is set.

Words: 1 Cycles: 1 Example

CLRF FLAG_REG

Before Instruction

FLAG_REG = 0x5A

After Instruction

FLAG_REG = 0x00 Z = 1

CLRW Clear W

Syntax: [

label

] CLRW Operands: None Operation: 00h → (W)

1 → Z Status Affected: Z Encoding:

00 0001 0xxx xxxx

Description:

W register is cleared. Zero bit (Z) is

set.

Words: 1 Cycles: 1 Example

CLRW

Before Instruction

W = 0x5A

After Instruction

W = 0x00 Z = 1

 1997 Microchip Technology Inc. Preliminary DS30561A-page 63

PIC12C67X

CLRWDT Clear Watchdog Timer

Syntax: [

label

] CLRWDT Operands: None Operation: 00h → WDT

0 → WDT prescaler, 1 → T

1 → PD Status Affected: TO, PD Encoding:

00 0000 0110 0100

Description:

CLRWDT instruction resets the Watch-

dog Timer. It also resets the prescaler

of the WDT. Status bits TO and PD

are set.

Words: 1 Cycles: 1 Example

CLRWDT

Before Instruction

WDT counter = ?

After Instruction

WDT counter = 0x00 WDT prescaler= 0

TO = 1 PD = 1

COMF Complement f

Syntax: [

label

] COMF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: (f

) → (dest) Status Affected: Z Encoding:

00 1001 dfff ffff

Description:

The contents of register 'f' are complemented. If 'd' is 0 the result is stored in W. If 'd' is 1 the result is stored back in register 'f'.

Words: 1 Cycles: 1 Example

COMF REG1,0

Before Instruction

REG1 = 0x13

After Instruction

REG1 = 0x13 W = 0xEC

DECF Decrement f

Syntax: [

label

] DECF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: (f) - 1 → (dest) Status Affected: Z Encoding:

00 0011 dfff ffff

Description:

Decrement register 'f'. If 'd' is 0 the

result is stored in the W register. If 'd'

is 1 the result is stored back in register

'f'

. Words: 1 Cycles: 1 Example

DECF CNT, 1

Before Instruction

CNT = 0x01 Z = 0

After Instruction

CNT = 0x00 Z = 1

DECFSZ Decrement f, Skip if 0

Syntax: [

label

] DECFSZ f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: (f) - 1 → (dest); skip if result = 0 Status Affected: None Encoding:

00 1011 dfff ffff

Description:

The contents of register 'f' are decre-

mented. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'.

If the result is 0, the next instruction,

which is already fetched, is discarded. A

NOP is executed instead making it a two

cycle instruction.

Words: 1 Cycles: 1(2) Example

HERE DECFSZ CNT, 1 GOTO LOOP CONTINUE •

•

Before Instruction

PC = address HERE

After Instruction

CNT = CNT - 1 if CNT = 0, PC = address CONTINUE if CNT ≠ 0, PC = address HERE+1

PIC12C67X

DS30561A-page 64 Preliminary  1997 Microchip Technology Inc.

GOTO Unconditional Branch

Syntax: [

label

] GOTO k Operands: 0 ≤ k ≤ 2047 Operation: k → PC<10:0>

PCLATH<4:3> → PC<12:11> Status Affected: None Encoding:

10 1kkk kkkk kkkk

Description:

GOTO is an unconditional branch. The

eleven bit immediate value is loaded

into PC bits <10:0>. The upper bits of

PC are loaded from PCLATH<4:3>.

GOTO is a two cycle instruction.

Words: 1 Cycles: 2 Example

GOTO THERE

After Instruction

PC = Address THERE

INCF Increment f

Syntax: [

label

] INCF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: (f) + 1 → (dest) Status Affected: Z Encoding:

00 1010 dfff ffff

Description:

The contents of register 'f' are incre-

mented. If 'd' is 0 the result is placed

in the W register . If 'd' is 1 the result is

placed back in register 'f'.

Words: 1 Cycles: 1 Example

INCF CNT, 1

Before Instruction

CNT = 0xFF Z = 0

After Instruction

CNT = 0x00 Z = 1

INCFSZ Increment f, Skip if 0

Syntax: [

label

] INCFSZ f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: (f) + 1 → (dest), skip if result = 0 Status Affected: None Encoding:

00 1111 dfff ffff

Description:

The contents of register 'f' are incre-

mented. If 'd' is 0 the result is placed

in the W register . If 'd' is 1 the result is

placed back in register 'f'.

If the result is 0, the next instruction,

which is already fetched, is discarded.

A NOP is executed instead making it a

two cycle instruction

. Words: 1 Cycles: 1(2) Example

HERE INCFSZ CNT, 1 GOTO LOOP CONTINUE •

•

Before Instruction

PC = address HERE

After Instruction

CNT = CNT + 1 if CNT= 0, PC = address CONTINUE if CNT≠ 0, PC = address HERE +1

IORLW Inclusive OR Literal with W

Syntax: [

label

] IORLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .OR. k → (W) Status Affected: Z Encoding:

11 1000 kkkk kkkk

Description:

The contents of the W register is OR’ed with the eight bit literal 'k'. The result is placed in the W register

. Words: 1 Cycles: 1 Example

IORLW 0x35

Before Instruction

W = 0x9A

After Instruction

W = 0xBF Z = 1

 1997 Microchip Technology Inc. Preliminary DS30561A-page 65

PIC12C67X

IORWF Inclusive OR W with f

Syntax: [

label

] IORWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: (W) .OR. (f) → (dest) Status Affected: Z Encoding:

00 0100 dfff ffff

Description:

Inclusive OR the W register with regis-

ter 'f'. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'.

Words: 1 Cycles: 1 Example

IORWF RESULT, 0

Before Instruction

RESULT = 0x13 W = 0x91

After Instruction

RESULT = 0x13 W = 0x93 Z = 1

MOVLW Move Literal to W

Syntax: [

label

] MOVLW k Operands: 0 ≤ k ≤ 255 Operation: k → (W) Status Affected: None Encoding:

11 00xx kkkk kkkk

Description:

The eight bit literal 'k' is loaded into W register

. The don’t cares will assemble

as 0’s.

Words: 1 Cycles: 1 Example

MOVLW 0x5A

After Instruction

W = 0x5A

MOVF Move f

Syntax: [

label

] MOVF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: (f) → (dest) Status Affected: Z Encoding:

00 1000 dfff ffff

Description:

The contents of register f is moved to

a destination dependant upon the sta-

tus of d. If d = 0, destination is W reg-

ister. If d = 1, the destination is ﬁle

ﬁle register since status ﬂag Z is

affected.

Words: 1 Cycles: 1 Example

MOVF FSR, 0

After Instruction

W = value in FSR register Z = 1

MOVWF Move W to f

Syntax: [

label

] MOVWF f Operands: 0 ≤ f ≤ 127 Operation: (W) → (f) Status Affected: None Encoding:

00 0000 1fff ffff

Description:

Move data from W register to register 'f'

. Words: 1 Cycles: 1 Example

MOVWF OPTION

Before Instruction

OPTION = 0xFF W = 0x4F

After Instruction

OPTION = 0x4F W = 0x4F

PIC12C67X

DS30561A-page 66 Preliminary  1997 Microchip Technology Inc.

NOP No Operation

Syntax: [

label

] NOP Operands: None Operation: No operation Status Affected: None Encoding:

00 0000 0xx0 0000

Description:

No operation.

Words: 1 Cycles: 1 Example

NOP

OPTION Load Option Register

Syntax: [

label

] OPTION

Operands: None

Operation: (W) → OPTION Status Affected: None Encoding:

00 0000 0110 0010

Description:

The contents of the W register are loaded in the OPTION register. This instruction is supported for code compatibility with PIC16C5X products. Since OPTION is a readable/writable register, the user can directly address it.

Words: 1 Cycles: 1

Example

To maintain upward compatibility with future PIC12C67X products, do not use this instruction.

RETFIE Return from Interrupt

Syntax: [

label

] RETFIE Operands: None Operation: TOS → PC,

1 → GIE Status Affected: None Encoding:

00 0000 0000 1001

Description:

Return from Interrupt. Stack is POP ed

and Top of Stack (TOS) is loaded in

the PC. Interrupts are enabled by set-

ting Global Interrupt Enable bit, GIE

(INTCON<7>). This is a two cycle

instruction.

Words: 1 Cycles: 2 Example

RETFIE

After Interrupt

PC = TOS GIE = 1

RETLW Return with Literal in W

Syntax: [

label

] RETLW k Operands: 0 ≤ k ≤ 255 Operation: k → (W);

TOS → PC Status Affected: None Encoding:

11 01xx kkkk kkkk

Description:

The W register is loaded with the eight

bit literal 'k'. The program counter is

loaded from the top of the stack (the

return address). This is a two cycle

instruction.

Words: 1 Cycles: 2 Example

TABLE

CALL TABLE ;W contains table

;offset value

• ;W now has table value

•

ADDWF PC ;W = offset

RETLW k1 ;Begin table

RETLW k2 ;

•

RETLW kn ; End of table

Before Instruction

W = 0x07

After Instruction

W = value of k8

 1997 Microchip Technology Inc. Preliminary DS30561A-page 67

PIC12C67X

RETURN Return from Subroutine

Syntax: [

label

] RETURN Operands: None Operation: TOS → PC Status Affected: None Encoding:

00 0000 0000 1000

Description:

Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two cycle instruction.

Words: 1 Cycles: 2 Example

RETURN

After Interrupt

PC = TOS

RLF Rotate Left f through Carry

Syntax: [

label

] RLF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: See description below Status Affected: C Encoding:

00 1101 dfff ffff

Description:

The contents of register 'f' are rotated

one bit to the left through the Carry

Flag. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

stored back in register 'f'.

Words: 1 Cycles: 1 Example

RLF REG1,0

Before Instruction

REG1 = 1110 0110 C = 0

After Instruction

REG1 = 1110 0110 W = 1100 1100 C = 1

RRF Rotate Right f through Carry

Syntax: [

label

] RRF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: See description below Status Affected: C Encoding:

00 1100 dfff ffff

Description:

The contents of register 'f' are rotated

one bit to the right through the Carry

Flag. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'.

Words: 1 Cycles: 1 Example

RRF REG1,0

Before Instruction

REG1 = 1110 0110 C = 0

After Instruction

REG1 = 1110 0110 W = 0111 0011 C = 0

SLEEP

Syntax: [

label

] SLEEP Operands: None Operation: 00h → WDT,

0 → WDT prescaler, 1 → T

0 → PD Status Affected: TO, PD Encoding:

00 0000 0110 0011

Description:

The power-down status bit, PD is

cleared. Time-out status bit, TO is

set. Watchdog Timer and its pres-

caler are cleared.

The processor is put into SLEEP

mode with the oscillator stopped.

Words: 1 Cycles: 1 Example: SLEEP

PIC12C67X

DS30561A-page 68 Preliminary  1997 Microchip Technology Inc.

SUBLW Subtract W from Literal

Syntax: [

label

] SUBLW k Operands: 0 ≤ k ≤ 255 Operation: k - (W) → (W) Status

Affected:

C, DC, Z

Encoding: 11 110x kkkk kkkk Description:

The W register is subtracted (2’s complement method) from the eight bit literal 'k'. The result is placed in the W register.

Words: 1 Cycles: 1 Example 1: SUBLW 0x02

Before Instruction

W = 1 C = ?

After Instruction

W = 1 C = 1; result is positive

Example 2: Before Instruction

W = 2 C = ?

After Instruction

W = 0 C = 1; result is zero

Example 3: Before Instruction

W = 3 C = ?

After Instruction

W = 0xFF C = 0; result is negative

SUBWF Subtract W from f

Syntax: [

label

] SUBWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: (f) - (W) → (dest) Status

Affected:

C, DC, Z

Encoding: 00 0010 dfff ffff Description:

Subtract (2’s complement method) W reg-

ister from register 'f'. If 'd' is 0 the result is

stored in the W register. If 'd' is 1 the

result is stored back in register 'f'.

Words: 1 Cycles: 1 Example 1: SUBWF REG1,1

Before Instruction

REG1 = 3 W = 2 C = ?

After Instruction

REG1 = 1 W = 2 C = 1; result is positive

Example 2: Before Instruction

REG1 = 2 W = 2 C = ?

After Instruction

REG1 = 0 W = 2 C = 1; result is zero

Example 3: Before Instruction

REG1 = 1 W = 2 C = ?

After Instruction

REG1 = 0xFF W = 2 C = 0; result is negative

 1997 Microchip Technology Inc. Preliminary DS30561A-page 69

PIC12C67X

SWAPF Swap Nibbles in f

Syntax: [

label

] SWAPF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f<3:0>) → (dest<7:4>),

(f<7:4>) → (dest<3:0>) Status Affected: None Encoding:

1110 dfff ffff

Description:

The upper and lower nibbles of regis-

ter 'f' are exchanged. If 'd' is 0 the

result is placed in W register. If 'd' is 1

the result is placed in register 'f'.

Words: 1 Cycles: 1 Example

SWAPF REG, 0

Before Instruction

REG1 = 0xA5

After Instruction

REG1 = 0xA5 W = 0x5A

TRIS Load TRIS Register

Syntax: [

label

] TRIS f

Operands: 5 ≤ f ≤ 7

Operation: (W) → TRIS register f; Status Affected: None Encoding:

0000 0110 0fff

Description:

The instruction is supported for code

compatibility with the PIC16C5X prod-

ucts. Since TRIS registers are read-

able and writable, the user can directly

address them.

Words: 1 Cycles: 1 Example

To maintain upward compatibility with future PIC12C67X products, do not use this instruction.

XORLW Exclusive OR Literal with W

Syntax: [

label

] XORLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .XOR. k → (W) Status Affected: Z Encoding: 11 1010 kkkk kkkk Description:

The contents of the W register are XOR’ed with the eight bit literal 'k'. The result is placed in the W register.

Words: 1 Cycles: 1 Example: XORLW 0xAF

Before Instruction

W = 0xB5

After Instruction

W = 0x1A

XORWF Exclusive OR W with f

Syntax: [

label

] XORWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: (W) .XOR. (f) → (dest) Status Affected: Z Encoding:

00 0110 dfff ffff

Description:

Exclusive OR the contents of the W

result is stored in the W register. If 'd'

is 1 the result is stored back in register

'f'.

Words: 1 Cycles: 1 Example XORWF

REG 1

Before Instruction

REG = 0xAF W = 0xB5

After Instruction

REG = 0x1A W = 0xB5

PIC12C67X

DS30561A-page 70 Preliminary  1997 Microchip Technology Inc.

NOTES:

PIC12C67X

 1997 Microchip Technology Inc. Preliminary DS30561A-page 71

10.0 DEVELOPMENT SUPPORT

10.1 Development Tools

The PICmicrο microcontrollers are supported with a full range of hardware and software dev elopment tools:

• PICMASTER/PICMASTER CE Real-Time In-Circuit Emulator

• ICEPIC Low-Cost PIC16C5X and PIC16CXXX In-Circuit Emulator

• PRO MATE



II Universal Programmer

• PICSTART



Plus Entry-Level Prototype

Programmer

• PICDEM-1 Low-Cost Demonstration Board

• PICDEM-2 Low-Cost Demonstration Board

• PICDEM-3 Low-Cost Demonstration Board

• MPASM Assembler

• MPLAB SIM Software Simulator

• MPLAB-C (C Compiler)

• Fuzzy Logic Development System (

fuzzy

TECH−MP)

10.2 PICMASTER: High Performance

Universal In-Circuit Emulator with MPLAB IDE

The PICMASTER Universal In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for all microcontrollers in the PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX families. PICMASTER is supplied with the MPLAB Integrated Development Environment (IDE), which allows editing, “make” and download, and source debugging from a single environment.

Interchangeable target probes allow the system to be easily reconﬁgured for emulation of different processors. The universal architecture of the PICMASTER allows expansion to support all new Microchip microcontrollers.

The PICMASTER Emulator System has been designed as a real-time emulation system with advanced features that are generally found on more expensive development tools. The PC compatible 386 (and higher) machine platform and Microsoft Windows



3.x environment were chosen to best make these fea-

tures available to you, the end user. A CE compliant version of PICMASTER is availab le for

European Union (EU) countries.

10.3 ICEPIC: Low-Cost PIC16CXXX In-Circuit Emulator

ICEPIC is a low-cost in-circuit emulator solution for the Microchip PIC16C5X and PIC16CXXX families of 8-bit OTP microcontrollers.

ICEPIC is designed to operate on PC-compatible machines ranging from 286-AT



through Pentium based machines under Windows 3.x environment. ICEPIC features real time, non-intrusive emulation.

10.4 PRO MATE II: Universal Programmer

The PRO MATE II Universal Programmer is a full-featured programmer capable of operating in stand-alone mode as well as PC-hosted mode.

The PRO MATE II has programmable V

DD and VPP

supplies which allows it to verify programmed memory at V

DD min and VDD max for maximum reliability. It has

an LCD display for displaying error messages, keys to enter commands and a modular detachable socket assembly to support various package types. In standalone mode the PRO MATE II can read, verify or program PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX devices. It can also set conﬁguration and code-protect bits in this mode.

10.5 PICSTART Plus Entry Level

Development System

The PICSTART programmer is an easy-to-use, lowcost prototype programmer. It connects to the PC via one of the COM (RS-232) ports. MPLAB Integrated Development Environment software makes using the programmer simple and efﬁcient. PICSTART Plus is not recommended for production programming.

PICSTART Plus supports all PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX devices with up to 40 pins. Larger pin count devices such as the PIC16C923 and PIC16C924 may be supported with an adapter socket.

PIC12C67X

DS30561A-page 72 Preliminary  1997 Microchip Technology Inc.

10.6 PICDEM-1 Low-Cost PIC16/17 Demonstration Board

The PICDEM-1 is a simple board which demonstrates the capabilities of several of Microchip’s microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The users can program the sample microcontrollers provided with the PICDEM-1 board, on a PRO MATE II or PICSTART-Plus programmer, and easily test ﬁrmware. The user can also connect the PICDEM-1 board to the PICMASTER emulator and download the ﬁrmware to the emulator for testing. Additional prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). Some of the features include an RS-232 interface, a potentiometer for simulated analog input, push-button switches and eight LEDs connected to PORTB.

10.7 PICDEM-2 Low-Cost PIC16CXX Demonstration Board

The PICDEM-2 is a simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-2 board, on a PRO MATE II programmer or PICSTART-Plus, and easily test ﬁrmware. The PICMASTER emulator may also be used with the PICDEM-2 board to test ﬁrmware. Additional prototype area has been provided to the user for adding additional hardware and connecting it to the microcontroller socket(s). Some of the f eatures include a RS-232 interface, push-button switches, a potentiometer for simulated analog input, a Serial EEPROM to demonstrate usage of the I

C bus and separate headers for connec-

tion to an LCD module and a keypad.

10.8 PICDEM-3 Low-Cost PIC16CXXX Demonstration Board

The PICDEM-3 is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with a LCD Module. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-3 board, on a PRO MATE II programmer or PICSTART Plus with an adapter socket, and easily test ﬁrmware. The PICMASTER emulator may also be used with the PICDEM-3 board to test ﬁrmware. Additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). Some of the f eatures include

an RS-232 interface, push-button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external LCD module and a keypad. Also provided on the PICDEM-3 board is an LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature and day of the week. The PICDEM-3 provides an additional RS-232 interface and Windows 3.1 software for showing the demultiplex ed LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals.

10.9 MPLAB Integrated Development Environment Software

The MPLAB IDE Software brings an ease of software development previously unseen in the 8-bit microcontroller market. MPLAB is a windows based application which contains:

• A full featured editor

• Three operating modes

- editor

- emulator

- simulator

• A project manager

• Customizable tool bar and key mapping

• A status bar with project information

• Extensive on-line help

MPLAB allows you to:

• Edit your source ﬁles (either assembly or ‘C’)

• One touch assemble (or compile) and download

to PIC16/17 tools (automatically updates all project information)

• Debug using:

- source ﬁles

- absolute listing ﬁle

• Transfer data dynamically via DDE (soon to be

replaced by OLE)

• Run up to four emulators on the same PC

The ability to use MPLAB with Microchip’s simulator allows a consistent platform and the ability to easily switch from the low cost simulator to the full featured emulator with minimal retraining due to development tools.

10.10 Assembler (MPASM)

The MPASM Universal Macro Assembler is a PChosted symbolic assembler. It suppor ts all microcontroller series including the PIC12C5XX, PIC14000, PIC16C5X, PIC16CXXX, and PIC17CXX families.

MPASM offers full featured Macro capabilities, conditional assembly , and se ver al source and listing formats. It generates various object code formats to support Microchip's development tools as well as third party programmers.

MPASM allows full symbolic debugging from PICMASTER, Microchip’s Universal Emulator System.

PIC12C67X

 1997 Microchip Technology Inc. Preliminary DS30561A-page 73

MPASM has the following features to assist in developing software for speciﬁc use applications.

• Provides translation of Assembler source code to object code for all Microchip microcontrollers.

• Macro assembly capability.

• Produces all the ﬁles (Object, Listing, Symbol, and special) required for symbolic debug with Microchip’s emulator systems.

• Supports Hex (default), Decimal and Octal source and listing formats.

MPASM provides a rich directive language to support programming of the PIC16/17. Directives are helpful in making the development of your assemb le source code shorter and more maintainable.

10.11 Software Simulator (MPLAB-SIM)

The MPLAB-SIM Software Simulator allows code development in a PC host environment. It allows the user to simulate the PIC16/17 series microcontrollers on an instruction level. On any given instruction, the user may examine or modify any of the data areas or provide external stimulus to any of the pins. The input/ output radix can be set by the user and the execution can be performed in; single step , ex ecute until break, or in a trace mode.

MPLAB-SIM fully supports symbolic debugging using MPLAB-C and MPASM. The Software Simulator offers the low cost ﬂexibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool.

10.12 C Compiler (MPLAB-C)

The MPLAB-C Code Development System is a complete ‘C’ compiler and integrated development environment for Microchip’s PIC16/17 family of microcontrollers. The compiler provides powerful integration capabilities and ease of use not found with other compilers.

For easier source level debugging, the compiler provides symbol information that is compatible with the MPLAB IDE memory display.

10.13 Fuzzy Logic Development System

(

fuzzy

TECH-MP)

fuzzy

TECH-MP fuzzy logic development tool is available in two versions - a low cost introductory version, MP Explorer, for designers to gain a comprehensive working knowledge of fuzzy logic system design; and a full-featured version,

fuzzy

TECH-MP, edition for imple-

menting more complex systems. Both versions include Microchip’s

fuzzy

LAB demonstration board for hands-on experience with fuzzy logic systems implementation.

10.14 MP-DriveWay – Application Code

Generator

MP-DriveWay is an easy-to-use Windows-based Application Code Generator. With MP-DriveWay you can visually conﬁgure all the peripherals in a PIC16/17 device and, with a click of the mouse, generate all the initialization and many functional code modules in C language. The output is fully compatible with Microchip’s MPLAB-C C compiler. The code produced is highly modular and allows easy integration of your own code. MP-DriveWay is intelligent enough to maintain your code through subsequent code generation.

10.15 SEEVAL Evaluation and Programming System

The SEEVAL SEEPROM Designer’s Kit supports all Microchip 2-wire and 3-wire Serial EEPROMs. The kit includes everything necessary to read, write, erase or program special features of any Microchip SEEPROM product including Smart Serials and secure serials. The Total Endurance Disk is included to aid in tradeoff analysis and reliability calculations. The total kit can signiﬁcantly reduce time-to-market and result in an optimized system.

10.16 KEELOQ Evaluation and Programming Tools

KEELOQ evaluation and programming tools support Microchips HCS Secure Data Products. The HCS evaluation kit includes an LCD display to show changing codes, a decoder to decode transmissions, and a programming interface to program test transmitters.

PIC12C67X

DS30561A-page 74 Preliminary  1997 Microchip Technology Inc.

TABLE 10-1: DEVELOPMENT TOOLS FROM MICROCHIP

PIC12C5XX PIC14000 PIC16C5X PIC16CXXX PIC16C6X PIC16C7XX PIC16C8X PIC16C9XX PIC17C4X PIC17C75X

24CXX

25CXX

93CXX

HCS200

HCS300

HCS301

Emulator Products

PICMASTER



PICMASTER-CE

In-Circuit Emulator

✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔

Available

3Q97

ICEPIC Low-Cost

In-Circuit Emulator

✔ ✔ ✔ ✔ ✔ ✔

Software Tools

MPLAB

Integrated

Development

Environment

✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔

MPLAB C

Compiler

✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔

fuzzy

TECH



-MP

Explorer/Edition

Fuzzy Logic

Dev. Tool

✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔

MP-DriveWay

Applications

Code Generator

✔ ✔ ✔ ✔ ✔ ✔

Total Endurance

Software Model

✔

Programmers

PICSTART



Lite Ultra Low-Cost

Dev. Kit

✔ ✔ ✔ ✔

PICSTART



Plus Low-Cost

Universal Dev. Kit

✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔

PRO MATE



Universal

Programmer

✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔

KEELOQ



Programmer

✔

Demo Boards

SEEVAL



Designers Kit

✔

PICDEM-1

✔ ✔ ✔ ✔

PICDEM-2

✔ ✔

PICDEM-3

✔

KEELOQ



Evaluation Kit

✔

 1997 Microchip Technology Inc. Preliminary DS30561A-page 75

PIC12C67X

11.0 ELECTRICAL CHARACTERISTICS FOR PIC12C67X

Absolute Maximum Ratings †

Ambient temperature under bias............................................................................................................. .–40° to +125°C

Storage temperature............................................................................................................................. –65°C to +150°C

Voltage on any pin with respect to V

SS (except VDD and MCLR)...................................................–0.3V to (VDD + 0.3V)

Voltage on V

DD with respect to VSS ................................................................................................................ 0 to +7.5V

Voltage on MCLR

with respect to VSS (Note 2)..................................................................................................0 to +14V

Total power dissipation (Note 1)...........................................................................................................................700 mW

Maximum current out of V

SS pin ...........................................................................................................................200 mA

Maximum current into V

DD pin..............................................................................................................................150 mA

Input clamp current, I

IK (VI < 0 or VI > VDD).....................................................................................................................± 20 mA

Output clamp current, I

OK (VO < 0 or VO > VDD).............................................................................................................± 20 mA

Maximum output current sunk by any I/O pin..........................................................................................................25 mA

Maximum output current sourced by any I/O pin ....................................................................................................25 mA

Maximum current sunk by GPIO pins combined...................................................................................................100 mA

Maximum current sourced by GPIO pins combined..............................................................................................100 mA

Note 1: Power dissipation is calculated as follows: Pdis = V

DD x {IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOl x IOL).

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions abov e those indicated in the operation listings of this speciﬁcation is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

PIC12C67X

DS30561A-page 76 Preliminary  1997 Microchip Technology Inc.

TABLE 11-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS

AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)

OSC

PIC12C671-04 PIC12C672-04

PIC12C671-10 PIC12C672-10

PIC12LC671-04 PIC12LC672-04

PIC12C671/JW PIC12C672/JW

INTRC

VDD: 3.0V to 5.5V IDD: 5 mA max. at 5.5V IPD: 21 µA max. at 4V Freq: 4 MHz max.

VDD: 3.0V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 µA typ. at 4V Freq: 4 MHz max.

VDD: 2.5V to 5.5V IDD: 2.0 mA typ. at 2.5V IPD: 0.9 µA typ. at 2.5V Freq: 4 MHz max.

VDD: 3.0V to 5.5V IDD: 5 mA max. at 5.5V IPD: 21 µA max. at 4V Freq: 4 MHz max.

EXTRC

VDD: 3.0V to 5.5V IDD: 5 mA max. at 5.5V I

PD: 21 µA max. at 4V

Freq: 4 MHz max.

VDD: 3.0V to 5.5V IDD: 2.7 mA typ. at 5.5V I

PD: 1.5 µA typ. at 4V

Freq: 4 MHz max.

DD: 2.5V to 5.5V

IDD: 2.0 mA typ. at 2.5V I

PD: 0.9 µA typ. at 2.5V

Freq: 4 MHz max.

DD: 3.0V to 5.5V

IDD: 5 mA max. at 5.5V I

PD: 21 µA max. at 4V

Freq: 4 MHz max.

VDD: 3.0V to 5.5V IDD: 5 mA max. at 5.5V IPD: 21 µA max. at 4V Freq: 4 MHz max.

VDD: 3.0V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 µA typ. at 4V Freq: 4 MHz max.

VDD: 2.5V to 5.5V IDD: 2.0 mA typ. at 2.5V IPD: 0.9 µA typ. at 2.5V Freq: 4 MHz max.

VDD: 3.0V to 5.5V IDD: 5 mA max. at 5.5V IPD: 21 µA max. at 4V Freq: 4 MHz max.

VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V

Do not use in HS mode

VDD: 3.0V to 5.5V IDD: 13.5 mA typ. at 5.5V IDD: 30 mA max. at 5.5V IDD: 30 mA max. at 5.5V IPD: 1.5 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V Freq: 4 MHz max. Freq: 10 MHz max. Freq: 10 MHz max.

VDD: 3.0V to 5.5V IDD: 52.5 µA typ. at 32 kHz, 4.0V IPD: 0.9 µA typ. at 4.0V Freq: 200 kHz max.

Do not use in LP mode

VDD: 2.5V to 5.5V IDD: 48 µA max. at 32 kHz, 2.5V IPD: 5.0 µA max. at 2.5V Freq: 200 kHz max.

VDD: 2.5V to 5.5V

IDD: 48 µA max. at 32 kHz, 2.5V

IPD: 5.0 µA max. at 2.5V

Freq: 200 kHz max.

The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX speciﬁcations. It is recommended that the user select the device type that ensures the speciﬁcations required.

 1997 Microchip Technology Inc. Preliminary DS30561A-page 77

PIC12C67X

11.1 DC Characteristics: PIC12C671-04 (Commercial, Industrial, Extended

(5)

)

PIC12C671-10 (Commercial, Industrial, Extended

(5)

)

PIC12C672-04 (Commercial, Industrial, Extended

(5)

)

PIC12C672-10 (Commercial, Industrial, Extended

(5)

)

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise speciﬁed)

Operating temperature 0˚C ≤ T

A ≤ +70˚C (commercial)

–40˚C ≤ T

A ≤ +85˚C (industrial)

–40°C ≤ T

A ≤ +125˚C (extended)

Param.

No.

Characteristic Sym Min Typ† Max Units Conditions

D001 D001A

Supply Voltage V

DD 3.0

4.5--

5.5

5.5VV

XT, INTRC, EXTRC and LP osc conﬁguration HS osc conﬁguration

D002* RAM Data Retention

Voltage (Note 1)

DR - 1.5 - V Device in SLEEP mode

D003 V

DD start voltage to

ensure internal Poweron Reset signal

VPOR - VSS - V See section on Power-on Reset for details

D004* V

DD rise rate to ensure

internal Power-on Reset signal

SVDD 0.05 - - V/ms See section on Power-on Reset for details

D010

D010C D013

Supply Current (Note 2) I

DD -

2.7

7.7

13.5

mA mA

XT, EXTRC osc conﬁguration (PIC12C67X-04) F

OSC = 4 MHz, VDD = 5.5V (Note 4)

INTRC osc conﬁguration F

OSC = 4 MHz, VDD = 5.5V

HS osc conﬁguration (PIC12C67X-10) F

OSC = 20 MHz, VDD = 5.5V

D020 D021 D021A D021B

Power-down Current (Note 3)

PD -

5.5

1.5

µA µA µA µA

DD = 4.0V, WDT enabled, –40°C to +85°C

DD = 4.0V, WDT disabled, 0°C to +70°C

DD = 4.0V, WDT disabled, –40°C to +85°C

DD = 4.0V, WDT disabled, –40°C to +125°C

* These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: This is the limit to which V

DD can be lowered in SLEEP mode without losing RAM data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin

loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all I

DD measurements in active operation mode are:

OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to V

MCLR

= VDD; WDT enabled/disabled as speciﬁed.

3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to V

DD and VSS.

4: For EXTRC osc conﬁgurations, current through Re xt is not included. The current through the resistor can be

estimated by the formula Ir = V

DD/2Rext (mA) with Rext in kOhm.

5: Extended operating range is Advance Information for this device.

PIC12C67X

DS30561A-page 78 Preliminary  1997 Microchip Technology Inc.

11.2 DC Characteristics: PIC12LC671-04 (Commercial, Industrial) PIC12LC672-04 (Commercial, Industrial)

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise speciﬁed)

Operating temperature 0˚C ≤ TA ≤ +70˚C (commercial)

–40˚C ≤ T

A ≤ +85˚C (industrial)

Param

No.

Characteristic Sym Min Typ† Max Units Conditions

D001 Supply Voltage V

DD 2.5 - 5.5 V XT, INTRC, EXTRC and LP osc conﬁguration

(DC - 4 MHz)

D002* RAM Data Retention

Voltage (Note 1)

DR - 1.5 - V Device in SLEEP mode

D003 V

DD start voltage to

ensure internal Power-on Reset signal

POR - VSS - V See section on Power-on Reset for details

D004* V

DD rise rate to

ensure internal Power-on Reset signal

VDD 0.05 - - V/ms See section on Power-on Reset for details

D010 D010B D010A

Supply Current (Note 2)

DD -

2.0

22.5

3.8

3.8 48

mA mA

µA

XT, EXTRC osc conﬁguration F

OSC = 4 MHz, VDD = 3.0V (Note 4)

INTRC osc conﬁguration F

OSC = 4 MHz, VDD = 3.0V

LP osc conﬁguration F

OSC = 32 kHz, VDD = 3.0V, WDT disabled

D020 D021 D021A

Power-down Current (Note 3)

PD -

5.5

0.9

µA µA µA

VDD = 3.0V, WDT enabled, –40°C to +85°C V

DD = 3.0V, WDT disabled, 0°C to +70°C

DD = 3.0V, WDT disabled, –40°C to +85°C

* These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: This is the limit to which V

DD can be lowered in SLEEP mode without losing RAM data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin

loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all I

DD measurements in active operation mode are:

OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to V

MCLR

= VDD; WDT enabled/disabled as speciﬁed.

3: The pow er-down current in SLEEP mode does not depend on the oscillator type. Power-down current is mea-

sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to V

DD and VSS.

4: For EXTRC osc conﬁguration, current through Rext is not included. The current through the resistor can be

estimated by the formula Ir = V

DD/2Rext (mA) with Rext in kOhm.

 1997 Microchip Technology Inc. Preliminary DS30561A-page 79

PIC12C67X

11.3 DC Characteristics: PIC12C671-04 (Commercial, Industrial, Extended

(4)

)

PIC12C671-10 (Commercial, Industrial, Extended

(4)

)

PIC12C672-04 (Commercial, Industrial, Extended

(4)

)

PIC12C672-10 (Commercial, Industrial, Extended

(4)

) PIC12LC671-04 (Commercial, Industrial) PIC12LC672-04 (Commercial, Industrial)

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise speciﬁed)

Operating temperature 0˚C ≤ T

A ≤ +70˚C (commercial)

–40˚C ≤ T

A ≤ +85˚C (industrial)

–40°C ≤ T

A ≤ +125˚C (extended)

Operating voltage V

DD range as described in DC spec Section 11.1 and

Section 11.2.

Param

No.

Characteristic Sym Min Typ†Max Units Conditions

Input Low Voltage

I/O ports V

D030 with TTL buffer VSS - 0.5V V D031 with Schmitt Trigger buffer V

SS - 0.2VDD V

D032 MCLR

, GP2/T0CKI/AN2/INT

(in RC mode)

VSS - 0.2VDD V

D033 OSC1 (in XT, HS and LP) V

SS - 0.3VDD V Note1

Input High Voltage

I/O ports V

IH -

D040 with TTL buffer 2.0 - V

DD V 4.5 ≤ VDD ≤ 5.5V

D040A 0.8V

DD - VDD V For VDD > 5.5V or VDD < 4.5V

D041 with Schmitt Trigger buffer 0.8V

DD - VDD V For entire VDD range

D042 MCLR

, GP2/T0CKI/AN2/INT 0.8VDD - VDD V

D042A OSC1 (XT, HS and LP) 0.7V

DD - VDD V Note1

D043 OSC1 (in EXTRC mode) 0.9V

DD - VDD V

D070 GPIO weak pull-up current I

PUR 50 250 400 µA VDD = 5V, VPIN = VSS

Input Leakage Current (Notes 2, 3)

D060 I/O ports I

IL - - ±1 µA Vss ≤ VPIN ≤ VDD, Pin at hi-

impedance

D061 MCLR

, RA4/T0CKI - - ±5 µA Vss ≤ VPIN ≤ VDD

D063 OSC1 - - ±5 µA Vss ≤ VPIN ≤ VDD, XT, HS and LP

osc conﬁguration

Output Low Voltage

D080 I/O ports V

OL - - 0.6 V IOL = 8.5 mA, VDD = 4.5V,

–40°C to +85°C

D080A - - 0.6 V I

OL = 7.0 mA, VDD = 4.5V,

–40°C to +125°C

D083 OSC2/CLKOUT - - 0.6 V I

OL = 1.6 mA, VDD = 4.5V,

–40°C to +85°C

D083A - - 0.6 V I

OL = 1.2 mA, VDD = 4.5V,

–40°C to +125°C

† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: In EXTRC oscillator conﬁguration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that

the PIC12C67X be driven with external clock in RC mode.

2: The leakage current on the MCLR

pin is strongly dependent on the applied voltage lev el. The speciﬁed levels

represent normal operating conditions. Higher leakage current may be measured at different input voltages.

3: Negative current is deﬁned as coming out of the pin.

4: Extended operating range is Advance Information for this device.

PIC12C67X

DS30561A-page 80 Preliminary  1997 Microchip Technology Inc.

Output High Voltage

D090 I/O ports (Note 3) V

OH VDD - 0.7 - - V IOH = -3.0 mA, VDD = 4.5V,

–40°C to +85°C

D090A V

DD - 0.7 - - V IOH = -2.5 mA, VDD = 4.5V,

–40°C to +125°C

D092 OSC2/CLKOUT V

DD - 0.7 - - V IOH = -1.3 mA, VDD = 4.5V,

–40°C to +85°C

D092A V

DD - 0.7 - - V IOH = -1.0 mA, VDD = 4.5V,

–40°C to +125°C

Capacitive Loading Specs on Output Pins

D100 OSC2 pin C

OSC2 - - 15 pF In XT, HS and LP modes when

external clock is used to drive OSC1.

D101 All I/O pins and OSC2 C

IO - - 50 pF

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise speciﬁed)

Operating temperature 0˚C ≤ T

A ≤ +70˚C (commercial)

–40˚C ≤ T

A ≤ +85˚C (industrial)

–40°C ≤ T

A ≤ +125˚C (extended)

Operating voltage V

DD range as described in DC spec Section 11.1 and

Section 11.2.

Param

No.

Characteristic Sym Min Typ†Max Units Conditions

† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: In EXTRC oscillator conﬁguration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that

the PIC12C67X be driven with external clock in RC mode.

2: The leakage current on the MCLR

pin is strongly dependent on the applied voltage lev el. The speciﬁed levels

represent normal operating conditions. Higher leakage current may be measured at different input voltages.

3: Negative current is deﬁned as coming out of the pin.

4: Extended operating range is Advance Information for this device.

 1997 Microchip Technology Inc. Preliminary DS30561A-page 81

PIC12C67X

11.4 Timing Parameter Symbology

The timing parameter symbols have been created following one of the following formats:

FIGURE 11-1: LOAD CONDITIONS

1. TppS2ppS

3. T

CC:ST (I

C speciﬁcations only)

2. TppS

4. Ts (I

C speciﬁcations only)

F Frequency T Time Lowercase letters (pp) and their meanings:

cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T1CKI mc MCLR

wr WR

Uppercase letters and their meanings:

F Fall P Period H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-impedance

C only

AA output access High High BUF Bus free Low Low

CC:ST (I

C speciﬁcations only)

HD Hold SU Setup

DAT DATA input hold STO STOP condition STA START condition

VDD/2

Pin Pin

VSS

RL = 464Ω C

L = 50 pF for all pins except OSC2

15 pF for OSC2 output

Load condition 1

Load condition 2

PIC12C67X

DS30561A-page 82 Preliminary  1997 Microchip Technology Inc.

11.5 Timing Diagrams and Speciﬁcations FIGURE 11-2: EXTERNAL CLOCK TIMING

TABLE 11-2: CLOCK TIMING REQUIREMENTS

Parameter

No.

Sym Characteristic Min Typ† Max Units Conditions

Fos External CLKIN Frequency

(Note 1)

DC — 4 MHz XT and EXTRC osc mode DC — 4 MHz HS osc mode (PIC12C67X-04) DC — 200 kHz LP osc mode

Oscillator Frequency (Note 1)

DC — 4 MHz EXTRC osc mode

.455 — 4 MHz XT osc mode

4 — 4 MHz HS osc mode (PIC12C67X-04) 4 — 10 MHz HS osc mode (PIC12C67X-10) 5 — 200 kHz LP osc mode

1 Tosc External CLKIN Period

(Note 1)

250 — — ns XT and EXTRC osc mode 250 — — ns HS osc mode (PIC12C67X-04) 100 — — ns HS osc mode (PIC12C67X-10)

5 — — µs LP osc mode

Oscillator Period (Note 1)

250 — — ns EXTRC osc mode 250 — 10,000 ns XT osc mode 250 — 250 ns HS osc mode (PIC12C67X-04) 100 — 250 ns HS osc mode (PIC12C67X-10)

5 — — µs LP osc mode 2 TCY Instruction Cycle Time (Note 1) 200 — DC ns TCY = 4/FOSC 3 TosL,

TosH

External Clock in (OSC1) High or Low Time

50 — — ns XT oscillator

2.5 — — µs LP oscillator 10 — — ns HS oscillator

4 TosR,

TosF

External Clock in (OSC1) Rise or Fall Time

— — 25 ns XT oscillator — — 50 ns LP oscillator — — 15 ns HS oscillator

† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All speciﬁed values are based on

characterization data for that particular oscillator type under standard operating conditions with the device executing code . Exceeding these speciﬁed limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. OSC2 is disconnected (has no loading) for the PIC12C67X.

OSC1

CLKOUT

Q4 Q1 Q2 Q3 Q4 Q1

 1997 Microchip Technology Inc. Preliminary DS30561A-page 83

PIC12C67X

FIGURE 11-3: CLKOUT AND I/O TIMING

TABLE 11-3: CLKOUT AND I/O TIMING REQUIREMENTS

Parameter

No.

Sym Characteristic Min Typ† Max Units Conditions

10* TosH2ckL OSC1↑ to CLKOUT↓ — 15 30 ns Note 1 11* TosH2ckH OSC1↑ to CLKOUT↑ — 15 30 ns Note 1 12* TckR CLKOUT rise time — 5 15 ns Note 1 13* TckF CLKOUT fall time — 5 15 ns Note 1 14* TckL2ioV CLKOUT ↓ to Port out valid — — 0.5TCY + 20 ns Note 1 15* TioV2ckH Port in valid before CLKOUT ↑ 0.25TCY + 25 — — ns Note 1 16* TckH2ioI Port in hold after CLKOUT ↑ 0 — — ns Note 1 17* TosH2ioV OSC1↑ (Q1 cycle) to

Port out valid

— — 80 - 100 ns

18* TosH2ioI OSC1↑ (Q2 cycle) to

Port input invalid (I/O in hold time)

TBD — — ns

19* TioV2osH Port input valid to OSC1↑ (I/O in setup time) TBD — — ns 20* TioR Port output rise time PIC12C67X — 10 25 ns

PIC12LC67X — — 60 ns

21* TioF Port output fall time PIC12C67X — 10 25 ns

PIC12LC67X — — 60 ns 22††* Tinp INT pin high or low time 20 — — ns 23††* Trbp GPIO change INT high or low time 20 — — ns

* These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

†† These parameters are asynchronous events not related to any internal clock edges.

Note 1: Measurements are taken in EXTRC and INTRC modes where CLKOUT output is 4 x T

OSC.

Note: Refer to Figure 11-1 for load conditions.

OSC1

CLKOUT

I/O Pin (input)

I/O Pin (output)

Q2 Q3

20, 21

old value

new value

PIC12C67X

DS30561A-page 84 Preliminary  1997 Microchip Technology Inc.

FIGURE 11-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, AND POWER-UP

TIMER TIMING

TABLE 11-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER

Parameter

No.

Sym Characteristic Min Typ† Max Units Conditions

30 TmcL MCLR Pulse Width (low) 2 — — µs VDD = 5V, –40˚C to +125˚C

31* Twdt Watchdog Timer Time-out Period

(No Prescaler)

7 18 33 ms VDD = 5V, –40˚C to +125˚C

32 Tost Oscillation Start-up Timer Period — 1024TOSC — — TOSC = OSC1 period

33* Tpwrt Power up Timer Period 28 72 132 ms VDD = 5V, –40˚C to +125˚C

34 TIOZ I/O Hi-impedance from MCLR Low

or Watchdog Timer Reset

— — 2.1 µs

* These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

VDD

MCLR

Internal

POR

PWRT

Timeout

OSC

Timeout

Internal

RESET

Watchdog

Timer

RESET

I/O Pins

 1997 Microchip Technology Inc. Preliminary DS30561A-page 85

PIC12C67X

FIGURE 11-5: TIMER0 CLOCK TIMINGS

TABLE 11-5: TIMER0 CLOCK REQUIREMENTS

Param

No.

Sym Characteristic Min Typ† Max Units Conditions

Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20* — — ns

With Prescaler 10* — — ns

41 Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20* — — ns

With Prescaler 10* — — ns

42 Tt0P T0CKI Period Greater of:

20µs or TCY + 40* N

— — ns N = prescale value

(1, 2, 4,..., 256)

48 Tcke2tmrI Delay from external clock edge to timer increment 2Tosc — 7Tosc —

* These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note: Refer to Figure 11-1 for load conditions.

GP2/T0CKI

TMR0

PIC12C67X

DS30561A-page 86 Preliminary  1997 Microchip Technology Inc.

TABLE 11-6: GPIO PULL-UP RESISTOR RANGES

VDD (Volts) Temperature (°C) Min Typ Max Units

GP0/GP1

2.5 –40 50K 62K 84K kΩ 25 63K 73K 84K kΩ 85 63K 80K 84K kΩ

125 63K 81K 84K kΩ

5.5 –40 19K 22K 27K kΩ 25 25K 27K 31K kΩ 85 28K 33K 40K kΩ

125 31K 36K 43K kΩ

GP3

2.5 –40 490K 710K 965K kΩ 25 610K 890K 1.2M kΩ 85 769K 1.1M 1.5M kΩ

125 810K 1.2M 1.6M kΩ

5.5 –40 310K 410K 510K kΩ 25 360K 470K 580K kΩ 85 430K 550K 670K kΩ

125 465K 585K 715K kΩ

* These parameters are characterized but not tested.

 1997 Microchip Technology Inc. Preliminary DS30561A-page 87

PIC12C67X

TABLE 11-7: A/D CONVERTER CHARACTERISTICS:

PIC12C671-04 (COMMERCIAL, INDUSTRIAL, EXTENDED

(3)

)

PIC12C671-10 (COMMERCIAL, INDUSTRIAL, EXTENDED

(3)

)

PIC12C672-04 (COMMERCIAL, INDUSTRIAL, EXTENDED

(3)

)

PIC12C672-10 (COMMERCIAL, INDUSTRIAL, EXTENDED

(3)

)

Parameter

No.

Sym Characteristic Min Typ† Max Units Conditions

NR Resolution — — 8-bits — VREF = VDD = 5.12V, VSS ≤ AIN ≤ VREF

NINT Integral error — — less than

±1 LSb

— VREF = VDD = 5.12V, VSS ≤ AIN ≤ VREF

NDIF Differential error — — less than

±1 LSb

— VREF = VDD = 5.12V, VSS ≤ AIN ≤ VREF

NFS Full scale error — — less than

±1 LSb

— VREF = VDD = 5.12V, VSS ≤ AIN ≤ VREF

NOFF Offset error — — less than

±1 LSb

— VREF = VDD = 5.12V, VSS ≤ AIN ≤ VREF

— Monotonicity — guaranteed — — VSS ≤ AIN ≤ VREF

VREF Reference voltage 3.0V — VDD + 0.3 V

VAIN Analog input voltage VSS - 0.3 — VREF + 0.3 V ZAIN Recommended

impedance of analog voltage source

— — 10.0 kΩ

IAD A/D conversion cur-

rent (VDD)

— 180 — µA Average current consumption when

A/D is on. (Note 1)

IREF VREF input current

(Note 2)

— — 1

mAµADuring sampling

All other times

* These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes

any such leakage from the A/D module.

2: VREF current is from GP1 pin or VDD pin, whichever is selected as reference input.

3: Extended operating range is Advance Information for this device.

PIC12C67X

DS30561A-page 88 Preliminary  1997 Microchip Technology Inc.

TABLE 11-8: A/D CONVERTER CHARACTERISTICS:

PIC12LC671-04 (COMMERCIAL, INDUSTRIAL, EXTENDED

(4)

)

PIC12LC672-04 (COMMERCIAL, INDUSTRIAL, EXTENDED

(4)

)

Parameter

No.

Sym Characteristic Min Typ† Max Units Conditions

NR Resolution — — 8-bits — VREF = VDD = 3.0V (Note 1)

NINT Integral error — — less than

±1 LSb

— VREF = VDD = 3.0V (Note 1)

NDIF Differential error — — less than

±1 LSb

— VREF = VDD = 3.0V (Note 1)

NFS Full scale error — — less than

±1 LSb

— VREF = VDD = 3.0V (Note 1)

NOFF Offset error — — less than

±1 LSb

— VREF = VDD = 3.0V (Note 1)

— Monotonicity — guaranteed — — VSS ≤ AIN ≤ VREF

VREF Reference voltage 3.0V — VDD + 0.3 V

VAIN Analog input voltage VSS - 0.3 — VREF + 0.3 V ZAIN Recommended

impedance of analog voltage source

— — 10.0 kΩ

IAD A/D conversion cur-

rent (VDD)

— 90 — µA Average current consumption when

A/D is on. (Note 2)

IREF VREF input current

(Note 3)

— — 1

mAµADuring sampling

All other times

* These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: These speciﬁcations apply if V

REF = 3.0V and if VDD ≥ 3.0V. VIN must be between VSS and VREF

2: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes

any such leakage from the A/D module.

3: VREF current is from GP1 pin or VDD pin, whichever is selected as reference input.

4: Extended operating range is Advance Information for this device.

 1997 Microchip Technology Inc. Preliminary DS30561A-page 89

PIC12C67X

FIGURE 11-6: A/D CONVERSION TIMING

TABLE 11-9: A/D CONVERSION REQUIREMENTS

Parameter

No.

Sym Characteristic Min Typ† Max Units Conditions

130 TAD A/D clock period 1.6

2.0

— —

µsµsVREF ≥ 3.0V

VREF full range

130 TAD A/D Internal RC

Oscillator source

ADCS1:ADCS0 = 11 (RC oscillator source)

3.0 6.0 9.0 µs PIC12LC67X, V

DD = 3.0V

2.0 4.0 6.0 µs PIC12C67X

131 TCNV Conversion time

(not including S/H time). Note 1

— 9.5TAD — —

132 TACQ Acquisition time Note 2 20 — µs

* These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: ADRES register may be read on the following TCY cycle.

131

130

132

BSF ADCON0, GO

A/D CLK

A/D DATA

ADRES

ADIF

SAMPLE

OLD_DATA

SAMPLING STOPPED

DONE

NEW_DATA

OSC/2)

(1)

7 6 5 4 3 2 1 0

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEP instruction to be executed.

1 Tcy

PIC12C67X

DS30561A-page 90 Preliminary  1997 Microchip Technology Inc.

NOTES:

 1997 Microchip Technology Inc. Preliminary DS30561A-page 91

PIC12C67X

12.0 DC AND AC CHARACTERISTICS - PIC12C67X

The graphs and tables provided in this section are for design guidance and are not tested or guaranteed. In some graphs or tables the data presented are outside speciﬁed operating range (e.g., outside speciﬁed V

DD range). This is

for information only and devices will operate properly only within the speciﬁed range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of

time. “Typical” represents the mean of the distribution while “max” or “min” represents (mean + 3σ) and (mean – 3σ) respectively, where σ is standard deviation.

FIGURE 12-1: CALIBRATED INTERNAL RC FREQUENCY RANGE VS. TEMPERATURE (VDD = 5.0V)

(INTERNAL RC IS CALIBRATED TO 25°C, 5.0V)

FIGURE 12-2: CALIBRATED INTERNAL RC FREQUENCY RANGE VS. TEMPERATURE (V

DD = 3.0V)

(INTERNAL RC IS CALIBRATED TO 25°C, 5.0V)

Temperature (°C)

Frequency (MHz)

-40 25 85

3.7

3.95

4.2

125

3.75

3.8

3.85

3.9

4.0

4.05

4.1

4.15

Frequency (MHz)

3.6

4.1

3.7

3.8

3.9

4.0

3.5

Temperature (°C)

-40 25 85

125

PIC12C67X

DS30561A-page 92 Preliminary  1997 Microchip Technology Inc.

FIGURE 12-3: INTERNAL RC FREQUENCY VS. CALIBRATION VALUE (VDD = 5.5V)

FIGURE 12-4: INTERNAL RC FREQUENCY VS. CALIBRATION VALUE (V

DD = 3.5V)

OSCCAL Value (Hex)

Frequency (MHz)

00 10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0

3.30

4.05

4.80

3.45

3.60

3.75

3.90

4.20

4.35

4.50

4.65

+125°C

+85°C

+25°C

-40°C

00 10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0

OSCCAL Value (Hex)

Frequency (MHz)

3.30

4.05

4.80

3.45

3.60

3.75

3.90

4.20

4.35

4.50

4.65

+125°C

+85°C

+25°C

-40°C

PIC12C67X

DS30561A-page 93 Preliminary  1997 Microchip Technology Inc.

TABLE 12-1: DYNAMIC IDD (TYPICAL) - WDT ENABLED, 25°C

Oscillator Frequency VDD = 2.5V VDD = 5.5V

External RC 4 MHz 250 µA* 620 µA* Internal RC 4 MHz 420 µA 1.1 mA XT 4 MHz 251 µA 775 µA LP 32 KHz 7 µA 37 µA *Does not include current through external R&C.

FIGURE 12-5: WDT TIMER TIME-OUT

PERIOD vs. VDD

2 3 4 5 6 7

DD (Volts)

WDT period (µs)

Max +125°C

Max +85°C

Typ +25°C

MIn –40°C

PIC12C67X

DS30561A-page 94 Preliminary  1997 Microchip Technology Inc.

FIGURE 12-6: IOH vs. VOH, VDD = 2.5 V

FIGURE 12-7: IOH vs. VOH, VDD = 5.5 V

500m 1.0 1.5

VOH (Volts)

IOH (mA)

2.0 2.5

-1

-2

-3

-4

-5

-6

-7

Min +125°C

Max –40°C

Typ +25°C

Min +85°C

3.5 4.0 4.5

VOH (Volts)

IOH (mA)

5.0 5.5

-5

-10

-15

-20

-25

-30

Min +125°C

Max –40°C

Typ +25°C

Min +85°C

FIGURE 12-8: IOL vs. VOL, VDD = 2.5 V

FIGURE 12-9: IOL vs. VOL, VDD = 5.5 V

250.0m 500.0m 1.0 V

OL (Volts)

IOL (mA)

Min +85°C

Max –40°C

Typ +25°C

Min +125°C

500.0m 750.0m 1.0 V

OL (Volts)

IOL (mA)

250.0m

Min +85°C

Max –40°C

Typ +25°C

Min +125°C

 1997 Microchip Technology Inc. Preliminary DS30561A-page 95

PIC12C67X

13.0 PACKAGING INFORMATION

13.1 Package Marking Information

Legend: MM...M Microchip part number information

XX...X Customer speciﬁc information* AA Year code (last 2 digits of calendar year) BB Week code (week of January 1 is week ‘01’) C Facility code of the plant at which wafer is manufactured

C = Chandler, Arizona, U.S.A., S = Tempe, Arizona, U.S.A.

T = Tempe, Arizona, U.S.A. D Mask revision number E Assembly code of the plant or country of origin in which

part was assembled

Note: In the event the full Microchip part number cannot be marked on one line,

it will be carried over to the next line thus limiting the number of available characters for customer speciﬁc information.

* Standard OTP marking consists of Microchip part number, year code, week

code, facility code, mask rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Ofﬁce. For QTP devices, any special marking adders are included in QTP price.

MMMMMMMM XXXXXCDE

AABB

8-Lead PDIP (300 mil)

Example

8-Lead SOIC (208 mil)

MMMMMMM AABBCDE

XXXXXXX

8-Lead Windowed Ceramic Side Brazed (300 mil)

MMMMMM

Example

12C671/P 04ISAZ

9625

12C671

9624SAZ

04I/SM

12C671

PIC12C67X

DS30561A-page 96 Preliminary  1997 Microchip Technology Inc.

13.2 8-Lead Plastic Dual In-line (300 mil)

Package Group: Plastic Dual In-Line (PLA)

Symbol

Millimeters Inches

Min Max Notes Min Max Notes

α 0° 10° 0° 10°

A – 4.064 – 0.160 A1 0.381 – 0.015 – A2 3.048 3.810 0.120 0.150

B 0.355 0.559 0.014 0.022 B1 1.397 1.651 0.055 0.065

C 0.203 0.381 Typical 0.008 0.015 Typical

D 9.017 10.922 0.355 0.430

D1 7.620 7.620 Reference 0.300 0.300 Reference

E 7.620 8.255 0.300 0.325 E1 6.096 7.112 0.240 0.280 e1 2.489 2.591 Typical 0.098 0.102 Typical eA 7.620 7.620 Reference 0.300 0.300 Reference eB 7.874 9.906 0.310 0.390

L 3.048 3.556 0.120 0.140 N 8 8 8 8 S 0.889 – 0.035 –

S1 0.254 – 0.010 –

Pin No. 1 Indicator Area

Base Plane

Seating Plane

 1997 Microchip Technology Inc. Preliminary DS30561A-page 97

PIC12C67X

13.3 8-Lead Plastic Surface Mount (SOIC - Medium, 208 mil Body)

Package Group: Plastic SOIC (SM)

Symbol

Millimeters Inches

Min Max Notes Min Max Notes

α 0° 8° 0° 8°

A 1.778 2.00 0.070 0.079

A1 0.101 0.249 0.004 0.010

B 0.355 0.483 0.014 0.019 C 0.190 0.249 0.007 0.010 D 5.080 5.334 0.200 0.210 E 5.156 5.411 0.203 0.213

e 1.270 1.270 Reference 0.050 0.050 Reference

H* 7.670 8.103 0.302 0.319

h 0.381 0.762 0.015 0.030 L 0.508 1.016 0.020 0.040

N 14 14 14 14

CP – 0.102 – 0.004

Index Area

Chamfer h x 45°

h x 45°

Seating Plane

Base Plane

PIC12C67X

DS30561A-page 98 Preliminary  1997 Microchip Technology Inc.

13.4 8-Lead Ceramic Side Brazed Dual In-Line with Window (JW) (300 mil)

Package Group: Ceramic Side Brazed Dual In-Line (CER)

Symbol

Millimeters Inches

Min Max Notes Min Max Notes

α 0° 10° 0° 10° A 3.937 5.030 0.155 0.198

A1 0.635 1.143 0.025 0.045 A2 2.921 3.429 0.115 0.135 A3 1.778 2.413 0.070 0.095

B 0.406 0.508 0.016 0.020

B1 1.371 1.371 Typical 0.054 0.054 Typical

C 0.228 0.305 Typical 0.009 0.012 Typical D 13.004 13.412 0.512 0.528

D1 7.416 7.824 BSC 0.292 0.308 BSC

E 7.569 8.230 0.298 0.324

E1 7.112 7.620 0.280 0.300 e1 2.540 2.540 Typical 0.100 0.100 Typical eA 7.620 7.620 BSC 0.300 0.300 BSC eB 7.620 9.652 0.300 0.380

L 3.302 4.064 0.130 0.160 S 2.540 3.048 0.100 0.120

S1 0.127 — 0.005 —

Pin No. 1 Indicator Area

A3AA2

Base Plane

Seating Plane

 1997 Microchip Technology Inc. Preliminary DS30561A-page 99

PIC12C67X

APPENDIX A: COMPATIBILITY

To convert code written for PIC16C5X to PIC12C67X, the user should take the following steps:

1. Remove any program memory page select operations (PA2, PA1, PA0 bits) for CALL, GOTO .

2. Revisit any computed jump operations (write to PC or add to PC, etc.) to make sure page bits are set properly under the new scheme.

3. Eliminate any data memory page switching. Redeﬁne data variables to reallocate them.

4. Verify all writes to STATUS, OPTION, and FSR registers since these have changed.

5. Change reset vector to 0000h.

PIC12C67X

DS30561A-page 100 Preliminary  1997 Microchip Technology Inc.

NOTES:

Microchip Technology Inc PIC12C671-04-P, PIC12C671-04-SM, PIC12C672-04I-P, PIC12C672-04I-SM, PIC12C672-10-P Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual