3.4 PARTS LOCATION................................................................................................................... 3-36
3.5 ELECTRICAL PARTS LIST...................................................................................................... 3-38
Please use this service manual with referring to the user guide ( D.F.U. ) without fail.
SA8400
Part no. 13AK855012
2nd Issue 2003.12
ecm
Page 2
MARANTZ DESIGN AND SERVICE
Using superior design and selected high grade components,
Only original
MARANTZ
parts can insure that your
MARANTZ
MARANTZ
product will continue to perform to the specifi cations for which
company has created the ultimate in stereo sound.
it is famous.
Parts for your
MARANTZ
ORDERING PARTS :
equipment are generally available to our National Marantz Subsidiary or Agent.
Parts can be ordered either by mail or by Fax.. In both cases, the correct part number has to be specifi ed.
The following information must be supplied to eliminate delays in processing your order :
1. Complete address
2. Complete part numbers and quantities required
3. Description of parts
4. Model number for which part is required
5. Way of shipment
6. Signature : any order form or Fax. must be signed, otherwise such part order will be considered as null and void.
CAUTION : After servicing this appliance and prior to returning to customer, measure the resistance between either primary AC
cord connector pins ( with unit NOT connected to AC mains and its Power switch ON ), and the face or Front Panel of product
and controls and chassis bottom.
Any resistance measurement less than 1 Megohms should cause unit to be repaired or corrected before AC power is applied,
and verifi ed before it is return to the user/customer.
Ref. UL Standard No. 1492.
In case of diffi culties, do not hesitate to contact the Technical
Department at above mentioned address.
030307MIT
Page 3
1. TECHNICAL SPECIFICATIONS AND UPDATE DISC
Super Audio CDCD
Audio Characteristics
Analog output
Channels2channels2channels
Frequency range2Hz — 100kHz2Hz — 20kHz
Frequency characteristics2Hz — 50kHz (-3dB)2Hz — 20kHz
Dynamic range114dBMore than 100dB
THD (1kHz)0.0009%0.0020%
Wow & Flutter Precision of quartzPrecision of quartz
Output level2.2V2.2V
Update of the CPU (IC731)..............................................................................*SA8400CDR
1
Page 4
2. SERVICE HINTS AND TOOLS
SERVICE HINTS
SERVICE TOOLS
Audio signals disc4822 397 30184
Disc without errors (SBC444)+
Disc with DO errors, black spots and fingerprints (SBC444A)4822 397 30245
Disc (65 min 1kHz) without no pause4822 397 30155
Max. diameter disc (58.0 mm)4822 397 60141
Torx screwdrivers
Set (straight)4822 395 50145
Set (square)4822 395 50132
13th order filter4822 395 30204
DVD test disc (PAL)4822 397 10131
DVD test disc (NTSC) ALMEDIOTDV-540
2
Page 5
3. WARNING AND LASER SAFETY INSTRUCTIONS
GB
WARNING
All ICs and many other semi-conductors are
susceptible to electrostatic discharges (ESD).
Careless handling during repair can reduce
life drastically.
When repairing, make sure that you are
connected with the same potential as the
mass of the set via a wrist wrap with
resistance.
Keep components and tools also at this
potential.
F
ATTENTION
D
WARNUNG
I
WAARSCHUWING
AVVERTIMENTO
NL
Alle IC’s en vele andere halfgeleiders zijn
gevoelig voor elektrostatische ontladingen
(ESD).
Onzorgvuldig behandelen tijdens reparatie
kan de levensduur drastisch doen
verminderen.
Zorg ervoor dat u tijdens reparatie via een
polsband met weerstand verbonden bent met
hetzelfde potentiaal als de massa van het
apparaat.
Houd componenten en hulpmiddelen ook op
ditzelfde potentiaal.
Tous les IC et beaucoup d’autres semiconducteurs sont sensibles aux décharges
statiques (ESD).
Leur longévité pourrait être considérablement
écourtée par le fait qu’aucune précaution
n’est prise a leur manipulation.
Lors de réparations, s’assurer de bien être
relié au même potentiel que la masse de
l’appareil et enfiler le bracelet serti d’une
résistance de sécurité.
Veiller a ce que les composants ainsi que les
outils que l’on utilise soient également a ce
potentiel.
GB
Safety regulations require that the set be restored to its original condition
and that parts which are identical with those specified be used.
NL
Veiligheidsbepalingen vereisen, dat het apparaat in zijn oorspronkelijke
toestand wordt terug gebracht en dat onderdelen, identiek aan de
gespecifieerde worden toegepast.
Alle IC und viele andere Halbleiter sind
empfindlich gegen elektrostatische
Entladungen (ESD).
Unsorgfältige Behandlung bei der Reparatur
kann die Lebensdauer drastisch vermindern.
Sorgen sie dafür, das Sie im Reparaturfall
über ein Pulsarmband mit Widerstand mit
dem Massepotential des Gerätes verbunden
sind.
Halten Sie Bauteile und Hilfsmittel ebenfalls
auf diesem Potential.
D
Bei jeder Reparatur sind die geltenden Sicherheitsvorschriften zu beachten.
Der Originalzustand des Gerats darf nicht verandert werden.
Fur Reparaturen sind Original-Ersatzteile zu verwenden.
I
Le norme di sicurezza esigono che l’apparecchio venga rimesso nelle
condizioni originali e che siano utilizzati pezzi di ricambiago idetici a quelli
specificati.
Tutti IC e parecchi semi-conduttori sono
sensibili alle scariche statiche (ESD).
La loro longevita potrebbe essere fortemente
ridatta in caso di non osservazione della piu
grande cauzione alla loro manipolazione.
Durante le riparazioni occorre quindi essere
collegato allo stesso potenziale che quello
della massa dell’apparecchio tramite un
braccialetto a resistenza.
Assicurarsi che i componenti e anche gli
utensili con quali si lavora siano anche a
questo potenziale.
F
“Pour votre sécurité, ces documents
doivent être utilisés par des
spécialistes agrées, seuls habilités à
réparer votre appareil en panne.”
Les normes de sécurité exigent que l’appareil soit remis a l’état d’origine et
que soient utilisées les pièces de rechange identiques à celles spécifiées.
LASER SAFETY
This unit employs a laser. Only a qualified service person should remove the cover or attempt to service this
device, due to possible eye injury.
USE OF CONTROLS OR ADJUSTMENTS OR PERFORMANCE OF PROCEDURE OTHER THAN THOSE
SPECIFIED HEREIN MAY RESULT IN HAZARDOUS RADIATION EXPOSURE.
AVOID DIRECT EXPOSURE TO BEAM
WARNING
The use of optical instruments with this product will increase eye hazard.
Repair handling should take place as much as possible with a disc loaded inside the player
WARNING LOCATION: INSIDE ON LASER COVERSHIELD
CAUTION VISIBLE AND INVISIBLE LASER RADIATION WHEN OPEN AVOID EXPOSURE TO BEAM
ADVARSEL SYNLIG OG USYNLIG LASERSTRÅLING VED ÅBNING UNDGÅ UDS
ADVARSEL SYNLIG OG USYNLIG LASERSTRÅLING NÅR DEKSEL Å PNES UNNGÅ EKSPONERING FOR STRÅLEN
VARNING SYNLIG OCH OSYNLIG LASERSTRÅLNING NÄR DENNA DEL ÄR ÖPPNAD BETRAKTA EJ STRÅLEN
VARO! AVATT AESSA OLET ALTTIINA NÄKYVÄLLE JA NÄKYMÄTTÖMÄLLE LASER SÄTEILYLLE. ÄLÄ KATSO SÄTEESEEN
VORSICHT SICHTBARE UND UNSICHTBARE LASERSTRAHLUNG WENN ABDECKUNG GEÖFFNET NICHT DEM STRAHL AUSSETSEN
DANGER VISIBLE AND INVISIBLE LASER RADIATION WHEN OPEN AVOID DIRECT EXPOSURE TO BEAM
ATTENTION RAYONNEMENT LASER VISIBLE ET INVISIBLE EN CAS D'OUVERTURE EXPOSITION DANGEREUSE AU FAISCEAU
Æ
TTELSE FOR STRÅLING
030804ecm
3
Page 6
4. TAKING THE DISC OUT OF EMERGENCY
1. To open the stucked tray, insert a pin into the eject pinhole and push the eject lever.
2. Use a pin φ4mm or less.
This picture shows the unit upside down. The eject lever is pointed by the arrow.
The lever is thin so aim the narrow area carefully.
4
Page 7
5. UPDATE FIRMWARE
Have UPDATE DISC. (*SA8400CDR)
Attention : Don't turn off the unit until disk tray opens
automatically during the updating. When the turn off the unit
halfway, The unit can't be operated any more.
1) Press the POWER button while pressing the PLAY and OPEN/CLOSE buttons.
2) Press the OPEN/CLOSE button to open the tray, Insert
the update CD-ROM (part No.:*SA8400CDR).
3) Press the SOUND MODE and STOP buttons.
The Display indicates " VERSION UP ".
4) Press the OPEN/CLOSE button to close the tray.
The Display indicates " TOC Reading " >>> " FILE
CHECK " >>> " ERASE " >>> " WRITING ".
5) Software updating will be done automatically.
When the updating is fi nished, The disc tray opens
automatically.
(Updating takes about 1 minute.)
6) Remove the CD-ROM from the disc tray.
Update is completed, Press the POWER button to turn off the
unit.
5
Page 8
6. SERVICE MODE
The error code is indicated when a problem DISC is inserted fi rst.
Press the POWER button While pressing PLAY and OPEN/CLOSE Button
Table 4. Single Speed (16 to 50 kHz sample rates) Common Clock
Frequencies
Serial Clock - SCLK
Pin 11, Input
Function:
Clocks individual bits of serial data into the SDATA pin. The
required relationship between the Left/Right
clock, serial clock and serial data is defi ned by either the Mode
Control Byte in Control Port Mode or the
M0 - M4 pins in Hardware Mode. The options are detailed in
Figures 29-33
Left/Right Clock - LRCK
Pin 12, Input
Function:
The Left/Right clock determines which channel is currently being
input on the serial audio data input,
SDATA. The frequency of the Left/Right clock must be at the input
sample rate. Audio samples in
Left/Right sample pairs will be simultaneously output from the
digital-to-analog converter whereas
Right/Left pairs will exhibit a one sample period difference. The
required relationship between the
Left/Right clock, serial clock and serial data is defi ned by the
Mode Control Byte and the options are de-
tailed in Figures 29-33
256x384x512x768x
MCLK (MHz)
Soft Mute - MUTE
Pin 15, Input
Function:
The analog outputs will ramp to a muted state when enabled. The
ramp requires 1152 left/right clock cy-
cles in Single Speed, 2304 cycles in Double Speed and 4608
cycles in Quad Speed mode. The bias volt-
age on the outputs will be retained and MUTEC will go active at
the completion of the ramp period.
The analog outputs will ramp to a normal state when this function
transitions from the enabled to disabled
state. The ramp requires 1152 left/right clock cycles in Single
Speed, 2304 cycles in Double Speed and
4608 cycles in Quad Speed mode. The MUTEC will release
immediately on setting MUTE = 1.
The converter analog outputs will mute when enabled. The bias
voltage on the outputs will be retained
and MUTEC will go active during the mute period.
MuteDESCRIPTION
0Enabled
1Normal operation mode
Control Port / Hardware Mode Select - C/H
Pin 16, Input
Function:
Determines if the device will operate in either the Hardware Mode
or Control Port Mode.
C/H DESCRIPTION
0Hardware Mode Enabled
1Control Port Mode Enabled
Mute Control - MUTEC
Pin 17, Output
Function:
The Mute Control pin goes low during power-up initialization,
reset, muting, master clock to left/right clock
frequency ratio is incorrect or power-down. This pin is intended to
be used as a control for an external mute
circuit to prevent the clicks and pops that can occur in any single
supply system. Use of Mute Control is not
mandatory but recommended for designs requiring the absolute
minimum in extraneous clicks and pops.
Analog Ground - AGND
Pins 18 and 21, Inputs
Function:
Analog ground reference.
Differential Analog Outpus - AOUTR- , AOUTR+ and AOUTL- ,
AOUTL+
Pins 19, 20, 23 and 24, Outputs
Function:
The full scale differential analog output level is specifi ed in the
Analog Characteristics specifi cations table.
Serial Audio Data - SDATA
Pin 13, Input
Function:
Serial audio data is input on this pin. The selection of the Digital
Interface Format is determined by set-
tings of the Mode select as detailed in Figures 29-33. The data is
Analog Power - VA
Pin 22, Input
Function:
Power for the analog and reference circuits. Typically 5VDC.
18
Page 17
QD61 : CS4397
Common Mode Voltage - CMOUT
Pin 25, Output Function:
Filter connection for internal bias voltage, typically 50% of VREF.
Capacitors must be connected from CMOUT to analog ground,
as shown in Figure 6. CMOUT has a typical source impedence
of 25 kΩ and any current drawn from this pin will alter device
performance
Reference Ground - FILT-
Pin 26, Input Function:
Ground reference for the internal sampling circuits. Must be
connected to analog ground.
Reference Filter - FILT+
Pin 27, Output Function:
Positive reference for internal sampling circuits. External
capacitors are required from FILT+ to analog ground, as shown in
Figure 6. FILT+ is not intended to supply external current.
Voltage Reference Input- VREF
Pin 28, Input Function:
Analog voltage reference. Typically 5VDC.
HARDWARE MODE
Mode Select - M0, M1, M2, M3, M4
Pins 2, 3, 4, 5 and 14, Inputs Function:
The Mode Select pins determine the operational mode of the
device as detailed in Tables 9-14. The op-tions include;
Selection of the Digital Interface Format which determines the
required relationship between the Left/Right clock, serial clock
and serial data as detailed in Figures 29-33 Selection of the
standard 15 µs/50 µs digital de-emphasis fi lter response, Figure
28, which requires re-confi guration of the digital fi lter to maintain
the proper fi lter response for 32, 44.1 or 48 kHz sample rates.
Selection of the appropriate clocking mode to match the input
sample rates. Access to the Direct Stream Digital Mode Access
to the 8x Interpolation Input Mode
CONTROL PORT MODE
Address Bit 0 / Chip Select - AD0 / CS
Pin 2, Input Function:
2
In I
C mode, AD0 is a chip address bit. CS is used to enable the
control port interface in SPI mode. The device will enter the SPI
mode at anytime a high to low transition is detected on this pin.
Once the device has entered the SPI mode, it will remain until
either the part is reset or undergoes a power-down cycle.
Address Bit 1 / Control Data Input - AD1/CDIN
Pin 3, Input Function:
In I2C mode, AD1 is a chip address bit. CDIN is the control data
input line for the control port interface in SPI mode.
Serial Control Interface Clock - SCL/CCLK
Pin 4, Input Function:
In I2C mode, SCL clocks the serial control data into or from
SDA/CDOUT.
In SPI mode, CCLK clocks the serial data into AD1/CDIN and out
of SDA/CDOUT.
Serial Control Data I/O - SDA/CDOUT
Pin 5, Input/Output Function:
In I2C mode, SDA is a data input/output. CDOUT is the control
data output for the control port interface in SPI mode.
M1 - Mode Select
Pin 14, Input Function:
This pin is not used in Control Port Mode and must be terminated
to ground.
SCLK
LRCK
SDATA
MCLK
CLOCK
DIVIDER
M4
(AD0/CS)
SERIAL INTERFACE
AND FORMAT SELECT
INTERPOLATION
INTERPOLATION
HARDWARE MODE CONTROL
M3M2
(AD1/CDIN) (SCL/CCLK)
FILTER
FILTER
(CONTROL PORT)
M1
M0
(SDA/CDOUT)
SOFT MUTE
MULTI-BIT
∆Σ
MODULATOR
MULTI-BIT
∆Σ
MODULATOR
RESET MUTEC MUTE
DYNAMIC
ELEMENT
MATCHING
LOGIC
DYNAMIC
ELEMENT
MATCHING
LOGIC
DE-EMPHASIS
FILTER
SWITCHED
CAPACITOR-DAC
AND FILTER
SWITCHED
CAPACITOR-DAC
AND FILTER
VOLTAGE REFERENCE
VREFCMOUTFILT-
FILT+
AOUTL+
AOUTL-
AOUTR+
AOUTR-
1920
Page 18
11. EXPLODED VIEW AND PARTS LIST
S
U
P
E
R
A
U
D
I
O
C
D
T100
SYMBOLST YL E
5110
5126
5127
5128
5129
5150
5192
5404
5405
MARK
MATERIA L/ FINISH
(M)
STEEL /C OPPER
(U )
STEEL /BLACK
(A )
STEEL /CHROMATE
5405
3( M)
001B
017B
011B
PARTS NAME
+B .H .M .SCREW
+B .H .T APTITE SC REW W/ WASHER
+B .H .T APTITE SC REW (W /)
+B .H .T APTITE SC REW (B TYPE )
+B .H .T APTITE SC REW (W /T.L .WASHER )
+F .H .TAP TITE SCREW (B TY PE )
+P .H .M .SCR EW (M INUTE)
SPRING L OC K WASHER S
TOOT HED L OCK WASHER S
5129
3X8( M)
008B
5128
3X10( M)
003B
035Bx3
5128
3X8( M)
012B
5405
3( M)
5128
3X12( M)
x2
029B
5128
3X8( M)
020B
5128
3X10( M)
5126
3X10( M)
5128
3X8( M)
5126
3X8( M)
x4
x4
PY26
040B
x3
010B
x2
5405
3( M)
031B
5128
3X8( M)
5126
3X10( M)
002B
VX01
022B
009B
001D
030B
013B
021B
026B
PY16
016B
027B
5126
3X8( M)
007M
008M
015B
PR16
5128
3X8( M)
x2
5129
3X8( M)
1. 7X9( U)
S
U
P
E
R
A
U
D
I
O
Mecha Loader and
Mecha Traverse
Super Audio CD
PCB Module
014B
025G
032G
x2
5192
x2
C
D
L011
5405
2( M)
x2
5128
3X8( M)
x9
030G
5128
3X8( M)
x2
( 002M)
( 003M)
(006M)
5148
3X6( M)
x3
PH16
( 5110)
3X6( M)
x4
L003
( 5128)
2. 6X6( U)
x4
5129
3X8( M)
5128
3X8( M)
x9
PH26
5129
3X8( M)
x4
5110
3X6( M)
5405
3( M)
L013
/K/L ONLY
908G
024G
033G
x2
5128
3X10( M)
x4
L012
022L
002G
5128
3X8( M)
J001
925G
5126
3X8( M)
x3
L001
023G
x4
035Gx2
x2
027G
W002
5129
3X8( M)
5148
3X6( M)
x7
021L
x3
022G
001G
/F Only
5128
3X8( M) x2
5127
3X8( M)
PP16
031Gx2
/K/S ONLY
/S Only
5127
3X8( M)
x4
035G
W001
/N Only
5128
3X5( M)
920G
J608
5126
3X8( M)
901G
5110
3X8( M)
J607
2221
Page 19
POS.
NO
VERS.
COLOR
PART NO.
(FOR EUR)
DESCRIPTION
PART NO.
(MJI)
POS.
NO
VERS.
COLOR
PART NO.
(FOR EUR)
DESCRIPTION
PART NO.
(MJI)
001B GOLD 13AK248110 FRONT AL PANEL GOLD 13AK248110
001B BLACK 13AK248010 FRONT AL PANEL BLACK 13AK248010
002B GOLD 13AK105120 CHASSIS
13AK105120
FRONT MOLD PANEL GOLD
002B BLACK 13AK105020 CHASSIS
13AK105020
FRONT MOLD PANEL BLACK
003B 13AK355010 LENS ESCUTCHEON 13AK355010
011B 01AK251010 BADGE SUPER AUDIO CD LOGO 01AK251010
012B 01AK158020 WINDOW 01AK158020
015B 382K355010 LENS 382K355010
017B 24AW251010 BADGE NEW MARANTZ LOGO 24AW251010
020B GOLD 05AK270110 BUTTON POWER GOLD 05AK270110
020B BLACK 05AK270010 BUTTON POWER BLACK 05AK270010
021B GOLD 13AK270110 BUTTON 6 GOLD 13AK270110
021B BLACK 13AK270010 BUTTON 6 BLACK 13AK270010
022B GOLD 13AK270120 BUTTON 4 GOLD 13AK270120
022B BLACK 13AK270020 BUTTON 4 BLACK 13AK270020
029B GOLD 284T154250 KNOB PHONE VOLUME GOLD 284T154250
029B BLACK 284T154310 KNOB PHONE VOLUME BLACK 284T154310
030B 376K121010 LINK FOR POWER BUTTON 376K121010
040B GOLD 13AK063120 ESCUTCHEON GOLD 13AK063120
040B BLACK 13AK063020 ESCUTCHEON BLACK 13AK063020
032G 183J057010 LEG FRONT 183J057010
033G 183J057110 LEG REAR 183J057110
908G /K/L nsp BUSHING FOR MAINS CORD 450H259010
002M 13AK304010 MECHA LOADER AND
13AK304010
MECHA TRAVERSE
006M ZK13AK0020 SUPER AUDIO CD PCB MODULE ZK13AK0020
007M GOLD 13AK063110 ESCUTCHEON
13AK063110
FOR CD TRAY GOLD
007M BLACK 13AK063010 ESCUTCHEON
13AK063010
FOR CD TRAY BLACK
008M 392K063160 ESCUTCHEON
392K063160
SUPER AUDIO CD LOGO
J001 /F/N/S YJ04002550 JACK MAINS INLET TYPE HF-301 YJ04002550
J607 YT02011290 TERMINAL
PACKING
001T /F nsp USER GUIDE SA8400 /F 13AK851110
001T /K/L/S nsp USER GUIDE SA8400 /K/L/S 13AK851350
001T /N 13AK851310 USER GUIDE SA8400 /N 13AK851310
T100 ZK13AK0010 REMOTE CONTROLLER
ZK13AK0010
RC8400SA
W001 /F nsp MAINS CORD
ZC01802080
AC 125V 12A FOR F OFC
W001 /N ZC01803080 MAINS CORD
ZC01803080
AC 250V 10A CLASS2
W001 /S nsp MAINS CORD
ZC01804100
AC 250V 10A FOR UK
NOT STANDARD
SPARE PART
001S nsp PACKING CASE 13AK801010
002S nsp CUSHION L/R 02AJ809010
001D GOLD nsp LID TOP COVER GOLD 02AJ257120
001D BLACKnsp LID TOP COVER BLACK 02AJ257020
NOTE : "nsp" PART IS LISTED FOR REFERENCE ONLY, MARANTZ WILL NOT SUPPLY THESE PARTS.
23
Page 20
12. ELECTRICAL PARTS LIST
ASSIGNMENT OF COMMON PARTS CODES.
RESISTORS
R : 1) GD05 × × × 140, Carbon film fixed resistor, ±5% 1/4W
R : 2) GD05 × × × 160, Carbon film fixed resistor, ±5% 1/6W
2) On the occasion, be confirmed the common parts on
the parts list.
3) Refer to “Common Parts List” for the other common
parts (RI05, DD4, DK4).
➆
{
One-way type, Mylar ±10% 50V
Capacity value
NOTE ON SAFETY :
SymbolFire or electrical shock hazard. Only original
parts should be used to replaced any part marked with
symbol . Any other component substitution (other
than original type), may increase risk of fire or electrical
shock hazard.
Q603 HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q604 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q605 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
NOTE : "nsp" PART IS LISTED FOR REFERENCE ONLY, MARANTZ WILL NOT SUPPLY THESE PARTS.
25
Page 22
POS.
NO
VERS.
COLOR
PART NO.
(FOR EUR)
DESCRIPTION
PART NO.
(MJI)
POS.
NO
VERS.
COLOR
PART NO.
(FOR EUR)
DESCRIPTION
PART NO.
(MJI)
Q606 HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q607 HF201701H0 F.E.T. 2SK170 V RANK HF201701H0
Q608 HF100741H0 F.E.T. 2SJ74 V RANK HF100741H0
Q609 HF203691B0 F.E.T.
HF203691B0
2SK369 BL VGDS-40V PD0.4W
Q610 HF203691B0 F.E.T.
HF203691B0
2SK369 BL VGDS-40V PD0.4W
Q611 HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q612 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q613 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q614 HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q615 HF201701H0 F.E.T. 2SK170 V RANK HF201701H0
Q616 HF100741H0 F.E.T. 2SJ74 V RANK HF100741H0
Q617 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q618 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q619 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q620 HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q621 HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q622 HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q623 HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q624 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q651 HF203691B0 F.E.T.
HF203691B0
2SK369 BL VGDS-40V PD0.4W
Q652 HF203691B0 F.E.T.
HF203691B0
2SK369 BL VGDS-40V PD0.4W
Q653 HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q654 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q655 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q656 HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q657 HF201701H0 F.E.T. 2SK170 V RANK HF201701H0
Q658 HF100741H0 F.E.T. 2SJ74 V RANK HF100741H0
Q659 HF203691B0 F.E.T.
HF203691B0
2SK369 BL VGDS-40V PD0.4W
Q660 HF203691B0 F.E.T.
HF203691B0
2SK369 BL VGDS-40V PD0.4W
Q661 HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q662 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q663 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q664 HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q665 HF201701H0 F.E.T. 2SK170 V RANK HF201701H0
Q666 HF100741H0 F.E.T. 2SJ74 V RANK HF100741H0
Q667 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q668 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q669 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q670 HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q671 HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q672 HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q673 HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q674 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
Q801 HC3690521F IC REG. BA05T 5V/1A TO220 HC3690521F
Q802 HC3690521F IC REG. BA05T 5V/1A TO220 HC3690521F
Q803 HC3850509F IC REG. NJM78M05F HC3850509F
Q821 HC3891209F IC REG. NJM7812FA +12V HC3891209F
Q822 HC3890809F IC REG. NJM7808F HC3890809F
Q851 HF202461C0 F.E.T. 2SK246 GR HF202461C0
Q852 HT41415100 TRS. 2SD1415A HT41415100
Q853 HT322402A0 TRS. 2SC2240 GR OR BL HT322402A0
Q855 HF202461C0 F.E.T. 2SK246 GR HF202461C0
Q856 HT21020100 TRS. 2SB1020A HT21020100
Q857 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
QD01 HC36J3321F IC REG. BA033T 3.3V FOR
HC36J3321F
DMAINS POWER
QD21 BA20004000 DIG. TRS. DTC114TS/UN4215 10K BA20004000
QD22 BA20004000 DIG. TRS. DTC114TS/UN4215 10K BA20004000
QD23 HT109702A0 TRS. 2SA970 GR OR BL HT109702A0
QD24 HT328782A0 TRS. 2SC2878 A OR B HT328782A0
QD61 HC10008880 IC CS4397
QN61 HT328782A0 TRS. 2SC2878 A OR B HT328782A0
QN62 HT328782A0 TRS. 2SC2878 A OR B HT328782A0
QN63 HT328782A0 TRS. 2SC2878 A OR B HT328782A0
QN64 HT328782A0 TRS. 2SC2878 A OR B HT328782A0
QN66 BA20004000 DIG. TRS. DTC114TS/UN4215 10K BA20004000
QT01
QY61 HT10001000 TRS.
DUAL LOW NOISE OP-AMP
Q903 HT321201B0 TRS. 2SC2120 Y HT321201B0
Q904 HT321201B0 TRS. 2SC2120 Y HT321201B0
Q905 HT109501A0 TRS. 2SA950 GR OR R HT109501A0
Q906 HT109501A0 TRS. 2SA950 GR OR R HT109501A0
Q907 HT328782A0 TRS. 2SC2878 A OR B HT328782A0
Q908 HT328782A0 TRS. 2SC2878 A OR B HT328782A0
Q909 HT328782A0 TRS. 2SC2878 A OR B HT328782A0
Q910 HT328782A0 TRS. 2SC2878 A OR B HT328782A0
No. Terminal Name I/O A/DClassifi cationFunctionPU PD SMT
102 VREFHI/OA ADCMax Reference Voltage input for ADC.
(Internal Reference Voltage mode, it will be an output state)
103 VREFLI/OA ADCMin Reference Voltage input for ADC.
(Internal Reference Voltage mode, it will be an output state)
104 AVDD18PVDD & GNDAnalog 1.8V Power.
105 AVDD33PVDD & GNDAnalog 3.3V Power.
106 DA0 (TSCON)OA DACDA0 output. (Track Servo output)
107 DA1 (SLED)OA DACDA1 output. (Sled Servo output)
108 DA2 (FSCON)OA DACDA2 output. (Focus Servo output)
109 DA3
(SLED2_TILT
110 AVSSPVDD & GNDAnalog Ground
111 FGID SPMFG signal input.*
112 SPWM1OD SPMSpindle motor PWM output 1.
113 SPWM2OD SPMSpindle motor PWM output 2.
114 GPWM0OD General PWMMulti-purpose PWM output 0.
115 GPWM1OD General PWMMulti-purpose PWM output 1.
116 GPWM2OD General PWMMulti-purpose PWM output 2.
117 GPWM3OD General PWMMulti-purpose PWM output 3.
118 GPWM4OD General PWMMulti-purpose PWM output 4.
119 GPWM5OD General PWMMulti-purpose PWM output 5.
120 XLCASOD DRAM I/FDRAM LCAS output. (Low-Byte row address strobe output)
121 XUCASOD DRAM I/FDRAM UCAS output. (Upper-Byte row address strobe output)
122 XMOEOD DRAM I/FDRAM output enable.
123 RA11OD DRAM I/FDRAM address output terminal 11.
124 RA10OD DRAM I/FDRAM address output terminal 10.
125 DVSSPVDD & GNDDigital Ground.
126 RA9OD DRAM I/FDRAM address output terminal 9.
127 RA8OD DRAM I/FDRAM address output terminal 8.
128 RA7OD DRAM I/FDRAM address output terminal 7.
129 RA6OD DRAM I/FDRAM address output terminal 6.
130 RA5OD DRAM I/FDRAM address output terminal 5.
131 DVDD33PVDD & GNDDigital 3.3V Power. (for I/O)
132 RA4OD DRAM I/FDRAM address output terminal 4.
133 RA3OD DRAM I/FDRAM address output terminal 3.
134 RA2OD DRAM I/FDRAM address output terminal 2.
135 RA1OD DRAM I/FDRAM address output terminal 1.
136 DVDD18PVDD & GNDDigital 1.8V Power. (for Internal Logic power)
137 RA0OD DRAM I/FDRAM address output terminal 0.
138 XRASOD DRAM I/FDRAM RAS output. (Column address strobe output)
139 XMWROD DRAM I/FDRAM Write enable.
140 RD7I/OD DRAM I/FDRAM data input/output terminal 7.*
141 RD6I/OD DRAM I/FDRAM data input/output terminal 6.*
142 DVSSPVDD & GNDDigital Ground.
143 RD5I/OD DRAM I/FDRAM data input/output terminal 5.*
144 RD4I/OD DRAM I/FDRAM data input/output terminal 4.*
145 RD3I/OD DRAM I/FDRAM data input/output terminal 3.*
146 RD2I/OD DRAM I/FDRAM data input/output terminal 2.*
147 RD1I/OD DRAM I/FDRAM data input/output terminal 1.*
148 RD0I/OD DRAM I/FDRAM data input/output terminal 0.*
149 RD15I/OD DRAM I/FDRAM data input/output terminal 15.*
150 RD14I/OD DRAM I/FDRAM data input/output terminal 14.*
151 RD13I/OD DRAM I/FDRAM data input/output terminal 13.*
152 RD12I/OD DRAM I/FDRAM data input/output terminal 12.*
153 RD11I/OD DRAM I/FDRAM data input/output terminal 11.*
154 RD10I/OD DRAM I/FDRAM data input/output terminal 10.*
155 RD9I/OD DRAM I/FDRAM data input/output terminal 9.*
156 DVDD18PVDD & GNDDigital 1.8V Power. (for internal Logic system)
157 DVDD33PVDD & GNDDigital 3.3V power for I/O.
158 RD8I/OD DRAM I/FDRAM data input/output terminal 8.*
159 TEST0OD TEST/MonitorTEST I/O 0.
160 TEST1OD TEST/MonitorTEST I/O 1.
161 TEST2OD TEST/MonitorTEST I/O 2.
162 TEST3OD TEST/MonitorTEST I/O 3.
163 TEST4OD TEST/MonitorTEST I/O 4.
OA DACDA3 output. (Sled Servo / Tilt Servo output)
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IC502 : CXD1885Q
No. Terminal Name I/O A/DClassifi cationFunctionPU PD SMT
164 TEST5OD TEST/MonitorTEST I/O 5.
165 TEST6OD TEST/MonitorTEST I/O 6.
166 TEST7OD TEST/MonitorTEST I/O 7.
167 TEST8OD TEST/MonitorTEST I/O 8.
168 TEST9OD TEST/MonitorTEST I/O 9.
169 TEST10OD TEST/MonitorTEST I/O 10.
170 TEST11OD TEST/MonitorTEST I/O 11.
171 TEST12OD TEST/MonitorTEST I/O 12.
172 TEST13OD TEST/MonitorTEST I/O 13.
173 TEST14OD TEST/MonitorTEST I/O 14.
174 TEST15OD TEST/MonitorTEST I/O 15.
175 MODSEL0ID TEST/MonitorTEST mode select 0. (GND, under normal conditions)
176 MODSEL1ID TEST/MonitorTEST mode select 1. (GND, under normal conditions)
177 DVSSPVDD & GNDDigital Ground.
178 MODSEL2ID TEST/MonitorTEST mode select 2. (GND, under normal conditions)
179 GIO0I/OD Multi-purposeMulti-purpose port 0.**
180 GIO1I/OD Multi-purposeMulti-purpose port 1.**
181 GIO2I/OD Multi-purposeMulti-purpose port 2.**
182 GIO3I/OD Multi-purposeMulti-purpose port 3.**
183 DVDD33PVDD & GNDDigital 3.3V Power for I/O.
184 GIO4I/OD General PortMulti-purpose port 4.**
185 GIO5I/OD General PortMulti-purpose port 5.**
186 GIO6I/OD General PortMulti-purpose port 6.**
187 GIO7I/OD General PortMulti-purpose port 7.**
188 DVDD18PVDD & GNDDigital 1.8V Power for I/O. (for internal Logic system)
189 GIO8I/OD General PortMulti-purpose port 8.**
190 GIO9I/OD General PortMulti-purpose port 9.***
191 GIO10I/OD General PortMulti-purpose port 10.**
192 GIO11I/OD General PortMulti-purpose port 11.**
193 GIO12I/OD General PortMulti-purpose port 12.***
194 DVSSPVDD & GNDDigital Ground.
195 GIO13I/OD Multi-purposeMulti-purpose port 13.***
196 GIO14I/OD General PortMulti-purpose port 14.***
197 GIO15I/OD General PortMulti-purpose port 15.***
198 GIO16I/OD General PortMulti-purpose port 16.**
199 GIO17I/OD General PortMulti-purpose port 17.**
200 GIO18I/OD General PortMulti-purpose port 18.**
201 GIO19I/OD General PortMulti-purpose port 19.**
202 TRSTID JTAG I/FJTAG Reset input.**
203 TMSID JTAG I/FJTAG Mode Select input.**
204 TDIID JTAG I/FJTAG Data Input.**
205 TCKID JTAG I/FJTAG Clock input.*
206 TDOOD JTAG I/FJTAG Data output.
207 VMCHGID MCU I/FVSTEM / external MCU access selection terminal of system
setting register for DSP. (L: VSTEM, H: external MCU)
208 DVDD18PVDD & GNDDigital 1.8V power for internal Logic system.
3-5
Page 33
IC401 : CXD2753R
3-6
Page 34
IC401 : CXD2753R
No. Pin NameI/O Functions
1 VSC- It fi xed to ground.( for Core)
2 XMSLATI Latch input for mCOM serial communication.
3 MSCKI Shift clock input for mCOM serial communication.
4 MSDATIIData input for mCOM serial communication.
5 VDC- +2.5V Power for Core.
6 MSDATOO Data output for mCOM serial communication. "Hi-Z" potential except the output mode.
7 MSREADYO Completion fl ag of output preparation for mCOM serial communication. "L" is outputted at the time of completion.
8 XMSDOEO Output enable pin for mCOM serial communication. "L" is outputted at the time of MSDATO mode.
9 XRSTI Reset pin. The whole IC is reset by at the time of "L" potential.
10 SMUTEIpd Soft Mute. Soft mute of the audio output is carried out at the time of "H" potential.It releases at the time of "L"
potential.
11 MCKII Master Clock input.
12 VSIO- It fi xed to Ground. Ground for I/O.
13 EXCKO1O External output Clock 1.
14 EXCKO2O External output Clock 2.
15 LRCKO 44.1kHz, 1Fs Clock output.
16 FRAMEO Frame signal output.
17 VDIO- +3.3V Power for I/O.
18 MNT0O Monitor output.
19 MNT1O Monitor output.
20 MNT2O Monitor output.
21 MNT3O Monitor output.
22 TESTOO Output terminal for a Test. (open)
23 TESTOO Output terminal for a Test.(open)
24 TESTOO Output terminal for a Test.(open)
25 TESTOO Output terminal for a Test.(open)
26 TCKI Clock input for a Test. It fi xed to "L" potential.
27 TDIIpu Input pin(pull-up) for a Test.(open)
28 VSC- It fi xed to Ground. Ground for CORE.
29 TDOO Output for a Test.(open).
30 TMSIpu Input pin(pull-up) for a Test.(open)
31 TRSTIpu Reset pin(pull-up) for a Test. Input the Power-on reset signal or fi xed to "L" potential.
32 TEST1ITest input pin. It fi xed to "L" potential.
33 TEST2ITest input pin. It fi xed to "L" potential.
34 TEST3ITest input pin. It fi xed to "L" potential.
35 VDC- +2.5V Power for CORE.
36 TESTOO Out put for TEST. It fi xed to open.
37 XBITO DST monitor.
38 SUPDT0O Supplementary data output. (LSB)
39 SUPDT1O Supplementary data output.
40 SUPDT2O Supplementary data output.
41 SUPDT3O Supplementary data output.
42 VSIO- Ground for I/O.
43 SUPDT4O Supplementary data output.
44 SUPDT5O Supplementary data output.
45 VDIO- +3.3V Power for I/O.
46 SUPDT6O Supplementary data output.
47 SUPDT7O Supplementary data output. (MSB)
48 XSUPAKO Supplementary data Acknowledge output terminal.
49 VSC- Ground for CORE.
50 TESTOO Output for TEST. (open)
51 TESTIIInput for TEST. It fi xed to "L" potential.
52 TESTIIInput for TEST. It fi xed to "L" potential.
53 TESTOO Output for TEST. (open)
54 VDC- +2.5V Power for CORE.
55 DSADMLO DSD Data output terminal for Lch Down Mix.
56 DSADMRO DSD Data output terminal for Rch Down Mix.
57 BCKASLII/O selection terminal of the Bit clock for DSD data output. L=input (Slave), H=output (Master)
58 VSDSD- Ground terminal for DSD data output.
59 BCKAIIBit clock input terminal for DSD data output. Input a Bit clock into this terminal at the time of BCKASL="L"
potential.
60 BCKAOO Bit clock output terminal for DSD data output. Bit clock output from this terminal at the time of BCKASL="H"
potential.
61 PHREFIIReference phase signal input terminal for DSD output phase modulation.
62 PHREFOO Reference phase signal output terminal for DSD output phase modulation.
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IC401 : CXD2753R
No. Pin NameI/O Functions
63 ZDFLO Lch zero-data detection fl ag (at the time of mcom setup). It will be set to "H" if non-sound data continues 300
msecs.
64 DSALO DSD data output terminal for Lch speaker.
65 ZDFRO Rch zero-data detection fl ag (at the time of mcom setup). It will be set to "H" if non-sound data continues 300
msecs.
66 DSARO DSD data output terminal for Rch speaker.
67 VDDSD- +3.3V Power for DSD data output.
68 ZDFCO Cch zero-data detection fl ag (at the time of mcom setup). It will be set to "H" if non-sound data continues 300
msecs.
69 DSACO DSD data output terminal for Cch speaker.
70 ZDFLFEO LFEch zero-data detection fl ag (at the time of mcom setup). It will be set to "H" if non-sound data continues 300
msecs.
71 DSASWO DSD data output terminal for SWch speaker.
72 VSDSD- Ground for DSD data output.
73 ZDFLSO LSch zero-data detection fl ag (at the time of mcom setup). It will be set to "H" if non-sound data continues 300
msecs.
74 DSALSO DSD data output terminal for LSch speaker.
75 ZDFRSO RSch zero-data detection fl ag (at the time of mcom setup). It will be set to "H" if non-sound data continues 300
msecs.
76 DSARSO DSD data output terminal for RSch speaker.
77 VDDSDO +3.3V Power for DSD data output.
78 IOUT0O Data output terminal 0 for IEEE1394 link chip I/F.
79 IOUT1O Data output terminal 1 for IEEE1394 link chip I/F.
80 VSC- Ground for CORE.
81 IOUT2O Data output terminal 2 for IEEE1394 link chip I/F.
82 IOUT3O Data output terminal 3 for IEEE1394 link chip I/F.
83 VDC- +2.5V Power for CORE.
84 IOUT4O Data output terminal 4 for IEEE1394 link chip I/F.
85 IOUT5O Data output terminal 5 for IEEE1394 link chip I/F.
86 VSIO- Ground for I/O.
87 IANCOO Transmission information data output terminal for IEEE1394 link chip I/F.
88 IFULLI Data transmission hold request signal input terminal for IEEE1394 link chip I/F.
89 IEMPTYI High speed transmission request signal input terminal for IEEE1394 link chip I/F.
90 VDIO- +3.3V Power for I/O.
91 IFRMO Frame reference signal output terminal for IEEE1394 link chip I/F.
92 IOUTEO Enable signal output terminal for IEEE1394 link chip I/F.
93 IBCKO Data transmission clock output terminal for IEEE1394 link chip I/F.
94 VSC- Ground for CORE.
95 TESTIITEST input terminal. It fi xed to "H" potential.
96 TESTIITEST input terminal. It fi xed to "L" potential.
97 TESTIIpu TEST input terminal. It fi xed to "H" potential.
98 TESTOO TEST output terminal. (open)
99 VDC- +2.5V Power for CORE.
100 TESTIITEST input terminal. It fi xed to "L" potential.
101 TESTIITEST input terminal. It fi xed to "L" potential.
102 TESTIITEST input terminal. It fi xed to "L" potential.
103 TESTIITEST input terminal. It fi xed to "L" potential.
104 TESTIITEST input terminal. It fi xed to "L" potential.
105 TESTIITEST input terminal. It fi xed to "L" potential.
106 VSIO- Ground for I/O.
107 TESTIITEST input terminal. It fi xed to "L" potential.
108 TESTIITEST input terminal. It fi xed to "L" potential.
109 TESTIITEST input terminal. It fi xed to "L" potential.
110 VDIO- +3.3V Power for I/O.
111 WAD0I External A/D data input terminal(LSB) for PSP physical disc mark detection.
112 WAD1I External A/D data input terminal for PSP physical disc mark detection.
113 WAD2I External A/D data input terminal for PSP physical disc mark detection.
114 WAD3I External A/D data input terminal for PSP physical disc mark detection.
115 VSIO- Ground for I/O.
116 VSC- Ground for CORE.
117 WAD4I External A/D data input terminal for PSP physical disc mark detection.
118 WAD5I External A/D data input terminal for PSP physical disc mark detection.
119 WAD6I External A/D data input terminal for PSP physical disc mark detection.
120 WAD7I External A/D data input terminal(MSB) for PSP physical disc mark detection.
121 VDC- +2.5V Power for CORE.
122 TESTIITEST input terminal. It fi xed to "L" potential.
3-8
Page 36
IC401 : CXD2753R
No. Pin NameI/O Functions
123 WCKI Operation clock for PSP physical disc mark detection.
124 WAVDD- +2.5V Power. A/D Power supply for PSP physical disc mark detection.
125 WAVDD- +2.5V Power. A/D Power supply for PSP physical disc mark detection.
126 WARFIAi Analog RF signal input terminal for PSP physical disc mark detection.
127 WAVRBAi A/D bottom reference terminal for PSP physical disc mark detection.
128 WAVSS- A/D Ground terminal for PSP physical disc mark detection.
129 WAVSS- A/D Ground terminal for PSP physical disc mark detection.
130 VSIO- Ground for I/O.
131 DQ7I/O SDRAM data input/output terminal. (MSB)
132 DQ6I/O SDRAM data input/output terminal.
133 DQ5I/O SDRAM data input/output terminal.
134 DQ4I/O SDRAM data input/output terminal.
135 VDIO- +3.3V Power for I/O.
136 DQ3I/O SDRAM data input/output terminal.
137 DQ2I/O SDRAM data input/output terminal.
138 DQ1I/O SDRAM data input/output terminal.
139 DQ0I/O SDRAM data input/output terminal. (LSB)
140 VSIO- Ground for I/O.
141 DCLKO Clock output terminal for SDRAM.
142 DCKEO Clock enable output terminal for SDRAM.
143 XWEO Write enable output terminal for SDRAM.
144 XCASO Column address strobe output terminal for SDRAM.
145 XRASO Row address strobe output terminal for SDRAM.
146 VDIO- +3.3V Power for I/O.
147 TESTOO Output terminal for TEST. (open)
148 A11O Address output terminal for SDRAM. (MSB)
149 A10O Address output terminal for SDRAM.
150 VSC- Ground for CORE.
151 A9O Address output terminal for SDRAM.
152 A8O Address output terminal for SDRAM.
153 VDC- +2.5V Power for CORE.
154 A7O Address output terminal for SDRAM.
155 A6O Address output terminal for SDRAM.
156 A5O Address output terminal for SDRAM.
157 A4O Address output terminal for SDRAM.
158 VSIO- Ground for I/O.
159 A3O Address output terminal for SDRAM.
160 A2O Address output terminal for SDRAM.
161 A1O Address output terminal for SDRAM.
162 A0O Address output terminal for SDRAM. (LSB)
163 VDIO- +3.3V Power for I/O.
164 XSRQO Output terminal of the Data Request signal inputted a front-end processor.
165 XSHDIInput terminal of the header Flag outputted from a front-end processor.
166 SDCKIInput terminal of the data conveyance Clock outputted from a front-end processor.
167 XASKI Input terminal of the data valid Flag outputted from a front-end processor.
168 SDEFI Input terminal of the error Flag outputted from a front-end processor.
169 SD0IInput terminal of the stream Data outputted from a front-end processor.
170 SD1IInput terminal of the stream Data outputted from a front-end processor.
171 SD2IInput terminal of the stream Data outputted from a front-end processor.
172 SD3IInput terminal of the stream Data outputted from a front-end processor.
173 SD4IInput terminal of the stream Data outputted from a front-end processor.
174 SD5IInput terminal of the stream Data outputted from a front-end processor.
175 SD6IInput terminal of the stream Data outputted from a front-end processor.
176 SD7IInput terminal of the stream Data outputted from a front-end processor.
Ipu: Pull-up input Ipd: Pull-down input Ai: Analog input
(USER1:H/USER2:H)
1 P94/DA1/TB4INP94OH MULT_LED MULTI SURROUND(LED L=ON)
2 P93/DA0/TB3INP93OH DSCS1CHIP SELECT for FRONT DAC
3 P92/TB2IN/SOUT3 SOUT3OH DSDOCONTOROL SERIAL DATA for ALL
DAC
4 P91/TB1IN/SIN3P91IUSER1MODEL SELECT 1 H
5 P90/TB0IN/CLK3CLK3OH DSCLKDATA CLOCK for ALL DACCS4379 control data
6 BYTEBYTEIBYTEPULL UP(8bit)
7 CNVssCNVssICNVSSPULL DOWN 5.6k ohm)
8 P87/XCINP87OH DSCS2CHIP SELECT for SURROUND DACCS4379 SURROUND
9 P86/XCOUTP86OHDSCS3CHIP SELECT for DXP7001 DAC or
DISPLAY OFF
10 RESET~RESET~IRESETRESET INPUT
11 XOUTXOUTOX.TALOSC OUT
12 VSSVSS-VSSGND
13 XINXINIX.TALOSC IN
14 VCCVCC-3.3VPOWER INPUT
15 P85/NMI~P85IP_UP110K PULL UP(NON CONECT)NOT USE
16 P84/INT2~INT2~I/OIR_INIR INPUT SIGNAL(Ma:RC-5/
De:SHARP FORMAT)
17 P83/INT1~INT1~IMINTINT from CXD1885Q
18 P82/INT0~INT0~IDRVIRQCXD1885Q DATA REQUEST
SIGNAL(384fs/192fs)
20 P80/TA4OUT/UTA4OUT OLPWMTRAY CONTROL PWM SIGNAL
21 P77/TA3INP77OHSELDSDSELECT for DSD SIGNAL(PLD)
22 P76/TA3OUTP76OH SMUTEMUTING for CXD2753R
23 P75/TA2IN/W~P75OH DSDRSTRESET for CXD2753R
24 P74/TA2OUT/WP74IMSREADY SERIAL DATA READY from
CXD2753R
25 P73/CTS2~/RTS2~/
TA1IN/V~
26 P72/CLK2/
TA1OUT/V
27 P71/RXD2/SCL/
TA0IN/TB5IN
28 P70/TXD2/SDA/
TA0OUT
29 P67/TXD1P67OH CD_LEDFOR CD SELECT (LED L:ON)Flash(w:pull
CTS0~/CLKS1
33 P63/TXD0TXD0OH DRVRXSERIAL DATA for CXD1885Q
34 P62/RXD0RXD0IDRVTXSERIAL DATA from CXD1885Q
35 P61/CLK0CLK0OH DRVCLKDATA CLOCK for CXD1885Q
36 P60/CTS0~/RTS0~ CTS0~IDRVRDYDATA READY SIGNAL from
37 P57/RDY~/CLKOUT RDY~IMRDYREADY from CXD1885Q
38 P56/ALEP56IOPEN1OPEN(anytime)Flash (w:pull
39 P55/HOLD~P55IP_UP210K PULL UP(NON CONECT)Flash
40 P54/HLDA~P54-OPEN2OPEN
41 P53/BCLKP53-OPEN3OPEN
42 P52/RD~RD~OMRDREAD STROBE for XD1885Q
43 P51/WRH~/BHE~P51-OPEN4OPEN
44 P50/WRL~/WR~WR~OMWRWRITE STROBE for XD1885QFlash(w:pull
45 P47/CS3~CS3~OH MCSCHIP SELECT for CXD1885Q
46 P46/CS2~CS2~OH MCS2CHIP SELECT for 1M-SRAM
47 P45/CS1~P45OHOPN_DRV TRAY OPEN DRIVE CONTROL
48 P44/CS0~P44OHCLS_DRVTRAY CLOSE DRIVE CONTROL
49 P43/A19P43OOPEN4OPEN
50 P42/A18P42OOPEN5OPEN
51 P41/A17P41OOPEN5OPEN
52 P40/A16A16OA16ADRRES LINE
53 P37/A15A15OA15ADRRES LINE
54 P36/A14A14OA14ADRRES LINE
55 P35/A13A13OA13ADRRES LINE
56 P34/A12A12OA12ADRRES LINE
57 P33/A11A11OA11ADRRES LINE
58 P32/A10A10OA10ADRRES LINE
59 P31/A9A9OA9ADRRES LINE
60 VCCVCC----3.3V
61 P30/A8(/?/D7)A8OA8ADRRES LINE
62 VSSVSS----GND
63 P27/A7(/D7/D6)A7OA7ADRRES LINE
64 P26/A6(/D6/D5)A6OA6ADRRES LINE
65 P25/A5(/D5/D4)A5OA5ADRRES LINE
66 P24/A4(/D4/D3)A4OA4ADRRES LINE
67 P23/A3(/D3/D2)A3OA3ADRRES LINE
68 P22/A2(/D2/D1)A2OA2ADRRES LINE
69 P21/A1(/D1/D0)A1OA1ADRRES LINE
P73OH XMSLATSERIAL DATA LATCH for CXD2753R
CLK2OH MSCKSERIAL DATA CLK for CXD2753R
RXD2IMSDATAOSERIAL DATA INPUT from CXD2753R PULL UP
TXD2OH MSDATISERIAL DATA OUTPUT for
CXD2753R
P64OH DRVRSTRESET for CXD1885Q(RESET=L)Flash(w:pull
(USER1:H/USER2:H)
70 P20/A0(/D0/?)A0OA0ADRRES LINE
71 P17/D15/INT5~P17OHICLKIIC CLK FOR EE_ROM(AT24C04N)
72 P16/D14/INT4~P16I/OH IDATIIC DATA FOR EE_ROM(AT24C04N)
73 P15/D13/INT3~P15IOPN_SWTRAY OPEN DETECT SW
74 P14/D12P14ICLS_SWTRAY CLOSE DETECT SW
75 P13/D11P13OH PCMRSTDE:RESET for DXP7001 or
Ma:DISPLAY LED(L:ON)
76 P12/D10P12IFILTISACD: DAC SYSTEM CLK
SWITCHING CONTOROL IN
77 P11/D9P11OH MUT2MUTING for MULTI
CHANNEL(H:MUTE)
78 P10/D8P10OH MUT1MUTING for STEREO
CHANNEL(H:MUTE)
79 P07/D7D7I/OD78bit DATA LINE
80 P06/D6D6I/OD68bit DATA LINE
81 P05/D5D5I/OD58bit DATA LINE
82 P04/D4D4I/OD48bit DATA LINE
83 P03/D3D3I/OD38bit DATA LINE
84 P02/D2D2I/OD28bit DATA LINE
85 P01/D1D1I/OD18bit DATA LINE
86 P00/D0D0I/OD08bit DATA LINE
87 P107/AN7/KI3~P107OH MODECD/SACD SWITCHING
SIGNAL(L:CD,SACD:H)
88 P106/AN6/KI2~P106OL FCSDISPLAY CHIP SERECT for FL
DRIVER
89 P105/AN5/KI1~P105OH DSRST2DSP RESET2 for SURROUND
CHANNEL or ATT
90 P104/AN4/KI0~P104OH DSRST1DSP RESET1 for FRONT CHANNELRESET for DAC
91 P103/AN3P103OLFRRSTDISPLAY DRIVER RESETML9207-01GP reset
92 P102/AN2AN2IKEY2KEYS SENS
93 P101/AN1AN1IKEY1KEYS SENS
94 AVSSAVSS-GNDAD GND
95 P100/AN0AN0IKEY0KEYS SENS
96 VRefVrefI3.3VAD reference
97 AVccAVcc-3.3VAD Vcc
98 P97/ADTRG~/SIN4 P97IUSER2MODEL SELECT 2H
99 P96/ANEX1/SOUT4 SOUT4OL FDATDISPLAY DATA for FL DRIVERML9207-01GP control
100 P95/ANEX0/CLK4CLK4OLFCLKDISPLAY CLOCK for FL DRIVERML9207-01GP control
Flash(w:pull
up)
(Low:384fs/
Hi:192fs)
RELAY/TR
RELAY/TR
RESET for
DXP7001(reset=L)
for FILTER-SW
Switching of digital
audio data for SACD
and CD(L=CD,
H=SACD)
Data transwission
hold to recognition of
the next DISC
ML9207-01GP chip
select
Mute signal fo Search
(reset=L)
data
clock
3-12
Page 40
IC501 : CDX1881AR
SDEN
SDATASCLK
V33
LCP
LCN
MNTRCEFE
TE
PI
V25
V125
TPH
DFT
LINK
33343536373839404142434445464748
RX
MEV
VNA
FNN
FNP
DIP
DIN
BYP
RFAC
VPA
AIP
AIN
ATO N
ATO P
RFSIN
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
CXD1881AR
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
MEVO
MIN
MLPF
MB
MP
MIRR
LDON
VNB
CDPD
DVDPD
COLD
DVDLD
VC
VPB
CD_E
RFDC
64
123456789
A2
B2
C2
D2
CP
CN
DVDRFP
DVDRFN
CD_F
17
10
111213141516
B
D
C
A
CD_B
CD_D
CD_C
CD_A
3-13
Page 41
IC501 : CDX1881AR
1
DVDRFP
DVDRFN
RFSIN
CD_A
CD_B
CD_C
CD_D
CD_E
CD_F
DVDPD
CDPD
MUX
2
63
SIGR b3
INPUT
SEL
A
12
16
B
11
15
MUX
C
10
14
D
9
13
PDCR b3
CD/DVD
18
17
RFCR b2-0
12dB is added
@ high gain mode
(CDR b5=1)
A2
3
B2
4
C2
5
D2
6
RFCR b2-0
CDR b4
LD H/L
23
24
2
RFCR b7-6
INPUT IMP
SEL
A
B
C
D
6dB is added
@ high gain mode
(CDR b5=1)
GCA
GCA
3
GCA
EQ
GCA
EQ
GCA
EQ
GCA
EQ
3
TRCR2 b6-4
DPD EQ
CCR b5
APC SEL
DVD/CD
26
LDON
ATT
SIGR b7-4
ATT
W/LPF
GCA
W/LPF
GCA
W/LPF
GCA
W/LPF
GCA
SIGR b2-0
12dB is added
@ high gain mode
(CDR b5=1)
GCA
GCA
GCA
GCA
4D
SUM
3
Dual APC
22
ATO P
ATO N
62 61 60 59
4
3
SIGR b2-0
12dB is added
@ high gain mode
(CDR b5=1)
+/-4dB
GCA
TRCR2 b3-0
Comp.
VC
TRCR b6
DPD COMP HYS ON
AGCO
21
CDLD
DVDLD
AIN
4
3B
Btm Env
50
MEV
AIP
INPUT
BIAS
RFCR b5-4
INPUT IMP SEL
SSOUT
CAR b1-0
Env/Clamp
B+D
SUM
Amp.
A+C
A+D
B+C
RESUM
PHASE
DETECTOR
PHASE
DETECTOR
BENV
Pll
AGC BTM ENV
MUX
32
MEVO
2
2
31
FCCR b7-0
FBCR b6-0
AGC
TENV
TOPHLD
TOPHLD
CDR b5
High Gain
CTCR b5-4
MEVO SEL
MUX
Btm clamp
& clip
MIN
Clamp
& Env
+3dB
2
CAR b3-2
SIGDET
GCA +/-4dB
FNP
53 52
PROGRAMMABLE
EQUALIZER
FILTER
DIFFERENTIATOR
AGCO
2
Level
DAC
4
FOCR b7-4
FS Gain
70kHz
LPF
CER b4-0
CE offset
CFR b2-0
CE-ATT
CFR b3
CEPOL
PDCR b3
CD/DVD
MRCR b6-4
MRCR b7-0
droop rate
control
Mirr Comp
ATT Level
TOP HLD
TOP ENV
BTM HLD
BTM ENV
28
DIN
FNN
DIP
55 5457
FULL WAVE
RECTIFIER
CCR b4-0
FE offset
70kHz+/-6dB, 4bit
LPFGCA
PIOR b4-0
5
PI offset
Offset
cancel
CTCR b7
BCA DET
CBR b3-2
Buff
CGR b0
CO Gain
0-+8dB, 4bit
OUTPUT INHIBIT
4
GCA
Offset
cancel
CTCR b3-0
4
LPF
3
ATT
Pol sel.
buff (Ð12dB)
SUBMUX
LPFGCA
TRCR2 b7
CP/CN
Low lmp
CHR b7-6
Mirr Defect
Comp ATT
2
for PI output ref.
CONTROL
Signals
To each block
CEFDB
3
ATT
MUX
ATT
MUX
Offset
GCA
Vref
CGR b5-4
Gain
CDR b7
LINKEN
30
MB29MP
MLPF
RFAC
CGR b1
OUTPUT INHIBIT
AGC
CHARGE
PUMP
5
Offset
cancel
FOCR b3-0
TOPHLD
DAC
2
Offset
cancel
6
TRCR b5-0
TR offset
V25/3
VCI for servo input
SERIAL PORT
REGISTER
MUXMUX
LINK
AGC HOLD
RFCR b3
4
FO Gain
COMP
PI
FE
TE
CE
V25
V125
V25/3
PIOR b7-5
3
CFR b7-5
TR Gain
for TE, FE & CE output ref.
V25/2
VC
V33 for output buff
CCR b7
DISK DET
27
58
19
VPA
VPB
MIRR
HOLDEN
CDR b6
Pll
SEL
2
CBR b1-0
SEL
2
CAR b7-4
TE MASK SEL
MON
SEL
3
TE
RST
CDR b2
CDR b3
2533
VNA51VNB
56
BYP
49
RX
40
FE
38
PI
35
TPH
34
DFT
61
RFDC
41
CE
42
MNTR
44
LCP
43
LCN
7
CP
8
CN
39
TE
36
V125
37
V25
20
VC
48
SDEN
47
SD ATA
46
SCLK
45
V33
3-14
Page 42
IC501 : CDX1881AR
Power Supply Pins
NameI/O Function
VPA-Power for RF and serial port
VPB-Power for servo
VNA- GND for RF and serial port
VNB- GND for servo
V33- Power for output buffer
V25- Reference Power for servo output
Input Pins
NameI/O Function
DVDRFP, DVDRFNIRF signal input
RFSINIRF signal input
AIP,AINIAGC amp. input
DIP,DINIAnalog input for RF single buffer
A,B,C,DIPhoto detector interface input
A2, B2, C2, D2I Photo detector interface input
CD_A, B, C, DICD photo detector interface input
CD_E, FICD photo detector interface input
MINI RF signal input for mirror
DVDPDIAPC input
CDPDIAPC input
LDONI APC input ON/OFF (L:Open)
I Link signal input (L:Open)
O Mirror monitor output
Output Pins
NameI/O Function
ATOP,ATONODifferential attenuator output
FNP,FNNODifferential normal output
RFACOSingle end normal output
RFDCORF signal output
FEOFocus error signal output
TEOTracking error signal output
CEOCenter error signal output
MEVOORFDDC bottom envelope output
DFTODefect output
MIRROMirror detected output
PIOPull-in signal output
DVDLDOAPC output
CDLDOAPC output
MNTROMonitor output
Analog Pins
NameI/O Function
BYP-RF AGC integration capacitor connecting terminal
CP-Differential phase tracking LPF terminal
CN- Differential phase tracking LPF terminal
LCP- Lens shift offset cancel LPF terminal
LCN-Lens shift offset cancel LPF terminal
MP-MIRR top hold terminal
MB-MIRR bottom hold terminal
MEV- RFDC bottom envelope terminal
MLPF- Mirror LPF terminal
TPH-PI top hold terminal
VC-Reference voltage output
V125-Reference voltage output
RX-Reference resistor input
Serial Port Pins
NameI/O Function
SDENISerial data enable
SDATA I/O Serial data
SCLKISerial clock
3-15
Page 43
IC402 : 16M SDRAM (EM636165TS-7 etc)
15
SS
V
DQ14DQ
48
49
50
123456789
1
0
DD
DQ
V
DQ
SSQ
V
47
SSQ
V
12
DQ13DQ
45
46
2
3
DQ
DQ
10DQ11
DDQ
V
DQ
4241403938373635343332313029282726
43
44
4
5
DDQ
DQ
DQ
V
8
SSQ
V
1011121314151617181920
SSQ
V
DQ9DQ
6
DQ7DQ
DDQ
V
DDQ
V
UDQM
N.C/RFU
WE
LDQM
CLK
CAS
CKE
RAS
N.C
CS
9
A
BA
A8A7A6A5A
21
A0A
/AP
10
A
SS
4
V
23
25
24
22
1
2
3
A
A
DD
V
Terminal Function
Pin NameFunctionPin No.Symbol
1VDDPower Supply/GroundPower and ground for the input buffer and the core logic
2DQ0Data Input/OutputData input/output are mutiplexed on the same pin
3DQ1Data Input/OutputData input/output are mutiplexed on the same pin
4VSSQData Output Power/GroundIsolated power supply and ground for the output buffer
5DQ2Data Input/OutputData input/output are mutiplexed on the same pin
6DQ3Data Input/OutputData input/output are mutiplexed on the same pin
7VDDQData Output Power/GroundIsolated power supply and ground for the output buffer
8DQ4Data Input/OutputData input/output are mutiplexed on the same pin
9DQ5Data Input/OutputData input/output are mutiplexed on the same pin
10VSSQData Output Power/GroundIsolated power supply and ground for the output buffer
11DQ6Data Input/OutputData input/output are multiplexed on the same pin
12DQ7Data Input/OutputData input/output are multiplexed on the same pin
13VDDQData Output Power/GroundIsolated power supply and ground for the output buffer
14L DQMData Input/Output MaskBlocks data input when active
15WEWrite EnableEnables write operation and row precharge
16CASColumn Address StrobeLatches column address on the positive going edge of the CLK at low
17RASRow Address StrobeLatches row address on the positive going edge of the CLK at low
18CSChip Select
19BABank Select AddressSelects bank to be activated during row address latch time
20A10/APAddressRow/column addresses are multiplexed on the same pin
21A0AddressRow/column addresses are multiplexed on the same pin
22A1AddressRow/column addresses are multiplexed on the same pin
23A2AddressRow/column addresses are multiplexed on the same pin
24A3AddressRow/column addresses are multiplexed on the same pin
25VDDPower Supply/GroundPower and ground for the input buffer and the core logic
26VSSPower Supply/GroundPower and ground for the input buffer and the core logic
27A4AddressRow/column addresses are multiplexed on the same pin
28A5AddressRow/column addresses are multiplexed on the same pin
29A6AddressRow/column addresses are multiplexed on the same pin
30A7AddressRow/column addresses are multiplexed on the same pin
31A8AddressRow/column addresses are multiplexed on the same pin
32A9AddressRow/column addresses are multiplexed on the same pin
33N. CNo ConnectionNo connect pin
34CKEClock EnableMasks system clock to freeze operation from the next clock cycle
35CLKSystem ClockActive on the positive going edge to sample all inputs
36U DQMData Input/Output MaskBlocks data input when active
37N. C/RFUNC/ReservedNo connect pin
38VDDQData Output Power/GroundIsolated power supply and ground for the output buffer
39DQ8Data Input/OutputData input/output are multiplexed on the same pin
40DQ9Data Input/OutputData input/output are multiplexed on the same pin
41VSSQData Output Power/GroundIsolated power supply and ground for the output buffer
42DQ10Data Input/OutputData input/output are multiplexed on the same pin
43DQ11Data Input/OutputData input/output are multiplexed on the same pin
44VDDQData Output Power/GroundIsolated power supply and ground for the output buffer
45DQ12Data Input/OutputData input/output are multiplexed on the same pin
46DQ13Data Input/OutputData input/output are multiplexed on the same pin
47VSSQData Output Power/GroundIsolated power supply and ground for the output buffer
48DQ14Data Input/OutputData input/output are multiplexed on the same pin
49DQ15Data Input/OutputData input/output are multiplexed on the same pin
50VSSPower Supply/GroundPower and ground for the input buffer and the core logic
Disables or enables device operation by masking or enabling all
inputs except CLK, CKE, and LDQM