4. PARTS LOCATION .......................................................................................................... 3-37
5. ELECTRICAL PARTS LIST .............................................................................................. 3-42
Please use this service manual with referring to the user guide ( D.F.U. ) without fail.
SA-7S1
Part no. 90M27AK855010
First Issue 2006.09
MZ
MARANTZ DESIGN AND SERVICE
Using superior design and selected high grade components,
Only original
MARANTZ
parts can insure that your
MARANTZ
MARANTZ
product will continue to perform to the specifi cations for which
company has created the ultimate in stereo sound.
it is famous.
Parts for your
MARANTZ
ORDERING PARTS :
equipment are generally available to our National Marantz Subsidiary or Agent.
Parts can be ordered either by mail or by Fax.. In both cases, the correct part number has to be specifi ed.
The following information must be supplied to eliminate delays in processing your order :
1. Complete address
2. Complete part numbers and quantities required
3. Description of parts
4. Model number for which part is required
5. Way of shipment
6. Signature : any order form or Fax. must be signed, otherwise such part order will be considered as null and void.
2ND FLOOR BANGUNAN INFINITE CENTRE
LOT 1, JALAN 13/6, 46200 PETALING JAYA
SELANGOR DARUL EHSAN, MALAYSIA
PHONE : +60 - 3 - 7954 8088
FAX:+60-3-79547088
CAUTION : After servicing this appliance and prior to returning to customer, measure the resistance between either primary AC
cord connector pins ( with unit NOT connected to AC mains and its Power switch ON ), and the face or Front Panel of product and
controls and chassis bottom.
Any resistance measurement less than 1 Megohms should cause unit to be repaired or corrected before AC power is applied, and
verifi ed before it is return to the user/customer.
Ref. UL Standard No. 6500.
In case of diffi culties, do not hesitate to contact the Technical
Department at above mentioned address.
060607MZ
1. TECHNICAL SPECIFICATIONS AND UPDATE DISC
Super Audio CDCD
Audio Characteristics
Analog output
Channels2channels2channels
Frequency range2Hz — 100kHz2Hz — 20kHz
Frequency characteristics2Hz — 50kHz (-3dB)2Hz — 20kHz
Dynamic range112dB100dB
THD (1kHz)0.0010%0.0020%
Wow & Flutter Precision of quartzPrecision of quartz
Output level2.3V RMS stereo2.3V RMS stereo
Update of the CPU (IC731) .......................................................................90M-SA11S1DVD
1-1
18
2. SERVICE HINTS AND TOOLS
SERVICE HINTS
SERVICE TOOLS
Audio signals disc4822 397 30184
Disc without errors (SBC444)+
Disc with DO errors, black spots and fingerprints (SBC444A)4822 397 30245
Disc (65 min 1kHz) without no pause4822 397 30155
Max. diameter disc (58.0 mm)4822 397 60141
Torx screwdrivers
Set (straight)4822 395 50145
Set (square)4822 395 50132
13th order filter4822 395 30204
DVD test disc (PAL)4822 397 10131
DVD test disc (NTSC) ALMEDIOTDV-540
1-2
3. WARNING AND LASER SAFETY INSTRUCTIONS
GB
WARNING
All ICs and many other semi-conductors are
susceptible to electrostatic discharges (ESD).
Careless handling during repair can reduce
life drastically.
When repairing, make sure that you are
connected with the same potential as the
mass of the set via a wrist wrap with
resistance.
Keep components and tools also at this
potential.
F
ATTENTION
D
WARNUNG
I
WAARSCHUWING
AVVERTIMENTO
NL
Alle IC’s en vele andere halfgeleiders zijn
gevoelig voor elektrostatische ontladingen
(ESD).
Onzorgvuldig behandelen tijdens reparatie
kan de levensduur drastisch doen
verminderen.
Zorg ervoor dat u tijdens reparatie via een
polsband met weerstand verbonden bent met
hetzelfde potentiaal als de massa van het
apparaat.
Houd componenten en hulpmiddelen ook op
ditzelfde potentiaal.
Tous les IC et beaucoup d’autres semiconducteurs sont sensibles aux décharges
statiques (ESD).
Leur longévité pourrait être considérablement
écourtée par le fait qu’aucune précaution
n’est prise a leur manipulation.
Lors de réparations, s’assurer de bien être
relié au même potentiel que la masse de
l’appareil et enfiler le bracelet serti d’une
résistance de sécurité.
Veiller a ce que les composants ainsi que les
outils que l’on utilise soient également a ce
potentiel.
GB
Safety regulations require that the set be restored to its original condition
and that parts which are identical with those specified be used.
NL
Veiligheidsbepalingen vereisen, dat het apparaat in zijn oorspronkelijke
toestand wordt terug gebracht en dat onderdelen, identiek aan de
gespecifieerde worden toegepast.
Alle IC und viele andere Halbleiter sind
empfindlich gegen elektrostatische
Entladungen (ESD).
Unsorgfältige Behandlung bei der Reparatur
kann die Lebensdauer drastisch vermindern.
Sorgen sie dafür, das Sie im Reparaturfall
über ein Pulsarmband mit Widerstand mit
dem Massepotential des Gerätes verbunden
sind.
Halten Sie Bauteile und Hilfsmittel ebenfalls
auf diesem Potential.
D
Bei jeder Reparatur sind die geltenden Sicherheitsvorschriften zu beachten.
Der Originalzustand des Gerats darf nicht verandert werden.
Fur Reparaturen sind Original-Ersatzteile zu verwenden.
I
Le norme di sicurezza esigono che l’apparecchio venga rimesso nelle
condizioni originali e che siano utilizzati pezzi di ricambiago idetici a quelli
specificati.
Tutti IC e parecchi semi-conduttori sono
sensibili alle scariche statiche (ESD).
La loro longevita potrebbe essere fortemente
ridatta in caso di non osservazione della piu
grande cauzione alla loro manipolazione.
Durante le riparazioni occorre quindi essere
collegato allo stesso potenziale che quello
della massa dell’apparecchio tramite un
braccialetto a resistenza.
Assicurarsi che i componenti e anche gli
utensili con quali si lavora siano anche a
questo potenziale.
F
“Pour votre sécurité, ces documents
doivent être utilisés par des
spécialistes agrées, seuls habilités à
réparer votre appareil en panne.”
Les normes de sécurité exigent que l’appareil soit remis a l’état d’origine et
que soient utilisées les pièces de rechange identiques à celles spécifiées.
LASER SAFETY
This unit employs a laser. Only a qualified service person should remove the cover or attempt to service this
device, due to possible eye injury.
USE OF CONTROLS OR ADJUSTMENTS OR PERFORMANCE OF PROCEDURE OTHER THAN THOSE
SPECIFIED HEREIN MAY RESULT IN HAZARDOUS RADIATION EXPOSURE.
AVOID DIRECT EXPOSURE TO BEAM
WARNING
The use of optical instruments with this product will increase eye hazard.
Repair handling should take place as much as possible with a disc loaded inside the player
WARNING LOCATION: INSIDE ON LASER COVERSHIELD
CAUTION VISIBLE AND INVISIBLE LASER RADIATION WHEN OPEN AVOID EXPOSURE TO BEAM
ADVARSEL SYNLIG OG USYNLIG LASERSTRÅLING VED ÅBNING UNDGÅ UDS
ADVARSEL SYNLIG OG USYNLIG LASERSTRÅLING NÅR DEKSEL Å PNES UNNGÅ EKSPONERING FOR STRÅLEN
VARNING SYNLIG OCH OSYNLIG LASERSTRÅLNING NÄR DENNA DEL ÄR ÖPPNAD BETRAKTA EJ STRÅLEN
VARO! AVATT AESSA OLET ALTTIINA NÄKYVÄLLE JA NÄKYMÄTTÖMÄLLE LASER SÄTEILYLLE. ÄLÄ KATSO SÄTEESEEN
VORSICHT SICHTBARE UND UNSICHTBARE LASERSTRAHLUNG WENN ABDECKUNG GEÖFFNET NICHT DEM STRAHL AUSSETSEN
DANGER VISIBLE AND INVISIBLE LASER RADIATION WHEN OPEN AVOID DIRECT EXPOSURE TO BEAM
ATTENTION RAYONNEMENT LASER VISIBLE ET INVISIBLE EN CAS D'OUVERTURE EXPOSITION DANGEREUSE AU FAISCEAU
1-3
Æ
TTELSE FOR STRÅLING
030804ecm
4. TAKING THE DISC OUT OF EMERGENCY
Push the Eject Lever, Disc tray is opened and Disc is taken
out.
1. Remove 2 screws and remove a side panel.
2. Push the eject lever by the pin (φ6mm or less).
3. The Disc tray opens, Now you can remove the disc
Remove 2 Screws
ネジ2本をはずします
Remove a side panel
サイドパネルを取り外します
Discの取り出しは、イジェクトレバーを押すとトレーが開きデ
ィスクを取り出せます。
1. ネジ2本を外しサイドパネルを取り外します。
2. ピン(直径6mm以下)でイジェクトレバーを押します。
3. ディスクトレーが開きディスクを取り出せます。
This hole is used
この穴にピンを差し込みます
This picture shows the unit upside down. The eject lever is
pointed by the arrow.
The lever is thin so aim the narrow area carefully.
1 GND GND GND
2 TMS JTAG terminal TMS
3 MODEMode SW for SACD or CD input(H=SACD, L=CD)IOB
4 D_INVDATA INVERS for SAR & DAPC(H=Correct, L=Invers)IOBIO_VREF_7
5 DAPCDAPC input(SACD : Lch data, CD : PCM data)IOB
6 DARDSACD Rch DATA inputIOB
7 DALRWord CLK for CD inputIOB
8 DSDODSDO 8bit serial data signalIOBIO VREF 7
9 DSCKDSDO data clock signalIOB
10 DSRST1RESET3 for timing( DIVIDER and DSP,DAC)PCIIOB IO_IRDY
11 GND GND GND
12 VCCO3.3v Power supply pins for output drivers (subject to banking rules) VCCO
13 CXPower control for TCXO(on/off)IOBIO TRDY
14 VCCINT2.5v Power supply pins for the internal core logic.VCCINT
15 DSCS3DSDO data Chip serect signalIOB
16 CA0Select signal A for FSX Switch selecterIOBIO VREF 6
17 CB0Select signal B fot FSX Switch selecterIOB
18 SACLOSACLO(SACD data CLock output)IOB
19 SYSRSystem Reset signal & MODE enable from front sub MPUIOB
20 SAROSARO(SACD Rch data output)IOBIO_VREF_6
21 SALOSALO(SACD Lch data output)IOB
22 384F
23 M1GND(Mode pins are used to specify the configuration mode.)M1
24 GND GND GND
25 M0GND(Mode pins are used to specify the configuration mode.)M0
26 VCCO3.3v Power supply pins for output drivers (subject to banking rules) VCCO
27 M2GND(Mode pins are used to specify the configuration mode.)M2
28 NCNC
29 NCNC
30 DACLODACLO(PCM data Clock output)IOBIO VREF 5
31 UNUSED NCIOB
32 DALRODALRO(PCM data word Clock output)IOB
33 VCCINT2.5v Power supply pins for the internal core logic.VCCINT
34 DAPCODAPCO(PCM data output)IOBIO_VREF_5
35 VCCINT2.5v Power supply pins for the internal core logic.VCCINT
36 LATCHDSDO 8bit data Latch signal inputGCLKIOB GCK1
37 VCCO3.3v Power supply pins for output drivers (subject to banking rules) VCCO
38 GND GND GND
39 GCK0NCGCLKIOB GCK0
40 x in 1SACD Master clk input(67MHz)IOB
41 x in 2CD Master clk input(33MHz)IOBIO VREF 4
42 VCCINT2.5v Power supply pins for the internal core logic.VCCINT
43 SAONSACD OSC Power supply onIOB
44 SYSOSystem clock for DACIOB
45 192FS192fs output for DSP56364 and SM5866AS IOBIO VREF 4
46 8FS8fs output for DSP56364 and SM5866AS IOB
47 DSRSTreset3 delayed 20msec for DSP and DACIOB
48 GND GND GND
49 DONEConnect to ROM(XCF01S)10pin 330 ohm pullupDONE
50 VCCO3.3v Power supply pins for output drivers (subject to banking rules) VCCO
51 PROGRAM Connect to ROM(XCF01S)7pin 10K ohm pullupPROGRAM
52 IO INIT Connect to ROM(XCF01S)8pin 3.3K ohm pullupIOBIO INIT
53 DSP RST Reset for DSP56364IOBIO D7
54 IMD1output AIOBIO_VREF_3
55 IMDAEX OR output from SHIFTresistr D0(A),D1(B)IOB
56 N SHfor DSP56364 of Noise shaper on/offIOBIO D6
57 DC_Ffor DSP56364 of DC-Filter on/offIOBIO_D5
58 Filter3for DSP56364 of filter3 control. IOB
59 Filter2for DSP56364 of filter2 control. IOBIO VREF 3
60 Filter1for DSP56364 of filter1 control. IOBIO D4
61 VCCINT2.5v Power supply pins for the internal core logic.VCCINT
62 TEST 2TEST 2PCIIOB IO TRDY
63 VCCO3.3v Power supply pins for output drivers (subject to banking rules) VCCO
64 GND GND GND
65 NCNCPCIIOB IO IRDY
66 IO D3 NCIOBIO D3
67 NCNCIOBIO_VREF_2
384fs output for DSP clock
IOB
1-331-34
Pin no Signal NameFunctionPin Usage Pin Name
68 GND To connect GNDIOB
69 NCNCIOBIO D2
70 TEST 3TEST 3IOBIO D1
71 FSIOEXT_Sampling clock(3 fs output)IOB
72 FSIEXT Sampling clock(3 fs input)IOBIO VREF 2
73 DOXCFConnect to ROM(XCF01S)1pin IOBIO DIN D0
74 IO_DOUT_
BUSY
75 CCLKConnect to ROM(XCF01S)2pin CCLK
76 VCCO3.3v Power supply pins for output drivers (subject to banking rules) VCCO
77 TDO JTAG terminal TDO
78 GND GND GND
79 TDI JTAG terminal TDI
80 FSXx fs output for PLL phase comparaterIOBIO CS
81 EXT CLK EXT CLK(1024fs input)IOBIO WRITE
82 SYCL768fs output for EnginIOBIO_VREF_1
83 NCNCIOB
84 ECKOSELECT out from Switch (osc out orEXT CLK)IOB
85 VCCINT2.5v Power supply pins for the internal core logic.VCCINT
86 DF-DADIG inputIOBIO VREF 1
87 DF-QADIG Reclock outIOB
88 DACLSACD or CD bit clock input GCLKIOB GCK2
89 GND GND GND
90 VCCO3.3v Power supply pins for output drivers (subject to banking rules) VCCO
91 CKI Clock Input Frequency for divider GCLKIOB GCK3
92 VCCINT2.5v Power supply pins for the internal core logic.VCCINT
93 NCNCIOBIO VREF 0
94 VCCINT2.5v Power supply pins for the internal core logic.VCCINT
95 NCNCIOB
96 EXONfor VCXO Power supply control (H=on)IOB
97 timo<0>reset3 delayed 1(1time of fs)IOBIO VREF 0
98 NCNCIOB
99 TCK JTAG terminal TCK
100 VCCO3.3v Power supply pins for output drivers (subject to banking rules) VCCO
MODE
(H SACD L CD)InputX/OutputX
3
5 DAPC 6 SAR)
nputX
EXOR
5 6
2
NV
4
RCK
7
BCLK
88
DSDO
DSCK
9
DSCS3
15
atchi
36
Tm ng
RESET3
10
XCLK
81
Xin
40
84
91
QA
88
DA
87
REG on
96
Xon
43
16
B
17
kout
kn
H x'tal on)
EXT on
H on
CD
SACD
DQ
>
CL
R
NOR
2
NCIOBIO_DOUT_
pin no InputX pin no
618
DAPC
5
pin no Shi t Resiste(74HC595)
MD1
D0
D2
DACRES
D3
NSH
D4
DCF
57
D5 FILTC
D6
FILTB
59
D7
FILTA
60
MDA EXOR "IMD0 IMD1"
55
100
20
22
34
44 SYSO
DividerA
(
1/2)256fs
A CD B SACD
C EXT
DividerA
(1/3)256fs
AB C
(fs2fs 4fs)
Divider
Dv der
8fs)
Data Switch
O
Latch
DividerReset
and
Dv derB 0
Dv derA
(
Dv derA
(
Dv de B
Dv de B
1/3)512fs
12 256fs
7
D0
IMDA
EXO
D1
A CD B SACD
C EXT
C
B
A
2
A
B
C
A CD B SACD
C EXT
DQ
>
55
R
DATA
7
latout
95
TM0
97
TM1
47
out0
82
768fs
SW
out1
36
384s
SW
out2
45
192s
O
out3
67
512s
out4
SW
46
8fs
FSX
80
8bt
Shift Resister
(74HC595)
DSPR
Delay pus
10 20msec
(12)
(1 2)
3
FSX switch2
OutpuX
SACLO
SALO
DACLO
DALRO
1
BUSY
g
Q114 : AT49BV040BQ111 : DSP56364UM (PEC777f2)
Pin Name Function
A0 - A18Addresses
CE
Chip Enable
OEOutput Enable
WEWrite Enable
I/O0 - I/O7 Data Inputs/Outputs
VCC
GND
ADDRESS
INPUTS
OE
WE
CE
OE, CE, AND WE
LOGIC
Y DECODER
X DECODER
VSOP Top View (8 x 14 mm) or
TSOP Top View (8 x 20 mm)
1
A11
2
A9
3
A8
4
A13
5
A14
6
A17
7
WE
8
VCC
9
A18
10
A16
11
A15
12
A12
13
A7
14
A6
15
A5
16
A4
DATA INPUTS/OUTPUTS
I/O7 I/O0
8
DATA LATCH
INPUT/OUTPUT
BUFFERS
Y GATING
MAIN MEMORY
(496K BYTES)
OPTIONAL BOOT
BLOCK (16K BYTES)
7FFFFH
04000H
03FFFH
00000H
OE
32
A10
31
CE
30
/O7
29
/O6
28
/O5
27
/O4
26
/O3
25
GND
24
/O2
23
/O1
22
/O0
21
A0
20
A1
19
A2
18
A3
17
PERIPHERAL
EXPANSION
AREA
EXT AL
GP O
ADDRESS
GENERATION UNIT
SIXCHANNELS
DMA UNIT
INTERNAL
DATA BUS
SWITCH
PLL
CLOCK
GEN
RESET
PINIT/ NM I
4
PROGRAM
INTERRUPT
12
ESAI
PIO_EB
CONT
Q211 : 2SK389FM
1. NC
2. DRAIN 2
3. GATE 2
8
4. SOURCE 2
7
5. SOURCE 1
6
6. GATE 1
7. DRAIN 1
5
8. SUBSTRAIGHT
(SUBSTRAIGHT: OPEN)
Q107 : NJM2880
NJM2880U
V
IN
Cont
PIN FUNCTION
1.CONTROL (Active High)
2.GND
3.NOISE BYPASS
4.V
OUT
5.V
IN
Thermal
Protecton
Bandgap
Reference
V
OUT
Noise
Bypass
1
2
3
4
Q202 : NJM2887
GND
5
SHI
24-BIT
DSP56300
CORE
PR
OGRAM
DECODE
CONT
MO D A/IRQ A
MO D B/IRQ B
MODD/IRQ D
PROGRAM
PROGRAM ROM
Boots rap ROM
PROGRAM
ADDRESS
GEN
RAM
0 5 K x 24
8K x2 4
192x 24
PM EB
DDB
YD B
XD B
PD B
GD B
TWO 56 BITACC UMULATORS
1-361-35
X
MEMORY
RAM
1K X24
XM E B
YA B
XAB
PA B
DA B
DATA ALU
→
24 X24+56 56 B T MAC
BARREL SHIFTER
24 BITS BUS
Y MEMORY
RAM
1 5KX 24
MEMOR Y
EXPANSION
AREA
YM _ E B
DRAM& SRAM
'$*+$,
"-""%"
EXTERNAL
ADDRESS BUS
SWITCH
BUS
INTERFACE
EXTERNAL
DATA BUS
SWITCH
POWER
MGMT
JTAG
OnCEô
18
6
8
4
!" #$
"%&
ADDRESS
CONTROL
DATA
p()
Q102 : XCF01SQ201 : SM5866
CLK CE
TCK
TDI
Interface
Control
and
JTAG
Data
Address
Memory
OE/RESET
(DNC)
(DNC)
D0
2
3
CLK
4
TDI
VO20/VOG20
5
TMS
Top V e w
6
TCK
7
CF
8
9
10
CE
VCCJ
19
VCCO
18
VCCINT
17
TDO
16
(DNC)
15
(DNC)
14
(DNC)
13
CEO
(DNC)
GND
TMS
12
11
20
1
TDO
CF
Boundary
Pin Name
Scan Order
D0
CLK
OE/RESET
CE
CF
CEO
TMS
TCK
Pin Name
Scan Order
TDI
TDO
VCCINT+3 3V Supply Positive 3 3V supply voltage for internal logic
VCCO
VCCJ
GNDGround
DNCDo not connect (These pins must be left unconnected )2, 9, 12, 14, 15, 16
Boundary
Scan FunctionPin Description
4Data Out
3Output Enable
0Data In
20Data In
18Output Enable
15Data In
22Data Out
21Output Enable
12Data Out
11Output Enable
Boundary
Scan FunctionPin Description
D0 is the DATA output pin to provide data for configuring an
FPGA in serial mode The D0 output is set to a
high impedance state during ISPEN (when not clamped)
Configuration Clock Input Each rising edge on the CLK input
increments the internal address counter if the CLK input is
selected, CE
Output Enable/Reset (Open Drain I/O) When Low, this input
holds the address counter reset and the DATA output is in a
high impedance state This is a bidirectional opendrain pin
that is held Low while the PROM is reset Polarity is not
programmable
Chip Enable Input When CE is High, the device is put into
low power standby mode , the address counter is reset, and
the DATA pins are put in a high impedance state
Configuration Pulse (Open Drain Output) Allows JTAG
CONFIG instruction to intiate FPGA configuration w thout
powering down FPGA This is an open drain output that is
pulsed Low by the JTAG CONFIG command
Chip Enable Output Chip Enable Output (CEO) is connected
to the CE input of the next PROM in the chain This output is
Low when CE is Low and OE/RESET input is High, AND the
internal address counter has been incremented beyond its
Terminal Count (TC) value CEO returns to High when
OE/RESET goes Low or CE goes High
JTAG Mode Select Input The state of TMS on the rising edge
of TCK determines the state transitions at the Test Access
Port (TAP) controller TMS has an internal 50KΩ resistive
Mode Select
pull up to V
not driven
JTAG Clock Input This pin is the JTAG test clock It
sequences the TAP controler and a l the JTAG test and
Clock
programming electronics
Boundary
JTAG Serial Data Input This pin is the serial input to all JTAG
instruction and data registers TDI has an internal 50KΩ
Data In
resistive pull up to V
the pin is not driven
JTAG Serial Data Output This pin is the serial output for a l
JTAG instruction and data registers TDO has an internal
Data Out
50KΩ resistive pu l up to V
system f the pin is not driven
+3 3V, 2 5V, or 1 8V I/O Supply Positive 3 3V, 25V, or 1 8V
supply voltage connected to the output voltage drivers and
input buffers
+3 3V, 2 5V, or 18V JTAG I/O Supply Positive 3 3V, 2 5V, or
1 8V supply voltage connected to the TDO output voltage
driver and TCK, TMS, and TD I input buffers
is Low, and OE/RESET is High
to provide a logic "1" to the device if the pin is
CCJ
to provide a logic "1" to the device if
CCJ
to provide a logic "1" to the
CCJ
Data
OE/RESET
Serial
Interface
20 pin TSSOP
(VO20/VOG20)
1
3
819Data Out
10
7
13
5
6
20 pin TSSOP
(VO20/VOG20)
4
17
18
19
20
11
CEO
DATA (D0)
Serial Mode
ds123 01 30603
1
TSTN
TO
DVDD
SDI
SBCKA
SBCKD
RSTN
DI
BCKI
WCKI
DVSS
BCPOL
DSPOL
14
CVDD
NumberNameI O
1TSTNIp Test mode use only (tie HIGH or leave open for normal operation)
2TOO Test mode use only (leave open for normal operation)
3DVDD– Digital supply VDD
4SDIIp DSD data input
5SBCKAIp DSD bit clock input
6SBCKDIp DSD bit clock input ( ie LOW for DSD normal input mode)
7RSTNIp System reset (active LOW)
8DIIp PCM data input
9BCKIIp PCM b t clock input
10WCKIIp PCM word clock input
11DVSS– Digital ground VSS
12BCPOLIp DSD mode bit clock polarity select
13DSPOLIp DSD mode data polarity select
14CVDD– System clock supply VDD
15CKII System clock
16CVSS– System clock ground VSS
17AVSSB– B-channel analog ground VSS
18IOUTBNO B-channel analog output (inverse-phase)
19IOUTBO B-channel analog output (in-phase)
20RBI B-channel bu lt-in resistor connection
21AVDDB– B-channel analog supply VDD
22AVDDA– A-channel analog supply VDD
23IOUTANO A-channel analog output (inverse-phase)
24IOUTAO A-channel analog output (in-phase)
25RAI A-channel bu lt-in resistor connection
26AVSSA– A-channel analog ground VSS
27IMD0Ip Input mode select
28IMD1Ip Input mode select
1. Ip = input pin with buit-in pull-up resistor
1-371-38
BCKI
WCKIDISBCKD SBCKA SDI
28
IMD1
IMD0
AVSSA
RA
IOUTA
IOUTAN
AVDDA
AVDDB
RB
IOUTB
IOUTBN
AVSSB
CVSS
CKI
15
1
DVDD
CVDD
AVSSB
DVSS
CVSS
3
PCM input interface
11
Interpolation
14
15
CKI
16
Noise shaper
17
23 level
23 level
DEM DAC
DEM DAC
19 20 21 22
18
IOUTBRBAVDDB
IOUTBN
Description
AVDDA
DSD input interface
DSD filter
23 level
DEM DAC
DEM DAC
24 25
23
IOUTAN
23 level
IOUTA
4568910
12
BCPOL
13
DSPOL
7
RSTN
2
TO
1
TSTN
28
IMD1
27
IMD0
26
AVSSA
RA
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1-401-39
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