1.2 TEST MODE ........................................................................................................................................ 1-2
2.4 PARTS LOCATION ........................................................................................................................... 2-13
2.5 IC DATA ............................................................................................................................................ 2-17
2.3 EXPLODED VIEW AND PARTS LIST ............................................................................................... 2-36
2.4 ELECTRICAL PARTS LIST ............................................................................................................... 2-37
Please use this service manual with referring to the user guide ( D.F.U. ) without fail.
SA-14
R
Printed in Japan
410K855010 KKI
First Issue
2001. 03
Page 2
MARANTZ DESIGN AND SERVICE
MARANTZ AMERICA, INC.
Using superior design and selected high grade components, MARANTZ company has created the ultimate in stereo sound.
Only original
MARANTZ parts can insure that your MARANTZ product will continue to perform to the specifications for which
it is famous.
Parts for your
MARANTZ equipment are generally available to our National Marantz Subsidiary or Agent.
ORDERING PARTS :
Parts can be ordered either by mail or by Fax.. In both cases, the correct part number has to be specified.
The following information must be supplied to eliminate delays in processing your order :
1. Complete address
2. Complete part numbers and quantities required
3. Description of parts
4. Model number for which part is required
5. Way of shipment
6. Signature : any order form or Fax. must be signed, otherwise such part order will be considered as null and void.
SUPERSCOPE TECHNOLOGIES, INC.
MARANTZ PROFESSIONAL PRODUCTS
2640 WHITE OAK CIRCLE, SUITE A
AURORA, ILLINOIS 60504 USA
PHONE : 630 - 820 - 4800
FAX : 630 - 820 - 8103
WO KEE HONG DISTRIBUTION PTE LTD
130 JOO SENG ROAD
#03-02 OLIVINE BUILDING
SINGAPORE 368357
PHONE : +65 858 5535 / +65 381 8621
FAX : +65 858 6078
MALAYSIA
WO KEE HONG ELECTRONICS SDN. BHD.
SUITE 8.1, LEVEL 8, MENARA GENESIS,
NO. 33, JALAN SULTAN ISMAIL,
50250 KUALA LUMPUR, MALAYSIA
PHONE : +60 3 - 2457677
FAX : +60 3 - 2458180
CAUTION : After servicing this appliance and prior to returning to customer, measure the resistance between either primary AC
cord connector pins ( with unit NOT connected to AC mains and its Power switch ON ), and the face or Front Panel of product and
controls and chassis bottom.
Any resistance measurement less than 1 Megohms should cause unit to be repaired or corrected before AC power is applied, and
verified before it is return to the user/customer.
Ref. UL Standard No. 1492.
In case of difficulties, do not hesitate to contact the Technical
Department at above mentioned address.
001120KKI
Page 3
1.1 TECHNICAL SPECIFICATIONS
Audio Characteristics
Channels2channels2channels
Frequency range2 Hz - 100 kHz2 Hz - 20 kHz
Frequency characteristics2 Hz - 50 kHz (-3 dB)2 Hz - 20 kHz
Dynamic range113 dB100 dB
THD (1 kHz)0.0015 %0.0020 %
wow & flutterPrecision of quartzPrecision of quartz
Analog output
output level (unbalanced)2.2 V2.2 V
output level (balanced)4.3 V4.3 V
DSD mode:192Fs (8.4672MHz/16.9344MHz)
11SCLKISerial data clock
12LRCK(PCM)IPCM mode:Left/Right channel clock(44.1KHz)
CLKMODE(DSD)IDSD mode:Select H(3.3V)
13SDATA(PCM)IPCM mode:Serial audio data
DSD_L(DSD)
14M1(PCM)IPCM mode:(Low)
DSD_R(DSD)DSD mode:Direct Stream Digital audio data (Right)
15MUTEIMute input (Low active)
16C/HIControl port (H) /Hardware (L) mode select
17MUTECOMute control (Low active)
18AGNDAnalog ground
19AOUTR-ORight channel negative Analog out
20AOUTR+ORight channel positive Analog out
21ANDAnalog ground
22VAAnalog power supply +5.5V
23AOUTL+OLeft channel positive Analog out
24AOUTL-OLeft channel negative Analog out
25CMOUTOCommon mode voltage
26FILT-IReference ground
27FILT+OReference filter
28VREFVoltage reference input
DSD mode:Direct Stream Digital audio data (Left)
1-25
Page 18
1.9 EXPLODED VIEW AND PARTS LIST
VERS.
POS.
COLOR
NO
001B /C1G
/S1G
/U1G
001B /F1NFRONT PANEL ASSY GOLD
001B /U1BFRONT PANEL ASSY BLACK
002B /C1G
/S1G
/U1G
002B /F1NFRONT PANEL GOLD
002B /U1BFRONT PANEL BLACK410K248010
003B /C1G
/S1G
/U1G
003B /F1N4822 426 10497 ESCUTCHEON GOLD269J063110
003B /U1B4822 426 10496 ESCUTCHEON BLACK269J063010
005B GOLD 4822 381 12016 LENS IR GOLD256J355030
005B BLACK 4822 381 12015 LENS IR BLACK256J355040
006B GOLDRING GOLD NO.4410K353120
006B BLACKRING BLACK NO.1410K353010
007BSPRING FOR RING410K115010
008B GOLD 9965 000 01554 BADGE MNTZ GOLD313J251110
008B BLACK 9965 000 01553 BADGE MNTZ BLACK313J251010
009BWINDOW410K158010
010B GOLDBUSHING POWER/TRAY
001D GOLDLID TOP GOLD410K257110
001D BLACK LID TOP BLACK 410K257010
002DSHEET FOR TOP LID INSIDE 313J107010
005D GOLD 4822 502 14425 SCREW FOR TOP LID323S010020
005D BLACK 4822 502 21693 SCREW FOR TOP LID323S010030
006D GOLD 4822 426 10499 SIDE PANEL GOLD269J249110
006D BLACK 4822 426 10498 SIDE PANEL BLACK269J249010
009D GOLD 4822 502 14425 SCREW FOR SIDE PANEL323S010020
009D BLACK 4822 502 21693 SCREW FOR SIDE PANEL323S010030
4822 126 11687 CER. 0.1 F +80% -20% 25V DK98104200
DESCRIPTION
F +80% -20% 25V DK98104200
F +80% -20% 25V DK98104200
10% 50VDK96471300
F 50VOA10505020
F M 16VOA10601620
F M 35VOA47703520
F +80% -20% 25V DK98104200
F 10% 25VDK96223200
F M 50VOA22505020
F M 50VOA47505020
F +80% -20% 25V DK98104200
10 % 50VDK96472300
10% 50VDK96222300
F +80% -20% 25V DK98104200
F 25VOA10702540
F +80% -20% 25V DK98104200
F +80% -20% 25V DK98104200
5% 160VOF55182550
5% 160VOF55182550
5%DF95391500
5%DF95391500
F 16VOA47701640
F M 16VOA47701650
F 16VOA47701640
F M 16VOA47701650
F 16VOA47701640
F M 16VOA47701650
F 16VOA47701640
F M 16VOA47701650
F +80% -20% 25V DK98104200
5% 100VOF55681540
5% 100VOF55681540
F 16VOA47701640
F M 16VOA47701650
F 16VOA47701640
F M 16VOA47701650
F 16VOA47701640
F M 16VOA47701650
F 16VOA47701640
F M 16VOA47701650
F +80% -20% 25V DK98104200
F +80% -20% 25V DK98104200
F M 50VOA47505020
F 6.3VEY47600620
10% B 50VDK96102300
5 % 50VDD95120300
5 % 50VDD95120300
PART NO.
(MJI)
1-291-30
Page 21
POS.
NO
VERS.
COLOR
PART NO.
(PCS)
DESCRIPTION
PART NO.
(MJI)
POS.
NO
VERS.
COLOR
PART NO.
(PCS)
DESCRIPTION
PART NO.
(MJI)
C5164822 124 41539 ELECT 47 F M 16VOA47601620
C518
F +80% -20% 10VDK98105200
F +80% -20% 10VDK98105200
F +80% -20% 25V DK98104200
F +80% -20% 25V DK98104200
F +80% -20% 25V DK98104200
F +80% -20% 10VDK98105200
F +80% -20% 10VDK98105200
F +80% -20% 25V DK98104200
F M 16VOA47601620
F 16VOA47701640
F M 16VOA47701650
F 16VOA47701640
F M 16VOA47701650
F 16VOA47701640
F M 16VOA47701650
F 16VOA47701640
F M 16VOA47701650
5% 50VDD95101300
F 20% 16VOA68801620
F 20% 6.3VOA33800620
20% 6.3VOA33800620
F 16VOA22801620
F M 25VOA22702550
F 20% 25VOA10702550
F 20% 25VOA10702550
F 20% 16VOA47801620
F 16VOA22801620
F 20% 10VOA47701020
F M 35VOB47803520
F M 35VOB47803520
F 25VOA10702540
F 20% 25VOA10702550
F 25VOA10702540
F 20% 25VOA10702550
F M 25VOA47702550
F M 25VOA47702550
F +80% -20% 25V DK98104200
F +80% -20% 25V DK98104200
F +80% -20% 25V DK98104200
2.4 PARTS LOCATION ........................................................................................................................... 2-13
2.5 IC DATA ............................................................................................................................................ 2-17
2.6 EXPLODED VIEW AND PARTS LIST............................................................................................... 2-36
2.7 ELECTRICAL PARTS LIST ............................................................................................................... 2-37
Please use this service manual with referring to the user guide ( D.F.U. ) without fail.
R
CDM-15M / CDM-15MB
Page 26
2.1 REMOVING AND REINSTALLING THE MAIN
PART S
SACD MECHANISM SECTION
Perform steps of the disassembly method to remove the
SACD mechanism.
(H1)x4
ø
2.6x6mm
(G1)x1
ø1.7x3mm
(G1)x4
ø3x6mm
CD Servo PWB
Top Plate
Tray Ass'y
(H1)x1
ø
2.6x6mm
(H1)x2
ø
2.6x6mm
Tray Sensor
PWB
(H1)x2
ø
2x5mm
701x2
Pickup
Sensor PWB
(G1)x2
ø2x5mm
Mode Switch
PWB
308
(G2)x2
705x2
313
(G3)x1
714
(G3)x1
(G2)x1
701x2
312x2
326
327
716
711
317
719x2
343
M703710
328
715
329
711x2
711x4
324
309x2
2-2
318
301
303
325
PWB-D2
PWB-D3
712
SW52
SW51
711x2
713x2
325
711x2
PWB-D1
Page 27
How to remove the loading motor (See Fig. 2-1.)
1. Remove the lift lever.
2. Remove the screws (A1) x 4 pcs., to remove the gear cover.
3. Remove the screws (A2) x 2 pcs., to remove the loading motor.
(Adjusting the SACD mechanism completed products)
It is necessary to position the spindle motor, the sub-shaft
(mechanism), and the pickup to play a nonstandardized SACD
disc. If the pickup or motor is replaced at the service division,
these adjustments cannot be performed because of the facility
and measuring equipment matters.
The SACD mechanism completed products are adjusted for
the above reasons.
After installing:
After installing the SACD mechanism completed product,
remove the two solders shown below.(See Fig. 2-2.)
[REMARK]
• The two solders are used to eliminate static electricity before
installing the SACD mechanism completed product.
Loading
Motor
Lift Cover
(A2) x2
ø1.7x2mm
Gear Cover
Remove these two solders after installing
the SACD mechanism completed product.
(A1) x4
ø2x5mm
Figure 2-2Figure 2-1
2-3
Page 28
Adjusting the tension of the timing belt
Remove the gear unit and connect the ammeter to the DC
power as shown in Fig. 2-3.
If measurement of the loading motor current is possible,
move the motor in the direction of the arrow so as to obtain
40 - 50 mA, and fix the motor with screws (A1) x 2 pcs.
(See Fig. 2-4.)
33TEBInputTE balanceVrDTEB increase brings increase in gain on TP
34FEBInputFE balanceVrDFEB increase brings increase in gain on
35PSCInputVRCK frequency division ON/OFF-Frequency division OFF at High
36VCC2-Power terminal37NC-NC terminalVrDConnected to GND via C.
38EQDInputGroup delay correctionVrDGroup delay by raising EQD: rise rightward
39GND2-GND terminal40RFDC-DC feedback capacity41*RFAOutputRF total adding output2.2 [V]
42EQBInputBoost adjustmentVrDBoost quantity up by raising EQB.
43EQFInputFrequency adjustmentVrDShift to higher frequency by raising EQF.
44MDI1InputMonitor input45LDO1OutputDrive output46P1TNInputTE- input (DVD)VrA
47P1TPInputTE+ input (DVD)VrA
48NC-NC terminal-Used by connecting to GND.
49
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
P1FN
Input/Output
Function
InputFE- input (DVD)VrA
2-182-18
Voltage (TYP.)
Terminal DC
higher filter frequency except for servo LPF.
increase on sides A and B.
side and in delay capacity on sides A and C.
sides A and C (FP).
Remarks
Page 36
IC503 VHiTB6504F+-1: Stepping Motor Driver (TB6504F)
IC504 RH-iX2842AFZZ: Spindle Motor Driver (IX2842AF)
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Pin No.
Terminal
Name
FunctionPin No.
Terminal
Name
Function
1PGPower GND terminal15SGSignal GND terminal
2H1+Hall element 1 positive input terminal16VCCPower terminal
3H1-Hall element 1 negative input terminal17ECRTorque instruction reference input terminal
4*NCNot used18ECTorque instruction input terminal
5H2+Hall element 2 positive input terminal19*NCNot used
6H2-Hall element 2 negative input terminal20PCI
Current feedback phase compensating terminal
7VHHall bias terminal21VMMotor power terminal
8H3+Hall element 3 positive input terminal22CS1Current detection terminal 1
9H3-Hall element 3 negative input terminal23*NCNot used
10SSStart/Stop switching terminal24*NCNot used
11*TFLGThermal protection monitor terminal25*NCNot used
12FGFG signal output terminal26A3Drive output 3
13BRKBreak mode set terminal27A2Drive output 2
14*NCNot used28A1Drive output 1
2
H1+
3
H1-
5
H2+
8
H3+
6
H2-
9
H3-
7
VH
18
EC
17
10
ECR
S/S
16
Vcc
20
PCI
13
BRK
11
TSDF
12
FG
1
PG
26
A3
27
A2
28
A1
22
CS1
21
VM
15
SG
ER
EA
VTL
EP=ER x EA
FG
COMPARATOR
+ -
MATRIX HALL AMPLIFIER
DETE-
CTION
DIRECTION
DETECTION
DIRECTION SWITCHING
UPPER-SIDE
DISTRIBUTION
AMPLIFICATION
AMPLIFICATION
LOWER-SIDE
DISTRIBUTION
HALL BIAS
LOGIC
ABSOLUTE
VALUE
START/
STOP
THERMAL
PROTECTION
CIRCUIT
BREAK
CIRCUIT
Pin No. Terminal Name
1CK1Clock signal input
2, 3M1, M2Excitation mode set terminal
4REF INOutput reference value (VNF) set terminal H: VNF=0.5V, L: VNF=0.25V
5*MOMonitor output L: Initial condition
6*NCNot used
7VCCLogic side power terminal
8VMBOutput side power terminal
9øBB output
10PG-BPower ground
11NFBB channel current detection terminal
12øBB output
13øAA output
14*NFAA channel current detection terminal
15PG-APower ground
16øAA output
17VMAOutput side power terminal
18*NCNot used
19S-GNDSignal ground
20RESETReset signal input
21ENABLEEnable signal input
22OSCInternal oscillation frequency set terminal. Capacitor is externally mounted.
23CW/CCWClockwise/counterclockwise input
24CK2Clock signal input
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Note 1: Positive output/negative output means polarity toward input. (Ex. 18 pin output 'H' in case of 19 pin input 'H')
Note 2: Tray positive output/tray negative output means polarity toward mode. (Ex. 11 pin output 'H' in case of the forward mode)
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
For F and R (CH5 control is effective only in case of ON)
FROutput Mode
LLHigh impedance
LHReverse
HLForward
HHBreak
Page 38
IC602 RH-iX1474GEZZ: SACD Data Processor (IX1474GE) (2/2)
IC606 RH-iX1473GEZZ: Digital Servo (IX1473GE) (1/3)
1VSS-Digital ground terminal
2BCKOutputBit clock (1.4122 MHz) output terminal
3AOUTOutputAudio data output terminal
4DOUTOutputDigital-out output terminal
5*MBOVOutputWhen buffer memory over signal output terminal is over: "H"
6IPFOutputWhen AOUT output of correction flag output terminal shows the correction impossible
symbol: "H"
7*SBOKOutputWhen CRCC judgment result output terminal of sub-code Q data shows OK: "H"
8*CLCKInput/Output Can be selected by using the clock output/input terminal command bit for reading
sub-code P-W data.
9VDD-Digital + power terminal
10VSS-Digital ground terminal
11*DATAOutputSub-code P-W data output terminal
12*SFSYOutputReproductive frame sync signal output terminal
13SBSYOutputWhen sub-code sync of sub-code block sync output terminal is detected: "H" at the
position of SI
14*SPCKOutputOutput terminal of the clock (176.4 kHz) for reading processor status signals
15*SPDAOutputProcessor status signal output terminal
16*COFSOutputCorrection frame clock (7.35 kHz) output terminal
17*MDNITOutputCan monitor DSP internal flag and PLL clock by using microcomputer commands of
LSI internal signal monitor terminal
18VDD-Digital + power terminal
19TESIO0InputTest input/output terminal. Normally fixed at "L".
20P2VREF-PLL special 2VREF terminal
21*SPDOOutputVCO center frequency shift terminal
22*PDOSOutputPhase error (between EFM and PLCK) signal output terminal
(to be used in case of 8-time speed operation)
23PDOOutputOutput terminal for phase error signal between EFM signal and PLCK signal
24*TMAXSOutputTMAX detection result output terminal. Selected by command bit TMPS.
25TMAXOutput
26LPFNInputInversion input terminal of amplifier for low-pass filter
27LPFOOutputOutput terminal of amplifier for low-pass filter
28PVREF-VREF terminal for PLL system
29VCOREFInputVCO center frequency reference level terminal. Normally fixed at "PVREF".
30VCOFOutputFilter terminal for VCO
31AVSS-Analog system ground terminal
32SLCOOutputOutput terminal of DAC for generating data slice level
33RFIInputRF signal input terminal
34AVDD-Analog power terminal
35RFCTInputRFRP signal center level input terminal
36REZIInputInput terminal for RFRP zero-cross
37RFRPInputRF ripple signal input terminal
38FEIInputFocus error signal input terminal
39SBADInputSub-beam adding signal input terminal
40TSINInputTest input terminal. Normally fixed at "Vref".
41TEIInputTracking error signal input terminal (Input when tracking servo is ON.)
42TEZIInputInput terminal for tracking error zero cross
43FOOOutputFocus equalizer output terminal
Pin No.
Terminal
Name
Input/OutputFunction
Remarks
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
TMAX Detection resultTMAX Output
Longer than the specified frequency"P2VEFF"
Shorter than the specified frequency "VSS"
Within the specified frequency"HiZ"
Pin No.
84DVDD3-Digital power supply (3.3V)For logic cell
85-88SD3-SD0OutputMPEG data output
89SERROutputMEPG data reliability flag (Data error = "L")
90SBGNOutputMEPG output sector synchronous signal (Sector head = "L")
91SENBOutputMEPG data effective flag (Effective = "L")
92SDCKOutputMEPG data transfer clock
93DVSS-Digital power supply (0V)For logic cell
94SREQInputMEPG data request flag (In case of request = "L")Level TTL
95RSTNInputHard reset input (In case of reset = "L")
96DVDD3-Digital power supply (3.3V)For logic cell
97STDAOutputStatus data output
98STCKOutputStatus clock output
99UPWMOutputUniversal PWM output
100DVSS-Digital power supply (0V)For logic cell
44TROOutputTracking equalizer output terminal
45VREF-Analog reference power terminal
46*RFGCOutputOutputs 3-pole PWM signal of RF amplitude adjusting signal output terminal.
47TEBCOutputOutputs 3-pole PWM signal of tracking balance control signal output terminal.
48FMOOutputOutputs 3-pole PWM signal of feed equalizer output terminal.
49*FVOOutputOutputs speed error signal or 3-pole PWM signal of feed search EQ output terminal.
50DMOOutputTo output PWM signals of 3 poles of disc equalizer output terminal.
512VREF-Reference power terminal
52SELOutputLaser diode control signal
53FLGAOutputFLG-A output terminal
54FLGBOutputFLG-B output terminal
55*FLGCOutputFLG-C output terminal
56FLGDOutputFLG-D output terminal
57VDD-Power terminal
58VSS-Connected to GND.
59-62IO0-IO3Input/Output General-purpose I/O port
(60*)Can be switched to input/output port possible according to commands.
63/DMOUTInputTerminal for setting the mode outputting feed equalizer binary PWM from IO0 and 1
64/CKSE-X'tal select terminal. In case of 16.9344MHz: "H"; in case of 33.8688 MHz: "L"
65*/DACT-Test terminal
66TESINInputTest input terminal
67TESIO1Input/Output Test input/output terminal
68VSS-Digital ground terminal
69PXIInputDSP system clock oscillation circuit input terminal
70PXOOutputDSP system clock oscillation circuit output terminal
71VDD-Digital + power terminal
72XVSS-Ground terminal for system clock oscillation circuit
73XIInputSystem clock oscillation circuit input terminal
74*XOOutputSystem clock oscillation circuit output terminal
75XVDD-+ power terminal for system clock oscillation circuit
76DVDD-D/A conversion section power terminal
77*ROOutputChannel R data normal rotation output terminal
78DVSS-D/A conversion section analog ground terminal
79DVR-D/A conversion section reference voltage terminal
80*LOOutputChannel L data normal rotation output terminal
81DVDD-D/A conversion section power terminal
82TEST1InputTest terminal
83TEST2InputTest terminal
84TEST3InputTest terminal
85BUS0Input/Output Data input/output terminal for microcomputer interfaceSchmitt input
86BUS1Input/OutputCMOS port
87BUS2Input/Output
88BUS3Input/Output
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Terminal
Name
Input/OutputFunction
(PWM carrier = 88.2 kHz)
(PWM carrier = 88.2 kHz)
(PWM carrier = 88.2 kHz)
(PWM carrier = 88.2 kHz)
(PWM carrier = DPS 88.2 kHz, synchronizing with PXO)
In case of input port: can read terminal condition (H/L) by read commands possible.
In case of output port: can control terminal condition (H/L/HiZ) by commands possible.
terminals and disc equalizer binary PWM from IO2 and 3 terminals. "L": active.
Normally open
Normally open
Normally open
Remarks
Pull-up
resistor built in
Pull-up
resistor built in
Pull-up
resistor built in
2-252-26
Page 40
IC801 RH-iX1478GEZZ: System Microcomputer (IX1478GE)
1VDD-Power supply +3.3V
2-4HADR0-HADR2InputCPU address bus
5HCSInputCPU chip select
6HWRInputCPU write signal
7HRDInputCPU read signal
8-15HDAT0-HDAT7Input/OutputCPU data bus
16VSS-Digital GND
17VDD-Power supply +3.3V
18EXPPAL0, SLDCK 1OutputDriving clock output for stepping motor driver
19EXPPAL1, SLDCK 2OutputMode control output for stepping motor driver
20EXPPAL2, CW/CCWOutputRotating direction control output for stepping motor driver
21EXPPAL3, DACCKOutputClock signal for electronic capacity IC
22EXPPAU0, DACDTOutputData signal for electronic capacity IC
23*EXPPAU1Input/OutputGeneral input/output terminal Gr.A
24VSS-Digital GND
25VDD-Power supply +3.3V
26EXPPAU2InputGeneral input/output terminal Gr.A
27EXPPAU3OutputGeneral input/output terminal Gr.A
28EXPBL0, EXTCKOutputControl clock output to 1-bit amplifier
29EXPBL1, EXTDOOutputControl data output to 1-bit amplifier
30EXPBL2, EXTSTOutputControl strobe output to 1-bit amplifier
31EXPBL3, VOLCSOutputChip select signal for electronic capacity IC
32VSS-Digital GND
33VDD-Power supply +3.3V
34EXPBU0, EXTDIInputControl data input from 1-bit amplifier
35EXPBU1, MECSW1InputTray position detection input
36EXPBU2, MECSW2InputMechanism stop mode detection input
37EXPBU3, SMODEInputOperating mode set input. Opened (S-MODE)
38EXPC0, DVD_LOutputSACD disc inserted/CD stopped: L
39EXPC1, SMUTEOutputSoft mute signal for SACD decoder
40EXPC2, AMUTEOutputAudio mute. In case of playback/manual search
41VSS-Digital GND
42EXPC3Input/OutputGeneral input/output terminal Gr.C
43EXPC4, DSDCTLOutputOutput control signal for DSD 1-bit signal
44EXPC5, SEEKOutputGeneral input/output terminal Gr.C
45EXPD0, GAIN0OutputGain control signal for RF pre-amplifier
46EXPD1, GAIN1OutputGain control signal for RF pre-amplifier
47EXPD2, GAIN2OutputGain control signal for RF pre-amplifier
48VSS-Digital GND
49VDD-Power supply +3.3V
50EXPD3, MMUTEOutputMain relay control signal. After reading disc TOC: "H"
51EXPD4Input/OutputGeneral input/output terminal Gr.D
52EXPD5, EMPHOutputDe-emphasis signal output
53BUFDO, RST_01OutputBuffer output D/Reset signal output for peripheral IC
54BUFDIInputBuffer input D
55SBUFBOOutputSchmitt buffer output B
56SBUFBIInputSchmitt buffer input B
57SBUFAOOutputSchmitt buffer output A
58SBUFAIInputSchmitt buffer input A
59MRSTInputReset terminal
Pin No.
Terminal NameInput/Output
Function
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
60MODEInputMode switching terminal. Fix at "L".
61BUFCOInput/OutputBuffer output C
62TESTInputTest terminal. Fixed at "L".
63BUFCIInputBuffer input C. Not used.
64VSS-Digital GND
Terminal NameInput/Output
Function
Pins 1 to 15: Simultaneous changes possible. Operating frequency: approx. 10MHz
Pins 18 to 47: Simultaneous changes possible. (Static signal) Operating frequency: approx. 1kHz
Pins 50 to 57: Simultaneous changes almost impossible. Operating frequency: approx. 1kHz
IC901 VHiCXD2751Q-1: SACD Playback Signal Processor (CXD2751Q) (1/2)
1XSRQOutputOutput terminal for data request to be input in the front end processor.
2XSHDInputInput terminal for header flag to be output from the front end processor.
3VDD-Power supply terminal, +3.3V
4VSS-Ground terminal
5SDCKInputInput terminal for data transmitting clock to be output from the front end processor
6SMUTEInputSoft mute terminal
H: Soft mute of audio output, L: Released
7XMSLATInputLatch input terminal for microcomputer serial communication
Latches addresses and data when this terminal rises.
8MSCKInputShift clock input terminal for microcomputer serial communication
Inputs and shifts the serial input data when the clock to be input in this terminal rises.
Read-out data change when the clock to be input in this terminal falls.
9MSDATIInputData input terminal for microcomputer serial communication (Microcomputer -> CXD2751Q)
Inputs serial data and addresses for communication.
10MSDATOOutputData input terminal for microcomputer serial communication (CXD2751Q -> Microcomputer)
High impedance except during output
11MSREDYOutputReady-to-output flag for microcomputer serial communication. Outputs "L", if complete.
Open drain.
12*XMSDOEOutputData enable terminal for microcomputer serial communication
Makes this terminal active when using the try state buffer outside.
13XRSTInputResets entire IC when reset terminal is "L".
Clock which is output from output terminals EXCKO1, EXCKO2, and LRCK does not stop during reset.
14MCKIInputMaster clock input terminal
Inputs clock of 512Fs (22.579 MHz) or 768Fs (33.869 MHz).
15VSS-Ground terminal
16CK75SInputMaster clock select terminal. Selects "H" in case of 768Fs and "L" in case of 512Fs.
17EXCKO1OutputExternal output clock terminal 1. Outputs 768Fs/512Fs/256Fs/128Fs according to setting.
18*EXCKO2OutputExternal output clock terminal 2. Outputs 768Fs/512Fs/256Fs/128Fs according to setting.
19*LRCKInput/OutputIFs (44.1kHz) clock input/output terminal. Selects master/slave according to setting.
20*NC-Not used
21*MNT2OutputMonitor output terminal. Outputs partial internal operation according to setting.
22TRSTInputReset terminal for test. Inputs power-on reset signal or fixed at "L".
23TCKInputTest clock input terminal. Fixed at "L".
24*TDIInputTest input terminal. Open
25*TENA1InputTest input terminal. Open
26*TDOOutputTest input terminal. Open
27VST-Test ground terminal. Connected to ground
28VDD-Power supply terminal, +3.3V
29VSS-Ground terminal
30*, 31* MNT1, MNT0OutputMonitor output terminal. Outputs partial internal operation according to setting.
32*XBITOutputDST related monitor terminal. Not connected.
33*F75HZOutput75Hz clock output terminal
34*SUPDATOutputSupplementary data serial output terminal
35*XSUPAKOutputSupplementary data effective flag terminal
Outputs "L" when supplementary data are effective.
36*SUPENOutputSupplementary data byte-unit enable output terminal
Changes to "H" at the break of 1 byte (8 bits) of serial data.
37TEST1InputTest input terminal. Fixed at "L".
38VSS-Ground terminal
39TEST2InputTest input terminal. Fixed at "L".
40, 41VSS-Ground terminal
42*BCKDInput/OutputPhase reference signal input/output terminal for DSD data phase modulation output
Input/output according to setting
43*-45* NC-Not used
Pin No.
Terminal Name
Input/Output
Function
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Pin No.
1-3A15-A13InputBlock select addresses: Select 1/32 erase block. These addresses are latched during data entry,
4-8A12-A8InputWord select addresses: Select one word in 1.6k byte block.
9*, 10* NC-Not used
11WRInputWrite enable: Controls access to command user interface, to data cue register and to address
12/RPInputReset/power-down: By setting /RP at Low, control circuit is initialized when supplying power.
13VPP-Device power supply: 5.0 V
14/WP-Write/Erase power supply: 5.0±0.5V is applied during the writing/erasing operation.
15RY/BYOutputReady/Busy: Outputs the condition of the internal write state machine. "Low" shows the write
16,17A18, A17InputBlock select addresses: Select 1/32 erase block. These addresses are latched during data entry,
18-25A7-A0InputWord select addresses: Select one word in 1.6k byte block.
26/CEInputChip enable: Makes control logic, input buffer, decoder, and sense amplifier of the device active.
27GND-Ground
28/OEInputOutput enable: By setting /OE at Low, data are output from pin DQ.
29DQ0Input/Output Lower byte data input/output: Data and command input during cycle of writing command user
30DQ8Input/Output Upper byte data input/output: The function is the same as shown in case of the lower byte data
31DQ1Input/Output Lower byte data input/output: Data and command input during cycle of writing command user
32DQ9Input/Output Upper byte data input/output: The function is the same as shown in case of the lower byte data
33DQ2Input/Output Lower byte data input/output: Data and command input during cycle of writing command user
34DQ10Input/Output Upper byte data input/output: The function is the same as shown in case of the lower byte data
35DQ3Input/Output Lower byte data input/output: Data and command input during cycle of writing command user
36DQ11Input/Output Upper byte data input/output: The function is the same as shown in case of the lower byte data
37VCC-Device power supply: 5.0±0.5V
38DQ4Input/Output Lower byte data input/output: Data and command input during cycle of writing command user
39DQ12Input/Output Upper byte data input/output: The function is the same as shown in case of the lower byte data
40DQ5Input/Output Lower byte data input/output: Data and command input during cycle of writing command user
41DQ13Input/Output Upper byte data input/output: The function is the same as shown in case of the lower byte data
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Terminal Name Input/Output
erase and lock block.
These addresses are latched during data entry.
cue latch. At Low, WR is active to input address and data at leading edge.
When supplying/breaking power, /RP pin is maintained at Low to protect data.
If /RP is at Low, device is in condition of deep power down.
To return from the deep power down, 480ns is required.
When pin /RP is at Low, all chip operation is interrupted and reset.
After return, device reads array.
state machine is in operation. When the machine is waiting for the next instruction to operate,
interrupting erasing, or in deep power-down condition, RY/BY pin is in the float condition.
erase and lock block.
These addresses are latched during data entry.
Only when /CE is Low, chip becomes active.
If /OE is set at High, pin DP becomes in the float condition.
interface. Memory array, identifier, and status data output when reading various data.
Float condition in case of chip non-select or output disable.
input/output above. Operating only in x16 mode. Floating in x 8 mode. DQ15/A-1: address
interface. Memory array, identifier, and status data output when reading various data.
Float condition in case of chip non-select or output disable.
input/output above. Operating only in x16 mode. Floating in x 8 mode. DQ15/A-1: address
interface. Memory array, identifier, and status data output when reading various data.
Float condition in case of chip non-select or output disable.
input/output above. Operating only in x16 mode. Floating in x 8 mode. DQ15/A-1: address
interface. Memory array, identifier, and status data output when reading various data.
Float condition in case of chip non-select or output disable.
input/output above. Operating only in x16 mode. Floating in x 8 mode. DQ15/A-1: address
interface. Memory array, identifier, and status data output when reading various data.
Float condition in case of chip non-select or output disable.
input/output above. Operating only in x16 mode. Floating in x 8 mode. DQ15/A-1: address
interface. Memory array, identifier, and status data output when reading various data.
Float condition in case of chip non-select or output disable.
input/output above. Operating only in x16 mode. Floating in x 8 mode. DQ15/A-1: address
2-312-32
Function
Page 43
IC901 VHiCXD2751Q-1: SACD Playback Signal Processor (CXD2751Q) (2/2)
IC902 VHiADC08351-1: A/D Converter (ADC08351)
1OECMOS/TTL compatible digital input terminal.
When this terminal is set to Low, digital output of ADC08351 becomes enable.
When this terminal is set to High, digital output changes to the high-impedance condition.
2DGNDGround return circuit terminal for digital power supply.
3-10D0-D7Conversion data output terminal. C0 shows LSB, and D7 shows MBS.
Effective data are output on data bus immediately after CLK input rising edge.
When OE terminal is set to Low, these terminals become enable.
11VDPositive digital power voltage terminal. Connected to +3V power supply.
VA and VD are supplied from the common power supply.
12CLKCMOS/TTL compatible clock input terminal. VIN is sampled at CLK input trailing edge.
13VDPositive digital power voltage terminal. Connected to +3V voltage power.
14VREFPositive reference voltage input terminal. Voltage of this terminal ranges from 0.75V to VA.
15PDCMOS/TTL compatible digital input terminal.
When this terminal is set to High, ADC08351 enters the power down mode, minimizing power consumption.
When this is set to Low, the device enters the normal operation mode.
16VAPositive analog power voltage terminal: To connect +3V voltage power.
17VINAnalog signal input. Convertible input ranges from 0.5Vp-p to 0.68Va.
18, 19AGNDGround return circuit terminal for analog power supply.
20DGNDGround return circuit terminal for digital power supply.
Pin No. Terminal NameFunction
Pin No.
Terminal Name
Input/Output
Function
46BCKAInput/OutputShift clock input/output terminal for DSD data output. Input/output according to setting.
47DSALOutputLch-DSD data output terminal. Phase modulation output according to setting.
48DSAROutputRch-DSD data output terminal. Phase modulation output according to setting.
49ZDFLGLOutputLch zero data detection flag. "H": when silent data continue for 300msec.
50ZDFLGROutputRch zero data detection flag. "H": when silent data continue for 300msec.
51A0OutputDRAM address output terminal (LSB)
52A1OutputDRAM address output terminal
53VDD-Power supply terminal, +3.3V
54VSS-Ground terminal
55-62A2-A9OutputDRAM address output terminal
63A10OutputDRAM address output terminal (MSB)
64*NC-Not used
65VSS-Ground terminal
66XWEOutputDRAM write enable output terminal. Connected to WE terminal of DRAM.
67XCASOutputDRAM column address strobe output terminal. Connected to CAS terminal of DRAM.
68XRASOutputDRAM row address strobe output terminal. Connected RAS terminal of DRAM.
69XOEOutputDRAM read enable output terminal. Connected OE terminal of DRAM.
70-77DQ0-DQ7Input/OutputDRAM data input/output terminal
78VDD-Power supply terminal, +3.3V
79VSS-Ground terminal
80WCKInputOperation clock for detecting PSP physical disc mark. Inputs 27.00MHz.
81WRFDInputRF data input terminal for detecting PSP physical disc mark
Inputs RF data made binary by slicer.
82WAD0InputA/D data input/output terminal for detecting PSP physical disc mark (LSB)
83-88WAD1-WAD6InputA/D data input/output terminal for detecting PSP physical disc mark
89WAD7InputA/D data input/output terminal for detecting PSP physical disc mark (MSB)
90VSS-Ground terminal
91SD7InputInput terminal for stream data to be output from the front end processor (MSB)
92-97SD6-SD1InputInput terminal for stream data to be output from the front end processor
98SD0InputInput terminal for stream data to be output from the front end processor (LSB)
99SDEFInputInput terminal for error flag to be output from the front end processor
100XSAKInputInput terminal for data effective flag to be output from the front end processor
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.