LG Display LC470MUK-SCA1 Specification

LC470MUK

Product Specification

SPECIFICATION

FOR

APPROVAL

)

(
(

Preliminary Specification

)

Final Specification

●

47.0” WUXGA TFT LCDTitle

SET MODEL

APPROVED BY

LGEBUYER

LC470MUK-SCA1LCM MODEL

*When you obtain standard approval,

please use the above model name without suffix

SIGNATURE

DATE

/

/

/

APPROVED BY

P.Y. Kim / Team Leader

REVIEWED BY

Y.J. Heo/ Project Leader

PREPARED BY

Q-H. Jo / Engineer

LG.Display Co., Ltd.SUPPLIER

LC470MUK*MODEL
SCA1 (RoHS Verified)SUFFIX

SIGNATURE

DATE

Please return 1 copy for your confirmation with

your signature and comments.

Ver. 1.0

TV Products Development Dept.

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LG. Display Co., Ltd

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Product Specification

CONTENTS

LC470MUK

Number

1
2
3

3-1
3-2
3-3

3-4
3-5

3-6
4
5

CONTENTS
RECORD OF REVISIONS
GENERAL DESCRIPTION

ABSOLUTE MAXIMUM RATINGS
ELECTRICAL SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
INTERFACE CONNECTIONS
SIGNAL TIMING SPECIFICATIONS

DATA MAPPING AND TIMING
PANEL PIXEL STRUCTURE

POWER SEQUENCE
OPTICAL SPECIFICATIONS
MECHANICAL CHARACTERISTICS

ITEM

Page

0COVER
1

2
3
4
5
5
7
9

12
13
14
15

19
6
7

8

8-1

9

Ver. 1.0

7-1

9-1
9-2
9-3
9-4
9-5

RELIABILITY
INTERNATIONAL STANDARDS
ENVIRONMENT
PACKING
PACKING FORM

PRECAUTIONS
ASSEMBLY PRECAUTIONS
OPERATING PRECAUTIONS
ELECTROSTATIC DISCHARGE CONTROL
PRECAUTIONS FOR STRONG LIGHT EXPOSURE
STORAGE

21

22

22

23

23

24

24

24

25

25

25

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Product Specification

RECORD OF REVISIONS

DescriptionPageRevision DateRevision No.

Preliminary Specification(First Draft) -Sep. 18, 20090.1
Corrected the ‘MODULE CONNECTOR(CN1) PIN CONFIGURATION’7, 8Sep. 25, 20090.2
Corrected the ‘Last Data Latch to SOE Timing’10
Corrected the ‘ELECTRICAL CHARACTERISTICS’5Nov. 13, 20090.3
Added the ‘APPENDIX-IV’29
Corrected the ‘LCD Connector (CN1) and (CN2)’7,8Nov. 20, 20090.4
Changed the ‘ELECTRICAL CHARACTERISTICS’ and the ‘Note’5Dec. 30, 2009 0.5

LC470MUK

7,8

7,8

Modified the ‘MODULE CONNECTOR(CN1, CN2) PIN
CONFIGURATION’ for normal operation.

Modified the ‘Note’ for ‘MODULE CONNECTOR(CN1, CN2) PIN
CONFIGURATION’

Modified the ‘Note’ for ‘POWER SEQUENCE’14
Added the ‘Color Coordinates’ in ‘Table 6’15
Modified the ‘Common Voltage’5Jan. 7, 20100.6
Final Specification-Jan. 7, 20101.0

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LC470MUK

Product Specification

1. General Description

The LC470MUK is a Color Active Matrix Liquid Crystal Display with an integral the Source PCB and Gate
implanted on Panel (GIP). The matrix employs a-Si Thin Film Transistor as the active element.
It is a transmissive type display operating in the normally black mode. It has a 46.96 inch diagonally measured
active display area with WUXGA resolution (1080 vertical by 1920horizontal pixel array).
Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arranged in vertical stripes.
Gray scale or the luminance of the sub-pixel color is determined with a 8-bit gray scale signal for each dot.
Therefore, it can present a palette of more than 16.7M(true) colors.
It is intended to support LCD TV, PCTV where high brightness, super wide viewing angle, high color gamut,
high color depth and fast response time are important.

Power (VCC, VDD, VGH, VGL)
Source Control Signal
Gate Control Signal
Gamma Reference Voltage
mini-LVDS (RGB) for Left drive

CN1

(60pin)

S1 S1920

G1

Source Driver Circuit

Power (VCC, VDD, VGH, VGL)
Source Control Signal
Gate Control Signal
Gamma Reference Voltage
mini-LVDS (RGB) for Right drive

General Features

Drive IC Data Interface

TFT -LCD Panel

(1920 × RGB × 1080 pixels)

CN2

(60pin)

G1080

46.96 inches(1192.78mm) diagonalActive Screen Size

1061.8 (H) x 606.8 (V) x 1.8 (D) mm (Typ.)Outline Dimension

0.5415 mm x 0.5415 mmPixel Pitch
1920 horiz. by 1080 vert. Pixels, RGB stripe arrangementPixel Format
8-bit, 16.7 M colorsColor Depth

Source D-IC : 8-bit mini-LVDS, gamma reference voltage, and control signals
Gate D-IC : Gate In Panel

Viewing angle free ( R/L 178 (Min.), U/D 178 (Min.))Viewing Angle (CR>10)

2.50Kg (Typ.) Weight
Transmissive mode, Normally blackDisplay Mode
Hard coating(3H), Anti-glare treatment (Haze 10%)Surface Treatment (Top)

[Gate In Panel]

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LC470MUK

Product Specification

2. Absolute Maximum Ratings

The following items are maximum values which, if exceeded, may cause faulty operation or damage to the
LCD module.

Table 1. ABSOLUTE MAXIMUM RATINGS

Parameter Symbol

Unit Note

Min Max

VDC+4.0-0.5VCCLogic Power Voltage
VDC+30.0+18.0VGHGate High Voltage
VDC-4.0-8.0VGLGate Low Voltage

Source D-IC Analog Voltage VDD -0.3 +18.0 VDC
Gamma Ref. Voltage (Upper) VGMH ½VDD-0.5 VDD+0.5 VDC
Gamma Ref. Voltage (Low) VGML -0.3 ½ VDD+0.5 VDC

Operating Temperature TOP 0 +50 °C
Storage Temperature TST -20 +60 °C
Operating Ambient Humidity HOP 10 90 %RH
Storage Humidity HST 10 90 %RH

Value

Note:

1. Ambient temperature condition (Ta = 25 ± 2 °C )

2. Temperature and relative humidity range are shown in the figure below. Wet bulb temperature
should be Max 39 °C and no condensation of water.

3. Gravity mura can be guaranteed below 40℃ condition.

4. The maximum operating temperature is based on the test condition that the surface temperature
of display area is less than or equal to 68 ℃ with LCD module alone in a temperature controlled
chamber. Thermal management should be considered in final product design to prevent the surface

temperature of display area from being over 68 ℃. The range of operating temperature may

degrade in case of improper thermal management in final product design.

90%

60

60%

1

4°C+68-TSURPanel Front Temperature

2,3

40

50

40%

10%

Wet Bulb
Temperature [°C]

30

20

10

0

10 20 30 40 50 60 70 800-20
Dry Bulb Temperature [°C]

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Storage

Operation

Humidity

[(%)RH]

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LC470MUK

Product Specification

3. Electrical Specifications

3-1. Electrical Characteristics

It requires several power inputs. The VCC is the basic power of LCD Driving power sequence, Which is used
to logic power voltage of Source D-IC and GIP.

Table 2. ELECTRICAL CHARACTERISTICS

Parameter Symbol Condition MIN TYP MAX Unit Note

Logic Power Voltage VCC - 3.0 3.3 3.6 VDC
Logic High Level Input Voltage VIH 2.7 VCC VDC
Logic Low Level Input Voltage VIL 0 0.6 VDC
Source D-IC Analog Voltage VDD - 15.3 15.5 15.7 VDC

Half Source D-IC Analog
Voltage

Gamma Reference Voltage

Mini-LVDS Clock frequency CLK 3.0V≤VCC ≤3.6V 312 MHz
mini-LVDS input Voltage
(Center)
mini-LVDS input Voltage
Distortion (Center)

mini-LVDS differential
Voltage range

mini-LVDS differential
Voltage range Dip

Gate Low Voltage VGL -5.2 -5.0 -4.8 VDC
GIP Bi-Scan Voltage

GIP Refresh Voltage
GIP Start Pulse Voltage VST - VGL - VGH V

GIP Operating Clock GCLK - VGL - VGH V
Total Power Current
Total Power Consumption

H_VDD - 7.45 7.68 7.82 VDC 7

V

GMH

V

GML

VcomCommon Voltage

VIB

ΔVIB 0.8 V

VID 150 800 mV

ΔVID 25 800 mV

VGHGate High Voltage

VGI_P
VGI_N

VGH

even/odd

ILCD - 800 1040 mA 2

PLCD - 8.53 11.09 Watt 2

(GMA1 ~ GMA9) ½*VDD VDD-0.2

(GMA10 ~ GMA18) 0.2 ½*VDD

Reverse 6.47 6.77 7.07 V

0.7 + (VID/2)

Mini-LVDS Clock

and Data

@ 0℃ 28.7 29 29.3 VDC

- VGL - VGH VDC

- VGL - VGH V

(VCC-1.2)

− VID / 2

V7.076.776.47Normal

V

VDC28.32827.7@ 25℃

5

Note:

1. The specified current and power consumption are under the VLCD=12V., 25 ± 2°C, fV=120Hz
condition whereas mosaic pattern(8 x 6) is displayed and fVis the frame frequency.

2. The above spec is based on the basic model.

3. All of the typical gate voltage should be controlled within 1% voltage level

4. Ripple voltage level is recommended under 10%

5. In case of mini-LVDS signal spec, refer to Fig 2 for the more detail.

6. Logic Level Input Signal : SOE,POL,GSP,H_CONV,OPT_N

7. HVDD Voltage level is half of VDD and it should be between Gamma9 and Gamma10.

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VCM (0V)

LC470MUK

Product Specification

VGH

VGHM

GND

VGL

Without GPM With GPM

FIG. 1 Gate Output Wave form without GPM and with GPM

VID

△VID

△VIB

VIB

VID

* Differential Probe

△VID

* Active Probe

FIG. 2 Description of VID, ΔVIB, ΔVID

* Source PCB

FIG. 3 Measure point

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LC470MUK

Product Specification

3-2. Interface Connections

This LCD panel employs two kinds of interface connection, two 60-pin FFC connector are used for the
module electronics.

3-2-1. LCD Module

-LCD Connector (CN1): TF06L-60S-0.5SH (Manufactured by HRS) or Equivalent

Table 4-1. MODULE CONNECTOR(CN1) PIN CONFIGURATION

DescriptionSymbolNoDescriptionSymbolNo

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

1

LTD OUTPUTLTD_OUT2
3
4
5
6
7
8
9

48GroundGND
49Driver Power Supply VoltageVDD
50Driver Power Supply VoltageVDD
51Half Driver Power Supply VoltageH_VDD
52Half Driver Power Supply VoltageH_VDD
53GroundGND
54Logic Power Supply VoltageVCC
55Logic Power Supply VoltageVCC
56GroundGND
57Left Mini LVDS Receiver Signal(5-) LLV5 ­58Left Mini LVDS Receiver Signal(5+) LLV5 +
59Left Mini LVDS Receiver Signal(4-) LLV4 -

Left Mini LVDS Receiver Signal(3-) LLV3 -31GroundGND
Left Mini LVDS Receiver Signal(3+) LLV3 +32
Left Mini LVDS Receiver Clock Signal(-) LCLK -33GIP GATE Clock 1GCLK1
Left Mini LVDS Receiver Clock Signal(+) LCLK +34GIP GATE Clock 2GCLK2
Left Mini LVDS Receiver Signal(2-) LLV2 -35GIP GATE Clock 3GCLK3
Left Mini LVDS Receiver Signal(2+) LLV2 +36GIP GATE Clock 4GCLK4
Left Mini LVDS Receiver Signal(1-) LLV1 -37GIP GATE Clock 5GCLK5
Left Mini LVDS Receiver Signal(1+) LLV1 +38GIP GATE Clock 6GCLK6
Left Mini LVDS Receiver Signal(0-) LLV0 -39GIP Bi-Scan (Normal =VGL Rotate = VGH)VGI_N
Left Mini LVDS Receiver Signal(0+) LLV0 +40GIP Bi-Scan (Normal =VGH Rotate = VGL)VGI_P
GroundGND41GIP Panel VDD for Odd GATE TFTVGH_ODD
Source Output Enable SIGNALSOE42GIP Panel VDD for Even GATE TFTVGH_EVEN
Polarity Control SignalPOL43GATE Low VoltageVGL
GATE Start PulseGSP44VERTICAL START PULSEVST
"H“ H 2dot Inversion/ "L" H 1dot InversionH_CONV45GroundGND
“H” Normal Display / “L” Rotation DisplayOPT_N46VCOM Left Feed-Back OutputVCOM_L_FB
GroundGND47VCOM Left InputVCOM_L

GAMMA VOLTAGE 18 (Output From LCD)GMA 18
GAMMA VOLTAGE 16GMA 16
GAMMA VOLTAGE 15GMA 15
GAMMA VOLTAGE 14GMA 14
GAMMA VOLTAGE 12GMA 12
GAMMA VOLTAGE 10 (Output From LCD)GMA 10
GAMMA VOLTAGE 9 (Output From LCD)GMA 9
GAMMA VOLTAGE 7GMA 7
GAMMA VOLTAGE 5GMA 5
GAMMA VOLTAGE 4GMA 4
GAMMA VOLTAGE 3GMA 3
GAMMA VOLTAGE 1 (Output From LCD)GMA 1

GroundGND60Left Mini LVDS Receiver Signal(4+) LLV4 +

Note :

1. Pleaserefer to application note for details.
(GIP & Half VDD & Gamma Voltage & H_CONV setting)

2. These 'input signal' (OPT_N,H_CONV) should be connected.

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Product Specification

-LCD Connector (CN2):TF06L-60S-0.5SH(Manufactured by HRS) or Equivalent

Table 4-2. MODULE CONNECTOR(CN2) PIN CONFIGURATION

LC470MUK

DescriptionSymbolNoDescriptionSymbolNo

14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

1

GAMMA VOLTAGE 1 (Output From LCD)GMA 12
GAMMA VOLTAGE 3GMA 33
GAMMA VOLTAGE 4GMA 44
GAMMA VOLTAGE 5GMA 55
GAMMA VOLTAGE 7GMA 76
GAMMA VOLTAGE 9 (Output From LCD)GMA 97
GAMMA VOLTAGE 10 (Output From LCD)GMA 108
GAMMA VOLTAGE 12GMA 129
GAMMA VOLTAGE 14GMA 1410
GAMMA VOLTAGE 15GMA 1511
GAMMA VOLTAGE 16GMA 1612
GAMMA VOLTAGE 18 (Output From LCD)GMA 1813

59Right Mini LVDS Receiver Signal(2-) RLV2 -

Right Mini LVDS Receiver Signal(1-) RLV1 -31GroundGND
Right Mini LVDS Receiver Signal(1+) RLV1 +32
Right Mini LVDS Receiver Signal(0-) RLV0 -33

Right Mini LVDS Receiver Signal(0+) RLV0 +34
GroundGND35
Logic Power Supply VoltageVCC36
Logic Power Supply VoltageVCC37
GroundGND38
Half Driver Power Supply VoltageH_VDD39
Half Driver Power Supply VoltageH_VDD40
Driver Power Supply VoltageVDD41
Driver Power Supply VoltageVDD42
GroundGND43
VCOM Right InputVCOM_R44GroundGND
VCOM Right Feed-Back OutputVCOM_R_FB45“H” Normal Display / “L” Rotation DisplayOPT_N
GroundGND46"H“ H 2dot Inversion/ "L" H 1dot InversionH_CONV
VERTICAL START PULSEVST47GATE Start PulseGSP
GATE Low VoltageVGL48Polarity Control SignalPOL
GIP Panel VDD for Even GATE TFTVGH_EVEN49Source Output Enable SIGNALSOE
GIP Panel VDD for Odd GATE TFTVGH_ODD50GroundGND
GIP Bi-Scan (Normal =VGH Rotate = VGL)VGI_P51Right Mini LVDS Receiver Signal(5-) RLV5 ­GIP Bi-Scan (Normal =VGL Rotate = VGH)VGI_N52Right Mini LVDS Receiver Signal(5+) RLV5 +
GIP GATE Clock 6GCLK653Right Mini LVDS Receiver Signal(4-) RLV4 ­GIP GATE Clock 5GCLK554Right Mini LVDS Receiver Signal(4+) RLV4 +
GIP GATE Clock 4GCLK455Right Mini LVDS Receiver Signal(3-) RLV3 ­GIP GATE Clock 3GCLK356Right Mini LVDS Receiver Signal(3+) RLV3 +
GIP GATE Clock 2GCLK257Right Mini LVDS Receiver Clock Signal(-) LCLK ­GIP GATE Clock 1GCLK158Right Mini LVDS Receiver Clock Signal(+) LCLK +

LTD OUTPUTLTD_OUT

GroundGND60Right Mini LVDS Receiver Signal(2+) RLV2 +

Note :

1. Pleaserefer to application note for details.
(GIP & Half VDD & Gamma Voltage & H_CONV setting)

2. These 'input signal' (OPT_N,H_CONV) should be connected.

CN 2

CN 1

Source Right PCB

#1 #60

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Source Left PCB

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