LG Display LC420EUG-RDA1 Specification

Engineering Specification

LCM ENGINEERING

SPECIFICATION

LC420EUG

Ver. 0.6

*MODEL LC420EUG

SUFFIX RDA1

Update Jan.28, 2010

( ) Preliminary Specification
(

) Final Specification

●

1 /32

Engineering Specification

4

OPTICAL SPECIFICATIONS

CONTENTS

LC420EUG

Number ITEM

COVER 1

CONTENTS

RECORD OF REVISIONS

1 GENERAL DESCRIPTION

2 ABSOLUTE MAXIMUM RATINGS

3 ELECTRICAL SPECIFICATIONS

3-1 ELECTRICAL CHARACTERISTICS

3-2 INTERFACE CONNECTIONS

3-3 SIGNAL TIMING SPECIFICATIONS

3-4 DATA MAPPING AND TIMING

3-5 PANEL PIXEL STRUCTURE

3-6 POWER SEQUENCE

5 MECHANICAL CHARACTERISTICS

Page

2

3

4

5

6

6

9

12

15

16

17

18

22

6 RELIABILITY

7 INTERNATIONAL STANDARDS

7-1 LED Array - SAFETY

7-2 ENVIRONMENT

8 PRECAUTIONS

8-1 MOUNTING PRECAUTIONS

8-2 OPERATING PRECAUTIONS

8-3 ELECTROSTATIC DISCHARGE CONTROL

8-4 PRECAUTIONS FOR STRONG LIGHT EXPOSURE

8-5 STORAGE

8-6 HANDLING PRECAUTIONS FOR PROTECTION FILM

Ver. 0.6

25

26

26

26

27

27

27

28

28

28

28

2 /32

Engineering Specification

0.6Jan.28.2011

12-

update T6/T7 data setup time/data hold time

RECORD OF REVISIONS

Revision No. Revision Date Page Description

0.1 Nov 05, 2010 - Final Specification (First Draft)

0.2 Nov 11, 2010 5 Update LED Input voltage (Forward voltage)

0.3 Dec 09, 2010 6, 8 Electrical spec is updated

12 Signal Timing is updated

18 Optical Spec is updated

23, 24 2D Drawing is updated.

31 LED Array spec is updated..

- Final Specification

0.4 Dec 20, 2010 25 Update Table 13. ENVIRONMENT TEST CONDITION

LC420EUG

0.5 Jan.13.2011 5

23.24

-Updated the Note: The storage test condition and the operating t

est condition

-updated mechanical drawing

Ver. 0.6

3 /32

LC420EUG

Engineering Specification

1. General Description

The LC420EUG is a Color Active Matrix Liquid Crystal Display with an integral Light Emitting Diode (LED)
backlight system . The matrix employs a-Si Thin Film Transistor as the active element.
It is a transmissive display type which is operating in the normally black mode. It has a 42.02 inch diagonally
measured active display area with WUXGA resolution (1080 vertical by 1920 horizontal pixel array).
Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arrayed in vertical stripes.
Gray scale or the luminance of the sub-pixel color is determined with a 8-bit gray scale signal for each dot.
Therefore, it can present a palette of more than 16.7M(true) colors.
It is intended to support LCD TV, PCTV where high brightness, super wide viewing angle, high color gamut,
high color depth and fast response time are important.

Power (VCC,VDD,HVDD,VGH,VGL)
Source Control Signal

Gate Control Signal

Gamma Reference Voltage
mini-LVDS (RGB) for Left drive

CN1

(60pin)

S1 S1920

G1

Source Driver Circuit

Power (VCC,VDD,HVDD,VGH,VGL)
Source Control Signal

Gate Control Signal

Gamma Reference Voltage
mini-LVDS (RGB) for Right drive

CN2

(60pin)

G1080

TFT - LCD Panel

(1920 × RGB × 1080 pixels)

General Features

Active Screen Size 42.02 inches(1067.31mm) diagonal

Outline Dimension

Pixel Pitch 0.4845 mm x 0.4845 mm

Pixel Format 1920 horiz. by 1080 vert. Pixels, RGB stripe arrangement

Color Depth

Drive IC Data Interface

Luminance, White 400 cd/m2 (Center 1point ,Typ.)
Viewing Angle (CR>10) Viewing angle free ( R/L 178 (Min.), U/D 178 (Min.))

968.4(H) × 564(V) X 10.8(B)/21.3 mm(D) (Typ.)

8bit, 16,7 M colors (※ 1.06B colors @ 10 bit (D) System Output )
Source D-IC : 8-bit mini-LVDS, gamma reference voltage, and control signals

Gate D-IC : Gate In Panel

[Gate In Panel]

Power Consumption Total 75.32W [Logic= 7.32W, LED Backlight = 68W]
Weight 7.0 Kg (Typ.)
Display Operating Mode Transmissive mode, normally black

Surface Treatment Hard coating(3H), Anti-glare treatment of the front polarizer (Haze 10%)

Ver. 0.6

4 /32

LC420EUG

Operating Ambient Humidity

HOP1090%RH

Engineering Specification

2. Absolute Maximum Ratings

The following items are maximum values which, if exceeded, may cause faulty operation or permanent damage
to the LCD module.

Table 1. ABSOLUTE MAXIMUM RATINGS

Parameter Symbol

Logic Power Voltage VCC -0.5 +4.0 VDC

Gate High Voltage VGH +18.0 +30.0 VDC

Gate Low Voltage VGL -8.0 -4.0 VDC

Value

Unit Note

Min Max

Source D-IC Analog Voltage VDD -0.3 +18.0 VDC

Gamma Ref. Voltage (Upper) VGMH ½VDD-0.5 VDD+0.5 VDC

Gamma Ref. Voltage (Low) VGML -0.3 ½ VDD+0.5 VDC

LED Input voltage (Forward voltage)

Vf - +58 VDC

Panel Front Temperature TSUR - +68

Operating Temperature TOP 0 +50

Storage Temperature TST -20 +60

Storage Humidity HST 10 90 %RH

Note

1. Ambient temperature condition (Ta = 25 ± 2 °C )

2. Temperature and relative humidity range are shown in the figure below.
Wet bulb temperature should be Max 39°C, and no condensation of water.

3. Gravity mura can be guaranteed below 40°C condition.

4. The maximum operating temperatures is based on the test condition that the surface temperature

of display area is less than or equal to 68°C with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature of
display area from being over 68℃. The range of operating temperature may be degraded in case of
improper thermal management in final product design.

5. The storage test condition:-20℃ temperature/90% humidity to 60℃ temperature/40% humidity ;

the operating test condition: 0℃ temperature/90% humidity to 50℃ temperature/60% humidity.

90%

60

60%

°C

°C

°C

1

4

2,3

Ver. 0.6

Wet Bulb
Temperature [°C]

20

10

0

10 20 30 40 50 60 70 800-20
Dry Bulb Temperature [°C]

30

40

50

40%

10%

Storage

Operation

Humidity [(%)RH]

5 /32

LC420EUG

Mini-LVDS Clock

Distortion (Center)

∆VIB--0.8

V

Engineering Specification

3. Electrical Specifications

3-1. Electrical Characteristics

It requires several power inputs. The VCC is the basic power of LCD Driving power sequence, Which is used
to logic power voltage of Source D-IC and GIP.

Table 2. DC ELECTRICAL CHARACTERISTICS

Parameter Symbol Condition MIN TYP MAX Unit

Logic Power Voltage VCC - 3.0 3.3 3.6 VDC

Logic High Level Input Voltage VIH - 2.7 - VCC VDC

Logic Low Level Input Voltage VIL - 0 - 0.6 VDC

Source D-IC Analog Voltage VDD - 16.5 16.7 16.9 VDC

Half Source D-IC Analog
Voltage

Gamma Reference Voltage

Common Voltage Vcom

Mini-LVDS Clock frequency CLK 3.0V≤VCC ≤3.6V - 156 MHz

mini-LVDS input Voltage
(Center)
mini-LVDS input Voltage

H_VDD - 8.13 8.35 8.57 VDC 7

V

V

GMH

GML

VIB

(GMA1 ~ GMA9) ½*VDD - VDD-0.2 VDC

(GMA10 ~ GMA18) 0.2 - ½*VDD VDC

Normal 6.75 7.05 7.35 V

Reverse 6.75 7.05 7.35 V

0.7 + (VID/2) -

(VCC-1.2)

− VID / 2

V

Not

e

mini-LVDS differential
Voltage range
mini-LVDS differential
Voltage range Dip

Gate High Voltage VGH

Gate Low Voltage VGL - -5.2 -5.0 -4.8 VDC

GIP Bi-Scan Voltage

GIP Refresh Voltage

GIP Start Pulse Voltage VST - VGL - VGH V
GIP Operating Clock GCLK - VGL - VGH V
Total Power Current
Total Power Consumption

VID 200 - 800 mV

∆VID 25 - 800 mV

VGI_P
VGI_N

VGH

even/odd

ILCD - 610 790 mA 1

PLCD - 7.32 8.05 Watt 1

Notes : 1. The specified current and power consumption are under the VLCD=12V., 25 ± 2°C, f

and Data

@ 25℃

@ 0℃

- VGL - VGH VDC

- VGL - VGH V

27.7 28 28.3 VDC

28.7 29 29.3 VDC

V

=60Hz

condition whereas mosaic pattern(8 x 6) is displayed and fVis the frame frequency.(with LGD T-Con board).

2. The above spec is based on the basic model.

3. All of the typical gate voltage should be controlled within 1% voltage level

4. Ripple voltage level is recommended under 10%

5. In case of mini-LVDS signal spec, refer to Fig 2 for the more detail.

6. Logic Level Input Signal : SOE,POL,GSP,H_CONV,OPT_N

7. HVDD Voltage level is half of VDD and it should be between Gamma9 and Gamma10.

Ver. 0.6

5

6 /32

VCM (0V)

VIB

VIB VIB

VIB

VIB

VIB VIB

VIB

VCM (0V)

VCM (0V) VCM (0V)

VGH

VGHM

GND

VGL

VID

VID

VIDVID

Engineering Specification

Without GPM With GPM

FIG. 1 Gate Output Wave form without GPM and with GPM

△△△△VID

VID

VID VID

LC420EUG

△△△△VIB

VIB

VIBVIB

VID

VID

VIDVID

* Differential Probe

* Differential Probe

* Differential Probe* Differential Probe

△△△△VID

VID

VID VID

* Active Probe

* Active Probe

* Active Probe* Active Probe

FIG. 2 Description of VID, ∆VIB, ∆VID

*

* Source PCB

Source PCB

* *

Source PCBSource PCB

FIG. 3 Measure point

Ver. 0.6

7 /32

Engineering Specification

LED and the driver (no lighting, flicker, etc) has never been occurred. When you confirm it, the LCD

–

Table 3. ELECTRICAL CHARACTERISTICS (Continue)Table 3. ELECTRICAL CHARACTERISTICS (Continue)

LC420EUG

Parameter Symbol

Backlight Assembly :

Forward Current
(one array)

Forward Voltage V
Forward Voltage Variation
Power Consumption P
Burst Dimming Duty On duty 1 100 %
Burst Dimming Frequency 1/T 95 182 Hz 8

LED Array : (APPENDIX-III)

Life Time 30,000 50,000 Hrs 7

Anode I
Cathode I

F (anode)

F (cathode)

F

△V

F

BL

Min Typ Max

90.25 95 99.75 mAdc

40.6 44.8 49 Vdc 4

61.2 68 74.5 W 6

Values

380 mAdc

1.7 Vdc 5

Unit Note

±5%

2, 3

Notes :
The design of the LED driver must have specifications for the LED array in LCD Assembly.

The electrical characteristics of LED driver are based on Constant Current driving type.
The performance of the LED in LCM, for example life time or brightness, is extremely influenced by the
characteristics of the LED Driver. So, all the parameters of an LED driver should be carefully designed.
When you design or order the LED driver, please make sure unwanted lighting caused by the mismatch of the

Assembly should be operated in the same condition as installed in your instrument.

1. Electrical characteristics are based on LED Array specification.

2. Specified values are defined for a Backlight Assembly. (IBL : 2 LED array)

3. Each LED array has 2 anode terminal and 8 cathode terminals.
The forward current(IF) of the anode terminal is 380mA and it supplies 95mA into four strings, respectively

(7 LED Package / 1string)

Cathode #1

95mA

Cathode #4

95mA

Cathode #5

95mA

Cathode #8

95mA

(8 LED String / 1 Array)

Anode

#1

Anode

#2

380mA

380mA

°

°

°

°

°

°

°

°

°

°

°

°

°°°° °°°° °°°°

°°°° °°°° °°°°

°

°

°

°

°

°

°

°

°

°

°

°

°°°° °°°° °°°°

°°°° °°°° °°°°

4. The forward voltage(VF) of LED array depends on ambient temperature.

5. ∆VFmeans Max VF-Min VFin one Backlight. So VFvariation in a Backlight isn’t over Max. 1.7V

6. Maximum level of power consumption is measured at initial turn on.
Typical level of power consumption is measured after 1hrs aging at 25 ± 2°C.

7. The life time(MTTF) is determined as the time at which brightness of the LED is 50% compared to that of
initial value at the typical LED current on condition of continuous operating at 25 ± 2°C, based on duty 100%.

8. The reference method of burst dimming duty ratio.
It is recommended to use synchronous V-sync frequency to prevent waterfall.(Vsync x 2 =Burst Frequency)
Though PWM frequency is over 120Hz (max 252Hz), function of LED Driver is not affected.

Ver. 0.6

8 /32

LC420EUG

Engineering Specification

3-2. Interface Connections

This LCD module employs two kinds of interface connection, two 60-pin FFC connector are used for the
module electronics and 12-pin,13-pin connectors are used for the integral backlight system.

3-2-1. LCD Module

-LCD Connector (CN1): TF06L-60S-0.5SH (Manufactured by HIROSE)

Table 4. MODULE CONNECTOR(CN1) PIN CONFIGURATION

No Symbol Description No Symbol Description

1 LTD_OUT LTD OUTPUT
2 NC No Connection
3

4
5
6
7
8

9
10
11
12
13

14

15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

GCLK1 GIP GATE Clock 1 33 LLV3 + Left Mini LVDS Receiver Signal(3+)
GCLK2 GIP GATE Clock 2 34 LCLK - Left Mini LVDS Receiver Clock Signal(-)
GCLK3 GIP GATE Clock 3 35 LCLK + Left Mini LVDS Receiver Clock Signal(+)
GCLK4 GIP GATE Clock 4 36 LLV2 - Left Mini LVDS Receiver Signal(2-)
GCLK5 GIP GATE Clock 5 37 LLV2 + Left Mini LVDS Receiver Signal(2+)
GCLK6 GIP GATE Clock 6 38 LLV1 - Left Mini LVDS Receiver Signal(1-)

VGI_N GIP Bi-Scan (Normal =VGL Rotate = VGH) 39 LLV1 + Left Mini LVDS Receiver Signal(1+)
VGI_P GIP Bi-Scan (Normal =VGH Rotate = VGL) 40 LLV0 - Left Mini LVDS Receiver Signal(0-)

VGH_ODD GIP Panel VDD for Odd GATE TFT 41 LLV0 + Left Mini LVDS Receiver Signal(0+)

VGH_EVEN GIP Panel VDD for Even GATE TFT 42 GND Ground

VGL GATE Low Voltage 43 SOE Source Output Enable SIGNAL
VST VERTICAL START PULSE 44 POL Polarity Control Signal

GIP_Reset GIP Reset 45 GSP GATE Start Pulse

VCOM_L_FB VCOM Left Feed-Back Output 46 H_CONV "H“ H 2dot Inversion/ "L" H 1dot Inversion

VCOM_L VCOM Left Input 47 OPT_N “H” Normal Display / “L” Rotation Display

GND Ground 48 GND Ground
GND Ground 49

VDD Driver Power Supply Voltage 50

VDD Driver Power Supply Voltage 51
H_VDD Half Driver Power Supply Voltage 52
H_VDD Half Driver Power Supply Voltage 53

GND Ground 54

VCC Logic Power Supply Voltage 55

VCC Logic Power Supply Voltage 56

GND Ground 57

LLV5 - Left Mini LVDS Receiver Signal(5-) 58

LLV5 + Left Mini LVDS Receiver Signal(5+) 59

LLV4 - Left Mini LVDS Receiver Signal(4-) 60

31 LLV4 + Left Mini LVDS Receiver Signal(4+)
32 LLV3 - Left Mini LVDS Receiver Signal(3-)

GMA 18 GAMMA VOLTAGE 18 (Output From LCD)
GMA 16 GAMMA VOLTAGE 16
GMA 15 GAMMA VOLTAGE 15
GMA 14 GAMMA VOLTAGE 14
GMA 12 GAMMA VOLTAGE 12
GMA 10 GAMMA VOLTAGE 10 (Output From LCD)

GMA 9 GAMMA VOLTAGE 9 (Output From LCD)
GMA 7 GAMMA VOLTAGE 7
GMA 5 GAMMA VOLTAGE 5
GMA 4 GAMMA VOLTAGE 4
GMA 3 GAMMA VOLTAGE 3
GMA 1 GAMMA VOLTAGE 1(Output From LCD)

Note :

1. Please refer to application note for details.
(GIP & Half VDD & Gamma Voltage & H_CONV setting)

2. These 'input signal' (OPT_N,H_CONV) should be connected

Ver. 0.6

9 /32

Engineering Specification

17

POL

Polarity Control Signal

47

VST

VERTICAL START PULSE

-LCD Connector (CN2): TF06L-60S-0.5SH (Manufactured by HIROSE)

Table 5. MODULE CONNECTOR(CN2) PIN CONFIGURATION

No Symbol Description No Symbol Description

LC420EUG

1 GMA 1 GAMMA VOLTAGE 1 (Output From LCD)
2 GMA 3 GAMMA VOLTAGE 3
3 GMA 4 GAMMA VOLTAGE 4

4 GMA 5 GAMMA VOLTAGE 5
5 GMA 7 GAMMA VOLTAGE 7
6 GMA 9 GAMMA VOLTAGE 9 (Output From LCD)
7 GMA 10 GAMMA VOLTAGE 10 (Output From LCD)
8 GMA 12 GAMMA VOLTAGE 12

9 GMA 14 GAMMA VOLTAGE 14
10 GMA 15 GAMMA VOLTAGE 15
11 GMA 16 GAMMA VOLTAGE 16
12 GMA 18 GAMMA VOLTAGE 18 (Output From LCD)
13
14
15
16

18
19
20
21
22
23
24
25
26
27
28
29
30

GND Ground 43 GND Ground

OPT_N “H” Normal Display / “L” Rotation Display 44 VCOM_R VCOM Right Input

H_CONV "H“ H 2dot Inversion/ "L" H 1dot Inversion 45 VCOM_R_FB VCOM Right Feed-Back Output

GSP GATE Start Pulse 46 GIP_Reset GIP Reset

SOE Source Output Enable SIGNAL 48 VGL GATE Low Voltage
GND Ground 49 VGH_EVEN GIP Panel VDD for Even GATE TFT

RLV5 - Right Mini LVDS Receiver Signal(5-) 50 VGH_ODD GIP Panel VDD for Odd GATE TFT

RLV5 + Right Mini LVDS Receiver Signal(5+) 51 VGI_P GIP Bi-Scan (Normal =VGH Rotate = VGL)

RLV4 - Right Mini LVDS Receiver Signal(4-) 52 VGI_N GIP Bi-Scan (Normal =VGL Rotate = VGH)

RLV4 + Right Mini LVDS Receiver Signal(4+) 53 GCLK6 GIP GATE Clock 6

RLV3 - Right Mini LVDS Receiver Signal(3-) 54 GCLK5 GIP GATE Clock 5
RLV3 + Right Mini LVDS Receiver Signal(3+) 55 GCLK4 GIP GATE Clock 4
RCLK - Right Mini LVDS Receiver Clock Signal(-) 56 GCLK3 GIP GATE Clock 3

RCLK + Right Mini LVDS Receiver Clock Signal(+) 57 GCLK2 GIP GATE Clock 2

RLV2 - Right Mini LVDS Receiver Signal(2-) 58 GCLK1 GIP GATE Clock 1
RLV2 + Right Mini LVDS Receiver Signal(2+) 59

RLV1 - Right Mini LVDS Receiver Signal(1-) 60

31 RLV1 + Right Mini LVDS Receiver Signal(1+)
32 RLV0 - Right Mini LVDS Receiver Signal(0-)
33 RLV0 + Right Mini LVDS Receiver Signal(0+)
34 GND Ground
35 VCC Logic Power Supply Voltage
36 VCC Logic Power Supply Voltage
37 GND Ground
38 H_VDD Half Driver Power Supply Voltage
39 H_VDD Half Driver Power Supply Voltage
40 VDD Driver Power Supply Voltage
41 VDD Driver Power Supply Voltage
42 GND Ground

NC No Connection

LTD_OUT LTD OUTPUT

Note :

Ver. 0.6

1. Please refer to application note for details
(GIP & Half VDD & Gamma Voltage & H_CONV setting)

2. These 'input signal' (OPT_N,H_CONV) should be connected

10 /32

3-2-2. Backlight Module

8

L5 Cathode

LED Output Current

LC420EUG

Engineering Specification

[ CN201 ]

1) LED Array assy Connector (Plug)
: 20022HS-13B2(BK) (manufactured by Yeonho)

2) Mating Connector (Receptacle)
: 20022WR-13BD (manufactured by Yeonho)

[ CN202 ]

1) LED Array assy Connector (Plug)
: 20022HS-12B2 (manufactured by Yeonho)

2) Mating Connector (Receptacle)

: 20022WR-12BD (manufactured by Yeonho )

Table 5. BACKLIGHT CONNECTOR PIN CONFIGURATION(CN201,CN202)

No Symbol

1

2
3
4
5
6
7

9
10
11
12

13

Anode_L1

(1~4Cathode)

N.C

L1 Cathode

L2 Cathode

L3 Cathode

L4 Cathode

N.C

L6 Cathode

L7 Cathode

L8 Cathode

N.C

Anode_L2

(5~8Cathode)

Description

LED Input Current

Open

LED Output Current

LED Output Current

LED Output Current

LED Output Current

Open

LED Output Current

LED Output Current

LED Output Current

Open

LED Input Current

Note

No Symbol

1

2
3
4
5
6
7
8

9
10
11

12

Anode_R2

(5~8Cathode)

N.C

R8Cathode

R7 Cathode

R6 Cathode

R5 Cathode

R4 Cathode

R3 Cathode

R2 Cathode

R1 Cathode

N.C

Anode_R1

(1~4Cathode)

◆ Rear view of LCM

Description

LED Input Current

Open

LED Output Current

LED Output Current

LED Output Current

LED Output Current

LED Output Current

LED Output Current

LED Output Current

LED Output Current

Open

LED Input Current

Note

Ver. 0.6

13pin 12pin

R8

R8

R8

L8

L8

L8

L8

L7

L7

L7

L6

L6L7

L6

L6

L5

L5

L5

L5

L4

L4

L4

L4

L3

L3

L3

L3

L2

L2

L2

L2

L1

L1

L1

L1

1

CN202CN201

Rear Side

R8

R7

R7

R7

R7

R6

R6

R6

R6

R5

R5

R5

R5

R4

R4

R4

R4

R3

R3

R3

R3

R2

R2

R2

R2

R1

R1

R1

R1

11 /32

3-3. Signal Timing Specification3-3. Signal Timing Specification

TABLE 7. Timing Requirements

LC420EUG

Engineering Specification

Parameter Symbol Condition Min Typ Max Units

Clock pulse period

Clock pulse low period

Clock pulse high period

Data setup time

Data hold time

Reset low to SOE rising time

SOE to Reset input time

Receiver off to SOE timing

POL signal SOE setup time

POL signal SOE hold time

Reset High Period

SOE signal GSP setup time

T1

T2

T3

T6

T7

T8

T9

T10

T11

T12

T13

T14

6.4 6.7 ns

3.2 - - ns

3.2 - - ns

1.1 - - ns

1.1 - - ns

0 - - ns

200 - - ns

10 - -

-5 - - ns

6 - - ns

Over 50ns & more over 3

CLK

- 100 - - ns

CLK

cycle

Note

1

-

Note :

Ver. 0.6

SOE signal GSP Hold time

SOE signal Pulse Width

T15

T16

- 100 - - ns

- 200 - - ns

1. Mini-LVDS timing measure conditions
: 126MHz < Clock Frequency < 156MHz , 200mV < VID < 800mV @ 3.0<VCC<3.3

2. Setup time and hold time couldn’t be satisfied at the same time

t1

70%

t7

t2

t5

70%

30%

t5

30%

30%

70%

30%

t4

70%

t4

CLK-

CLK+

LV0+, -

to

LV5+,-

t6 t7

50%

t3

t6

FIG 4. Source D-IC Input Data Latch Timing Waveform

VDIFF

VDIFF

12 /32

Engineering Specification

LC420EUG

CLK+

LV0+,-

LV1+,-

to

LV5+,-

SOE

Read The Reset=H

Read The Reset=L 1stDATA

T1

T2

T3

NA

R=H R=H R=H NAR=L R=L NA D D DR=L DD

T13

NA

T8

70%

30%

NA NA NA NANA NA NA D D DNA DD

T9

FIG 5-1. Input Data Timing for 1stSource D-IC Chip

Last DATA

Ver. 0.6

CLK+

LV0+,-

LV1+,-

to

LV5+,-

SOE

(640)

D D D

D D D

(641)

NA NA NA NA NA R=LNA R=L R=L

NA NA NA NA NA NANA NA NA

T10

FIG 5-2. Last Data Latch to SOE Timing

T8

70%

30%

13 /32

Engineering Specification

LC420EUG

SOE

POL

GSP

GSP

70%

T16

T14

T11

70%

30%

30%

70%

T15

T12

70%

30%

70%

30%

70%

Ver. 0.6

SOE

1stline data 1stline output

FIG 6. POL, GSP and SOE Timing Waveform

14 /32

LC420EUG

Engineering Specification

3-4. Data Mapping and Timing

Display data and control signal (RESET) are input to LV0 to LV5. Data mapping is changed in response to
mode, and the mode is changed by mode.

3-4-1. Control signal input mode

CLK +

LV0 +

RESET RESET RESET RESET RESET RESET RESET RESET RESET RESET

3-4-2. Display data input mode

CLK+

LV0+

LV1+

LV2+

LV3+

LV4+

LV5+

Note :

1. For data mapping, please refer to panel pixel structure Fig.8

D01 D02 D03 D04 D05 D06D00

D11 D12 D13 D14 D15 D16D10 D17

D21 D22 D23 D24 D25 D26D20 D27

D31 D32 D33 D34 D35 D36D30 D37

D41 D42 D43 D44 D45 D46D40 D47

D51 D52 D53 D54 D55 D56D50 D57

DATA INPUT CYCLE

D07 D00

Fig. 7 Mini-LVDS Data

D10

D20

D30

D40

D50

Ver. 0.6

15 /32

3-5. Panel Pixel Structure

G1078

D1 D2 D3 D4 D5 D5758 D5759 D5760 D5761

G1

G2

G3

G4

G5

G6

LC420EUG

Engineering Specification

G1079

G1080

FIG. 8 Panel Pixel Structure

Ver. 0.6

16 /32

3-6. Power Sequence

GCLK

1~6

3-6-1. LCD Driving circuit

Power Supply For LCD
VCC

Power Supply For LCD
VDD, HVDD,VGH, Gamma Ref.
Voltage

Power Supply For LCD
VGL

0V

0V

Engineering Specification

70%

T2

50%

100%

T1

VGH

90%

LC420EUG

T7

GIP Signal For LCD

Power For LED

Table 9. POWER SEQUENCE

Parameter

T1 0.5 - ms
T2 0.5

T3 0

T4 10
T5 0 - ms

T6 / T6’ 20 - ms

T7 2 - sec

Note : 1. Power sequence for Source D-IC must follow the Case1 & 2.

※ Please refer to Appendix I I for more details.

2. VGH Odd signal should be started “High” status and VGH even & odd can not be “High at the
same time.

3. Power Off Sequence order is reverse of Power On Condition including Source D-IC.

4. GCLK On/Off Sequence
Normal : GCLK4  GCLK5  GCLK6  GCLK1  GCLK2  GCLK3.
Reverse :GCLK3  GCLK2 GCLK1  GCLK6  GCLK5  GCLK4.

5. VDD_odd/even transition time should be within V_ blank

6. Incase of T6’, If there is no abnormal display, no problem

Ver. 0.6

VGH
even/Odd

VST

Min Typ Max

T3

T4

Value

T5

..

..

..

T6

LED on

Ta= 25±2°C, fV=60Hz, Clk=148.5MHz

-

-

-

T6’

Unit Notes

ms

ms

ms 2

17 /32

LC420EUG

Contrast Ratio

CR

1100

1600

-

1

Engineering Specification

4. Optical Specification

Optical characteristics are determined after the unit has been ‘ON’ and stable in a dark environment at 25±2°C.
The values are specified at distance 50cm from the LCD surface at a viewing angle of Φ and θ equal to 0 °.

FIG. 9 shows additional information concerning the measurement equipment and method.

Optical Stage(x,y)

LCD Module

Pritchard 880 or
equivalent

50cm

FIG. 9 Optical Characteristic Measurement Equipment and Method

Ta= 25±2°C, VDD,H_VDD,VGH,VGL=typ.

Table 10. OPTICAL CHARACTERISTICS

Parameter Symbol

Surface Luminance, white L
Luminance Variation δ

Variation G to G

Response Time

Color Coordinates
[CIE1931]

Color Temperature 10,000 K
Color Gamut 72 %

Viewing Angle (CR>10)

x axis, right(φ=0°)
x axis, left (φ=180°)
y axis, up (φ=90°)
y axis, down (φ=270°)

Gray Scale - - - 7

Gray to Gray

(BW)

RED

GREEN

BLUE

WHITE

WH

WHITE

G to G BW - 8 12 ms

5P - - 1.3 3

σ

Rx
Ry 0.333
Gx 0.306
Gy 0.604
Bx 0.150

By 0.058
Wx 0.279
Wy 0.292

θr 89 - -

θl 89 - -
θu 89 - -
θd 89 - -

Min Typ Max

320 400 - cd/m

- 6 9 ms

Typ

-0.03

Value

0.644

, fV=60Hz,Clk=148.5MHz, Vf/If = typ.

Unit Note

2

Typ

+0.03

degree 6

2

4

Ver. 0.6

18 /32

Engineering Specification

is normal to the LCD module surface. For more information, see the FIG. 12.

Note : 1. Contrast Ratio(CR) is defined mathematically as

LC420EUG

Contrast Ratio =

Surface Luminance with all white pixels
Surface Luminance with all black pixels

It is measured at center 1-point.

2. Surface luminance are determined after the unit has been ‘ON’ and 1 Hour after lighting the
backlight in a dark environment at 25±2°C. Surface luminance is the luminance value at center
1-point across the LCD surface 50cm from the surface with all pixels displaying white.
For more information see the FIG. 10.

3. The variation in surface luminance , δ WHITE is defined as :
δ WHITE(5P) = Maximum(L
Where L

on1

to L

are the luminance with all pixels displaying white at 5 locations .

on5

on1,Lon2

For more information, see the FIG. 10.

4. Response time is the time required for the display to transit from any gray to white (Rise Time, TrR)
and from any gray to black (Decay time, TrD). For additional information see the FIG. 11.

※ G to GBWSpec stands for average value of all measured points.

Photo Detector : RD-80S / Field : 2 °

5. G to G σ is Variation of Gray to Gray response time composing a picture

G to G (σ) =

√

Σ(Xi- u)

N

6. Viewing angle is the angle at which the contrast ratio is greater than 10. The angles are

determined for the horizontal or x axis and the vertical or y axis with respect to the z axis which

7. Gray scale specification

Gamma Value is approximately 2.2. For more information, see the Table 11.

Table 11. GRAY SCALE SPECIFICATION

, L

2

, L

, L

on3

on4

) / Minimum(L

on5

Xi = Individual Data
u = Data average
N : The number of Data

on1,Lon2

, L

on3

, L

on4

, L

on5

)

Gray Level Luminance [%] (Typ)

L0 0.06
L15 0.27
L31 1.04
L47 2.49
L63 4.68
L79 7.66
L95 11.5

L111 16.1
L127 21.6
L143 28.1
L159 35.4
L175 43.7
L191 53.0
L207 63.2
L223 74.5

L239 86.7
L255 100

Ver. 0.6

Positive
Voltage

Negative

Voltage

Gray Level Gamma Ref.

L0 Gamma9

L1 Gamma8
L31 Gamma7
L63 Gamma6

L127 Gamma5
L191 Gamma4
L223 Gamma3
L255 Gamma1
L255 Gamma18
L223 Gamma16
L191 Gamma15
L127 Gamma14

L63 Gamma13
L31 Gamma12

L1 Gamma11

L0 Gamma10

19 /32

Engineering Specification

Measuring point for surface luminance & measuring point for luminance variation.

H

A

③③③③②②②②

LC420EUG

V

①①①①

B

A : H / 4 mm

④④④④

FIG. 10 5 Points for Luminance Measure

Response time is defined as the following figure and shall be measured by switching the input signal for
“Gray(N)” and “Gray(M)”.

TrR

100

90

⑤⑤⑤⑤

TrD

B : V / 4 mm
@ H,V : Active Area

Ver. 0.6

Optical
Response

10

0

Gray(N)

N,M = Black~White, N<M

FIG. 11 Response Time

Gray(M)

Gray(N)

20 /32

Dimension of viewing angle range

LC420EUG

Engineering Specification

φ

= 180°, Left

φ

= 270°, Down

Normal

E

θ

φ

FIG. 12 Viewing Angle

Y

φ

= 90°, Up

φ

= 0°, Right

Ver. 0.6

21 /32

Engineering Specification

Note : Please refer to a mechanical drawing in terms of tolerance at the next page.

5. Mechanical Characteristics

Table 12 provides general mechanical characteristics.

Table 12. MECHANICAL CHARACTERISTICS

Item Value

Horizontal 968.4 mm

LC420EUG

Outline Dimension

Bezel Area

Active Display Area

Weight

Vertical 564.0 mm

Depth 21.3 mm

Horizontal 944.8 mm (*1)

Vertical 531.0 mm

Horizontal 930.24 mm

Vertical 523.26 mm

7.0 Kg (Typ.), 7.4 kg (Max.)

*1: The horizontal dimension of bezel area is based on polarizer.

Ver. 0.6

22 /32

[ FRONT VIEW ]

LC420EUG

Engineering Specification

Set : Top

Set : Down

Ver. 0.6

23 /32

[ REAR VIEW ]

LC420EUG

Engineering Specification

Ver. 0.6

24 /32

Engineering Specification

6. Reliability

Table 13. ENVIRONMENT TEST CONDITION

No. Test Item Condition

LC420EUG

1 High temperature storage test

2 Low temperature storage test

3 High temperature operation test

4 Low temperature operation test

5 Humidity condition Operation

Ta= 60°C 240h

Ta= -20°C 240h

Ta= 50°C 50%RH 240h

Ta= 0°C 240h

Ta= 40 °C ,90%RH

Note : Before and after Reliability test, LCM should be operated with normal function.

Ver. 0.6

25 /32

Engineering Specification

7. International Standards

7-1. LED Array - Safty

1. Laser (LED Backlight) Information

Class 1M LED Product

IEC60825-1 : 2001

Embedded LED Power (Class 1M)

2. Caution
: LED inside.

Class 1M laser (LEDs) radiation when open.
Do not open while operating.

7-2. Environment

a) RoHS, Directive 2002/95/EC of the European Parliament and of the council of 27 January 2003

LC420EUG

Ver. 0.6

26 /32

LC420EUG

(8) Wipe off saliva or water drops as soon as possible. Their long time contact with polarizer causes

Engineering Specification

8. Precautions

Please pay attention to the followings when you use this TFT LCD module.

8-1. Mounting Precautions

(1) You must mount a module using specified mounting holes (Details refer to the drawings).
(2) You should consider the mounting structure so that uneven force (ex. Twisted stress) is not applied to

the module. And the case on which a module is mounted should have sufficient strength so that external

force is not transmitted directly to the module.

(3) Please attach the surface transparent protective plate to the surface in order to protect the polarizer.

Transparent protective plate should have sufficient strength in order to the resist external force.
(4) You should adopt radiation structure to satisfy the temperature specification.
(5) Acetic acid type and chlorine type materials for the cover case are not desirable because the former

generates corrosive gas of attacking the polarizer at high temperature and the latter causes circuit break
by electro-chemical reaction.

(6) Do not touch, push or rub the exposed polarizers with glass, tweezers or anything harder than HB

pencil lead. And please do not rub with dust clothes with chemical treatment.

Do not touch the surface of polarizer for bare hand or greasy cloth.(Some cosmetics are detrimental

to the polarizer.)
(7) When the surface becomes dusty, please wipe gently with absorbent cotton or other soft materials like

chamois soaks with petroleum benzine. Normal-hexane is recommended for cleaning the adhesives
used to attach front / rear polarizers. Do not use acetone, toluene and alcohol because they cause
chemical damage to the polarizer

deformations and color fading.

(9) Do not open the case because inside circuits do not have sufficient strength.

8-2. Operating Precautions

(1) The spike noise causes the mis-operation of circuits. It should be lower than following voltage :

V=±200mV(Over and under shoot voltage)
(2) Response time depends on the temperature.(In lower temperature, it becomes longer.)
(3) Brightness depends on the temperature. (In lower temperature, it becomes lower.)

And in lower temperature, response time(required time that brightness is stable after turned on)
becomes longer

(4) Be careful for condensation at sudden temperature change.Condensation makes damage to polarizer or

electrical contacted parts. And after fading condensation, smear or spot will occur.
(5) When fixed patterns are displayed for a long time, remnant image is likely to occur.
(6) Module has high frequency circuits. Sufficient suppression to the electromagnetic interference shall be

done by system manufacturers. Grounding and shielding methods may be important to minimized the
interference.

(7) Please do not give any mechanical and/or acoustical impact to LCM. Otherwise, LCM can’t be operated

its full characteristics perfectly.

(8) A screw which is fastened up the steels should be a machine screw.

(if not, it can causes conductive particles and deal LCM a fatal blow)
(9) Please do not set LCD on its edge.
(10) The conductive material and signal cables are kept away from LED driver inductor to prevent abnormal

display, sound noise and temperature rising.

Ver. 0.6

27 /32

LC420EUG

8-6. Handling Precautions for Protection Film

Engineering Specification

8-3. Electrostatic Discharge Control

Since a module is composed of electronic circuits, it is not strong to electrostatic discharge. Make certain that
treatment persons are connected to ground through wrist band etc. And don’t touch interface pin directly.

8-4. Precautions for Strong Light Exposure

Strong light exposure causes degradation of polarizer and color filter.

8-5. Storage

When storing modules as spares for a long time, the following precautions are necessary.

(1) Store them in a dark place. Do not expose the module to sunlight or fluorescent light. Keep the temperature

between 5°C and 35°C at normal humidity.

(2) The polarizer surface should not come in contact with any other object.

It is recommended that they be stored in the container in which they were shipped.
(3) Storage condition is guaranteed under packing conditions.
(4) The phase transition of Liquid Crystal could be recovered if the LCM is released at the normal condition
after the low or over the storage temperature.

(1) The protection film is attached to the bezel with a small masking tape.

When the protection film is peeled off, static electricity is generated between the film and polarizer.

This should be peeled off slowly and carefully by people who are electrically grounded and with well ion-

blown equipment or in such a condition, etc.
(2) When the module with protection film attached is stored for a long time, sometimes there remains a very

small amount of glue still on the bezel after the protection film is peeled off.
(3) You can remove the glue easily. When the glue remains on the bezel surface or its vestige is recognized,

please wipe them off with absorbent cotton waste or other soft material like chamois soaked with normal-

hexane.

Ver. 0.6

28 /32

# APPENDIX- I

■ LCM Label

Model

LC420EUG

LC420EUG

LC420EUGLC420EUG

(RD)(A1)

(RD)(A1)

(RD)(A1)(RD)(A1)

LC420EUG

Engineering Specification

UL, TUV Mark

LGD Logo

US PATENT No.

420

420

420420

LIGHT GUIDE:>PMMA<

LIGHT GUIDE:>PMMA<

LIGHT GUIDE:>PMMA<LIGHT GUIDE:>PMMA<

Serial No.

Origin

Ver. 0.6

29 /34

# APPENDIX- I I

■ LCM Source power sequence

< Source power sequence >

LC420EUG

Engineering Specification

- Input Signal : SOE,POL,GSP,H_CONV,OPT_N

Ver. 0.6

30 /32

Engineering Specification

# APPENDIX- III

■■■■ LED Array Electrical Spec

■■■■ Forward Current vs. Forward Voltage

LC420EUG

■■■■ Ambient Temperature vs. Forward Voltage

Ver. 0.6

31 /32

Engineering Specification

# APPENDIX- IV

■■■■ Local Dimming Block Pin Matching

L R

L1

L1

L1

L1

L2

L2

L2

L2

L3

L3

L3

L3

L4

L4

L4

L4

L5

L5

L5

L5

L6

L6

L6

L6

L7

L7

L7

L7

L8

L8

L8

L8

L8

L8

L8

L8

L7

L7

L7

L7

L6

L6

L6

L6

L5

L5

L5

L5

L4

L4

L4

L4

L3

L3

L3

L3

T-con

Front Side

R1

R1

R1

R1

R2

R2

R2

R2

R3

R3

R3

R3

R4

R4

R4

R4

R5

R5

R5

R5

R6

R6

R6

R6

R7

R7

R7

R7

R8

R8

R8

R8

R8

R8

R8

R8

R7

R7

R7

R7

R6

R6

R6

R6

R5

R5

R5

R5

R4

R4

R4

R4

R3

R3

R3

R3

LC420EUG

LED Driver CNT

Pin No CN_201 CN_202

1

2

3

4

5

6

7

8

9

10

11

12

13

Anode_L1

(1~4Cathode)

N.C N.C
L1 Cathode R8Cathode
L2 Cathode R7 Cathode
L3 Cathode R6 Cathode
L4 Cathode R5 Cathode

N.C R4 Cathode
L5 Cathode R3 Cathode
L6 Cathode R2 Cathode
L7 Cathode R1 Cathode
L8 Cathode N.C

N.C

Anode_L2

(5~8Cathode)

Anode_R2

(5~8Cathode)

Anode_R1

(1~4Cathode)

-

L2

L2

L2

L2

L1

L1

L1

L1

Ver. 0.6

T-con

Rear Side

R2

R2

R2

R2

R1

R1

R1

R1

32 /32