LG Display LC420EUG-RDA1 Specification

Engineering Specification

LCM ENGINEERING

SPECIFICATION

LC420EUG

Ver. 0.6

*MODEL LC420EUG

SUFFIX RDA1

Update Jan.28, 2010

( ) Preliminary Specification (

) Final Specification

●

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Engineering Specification

OPTICAL SPECIFICATIONS

CONTENTS

LC420EUG

Number ITEM

COVER 1

CONTENTS

RECORD OF REVISIONS

1 GENERAL DESCRIPTION

2 ABSOLUTE MAXIMUM RATINGS

3 ELECTRICAL SPECIFICATIONS

3-1 ELECTRICAL CHARACTERISTICS

3-2 INTERFACE CONNECTIONS

3-3 SIGNAL TIMING SPECIFICATIONS

3-4 DATA MAPPING AND TIMING

3-5 PANEL PIXEL STRUCTURE

3-6 POWER SEQUENCE

5 MECHANICAL CHARACTERISTICS

Page

6 RELIABILITY

7 INTERNATIONAL STANDARDS

7-1 LED Array - SAFETY

7-2 ENVIRONMENT

8 PRECAUTIONS

8-1 MOUNTING PRECAUTIONS

8-2 OPERATING PRECAUTIONS

8-3 ELECTROSTATIC DISCHARGE CONTROL

8-4 PRECAUTIONS FOR STRONG LIGHT EXPOSURE

8-5 STORAGE

8-6 HANDLING PRECAUTIONS FOR PROTECTION FILM

Ver. 0.6

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Engineering Specification

0.6Jan.28.2011

12-

update T6/T7 data setup time/data hold time

RECORD OF REVISIONS

Revision No. Revision Date Page Description

0.1 Nov 05, 2010 - Final Specification (First Draft)

0.2 Nov 11, 2010 5 Update LED Input voltage (Forward voltage)

0.3 Dec 09, 2010 6, 8 Electrical spec is updated

12 Signal Timing is updated

18 Optical Spec is updated

23, 24 2D Drawing is updated.

31 LED Array spec is updated..

- Final Specification

0.4 Dec 20, 2010 25 Update Table 13. ENVIRONMENT TEST CONDITION

LC420EUG

0.5 Jan.13.2011 5

23.24

-Updated the Note: The storage test condition and the operating t

est condition

-updated mechanical drawing

Ver. 0.6

3 /32

LC420EUG

Engineering Specification

1. General Description

The LC420EUG is a Color Active Matrix Liquid Crystal Display with an integral Light Emitting Diode (LED) backlight system . The matrix employs a-Si Thin Film Transistor as the active element. It is a transmissive display type which is operating in the normally black mode. It has a 42.02 inch diagonally measured active display area with WUXGA resolution (1080 vertical by 1920 horizontal pixel array). Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arrayed in vertical stripes. Gray scale or the luminance of the sub-pixel color is determined with a 8-bit gray scale signal for each dot. Therefore, it can present a palette of more than 16.7M(true) colors. It is intended to support LCD TV, PCTV where high brightness, super wide viewing angle, high color gamut, high color depth and fast response time are important.

Power (VCC,VDD,HVDD,VGH,VGL) Source Control Signal

Gate Control Signal

Gamma Reference Voltage mini-LVDS (RGB) for Left drive

CN1

(60pin)

S1 S1920

Source Driver Circuit

Power (VCC,VDD,HVDD,VGH,VGL) Source Control Signal

Gate Control Signal

Gamma Reference Voltage mini-LVDS (RGB) for Right drive

CN2

(60pin)

G1080

TFT - LCD Panel

(1920 × RGB × 1080 pixels)

General Features

Active Screen Size 42.02 inches(1067.31mm) diagonal

Outline Dimension

Pixel Pitch 0.4845 mm x 0.4845 mm

Pixel Format 1920 horiz. by 1080 vert. Pixels, RGB stripe arrangement

Color Depth

Drive IC Data Interface

Luminance, White 400 cd/m2 (Center 1point ,Typ.) Viewing Angle (CR>10) Viewing angle free ( R/L 178 (Min.), U/D 178 (Min.))

968.4(H) × 564(V) X 10.8(B)/21.3 mm(D) (Typ.)

8bit, 16,7 M colors (※ 1.06B colors @ 10 bit (D) System Output ) Source D-IC : 8-bit mini-LVDS, gamma reference voltage, and control signals

Gate D-IC : Gate In Panel

[Gate In Panel]

Power Consumption Total 75.32W [Logic= 7.32W, LED Backlight = 68W] Weight 7.0 Kg (Typ.) Display Operating Mode Transmissive mode, normally black

Surface Treatment Hard coating(3H), Anti-glare treatment of the front polarizer (Haze 10%)

Ver. 0.6

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LC420EUG

Operating Ambient Humidity

HOP1090%RH

Engineering Specification

2. Absolute Maximum Ratings

The following items are maximum values which, if exceeded, may cause faulty operation or permanent damage to the LCD module.

Table 1. ABSOLUTE MAXIMUM RATINGS

Parameter Symbol

Logic Power Voltage VCC -0.5 +4.0 VDC

Gate High Voltage VGH +18.0 +30.0 VDC

Gate Low Voltage VGL -8.0 -4.0 VDC

Value

Unit Note

Min Max

Source D-IC Analog Voltage VDD -0.3 +18.0 VDC

Gamma Ref. Voltage (Upper) VGMH ½VDD-0.5 VDD+0.5 VDC

Gamma Ref. Voltage (Low) VGML -0.3 ½ VDD+0.5 VDC

LED Input voltage (Forward voltage)

Vf - +58 VDC

Panel Front Temperature TSUR - +68

Operating Temperature TOP 0 +50

Storage Temperature TST -20 +60

Storage Humidity HST 10 90 %RH

Note

1. Ambient temperature condition (Ta = 25 ± 2 °C )

2. Temperature and relative humidity range are shown in the figure below. Wet bulb temperature should be Max 39°C, and no condensation of water.

3. Gravity mura can be guaranteed below 40°C condition.

4. The maximum operating temperatures is based on the test condition that the surface temperature

of display area is less than or equal to 68°C with LCD module alone in a temperature controlled chamber. Thermal management should be considered in final product design to prevent the surface temperature of display area from being over 68℃. The range of operating temperature may be degraded in case of improper thermal management in final product design.

5. The storage test condition:-20℃ temperature/90% humidity to 60℃ temperature/40% humidity ;

the operating test condition: 0℃ temperature/90% humidity to 50℃ temperature/60% humidity.

90%

60%

°C

2,3

Ver. 0.6

Wet Bulb Temperature [°C]

10 20 30 40 50 60 70 800-20 Dry Bulb Temperature [°C]

40%

10%

Storage

Operation

Humidity [(%)RH]

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LC420EUG

Mini-LVDS Clock

Distortion (Center)

∆VIB--0.8

Engineering Specification

3. Electrical Specifications

3-1. Electrical Characteristics

It requires several power inputs. The VCC is the basic power of LCD Driving power sequence, Which is used to logic power voltage of Source D-IC and GIP.

Table 2. DC ELECTRICAL CHARACTERISTICS

Parameter Symbol Condition MIN TYP MAX Unit

Logic Power Voltage VCC - 3.0 3.3 3.6 VDC

Logic High Level Input Voltage VIH - 2.7 - VCC VDC

Logic Low Level Input Voltage VIL - 0 - 0.6 VDC

Source D-IC Analog Voltage VDD - 16.5 16.7 16.9 VDC

Half Source D-IC Analog Voltage

Gamma Reference Voltage

Common Voltage Vcom

Mini-LVDS Clock frequency CLK 3.0V≤VCC ≤3.6V - 156 MHz

mini-LVDS input Voltage (Center) mini-LVDS input Voltage

H_VDD - 8.13 8.35 8.57 VDC 7

GMH

GML

VIB

(GMA1 ~ GMA9) ½*VDD - VDD-0.2 VDC

(GMA10 ~ GMA18) 0.2 - ½*VDD VDC

Normal 6.75 7.05 7.35 V

Reverse 6.75 7.05 7.35 V

0.7 + (VID/2) -

(VCC-1.2)

− VID / 2

Not

mini-LVDS differential Voltage range mini-LVDS differential Voltage range Dip

Gate High Voltage VGH

Gate Low Voltage VGL - -5.2 -5.0 -4.8 VDC

GIP Bi-Scan Voltage

GIP Refresh Voltage

GIP Start Pulse Voltage VST - VGL - VGH V GIP Operating Clock GCLK - VGL - VGH V Total Power Current Total Power Consumption

VID 200 - 800 mV

∆VID 25 - 800 mV

VGI_P VGI_N

VGH

even/odd

ILCD - 610 790 mA 1

PLCD - 7.32 8.05 Watt 1

Notes : 1. The specified current and power consumption are under the VLCD=12V., 25 ± 2°C, f

and Data

@ 25℃

@ 0℃

- VGL - VGH VDC

- VGL - VGH V

27.7 28 28.3 VDC

28.7 29 29.3 VDC

=60Hz

condition whereas mosaic pattern(8 x 6) is displayed and fVis the frame frequency.(with LGD T-Con board).

2. The above spec is based on the basic model.

3. All of the typical gate voltage should be controlled within 1% voltage level

4. Ripple voltage level is recommended under 10%

5. In case of mini-LVDS signal spec, refer to Fig 2 for the more detail.

6. Logic Level Input Signal : SOE,POL,GSP,H_CONV,OPT_N

7. HVDD Voltage level is half of VDD and it should be between Gamma9 and Gamma10.

Ver. 0.6

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VCM (0V)

VIB

VIB VIB

VIB

VIB VIB

VIB

VCM (0V)

VCM (0V) VCM (0V)

VGH

VGHM

GND

VGL

VID

VIDVID

Engineering Specification

Without GPM With GPM

FIG. 1 Gate Output Wave form without GPM and with GPM

△△△△VID

VID

VID VID

LC420EUG

△△△△VIB

VIB

VIBVIB

VID

VIDVID

* Differential Probe

* Differential Probe* Differential Probe

△△△△VID

VID

VID VID

* Active Probe

* Active Probe* Active Probe

FIG. 2 Description of VID, ∆VIB, ∆VID

* Source PCB

Source PCB

* *

Source PCBSource PCB

FIG. 3 Measure point

Ver. 0.6

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Engineering Specification

LED and the driver (no lighting, flicker, etc) has never been occurred. When you confirm it, the LCD

–

Table 3. ELECTRICAL CHARACTERISTICS (Continue)Table 3. ELECTRICAL CHARACTERISTICS (Continue)

LC420EUG

Parameter Symbol

Backlight Assembly :

Forward Current (one array)

Forward Voltage V Forward Voltage Variation Power Consumption P Burst Dimming Duty On duty 1 100 % Burst Dimming Frequency 1/T 95 182 Hz 8

LED Array : (APPENDIX-III)

Life Time 30,000 50,000 Hrs 7

Anode I Cathode I

F (anode)

F (cathode)

△V

Min Typ Max

90.25 95 99.75 mAdc

40.6 44.8 49 Vdc 4

61.2 68 74.5 W 6

Values

380 mAdc

1.7 Vdc 5

Unit Note

±5%

2, 3

Notes : The design of the LED driver must have specifications for the LED array in LCD Assembly.

The electrical characteristics of LED driver are based on Constant Current driving type. The performance of the LED in LCM, for example life time or brightness, is extremely influenced by the characteristics of the LED Driver. So, all the parameters of an LED driver should be carefully designed. When you design or order the LED driver, please make sure unwanted lighting caused by the mismatch of the

Assembly should be operated in the same condition as installed in your instrument.

1. Electrical characteristics are based on LED Array specification.

2. Specified values are defined for a Backlight Assembly. (IBL : 2 LED array)

3. Each LED array has 2 anode terminal and 8 cathode terminals. The forward current(IF) of the anode terminal is 380mA and it supplies 95mA into four strings, respectively

(7 LED Package / 1string)

Cathode #1

95mA

Cathode #4

95mA

Cathode #5

95mA

Cathode #8

95mA

(8 LED String / 1 Array)

Anode

380mA

°°°° °°°° °°°°

4. The forward voltage(VF) of LED array depends on ambient temperature.

5. ∆VFmeans Max VF-Min VFin one Backlight. So VFvariation in a Backlight isn’t over Max. 1.7V

6. Maximum level of power consumption is measured at initial turn on. Typical level of power consumption is measured after 1hrs aging at 25 ± 2°C.

7. The life time(MTTF) is determined as the time at which brightness of the LED is 50% compared to that of initial value at the typical LED current on condition of continuous operating at 25 ± 2°C, based on duty 100%.

8. The reference method of burst dimming duty ratio. It is recommended to use synchronous V-sync frequency to prevent waterfall.(Vsync x 2 =Burst Frequency) Though PWM frequency is over 120Hz (max 252Hz), function of LED Driver is not affected.

Ver. 0.6

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LC420EUG

Engineering Specification

3-2. Interface Connections

This LCD module employs two kinds of interface connection, two 60-pin FFC connector are used for the module electronics and 12-pin,13-pin connectors are used for the integral backlight system.

3-2-1. LCD Module

-LCD Connector (CN1): TF06L-60S-0.5SH (Manufactured by HIROSE)

Table 4. MODULE CONNECTOR(CN1) PIN CONFIGURATION

No Symbol Description No Symbol Description

1 LTD_OUT LTD OUTPUT 2 NC No Connection 3

4 5 6 7 8

9 10 11 12 13

15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

GCLK1 GIP GATE Clock 1 33 LLV3 + Left Mini LVDS Receiver Signal(3+) GCLK2 GIP GATE Clock 2 34 LCLK - Left Mini LVDS Receiver Clock Signal(-) GCLK3 GIP GATE Clock 3 35 LCLK + Left Mini LVDS Receiver Clock Signal(+) GCLK4 GIP GATE Clock 4 36 LLV2 - Left Mini LVDS Receiver Signal(2-) GCLK5 GIP GATE Clock 5 37 LLV2 + Left Mini LVDS Receiver Signal(2+) GCLK6 GIP GATE Clock 6 38 LLV1 - Left Mini LVDS Receiver Signal(1-)

VGI_N GIP Bi-Scan (Normal =VGL Rotate = VGH) 39 LLV1 + Left Mini LVDS Receiver Signal(1+) VGI_P GIP Bi-Scan (Normal =VGH Rotate = VGL) 40 LLV0 - Left Mini LVDS Receiver Signal(0-)

VGH_ODD GIP Panel VDD for Odd GATE TFT 41 LLV0 + Left Mini LVDS Receiver Signal(0+)

VGH_EVEN GIP Panel VDD for Even GATE TFT 42 GND Ground

VGL GATE Low Voltage 43 SOE Source Output Enable SIGNAL VST VERTICAL START PULSE 44 POL Polarity Control Signal

GIP_Reset GIP Reset 45 GSP GATE Start Pulse

VCOM_L_FB VCOM Left Feed-Back Output 46 H_CONV "H“ H 2dot Inversion/ "L" H 1dot Inversion

VCOM_L VCOM Left Input 47 OPT_N “H” Normal Display / “L” Rotation Display

GND Ground 48 GND Ground GND Ground 49

VDD Driver Power Supply Voltage 50

VDD Driver Power Supply Voltage 51 H_VDD Half Driver Power Supply Voltage 52 H_VDD Half Driver Power Supply Voltage 53

GND Ground 54

VCC Logic Power Supply Voltage 55

VCC Logic Power Supply Voltage 56

GND Ground 57

LLV5 - Left Mini LVDS Receiver Signal(5-) 58

LLV5 + Left Mini LVDS Receiver Signal(5+) 59

LLV4 - Left Mini LVDS Receiver Signal(4-) 60

31 LLV4 + Left Mini LVDS Receiver Signal(4+) 32 LLV3 - Left Mini LVDS Receiver Signal(3-)

GMA 18 GAMMA VOLTAGE 18 (Output From LCD) GMA 16 GAMMA VOLTAGE 16 GMA 15 GAMMA VOLTAGE 15 GMA 14 GAMMA VOLTAGE 14 GMA 12 GAMMA VOLTAGE 12 GMA 10 GAMMA VOLTAGE 10 (Output From LCD)

GMA 9 GAMMA VOLTAGE 9 (Output From LCD) GMA 7 GAMMA VOLTAGE 7 GMA 5 GAMMA VOLTAGE 5 GMA 4 GAMMA VOLTAGE 4 GMA 3 GAMMA VOLTAGE 3 GMA 1 GAMMA VOLTAGE 1(Output From LCD)

Note :

1. Please refer to application note for details. (GIP & Half VDD & Gamma Voltage & H_CONV setting)

2. These 'input signal' (OPT_N,H_CONV) should be connected

Ver. 0.6

9 /32

Engineering Specification

POL

Polarity Control Signal

VST

VERTICAL START PULSE

-LCD Connector (CN2): TF06L-60S-0.5SH (Manufactured by HIROSE)

Table 5. MODULE CONNECTOR(CN2) PIN CONFIGURATION

No Symbol Description No Symbol Description

LC420EUG

1 GMA 1 GAMMA VOLTAGE 1 (Output From LCD) 2 GMA 3 GAMMA VOLTAGE 3 3 GMA 4 GAMMA VOLTAGE 4

4 GMA 5 GAMMA VOLTAGE 5 5 GMA 7 GAMMA VOLTAGE 7 6 GMA 9 GAMMA VOLTAGE 9 (Output From LCD) 7 GMA 10 GAMMA VOLTAGE 10 (Output From LCD) 8 GMA 12 GAMMA VOLTAGE 12

9 GMA 14 GAMMA VOLTAGE 14 10 GMA 15 GAMMA VOLTAGE 15 11 GMA 16 GAMMA VOLTAGE 16 12 GMA 18 GAMMA VOLTAGE 18 (Output From LCD) 13 14 15 16

18 19 20 21 22 23 24 25 26 27 28 29 30

GND Ground 43 GND Ground

OPT_N “H” Normal Display / “L” Rotation Display 44 VCOM_R VCOM Right Input

H_CONV "H“ H 2dot Inversion/ "L" H 1dot Inversion 45 VCOM_R_FB VCOM Right Feed-Back Output

GSP GATE Start Pulse 46 GIP_Reset GIP Reset

SOE Source Output Enable SIGNAL 48 VGL GATE Low Voltage GND Ground 49 VGH_EVEN GIP Panel VDD for Even GATE TFT

RLV5 - Right Mini LVDS Receiver Signal(5-) 50 VGH_ODD GIP Panel VDD for Odd GATE TFT

RLV5 + Right Mini LVDS Receiver Signal(5+) 51 VGI_P GIP Bi-Scan (Normal =VGH Rotate = VGL)

RLV4 - Right Mini LVDS Receiver Signal(4-) 52 VGI_N GIP Bi-Scan (Normal =VGL Rotate = VGH)

RLV4 + Right Mini LVDS Receiver Signal(4+) 53 GCLK6 GIP GATE Clock 6

RLV3 - Right Mini LVDS Receiver Signal(3-) 54 GCLK5 GIP GATE Clock 5 RLV3 + Right Mini LVDS Receiver Signal(3+) 55 GCLK4 GIP GATE Clock 4 RCLK - Right Mini LVDS Receiver Clock Signal(-) 56 GCLK3 GIP GATE Clock 3

RCLK + Right Mini LVDS Receiver Clock Signal(+) 57 GCLK2 GIP GATE Clock 2

RLV2 - Right Mini LVDS Receiver Signal(2-) 58 GCLK1 GIP GATE Clock 1 RLV2 + Right Mini LVDS Receiver Signal(2+) 59

RLV1 - Right Mini LVDS Receiver Signal(1-) 60

31 RLV1 + Right Mini LVDS Receiver Signal(1+) 32 RLV0 - Right Mini LVDS Receiver Signal(0-) 33 RLV0 + Right Mini LVDS Receiver Signal(0+) 34 GND Ground 35 VCC Logic Power Supply Voltage 36 VCC Logic Power Supply Voltage 37 GND Ground 38 H_VDD Half Driver Power Supply Voltage 39 H_VDD Half Driver Power Supply Voltage 40 VDD Driver Power Supply Voltage 41 VDD Driver Power Supply Voltage 42 GND Ground

NC No Connection

LTD_OUT LTD OUTPUT

Note :

Ver. 0.6

1. Please refer to application note for details (GIP & Half VDD & Gamma Voltage & H_CONV setting)

2. These 'input signal' (OPT_N,H_CONV) should be connected

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LG Display LC420EUG-RDA1 Specification

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