Supports LCD module with maximum resolution up to 800x600 at 24bpp
Per pixel alpha channel
True color engine
Supports hardware display rotation
Capable of combining display memories with up to 6 blending layers
Image Signal Processor
8 bit YUV format image input
-23-
Capable of processing image of size up to 2.0 M pixels
IEEE Std 1180-1990 IDCT standards compliance
Supports progressive image processing to minimize storage space requirement
Supports reload-able DMA for VLD stream
Image Data Processing
Supports Digital Zoom
Supports RGB888/565, YUV444 image processing
High throughput hardware scaler. Capable of tailoring an image to an arbitrary size.
Horizontal scaling in averaging method
Vertical scaling in bilinear method
YUV and RGB color space conversion
Boundary padding
2D Accelerator
Supports 32-bpp ARGB8888, 24-bpp RGB888, 16-bpp RGB565, and 8-bpp index color modes
Supports SVG Tiny
Rectangle gradient fill
BitBlt: multi-BitBlt with 7 rotation, 16 binary ROP
Alpha blending with 7 rotation
Line drawing: normal line, dotted line, anti-aliasing
Circle drawing
Bezier curve drawing
Triangle flat fill
Font caching: normal font, italic font
Command queue with max depth of 2047
Audio CODEC
Supports HE-AAC codec decode
Supports AAC codec decode
Wavetable synthesis with up to 64 tones
Advanced wavetable synthesizer capable of generating simulated stereo
Wavetable including GM full set of 128 instruments and 47 sets of percussions
PCM Playback and Record
Digital Audio Playback
Audio Interface and Audio Front End
Supports I2S interface
High resolution D/A Converters for Stereo Audio
Stereo analog input for stereo audio source
Analog multiplexer for stereo audio
Stereo to mono conversion
-24-
3.1.5 General Description
Figure 3-1-2 depicts the block diagram of MT6235. Based on a dual-processor architecture,
MT6235 integrates both an ARM926EJ-S core and a digital signal processor core. ARM926EJ-S
is the main processor responsible for running high-level GSM/GPRS protocol software as well as
multi-media applications. The digital signal processor manages the
low-level MODEM as well as advanced audio functions. Except for a few mixed-signal circuitries,
the other building blocks in MT6235 are connected to either the microcontroller or the digital
signal processor.
MT6235consists of the following subsystems:
Microcontroller Unit (MCU) Subsystem: includes an ARM926EJ-S RISC processor and its
accompanying memory management and interrupt handling logics;
Digital Signal Processor (DSP) Subsystem: includes a DSP and its accompanying memory,
memory controller, and interrupt controller;
MCU/DSP Interface: the junction at which the MCU and the DSP exchange hardware and
software information;
Microcontroller Peripherals: includes all user interface modules and RF control interface
modules;
Microcontroller Coprocessors: runs computing-intensive processes in place of the
Microcontroller;
DSP Peripherals: hardware accelerators for GSM/GPRS/EDGE channel codec;
Multi-media Subsystem: integrates several advanced accelerators to support multi-media
applications;
Voice Front End: the data path for converting analog speech to and from digital speech;
Audio Front End: the data path for converting stereo audio from an audio source;
Baseband Front End: the data path for converting a digital signal to and from an analog signal
from the RF modules;
Timing Generator: generates the control signals related to the TDMA frame timing; and,
Power, Reset and Clock Subsystem: manages the power, reset, and clock distribution inside
MT6235.
-25-
Figure.3-1-2 MT6235 BLOCK DIAGRAM
-26-
3.2 Power Amplifier Module (SKY77547)
Figure.3-2-1 SKY77547 FUNCTIONAL BLOCK DIAGRAM
The SKY77547 is a transmit and receive front-end module (FEM) with Integrated Power
Amplifier Control (iPAC.) for quad-band cellular handsets comprising GSM850/900 and
DCS1800/PCS1900 operation. Designed in a low profile, compact form factor, the SKY77547
offers a complete Transmit VCO-to-Antenna and Antenna-to-Receive SAW filter solution. The
FEM also supports Class 12 General Packet Radio Service (GPRS) multi-slot operation.
The module consists of a GSM850/900 PA block and a DCS1800/PCS1900 PA block,
impedancematching circuitry for 50 Ω input and output impedances, Tx harmonics filtering, high
linearity and a low insertion loss PHEMT RF switch, and a Power Amplifier Control (PAC) block
with internal current sense resistor. A custom BiCMOS integrated circuit provides the internal
PAC function and decoder circuitry to control the RF switches. The two Heterojunction Bipolar
Transistor (HBT) PA blocks are fabricated onto a single Gallium Arsenide (GaAs) die. One PA
block supports the GSM850/900 bands and the other PA block supports the DCS1800/PCS1900
bands. Both PA blocks share common power supply pads to distribute current. The output of
each PA block and the outputs to the four receive pads are connected to the antenna pad through
a PHEMT RF switch. The GaAs die, PHEMT die, Silicon (Si) die and passive components are
mounted on a multi-layer laminate substrate. The assembly is encapsulated with plastic
overmold.
Band selection and control of transmit and receive are performed using four external control
pads. Refer to the block diagram in Figure 1 below. The band select pads, BS1 and BS2, select
GSM850, GSM900, DCS, and PCS modes of operation. Transmit enable Tx_EN controls receive
or transmit mode of the RF switch (Tx = logic 1). Proper timing between transmit enable Tx_EN
and Analog Power Control VRAMP allows for high isolation between the antenna and Tx–VCO
while the VCO is being tuned prior to the transmit burst.
The SKY77547 is compatible with logic levels from 1.2 V to VCC for BS1, BS2, and Tx_EN
pads, depending on the level applied to the VLOGIC pad. This feature provides additional
flexibility for the designer in the selection of FEM interface control logic.
-27-
3.3 Transceiver Module (AD6548)
Figure.3-3-1 AD6548 FUNCTIONAL BLOCK DIAGRAM
3.3.1 General Descriptions
The AD6548/9 provides a highly integrated direct conversion radio solution that combines, on a
single chip, all radio and power management functions necessary to build the most compact
GSM radio solution possible. The only external components required for a complete radio design
are the Rx SAWs, PA, Switchplexer and a few passives enabling an extremely small
cost effective GSM Radio solution.
The AD6548/9 uses the industry proven direct conversion receiver architecture of the
OthelloTM family. For Quad band applications the front end features four fully integrated
programmable gain differential LNAs. The RF is then downconverted by quadrature mixers and
then fed to the baseband programmable-gain amplifiers and active filters for channel selection.
The Receiver output pins can be directly connected to the baseband analog processor. The
Receive path features automatic calibration and tracking to remove DC offsets.
The transmitter features a translation-loop architecture for directly modulating baseband
signals onto the integrated TX VCO. The translation-loop modulator and TX VCO are extremely
low noise removing the need for external SAW filters prior to the PA.
The AD6548/9 uses a single integrated LO VCO for both the receive and the transmit circuits.
The synthesizer lock times are optimized for GPRS applications up to and including class 12.
To dramatically reduce the BOM both TX Translational loop and main PLL Loop Filters are fully
-28-
integrated into the device.
AD6548 incorporates a complete reference crystal calibration system. This allows the external
VCTCXO to be replaced with a low cost crystal. No other external components are required. The
AD6549 uses the traditional VCTCXO reference source.
The AD6548/9 also contains on-chip low dropout voltage regulators (LDOs) to deliver regulated
supply voltages to the functions on chip, with a battery input voltage of between 2.9V and 5.5V.
Comprehensive power down options are included to minimize power consumption in normal use.
A standard 3 wire serial interface is used to program the IC. The interface features
low-voltage digital interface buffers compatible with logic levels from 1.6V to 3.0V.
The AD6548/9 is packaged in a 5mm × 5mm , 32-lead LFCSP package.
ORDERING GUIDE Model Temperature
Range
AD6548BCPZ -20°C to +85°C LFCSP-32
AD6549BCPZ -20°C to +85°C LFCSP-32
Package
3.3.2 Features
Fully Integrated GSM Transceiver including
Direct Conversion Receiver
4 Differential LNAs
Integrated Active RX Channel Select Filters
Programmable Gain Baseband Amplifiers
Translation Loop Direct VCO Modulator
Integrated TX VCO and tank
External TX filters eliminated
Integrated Loop filter components
High performance multi band PLL system
Fast Fractional-N Synthesizer
Integrated Local Oscillator VCO
Fully Integrated Loop filters
Crystal Reference Oscillator & Tuning System (AD6548)
Power Management
Integrated LDOs allow direct battery supply connection
Small footprint
32-Lead 5 X 5 mm Chipscale Package
APPLICATIONS
Dual, Triple and Quad Band Radios
- GSM850, E-GSM 900, DCS1800 and PCS1900
- GPRS to Class 12- EDGE RX
-29-
3.3.3 Pin Descriptions
-30-
Loading...
+ 155 hidden pages
You need points to download manuals.
1 point = 1 manual.
You can buy points or you can get point for every manual you upload.