LG KF240 Service Manual

Service Manual

Internal Use Only

Service Manual

KF240

Model :KF240

Date: May, 2008 / Issue 1.0

- 3 -

1. INTRODUCTION .............................. 5

1.1 Purpose .................................................. 5

1.2 Regulatory Information............................ 5

1.3 Abbreviations .......................................... 7

2. SYSTEM SPECIFICATION............... 9

2.1 H/W Features.......................................... 9

2.2 Technical Specification ......................... 10

3. TECHNICAL BRIEF ....................... 15

3.1 Digital Main Processor(AD6900, U101) 15

3.2 Analog Main Processor(AD6855, U100)18

3.3 Power Amplifier Module

(SKY77318, U600)................................ 25

3.4 FEM (DGM1110M014, FL600) ............. 26

3.5 RTC(FC-135, X100).............................. 27

3.6 Crystal(26 MHz, X600).......................... 28

3.7 RF Tranceiver(AD6548, U601) ..............30

3.8 MEMORY(PF38F5060M0Y0BE, U201).36

3.9 BT Module with integrated FM tuner

(EWFMLBAXX, U200) ...........................39

3.10 SIM Card Interface...............................41

3.11 Micro-SD Card Interface ......................42

3.12 LCD Interface.......................................43

3.13 Battery Charger Interface.....................46

3.14 Keypad Interface..................................47

3.15 Audio Interface.....................................49

3.16 Camera Interface(2M Fixed Focus

Camera) ...............................................56

3.17 KEY BACLKLIGHT LED Interface .......59

3.18 Vibrator Interface .................................60

4. TROUBLE SHOOTING ...................61

4.1 RF Component.......................................61

4.2 RX Trouble.............................................62

4.3 TX Trouble .............................................67

4.4 Power On Trouble..................................73

4.5 Charging Trouble ...................................75

4.6 Vibrator Trouble .....................................77

4.7 LCD Trouble...........................................79

4.8 Camera Trouble .....................................83

4.9 Speaker/Receiver Trouble .....................87

4.10 Earphone Trouble ................................90

4.11 Microphone Trouble .............................92

4.12 SIM Card Interface Trouble..................94

4.13 Main key backlight Trouble ..................96

4.14 Slide key backlight Trouble ..................98

4.15 RTC Trouble ......................................101

4.16 Folder on/off Trouble..........................103

4.17 6 Micro SD Trouble ............................105

4.18 Bluetooth Trouble...............................107

4.19 FM Radio Trouble ..............................109

5. DOWNLOAD .....................................111

5.1 Download .............................................111

6. BLOCK DIAGRAM ........................117

7. CIRCUIT DIAGRAM ......................119

8. BGA IC Pin Check ........................129

9. PCB LAYOUT................................133

10. ENGINEERING MODE ................139

10.1 BB Test [MENU 1]..............................140

10.2 RF Test [MENU 2]..............................142

10.3 MF mode [MENU 3] ...........................142

10.4 Trace option [MENU 4] ......................143

10.5 Call timer [MENU 5] ...........................143

10.6 Fact. Reset [MENU 6] ........................143

10.7 S/W version........................................143

11. STAND ALONE TEST .................144

11.1 Introduction ........................................144

11.2 Setting Method...................................144

11.3 Means of Test ....................................145

12. AUTO CALIBRATION .................147

12.1 Overview ............................................147

12.2 Equipment List ...................................147

12.3 Test Jig Operation..............................148

12.4 Procedure ..........................................149

12.5 AGC ...................................................151

12.6 APC....................................................151

12.7 ADC ...................................................151

13. EXPLODED VIEW &

REPLACEMENT PART LIST ......153

13.1 Exploded View ...................................153

13.2 Replacement Parts ............................155

13.3 Accessory ..........................................171

Table Of Contents

LGE Internal Use Only

- 4 -

LGE Internal Use Only

Only for training and service purposes

- 5 -

1. INTRODUCTION

1.1 Purpose

This manual provides the information necessary to repair, calibration, description and download the features of this model.

1.2 Regulatory Information

A. Security

Toll fraud, the unauthorized use of telecommunications system by an unauthorized part (for example, persons other than your company’s employees, agents, subcontractors, or person working on your company’s behalf) can result in substantial additional charges for your telecommunications services. System users are responsible for the security of own system. There are may be risks of toll fraud associated with your telecommunications system. System users are responsible for programming and configuring the equipment to prevent unauthorized use. The manufacturer does not warrant that this product is immune from the above case but will prevent unauthorized use of common-carrier telecommunication service of facilities accessed through or connected to it. The manufacturer will not be responsible for any charges that result from such unauthorized use.

B. Incidence of Harm

If a telephone company determines that the equipment provided to customer is faulty and possibly causing harm or interruption in service to the telephone network, it should disconnect telephone service until repair can be done. A telephone company may temporarily disconnect service as long as repair is not done.

C. Changes in Service

A local telephone company may make changes in its communications facilities or procedure. If these changes could reasonably be expected to affect the use of the this phone or compatibility with the network, the telephone company is required to give advanced written notice to the user, allowing the user to take appropriate steps to maintain telephone service.

D. Maintenance Limitations

Maintenance limitations on this model must be performed only by the manufacturer or its authorized agent. The user may not make any changes and/or repairs expect as specifically noted in this manual. Therefore, note that unauthorized alternations or repair may affect the regulatory status of the system and may void any remaining warranty.

1. INTRODUCTION

LGE Internal Use Only

- 6 -

1. INTRODUCTION

E. Notice of Radiated Emissions

This model complies with rules regarding radiation and radio frequency emission as defined by local

regulatory agencies. In accordance with these agencies, you may be required to provide information

such as the following to the end user.

F. Pictures

The pictures in this manual are for illustrative purposes only; your actual hardware may look slightly different.

G. Interference and Attenuation

Phone may interfere with sensitive laboratory equipment, medical equipment, etc.Interference from unsuppressed engines or electric motors may cause problems.

H. Electrostatic Sensitive Devices

ATTENTION

Boards, which contain Electrostatic Sensitive Device (ESD), are indicated by the sign. Following information is ESD handling:

• Service personnel should ground themselves by using a wrist strap when exchange system boards.

• When repairs are made to a system board, they should spread the floor with anti-static matb which is also grounded.

• Use a suitable, grounded soldering iron.

• Keep sensitive parts in these protective packages until these are used.

• When returning system boards or parts like EEPROM to the factory, use the protective package as described.

LGE Internal Use Only

Only for training and service purposes

- 7 -

1. INTRODUCTION

1.3 Abbreviations

For the purposes of this manual, following abbreviations apply:

LGE Internal Use Only

APC Automatic Power Control

BB Baseband

BER Bit Error Ratio

CC-CV Constant Current - Constant Voltage

DAC Digital to Analog Converter

DCS Digital Communication System

dBm dB relative to 1 milli watt

DSP Digital Signal Processing

EEPROM Electrical Erasable Programmable Read-Only Memory

ESD Electrostatic Discharge

FPCB Flexible Printed Circuit Board

GMSK Gaussian Minimum Shift Keying

GPIB General Purpose Interface Bus

GSM Global System for Mobile Communications

IPUI International Portable User Identity

IF Intermediate Frequency

LCD Liquid Crystal Display

LDO Low Drop Output

LED Light Emitting Diode

OPLL Offset Phase Locked Loop

- 8 -

1. INTRODUCTION

LGE Internal Use Only

Only for training and service purposes

PAM Power Amplifier Module

PCB Printed Circuit Board

PGA Programmable Gain Amplifier

PLL Phase Locked Loop

PSTN Public Switched Telephone Network

RF Radio Frequency

RLR Receiving Loudness Rating

RMS Root Mean Square

RTC Real Time Clock

SAW Surface Acoustic Wave

SIM Subscriber Identity Module

SLR Sending Loudness Rating

SRAM Static Random Access Memory

PSRAM Pseudo SRAM

STMR Side Tone Masking Rating

TA Travel Adapter

TDD Time Division Duplex

TDMA Time Division Multiple Access

UART Universal Asynchronous Receiver/Transmitter

VCO Voltage Controlled Oscillator

VCTCXO Voltage Control Temperature Compensated Crystal Oscillator

WAP Wireless Application Protocol

- 9 -

2. SYSTEM SPECIFICATION

2.1 H/W Features

2. SYSTEM SPECIFICATION

LGE Internal Use Only

Item Feature Comment

Standard Battery Li-ion Polymer, 3.7V 800mAh

Stand by TIME Up to 200 hrs : Paging Period 5, RSSI 85dBm

Talk time Up to 200min : GSM Tx Level 7

Charging time Approx. 3 hours

RX Sensitivity GSM, EGSM: -109dBm, DCS: -109dBm

TX output power

GSM, EGSM: 32.5dBm(Level 5),

DCS , PCS: 29.5dBm(Level 0)

GPRS compatibility Class 10

SIM card type 3V Small

Display MAIN : TFT 176 × 220 pixel 262K Color

Hard icons. Key Pad

Status Indicator

0 ~ 9, #, *, Up/Down, Left/Right Navigation Key, OK Key Soft Key (Left/Right), Send, Clear, PWR Key Volume Key(Up/Down), Camera Key, MP3 Key

ANT Internal

EAR Phone Jack Yes

PC Synchronization Yes

Speech coding EFR/FR/HR

Data and Fax Yes

Vibrator Yes

Voice Recoding Yes

Microphone Yes

Speaker/Receiver 18x10 one way dual speaker

Travel Adapter Yes

MIDI SW MIDI

Camera 2M

Bluetooth / FM Radio Bluetooth version 2.0 / 76~108MHz supported

- 10 -

2. SYSTEM SPECIFICATION

2.2 Technical Specification

LGE Internal Use Only

Only for training and service purposes

Item Description Specification

GSM850

TX: 824 + n x 0.2 MHz RX: 869 + n x 0.2 MHz (n=1~128)

PCS

1Frequency Band TX: 1850.2 + (n-512) x 0.2 MHz

RX: 1930.2+ (n-1512) x 0.2 MHz (n=512~810)

DCS

TX: 1710.2 + (n-512) x 0.2 MHz RX: 1805.2 + (n-512) x 0.2 MHz (n=512~885)

2 Phase Error

RMS < 5 degrees Peak < 20 degrees

3 Frequency Error < 0.1 ppm

GSM

Level Power Toler. Level Power Toler.

5 33 dBm 2dB 13 17 dBm 3dB

6 31 dBm 3dB 14 15 dBm 3dB

7 29 dBm 3dB 15 13 dBm 3dB

8 27 dBm 3dB 16 11 dBm 5dB

9 25 dBm 3dB 17 9 dBm 5dB

10 23 dBm 3dB 18 7 dBm 5dB

11 21 dBm 3dB 19 5 dBm 5dB

4 Power Level 12 19 dBm 3dB

DCS/PCS

Level Power Toler. Level Power Toler.

0 30 dBm 2dB 8 14 dBm 3dB

1 28 dBm 3dB 9 12 dBm 4dB

2 26 dBm 3dB 10 10 dBm 4dB

3 24 dBm 3dB 11 8 dBm 4dB

4 22 dBm 3dB 12 6 dBm 4dB

5 20 dBm 3dB 13 4 dBm 4dB

6 18 dBm 3dB 14 2 dBm 5dB

7 16 dBm 3dB 15 0 dBm 5dB

- 11 -

2. SYSTEM SPECIFICATION

LGE Internal Use Only

Item Description Specification

GSM, EGSM

Offset from Carrier (kHz). Max. [dBc]

100 0.5

200 -30

250 -33

400 -60

600 ~ 1,200 -60

1,200 ~ 1,800 -60

1,800 ~ 3,000 -63

3,000 ~ 6,000 -65

5

Output RF Spectrum 6,000 -71

(due to modulation) DCS/PCS

Offset from Carrier (kHz). Max. [dBc]

100 0.5

200 -30

250 -33

400 -60

600 ~ 1,200 -60

1,200 ~ 1,800 -60

1,800 ~ 3,000 -65

3,000 ~ 6,000 -65

6,000 -73

GSM, EGSM

Offset from Carrier (kHz) Max. [dBm]

Output RF Spectrum 400 -19

6

(due to switching transient) 600 -21

1,200 -21

1,800 -24

Item Description Specification

DCS/PCS

Offset from Carrier (kHz) Max. [dBm]

Output RF Spectrum 400 -22

6

(due to switching transient) 600 -24

1,200 -24

1,800 -27

7 Spurious Emissions Conduction, Emission Status

GSM, EGSM

8Bit Error Ratio

BER (Class II) < 2.439% @-102 dBm

DCS, PCS

BER (Class II) < 2.439% @-100 dBm

9 RX Level Report Accuracy

10 SLR 8 3 dB

Frequency (Hz) Max.(dB) Min.(dB)

100 -12 -

200 0 -

300 0 -12

11 Sending Response 1,000 0 -6

2,000 4 -6

3,000 4 -6

3,400 4 -9

4,000 0 -

12 RLR 2 3 dB

Frequency (Hz) Max.(dB) Min.(dB)

100 -12 -

200 0 -

300 2 -12

500 * -5

13 Receiving Response

1,000 0 -5

3,000 2 -5

3,400 2 -10

4,000 2

*Mean that Adopt a straight line in between 300 Hz

and 1,000 Hz to be Max. level in the range.

- 12 -

2. SYSTEM SPECIFICATION

LGE Internal Use Only

Only for training and service purposes

- 13 -

2. SYSTEM SPECIFICATION

LGE Internal Use Only

Item Description Specification

14 STMR 13 5 dB

15 Stability Margin > 6 dB

dB to ARL (dB) Level Ratio (dB)

-35 17.5

-30 22.5

16 Distortion

-20 30.7

-10 33.3

0 33.7

7 31.7

10 25.5

17 Side Tone Distortion Three stage distortion < 10%

18

System frequency

≤2.5 ppm

(13 MHz) tolerance

19 32.768KHz tolerance ≤ 30 ppm

At least 65 dBspl under below conditions:

20 Ringer Volume 1. Ringer set as ringer.

2. Test distance set as 50 cm

Fast Charge : Typ. 430 mA

21 Charge Current Slow Charge : Typ. 80mA

Total Charging Time : < 3 hours

Bar Number Power

7 -93~

7 → 5 -93 2

22 Antenna Display 5 → 4 -98 2

4 → 2-101 2

2 → 1-104 2

1 → 0-106 2

0 → OFF ~-106

Battery Bar Number Voltage

3≤3.75 0.05 V

23 Battery Indicator 3 → 2 3.75 0.05 V

2 → 1 3.64 0.05 V

1 → 0 3.54 0.05 V

Item Description Specification

24

Low Voltage Warning ≤ 3.54 0.05V (Call)

(Blinking Bar) ≤ 3.4 0.05V (Standby)

25

Forced shut down

3.33 0.05V

Voltage

26 Sustain RTCwithout battery Over 50 hours

Li-Ion Battery

27 Battery Type

Standard Voltage = 3.7 V Battery full charge voltage = 4.2 V Capacity: 800mAh

Switching-mode charger

28 Travel Charger Input: 100 ~ 350V, 50/60 Hz

Output: 5.1 V, 700 mA

- 14 -

2. SYSTEM SPECIFICATION

LGE Internal Use Only

Only for training and service purposes

- 15 -

3. TECHNICAL BRIEF

LGE Internal Use Only

3.1 Digital Main Processor(AD6900, U101)

The AD6900 is an advanced, low-power baseband processing solution from Analog Devices, and is part of the AD20msp500 SoftFone® chipset family. The AD6900 is intended for use in a wide variety of feature-rich phones with GSM/GPRS/EGPRS based system connectivity requirements. It is designed to interface easily to an application/OS processor, or to stand alone as a fully integrated and easy-touse solution for mobile handset and wireless modem applications.

Figure. 3-1 AD6900 FUNCTIONAL BLOCK DIAGRAM

- 16 -

3. TECHNICAL BRIEF

LGE Internal Use Only

Only for training and service purposes

3.1.1 Features of AD6900

Complete Single-Chip Programmable Digital Baseband Processor with four main subsystems

MCU Control Processor Subsystem:

32-bit ARM926EJ-S® MCU Control Processor 260 MHz operation at 1.5V dedicated caches, 16K bytes each, for instructions and data 4kB Instruction Tightly Coupled Memory (TCM) 2-Mbit On-chip System SRAM Ciphering coprocessor for GPRS supporting GEA1 and GEA2 encryption algorithms Kasumi cipher coprocessor for GEA3 encryption Dedicated multichannel DMA controller

DSP Subsystem:

Blackfin 16-bit fixed-point DSP Processor 260 MHz operation at 1.5V Memory:

→ L1 program space: 64 kB SRAM and 16 kB configurable as instruction cache or SRAM → L1 data space: Two banks of 16K bytes, each with 8K bytes of dedicated SRAM and an

additional 8K bytes that can be configured as either cache or SRAM

→ L2 space: 64KB SRAM Ciphering coprocessor (GEA1 and GEA2) Kasumi cipher coprocessor for GEA3 encryption Dedicated multichannel DMA controller

Peripherals Subsystem:

Shared on-chip peripherals and off-chip interfaces: Support for Burst-mode, Page-mode, and NAND Flash memory Support for SRAM, SDRAM, and PSRAM (cellular RAM) Full-Speed USB 2.0 Dual-Role Interface with OTG (On-The-Go) Host Mode or traditional Peripheralonly mode

- 17 -

3. TECHNICAL BRIEF

LGE Internal Use Only

Applications Subsystem for Enhanced Multimedia:

Parallel Peripheral Interface (PPI) for 10-bit dedicated camera

sensor or video input interface (including ITU-656 and ITU-601 digital video)

Separate external bus interface for parallel LCD displays (or camera module inputs)

- reduces noise and loading on the

main EBUS interface

Dedicated multi-channel DMA controller

OTHER FEATURES

Real-Time Clock (RTC) with Alarm

Four General-Purpose Timers

Baseband Converter Interface

Compatible with Othello® radio subsystem

Highly configurable interrupt controller architecture

Programmable bus arbitration to optimize system performance

Supports 13 MHz and 26 MHz Input Clocks

Programmable Power Management and Clock Management

- Slow Clocking Scheme for Low Idle Mode Current

- Power Down modes

- Dynamic Core Voltage Scaling from 1.1 - 1.5V Independent I/O Voltage Domains On-chip support for EGPRS Data Services up to Class 10 Embedded Trace Macrocell for MCU Debug JTAG Interface for Test and In-Circuit Emulation of both the MCU and DSP Advanced features for security

LGE Internal Use Only

Only for training and service purposes

3. TECHNICAL BRIEF

- 18 -

3.2 Analog Main Processor(AD6855, U100)

The AD6855 is a complete mixed-signal baseband processor that combines all of the data converters and power supply regulators required for a GSM 900 / GSM 850 / DCS 1800 / PCS 1900 mobile on a single device, including HSCSD, GPRS and EGPRS.

Figure. 3-2-1 AD6855 FUNCTIONAL BLOCK DIAGRAM

- 19 -

3. TECHNICAL BRIEF

LGE Internal Use Only

3.2.1 General Description

The AD6855 baseband transmit section supports the following mobile station GMSK modulation power classes:

GSM 900/850 power classes 4 and DCS 1800 power classes 1 and 2, and PCS 1900 power classes 1 and 2.

The AD6855 baseband transmit section supports the following mobile station 8-PSK modulation power classes:

GSM 900/850 power classes E2 and E3, DCS 1800 power classes E2 and E3, and PCS 1900 power classes E2 and E3.

The AD6855 baseband receive section supports GMSK and 8-PSK applications. The AD6855 auxiliary section provides a voltage reference, an automatic frequency control DAC, an auxiliary ADC, and light controllers. The auxiliary ADC provides two channels for measuring temperature using discrete external devices placed in critical locations. The AD6855 audio section provides 8 kHz and 16 kHz sampling rates for voiceband data input and output and provides nine standard sample rates ranging from 8kHz to 48 kHz for personal audio output on two PCM Audio serial ports. The two Audio serial ports allow support for concurrency. The AD6855 power management section provides voltage regulators for digital and analog components, a battery charger, battery protection circuitry, and power supply activation logic. The AD6855 digital processor interface provides serial ports for control data, baseband transmit and receive data, and two for audio data.

- 20 -

3. TECHNICAL BRIEF

LGE Internal Use Only

Only for training and service purposes

3.2.2 Power Block

CSPORT interface, power management control interface and the circuit that generates power up RESET pulses (RESET2P8 and RESET1P8) for use by the DBB chip. All regulators except the USB interface regulator are powered from the main battery. The USB regulator is powered from USB VBUS. And the user presses KEYON which puts the AD6855 power management system into ACTIVATION state (see definitions below) and signals DBB software that it’s time to wake up and operate using the KEYOUT signal.

Figure. 3-2-2 AD6855 POWER BLOCK DIAGRAM

- 21 -

3. TECHNICAL BRIEF

LGE Internal Use Only

Figure. 3-2-3 AD6855 KEYON/KEYOUT BLOCK DIAGRAM

Figure. 3-2-4 AD6855 RESET GENERATION BLOCK DIAGRAM

- 22 -

3. TECHNICAL BRIEF

LGE Internal Use Only

Only for training and service purposes

Power On Reset Generator

The power-on reset signals (RESET1P8 and RESET2P8) are asserted based on the VCORE (if VAPPCFG = 0), VMEM, VEXT, and VPLL regulators. RESET1P8 and RESET2P8 are low when reset is enabled and high when reset is disabled. When the outputs of all four regulators reach their corresponding threshold voltages, reset will be disabled after a nominal reset period of 130ms. The outputs of all four regulators must remain at or above their corresponding threshold voltages for the duration of the reset period for reset to be disabled (pulled high). The nominal 130ms reset period is restarted whenever all four regulators reach their threshold voltages. The nominal reset period of 130ms can be extended by connecting an external capacitor to CRST. This capacitor is charged using a small current when reset is enabled. Once the capacitor reaches the threshold, reset is disabled. Reset will be enabled immediately if any one of the four regulators falls below their corresponding threshold voltages. In addition, reset will be enabled if VBAT falls below VRTC. The PWREN signal is the logical AND of all the state controls that enable or disable many of the regulators on the chip. If the regulators enabled by PWREN are disabled by PMT state controls described below then PWREN must go low. When PWREN goes low reset will be immediately enabled causing RESET1P8 and RESET2P8 to be pulled low. When reset is enabled, both RESET1P8 and RESET2P8 are actively pulled low. CRST is also actively pulled low when reset is enabled.

VABB Regulator Enable/Disable Logic Operation

The VABB regulator powers many on-chip analog circuits on the ABB. The VCXOEN signal, the VABBEn bit in the LDOControl1 Bit Positions ( Addr 0x35) register, and the AFCDACMode and AFCDACOn bits in the AuxControl1 Bit Positions ( Addr 0x13) register all particpate in controlling the VABB enable/disable. When the ABB power management system transitions from Off state, DDLO state, UVLO state, or Thermal Shutdown State to Power Key Activation, Charger Activation, USB Charger Activation, or Active State VABB will be enabled. During these state transitions ABBEn = 0 and AFCDACMode = 0, VRF is enabled. Once the ABB power management system is in Power Key Activation, Charger Activation, USB Charger Activation, Active-Standby or Active State the VABB regulator enable/disable is controlled by the information written to the VABBEn and AFCDACMode register bits by system software.

- 23 -

3. TECHNICAL BRIEF

LGE Internal Use Only

Digital Baseband Core (VCORE)

The Digital Baseband Core regulator supplies the digital baseband processor (DBB) core. The voltage on VCORE is selectable using the VCOREControl register. The VCOREActive code selects the voltage on VCORE in high power mode and the VCOREStandby code selects the voltage on VCORE in low-power mode.

DBB Interface (VINT)

The DBB interface regulator supplies the DBB/ABB digital interfaces. The output voltage of the VINT regulator is nominal 1.8V.

Memory (VMEM)

The VMEM regulator supplies the external memory(s) and the interface to the external memory on the digital baseband processor. The output voltage of the Memory Interface regulator can be selected as

1.8V nominal or 2.8V nominal using the VMEMSEL terminal.

External Interface (VEXT)

The External Interface regulator supplies the Radio digital interface and the high voltage (>1.8V) interface between the digital baseband processor and various peripherals, such as the LED indicators and the LCD display.

SIM Interface (VSIM)

AD6855 is designed to support 3.0 V and 1.8 V SIMs exclusively (i.e. no 5 V SIMs). The SIM Interface regulator supplies the SIM interface circuitry on the digital processor and the SIM card. By default the SIM Interface regulator output is 2.85 V, which can be decreased to 1.8 V if a 1.8 V SIM is detected.

Real-Time Clock (VRTC)

The Real-Time Clock regulator supplies the Real-Time Clock module. The Real-Time Clock regulator is optimized for low ground current.

Baseband Analog (VABB)

The Baseband Analog regulator supplies the analog portions of the AD6855. Operation of the VABB regulator is controlled by the VABBEn bit in the LDOControl1 register. If VABBEn = 0, the VABB regultor will be disabled unless the AFCDAC is enabled or VCXOEN = 1. If VABBEn = 1 (the default state) VABB is enabled along with VCORE, VMEM, and VEXT. The Baseband Analog regulator is optimized for high ripple rejection and low noise. The output of the Baseband Analog regulator should not be used as a supply for any external components.

- 24 -

3. TECHNICAL BRIEF

LGE Internal Use Only

Only for training and service purposes

Microphone (VMIC)

The Microphone regulator supplies the microphone interface circuitry. The Microphone regulator is optimized for extremely high ripple rejection up to 217 Hz and low noise.

VRF (VRF)

The VCXO regulator supplies the voltage controlled crystal oscillator (VCXO). The VCXO regulator is optimized for high ripple rejection and low noise.

USB Interface (VUSB)

The VUSB regulator supplies the USB transceiver located in the DBB. Digital Baseband PLL (VPLL) The VPLL regulator supplies the phase locked loop on the digital baseband (DBB).

General Purpose Regulator (VGP)

The General Purpose regulator is intended primarily to serve as a supply rail for camera modules. Its voltage is programmable by setting VGPSel[3:0] in theLDOControl2 Register. VGP is enabled by setting the VGPEn bit in LDOControl1 to 1.

Applications Regulator (VAPP)

The VAPP regulator is an adjustable regulator that uses an off chip pass device. It has two modes of operation selected by the state of the VAPPCFG terminal. If VAPPCFG is pulled low the VAPP regulator functions as a programmable voltage applications supply. In this mode, VAPP is enabled or disabled using the VAPPEn bit of LDOControl1.

3.3 Power Amplifier Module(SKY77318, U600)

3.3.1 Internal Block Diagram

3.3.2 General Description

The SKY77318 Power Amplifier Module (PAM) is designed in a low profile (1.2 mm), compact form factor for quad-band cellular handsets comprising GSM850/900, DCS1800, and PCS1900 operation. The PAM also supports Class 12 General Packet Radio Service (GPRS) multi-slot operation. The module consists of separate GSM PA and DCS1800/PCS1900 PA blocks, impedance-matching circuitry for 50 Ω input and output impedances and a Power Amplifier Control (PAC) block with an internal current-sense resistor. The custom BiCMOS integrated circuit provides the internal PAC function and interface circuitry. Fabricated onto a single Gallium Arsenide (GaAs) die, one Hetero-junction Bipolar Transistor (HBT) PA block supports the GSM bands and the other supports the DCS1800 and PCS1900 bands. Both PA blocks share common power supply pins to distribute current.

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3. TECHNICAL BRIEF

LGE Internal Use Only

Figure. 3-3-1 SKY77318 FUNCTIONAL BLOCK DIAGRAM

3.4 FEM (DGM1110M014, FL600)

The FEM is integrated of quadband RX SAWs, internal diplexer and ESD protection at Ant port to 8kV acc.

- 26 -

3. TECHNICAL BRIEF

LGE Internal Use Only

Only for training and service purposes

Figure 3-4-2 FEM CIRCUIT DIAGRAM

Figure 3-4-1 Band SW Logic Table

C645

100p

2V75_VCXO

R608

10

39p

C628

13

VDD

12

GND2

16

GND3

GND4

18

19

GND5

GND6

20

10

GSM1800_1900_TX

5

GSM1800_RX1

6

GSM1800_RX2

GSM1900_RX1

7

8

GSM1900_RX2

15

GSM850_900_TX

GSM850_RX1

1

2

GSM850_RX2

GSM900_RX1

3

GSM900_RX2

4

VC1

14

VC2

SFAY0011101

FL600

DGM1110M014

ANT

17

9

GND1

11

47p

C620

C626

0.1u

C644

100p

ANT_SW2

ANT_SW1

ANT_SW1 ANT_SW2

GSM850/900 TX L H

DCS/PCS TX H H

GSM850/900 RX L L

DCS/PCS RX H L

3.5 RTC(FC-135, X100)

The AD6900 supports a Real Time Clock function. A total of 25pF+/-10% capacitance to graound is required (including board trace capacitance) on each OSCIN and OSCOUT. RTC functionality allows the application software to implement standard clock, calendar, or organizer functions.

A 32KHz clock is required in AD6900 based systems to take advantage of power saving “slow clocking” mode. A combination of an oscillator circuit within the AD6900 IC and an external 32KHz crystal results in a stable 32kHz clock for use in the system. The purpose of this application note is to discuss the system issues that affect operation of the 32kHz oscillator circuit.

- 27 -

3. TECHNICAL BRIEF

LGE Internal Use Only

Figure. 3-5 32.768KHz Crystal Basic Connections

- 28 -

3. TECHNICAL BRIEF

LGE Internal Use Only

Only for training and service purposes

3.6 Crystal(26 MHz, X600)

The AD6548 requires only an external low cost as the frequency reference. The circuitry to oscillate the crystal and tune its frequency is fully integrated. The Oscillator is a balanced implementation requiring the crystal to be connected across 2 pins. There is a programmable capacitor array included for coarse tuning of fixed offsets, and an integrated varactor for dynamic control. The oscillator is designed for use with a 26MHz crystal. The crystal is connected as shown in figure 3-3.

Figure. 3-6-1 Crystal Oscillator External Connection

- 29 -

3. TECHNICAL BRIEF

LGE Internal Use Only

Dedicated control software ensures excellent frequency stability under all circumstances. The AD6548 reference oscillators provides a 26MHz 600mVpp (typical) output (REF_OP), for use as the baseband clock input.

The AD6548 integrates this frequency tuning range the tuning section comprises a switchable capacitor array for discrete steps and varactor for fine tuning. Contol of the tuning process is driven by software, whereby the frequency can be maintained accurately during reception gaps and initial frequency upon startup can be accurately estimated without the need for temperature sensors.

Figure. 3-6-2 Crystal Circuit Block Diagram

- 30 -

3. TECHNICAL BRIEF

LGE Internal Use Only

Only for training and service purposes

3.7 RF Tranceiver(AD6548, U601)

3.7.1 GENERAL DESCRIPTION

The AD6548 provides a highly integrated direct conversion radio solution that combines, on a single chip, all radio and power management functions necessary to build the most compact GSM radio solution possible. The only external components required for a complete radio design are the Rx SAWs, PA, Switchplexer and a few passives enabling an extremely small cost effective GSM Radio solution. The AD6548 uses the industry proven direct conversion receiver architecture of the OthelloTM family. For Quad band applications the front end features four fully integrated programmable gain differential LNAs. The RF is then downconverted by quadrature mixers and then fed to the baseband programmable-gain amplifiers and active filters for channel selection. The Receiver output pins can be directly connected to the baseband analog processor. The Receive path features automatic calibration and tracking to remove DC offsets.

Figure. 3-7-1 CIRCUIT DIAGRAM of RF Tranceiver

- 31 -

3. TECHNICAL BRIEF

The transmitter features a translation-loop architecture for directly modulating baseband signals onto the integrated TX VCO. The translation-loop modulator and TX VCO are extremely low noise removing the need for external SAW filters prior to the PA. The AD6548 uses a single integrated LO VCO for both the receive and the transmit circuits. The synthesizer lock times are optimized for GPRS applications up to and including class 12.

3.7.2 FUNCTIONAL DESCRIPTION

LGE Internal Use Only

Figure. 3-7-2 RECEIVER CHAIN BLOCK DIAGRAM

- 32 -

3. TECHNICAL BRIEF

LGE Internal Use Only

Only for training and service purposes

3.7.2.1 RECEIVER CHAIN

The AD6548/9 receiver section fully integrates all the RF and baseband signal processing. Each major block is described in the following sections.

Low Noise Amplifiers

The AD6548 includes four fully integrated Low Noise Amplifiers (LNAs), to support quad band applications without further external active components. The LNAs have differential inputs which minimize the effect of unwanted interferers. The inputs are easily matched to industry standard Front End Modules (FEMs) or discrete Rx SAW filters. The outputs of the LNAs are directly coupled to the down-converting mixers. The voltage gain of the LNAs are typically 24 dB. Each LNA can be switch to a low gain mode when receiving large input signals as part of the AGC system. Down-Converting Mixers Two quadrature mixers are used to mix down the signals from the LNAs, one for the high bands (1800 and 1900 MHz) and one for the low bands (850 and 900 MHz). The outputs of the mixers are connected to the baseband section through an integrated single pole filter with nominal cut-off frequency of 800kHz. This acts as a “roofing filter” for the largest blocking signals (i.e. those ≥ 3MHz) and prevents the baseband amplifiers from being overloaded.

Baseband Amplifiers / Low Pass Filters

The baseband amplifiers provide the majority of the analog receiver gain. The filtering is provided by an integrated 5thorder Chebyshev filter giving the necessary adjacent channel and blocking filtering, it is also acting as an anti-alias filtering for Baseband IC’s converters. A final low pass pole is possible Baseband Output D.C. Offset Correction In order to minimize D.C. offsets inherent in the receiver and maximize dynamic range a D.C offset correction circuit is integrated. This correction is triggered over the serial bus and then an offset tracking loop is enabled to minimize residual offsets under all conditions. The tracking loop is fully hardware integrated, requiring no software intervention.

Receiver Local Oscillator (LO) Generator

The Rx LO generator is used to avoid DC offset problems associated with LO leakage into the receiver RF path. By operating the VCO at a frequency other than the desired receive frequencies, any leakage of the VCO will fall out of band. The LO generator is used to convert the offset synthesized VCO output to the on-frequency quadrature LO required by the chipset. The LO generator is implemented as a regenerative frequency divider, performing a 2/3 multiplication of the VCO output for the high band (DCS1800/PCS1900) and a 1/3 multiplication for low band (E-GSM 900/GSM850).

LGE Internal Use Only

3. TECHNICAL BRIEF

- 33 -

3.7.2.2 Transmit Path

Overview

The transmit section of the AD6548/9 radio implements a translation loop modulator. This consists of a quadrature modulator, high speed phase-frequency detector (PFD) with charge pump output, loop filter, TX VCO and a feedback down converting mixer. The VCO output (divided by 2 for low band) is fed to the power amplifier with a portion internally fed back into the downconverting feedback mixer to close the feedback loop.

Quadrature Modulator

The Quadrature modulator takes the baseband I & Q signals and translates these into a GMSK signal at the Transmit Intermediate Frequency (TX IF). After bandpass filtering and limiting the TX IF signal is used as the reference input to the Phase Frequency Detector (PFD) of the transmit PLL.

Figure. 3-7-3 TRANSMIT PATH BLOCK DIAGRAM

LGE Internal Use Only

Only for training and service purposes

3. TECHNICAL BRIEF

- 34 -

Phase Frequency Detector (PFD)

The PFD ensures that the transmitted signal contains the required modulation and is accurately locked to the desired GSM channel. The downconverted feedback signal from the TX VCO and the Quadrature Modulator output are phase compared by the PFD. The PFD charge pump generates a current pulse proportional to the difference in phase which is applied to the loop filter.

Loop filter

To minimize complexity of the external PCB layout the TX loop filter is fully integrated into the IC. At power up the filter is automatically calibrated as part of the baseband filter cal, eliminating process tolerances. The calibration is fully integrated and requires no extra programming.

TX VCO

The Transmit Voltage Controlled Oscillator (TX VCO) and tank components are a fully integrated subsystem. The subsystem includes PA drivers so the outputs are used to directly drive the external PAs. The low noise oscillator design and internal filtering mean that external TX SAW filters are not required. In Low band operation the TX VCO output is divided by two and filtered. The TX VCO is automatically calibrated to ensure optimum performance over its operating frequency of 1648 to 1910 MHz.

Feedback Down-Converting Mixer

The feedback down converting mixer is used to translate the TX VCO output frequency to the TX IF. An integrated band pass filter exists between the mixer and the PFD to filter the mixers unwanted side band and higher order mixing products.

- 35 -

3. TECHNICAL BRIEF

LGE Internal Use Only

3.7.2.3 Main Frequency Synthesizer

The AD6548 has a single fast-locking fractional synthesizer used for VCO control in both receive and transmit mode. The entire system including VCO, tank, fractional N dividers, sigma delta compensation, charge pump and loop filters are fully integrated. The only external component is the frequency reference. The synthesizer is controlled via the serial interface. The VCO is fed into the respective dividers to generate the appropriate LO frequencies for the RX and TX bands.

Fractional N Dividers

The fractional N divider allows the PLL system to have a smaller step size than theb comparison frequency which is set by the external reference to 26 MHz. This feature allows all the GSM frequency band rasters to be achieved, with fast lock times and good phase noise characteristics. The divider section consists of a dual modulus 8/9 prescaler, integer M & A dividers, and fractional N system based on sigma-delta modulation to generate the required fractional divide ratio. The Denominator of the fractional divider can be set to 3 different values, (1040, 1170, 1235), depending on the mode of operation. For example a denominator of 1040 with an input fraction F maintains an average value of F/1040 allowing 25 kHz steps when operated at a reference of 26 MHz. The Overall count value is thus:

8*M + A + Fraction

Where: M is 4 bits, but the MSB is set to 1. A is 3 Bits. Fraction is N/ Denominator. The Denominator is set to one of 3 values: 1040, 1170, 1235. N is a 11 bit value. Values for M, A and N are loaded from serial interface word, but the denominator is automatically set according to the mode. Refer to the Programming Procedures for more details.

Phase Frequency Detector/Charge Pump

A Phase Frequency Detector (PFD) is used for the PLL phase detector. The charge pump is designed such that good matching of up and down currents is achieved over a wide output operating range. The charge pump output is internally routed to the integrated synthesizer loop filter.

Synthesizer Loop filter

To minimize complexity of the external PCB layout the Main Synthesizer loop filter is also fully integrated into the IC. No external components or adjustments are required.

Voltage Controlled Oscillator

The integrated voltage controlled oscillator (VCO) is a complete self-calibrating subsystem. This employs a fully automated digital self-calibration function to ensure optimum phase noise performance over the entire frequency range. The VCO generates frequencies between 2520MHz and 2985MHz as required to operate in the four GSM bands for RX and TX.

- 36 -

3. TECHNICAL BRIEF

3.8 MEMORY(PF38F5060M0Y0BE, U201)

The 512Mbit Ballaire Wireless Flash memory with LPSDRAM stacked device family offers multiple high-performance solutions. The Ballaire flash die is manufactured on 65 n m ETOX™IX Process Technology. It delivers 108 MHz synchronous burst and pagemode read rates with supports multipartitioning with Read-While-Write (RWW) or Read-While-Erase (RWE) dual operations. The LPSDRAM is a high-performance volatile memory operating at speeds up to 133 MHz with configurable burst lengths. The Ballaire stacked device features programmable driver strength and low-power operation. This Stacked Chip Scale Package (SCSP) device is packaged in a standard Intel® x16D footprint and signal ballout. This model uses 512Mbits Flash memory and 128Mbits LPSDRAM memory with stacked.

LGE Internal Use Only

Only for training and service purposes

Figure. 3-8-1 MEMORY BLOCK DIAGRAM

- 37 -

3. TECHNICAL BRIEF

The DBB External Bus Interface provides a memory-mapped interface to external devices such as NOR Flash, NAND Flash, SRAM, SDRAM, PSRAM, and other custom devices. The External Memory Interface contains three distinct memory controllers: a NAND Flash Controller (NFC), an SDRAM Controller (SDC), and the External Bus Controller (EBC). These three controllers share the external pins. They also share an arbiter through which the DMA controllers (via DDBUS, ADBUS, and DMABUS) and the processor cores (via DSPBUS and MCUEBUS) access external devices. The following figure shows the external memory interface block diagram.

The following table shows the pin list for the external memory interface which supported by Main Base Band chipset(AD6900).

LGE Internal Use Only

Figure. 3-8-2 DBB EBU SUBSYSTEM BLOCK DIAGRAM

- 38 -

3. TECHNICAL BRIEF

LGE Internal Use Only

Only for training and service purposes

Function Signal Name

Data DATA[15:0]

Address ADDR[25:0]

Write Enable nWE

Read Enable nRD

Valid Address nADV

General Purpose Chip Select nA0CS

General Purpose Chip Select nA1CS

General Purpose Chip Select nA2CS

General Purpose Chip Select nA3CS

General Purpose Chip Select nA4CS

General Purpose Chip Select nA5CS

SDRAM Chip Select nSDCS

NAND Flash Chip Select nNDCS

Auxiliary Chip Select nB0CS

Auxiliary Chip Select nB1CS

High Write / Byte Strobe / Data Mask/ Command Latch Enable nHWR / nUBS/ SDQM[1] / CLE

Low Write / Byte Strobe / Data Mask / Address Latch Enable nLWR / nLBS / SDQM[0] / ALE

Burst Memory Clock BURSTCLK

External Device Wait Input nWAIT

SDC Row Address Strobe nSDRAS

SDC Column Address Strobe nSDCAS

SDC Write Enable nSDWE

SDC address 10 SDA10

SDC Clock Enable SDCKE

SDC Clock Output SDCLKOUT

NFC Busy Request nNDBUSY

- 39 -

3. TECHNICAL BRIEF

3.9 BT Module with integrated FM tuner (EWFMLBAXX, U200)

LGE Internal Use Only

Figure. 3-9-1 Bluetooth Module BLOCK DIAGRAM

Figure. 3-9-2 BCM2048 POWER BLOCK DIAGRAM

- 40 -

3. TECHNICAL BRIEF

3.9.1 Power Block

To reduce the external BOM, the EWFMLBAXX features three internal voltage regulators for the Bluetooth and FM sections that eliminate the need for filtering between the digital and noise sensitive RF circuits. These regulators operate from either 2.3V to 5.5V input supplies that support direct connection to Lithium batteries, or to a 1.7V to 3.6V input supply. The pre-regulator, PRE-REG, regulates battery power supply down to a level acceptable to the internal main regulators, BT REG and FM REG. The PRE-REG and the BT REG are enabled by an external input VREG_CTL. If VREG_CTL is low, the BCM2048 is shut down. If pre-regulation is not required because the input power supply is in the range 1.7V to 3.6V, VDDR5V and VDDR3V should be tied together to form the input power supply. For more on supplying power to the EWFMLBAXX, refer to the reference schematic document, available from your Broadcom representative.

3.9.2 Operational Description

The EWFMLBAXX Bluetooth radio transceiver provides enhanced radio performance to meet the most stringent industrial temperature applications and the tightest integration into mobile handsets and portable devices. It is fully compatible with all standard TCXO frequencies and provides full radio compatibility to operate simultaneously with GPS and cellular radios. It also integrates a complete FM and RDS/RBDS solution. The integrated solution saves power and board space, minimizes the BOM, and maximizes interface flexibility over a separate Bluetooth and FM solution. The FM subsystem can operate independently of Bluetooth and achieve full performance while Bluetooth is operating. It is designed to cover from 76 MHz, up to 108 MHz, bands (US, Europe, Japan) and to operate from either the Bluetooth reference clock or a 32-kHz LPO input. The FM subsystem supports a conventional I2C compatible interface and analog outputs for legacy systems, as well as digital interface options, such as I2S and PCM. The I2S and PCM interfaces supports 48-kHz operation and can be either master or slave. The analog interface consists of high-quality, line-level stereo DACs. The EWFMLBAXX FM subsystem includes advanced RDS/RBDS capability. The EWFMLBAXX synchronizes, demodulates, and decodes RDS/RBDS signals including CRC processing, post data filter detection, signal quality estimation, and buffering thus making it easy for an external application to read and process the RDS/RBDS data. The FM radio provides excellent reception, with 1 µV for 26 dB (S+N)/N typical sensitivity and greater than 60-dB SNDR capability, allowing easier system integration and antenna design. The FM subsystem includes many sought-after features, including signal-dependant mono/stereo blend, soft mute, and signal bandwidth control. The system has digital RSSI, signal quality, and IF frequency error indicators for system monitoring. The FM subsystem contains embedded automatic search and scan features, and large RDS data buffers to simplify the interface with an external host.

LGE Internal Use Only

Only for training and service purposes

- 41 -

3. TECHNICAL BRIEF

3.10 SIM Card Interface

The Main Base Band Processor(AD6900) provides SIM Interface Module. The AD6900 checks status Periodically During established call mode whether SIM card is inserted or not, but it doesn't check during deep sleep mode. In order to communicate with SIM card, 3 signals SIM_DATA, SIM_CLK, SIM_RST. And This model supports only 3V SIM Card.

LGE Internal Use Only

(GPIO_100)

20071029

Add for China ESD

R317

15K

C337 22p

2V85_VSIM

C335

DNI

C334

DNI

220n

C331

C336

DNI

C333

2V85_VSIM

C338

1000p

J300

5000-6P-1.8SL

ENSY0018701

1

C1

2

C2 C3

3

4

C5 C6

5

C7

6

GND1

7 8

GND2GND3

9

10

GND4

SIM_CLK

nSIM_RST

SIM_DATA

Figure 3-10. SIM CARD Interface

Signals Description

SIM_RST This signal makes SIM card to HW default status.

SIM_CLK This signal is transferred to SIM card.

SIM_DATA This signal is interface datum.

- 42 -

3. TECHNICAL BRIEF

3.11 Micro-SD Card Interface

AD6900 provides an interface for Multi-Media Cards (MMC), Secure Digital Memory Cards (SD Card), and Secure Digital Input/Output Cards (SDIO). All of these cards use similar interface protocols. The main difference between MMC and SD support is the initialization sequence. The main difference between SD card and SDIO support is the use of interrupt and read wait signals for SDIO. Features of the MMC/SD interface (MMCI) include:

Support for a single MMC, SD Memory or SDIO card Support for 1-bit and 4-bit SD modes (SPI mode is not supported) A six-pin external interface with clock, command, and up to 4 data lines Card detection using one of the data pins Card interface clock generation from SYSCLK SDIO interrupt and read wait features

The following table lists the six pins in the MMCI The MMCI consists of an MMC/SD controller along with a peripheral bus interface. The controller handles the multi-media and secure digital card functions. This includes clock generation, power management, command transfer, and data transfer. The bus interface contains 32bit memory mapped registers, converts 16-bit PBUS accesses to 32-bit register accesses,

LGE Internal Use Only

Only for training and service purposes

(1608)

Change the power for uSD card from 2V85_TF to 2V93_VEXT

R328

1M

100K

R322

4.7uC340

ECCH0006201

2V93_VEXT

VSS

5

CLK

3

CMD

7

DAT0

DAT1

8

DAT2

1

DAT3

2

GND1

9

GND2

10

GND3

11 12

GND4

4

VDD

6

ENSY0021401

SCHB1A0206J301

R320

100K

R327 0

2V93_VEXT

100K

R324

100K

R321

MC_D3

MC_CMD

MC_CLK

MC_D0

MC_D1MC_D2

MC_DET

Figure 3-11. Micro-SD Interface

- 43 -

3. TECHNICAL BRIEF

3.12 LCD Interface

LCD Module provides 2 LCD, Primary LCD(240x320, 262K Color) and Secondary LCD(128x160, 262k Color). The controller handles the multi-media and secure digital card functions. This includes clock generation, power management, command transfer, and data transfer. The bus interface contains 32bit memory mapped registers, converts 16-bit PBUS accesses to 32-bit register accesses, Two LCD shared Data bus, RD, WR and RS but CS (chip select signal). BLU (Back Light Unit) is shared primary and secondary LCD and include 5 white LEDs. White LCD driver is AAT3169 and it is descripted at next page.

LGE Internal Use Only

Eliminated Pull down resistor by Lee 071105

IF2 IF1

4

5

6

7

8

9

21

22

23

24

25

26

27

28

29

3

30

31

32

33

34

35

ENQY0013901 04-6293-035-000-829

1

10

11

12

13

14

15

16

17

18

19

2

20

CN101

18p

C102 C103

0.1u

2V93_VEXT

LCD_DATA05

LCD_DATA06

LCD_DATA07

LCD_ID1

LCD_VSYNC

MLED3

MLED

MLED2

MLED1

nLCD_RD

LCD_DATA00

LCD_DATA01

LCD_DATA02

LCD_DATA03

LCD_DATA04

nLCD_RESET

nLCD_MAIN_CS

LCD_RS

nLCD_WE

LCD_DATA10

LCD_DATA11

LCD_DATA09 LCD_DATA08

LCD_DATA12

LCD_DATA13

LCD_DATA14

LCD_DATA15

Figure 3-12-1. LCD Interface

- 44 -

3. TECHNICAL BRIEF

The AAT3157 is a low noise, constant frequency charge pump DC/DC converter that uses a tri-mode load switch (1X), fractional (1.5X), and doubling (2X) conversion to maximize efficiency for white LED applications. The AAT3157 is capable of driving six LEDs for a total of 180mA from a 2.7V to 5.5V input. The current sinks may be operated individually or in parallel for driving higher current LEDs. A low external parts count (two 1µF flying capacitors and two small 1µF capacitors at IN and OUTCP) make this part ideally suited for small, battery-powered applications. AnalogicTech's AS2Cwire¢‚ (Advanced Simple Serial Control¢‚) serial digital input is used to enable, disable, and set current for each LED with a 16 setting down to 50 µA. The lowcurrent mode supply current can be as low as 50 µA to save power. Each output of the AAT3157 is equipped with built in protection for output short-circuit and autodisable for load short-circuit conditions. Built-in softstart circuitry prevents excessive inrush current during start-up. A low-current shutdown feature disconnects the load from the input and reduces quiescent current to less than 1µA. The AAT3157 is available in a Pb-free, space-saving 2.85x3.0mm 12-pin TSOPJW package.

LGE Internal Use Only

Only for training and service purposes

Figure 3-12-2. AAT3169 CIRCUIT DIAGRAM

VBAT

AAT3157ITP-T1U501

C1+

C1-

C2+

C2-

D1 D2 D3

NC

10

C511

9 7

6

1 2 3 12

1u

C512

1u

MLED1 MLED2 MLED3

C522

C521C520

47p

47p47p

MLED

LCD_BACKLIGHT_CTRL

FB501 SFBH0007102 BLM15AG100PN1

C518 47p

C519

1u

C510

1u

R505

100K

5

IN

8

CP

11

EN_SET

4

GND

EUSY0238702

- 45 -

3. TECHNICAL BRIEF

The current level magnitude is controlled by AnalogicTech’s Simple Serial Control(S2C wire) Serial interface. The interface records rising edges of the EN/SET pin and decodes them into 16 different states. The 16 current level setting available are indicated table in below. This model uses level 5 in maximum 20mA group and level 15 in low current mode. But it don’t use low current stage.

LGE Internal Use Only

Figure 3-12-3 AAT3157 current level setting

Data Output(mA/Ch) Data Output(mA/Ch)

1 20.0 9 5.0

2 17.0 10 4.2

3 14.0 11 3.4

4 12.0 12 2.8

5 10.0 13 1.0

6 8.6 14 0.5

7 7.0 15 0.1

8 6.0 16 0.05

- 46 -

3. TECHNICAL BRIEF

3.13 Battery Charger Interface

The ISL6299 is a fully integrated low-cost single-cell Li-ion or Li-polymer battery charger. The charger accepts two power inputs, normally one from a USB port and the Other from a desktop cradle. The ISL6299 is an ideal charger for smart handheld devices that need to communicate with a personal computer via USB. The ISL6299 features 28V and 7V maximum voltages for the cradle and the USB inputs respectively. Due to the 28V rating for the cradle input, low-cost, large output tolerance adapters can be used safely. When both inputs are powered, the cradle input is used to charge the battery.

LGE Internal Use Only

Only for training and service purposes

Figure 3-13 BATTERY CHARGER BLOCK

VUSBIN

R208

VCHARGE

R209

VBAT

1

2

ISL6299U202

CRDL

USB

BAT

10

_PPR

_CHG

GND

PGND

3 4

8 11

C212

1u

(GPIO_037) USB_DET

nCHG_EN

(GPIO_059)

R212

100K

R210

39K

(1%)

R213

10K

1

C210

1u

C211

1u

6

9

7 5

R211

100K

IMIN

ICDL

USBON _EN

EUSY0254701

- 47 -

3. TECHNICAL BRIEF

3.14 Keypad Interface

LGE Internal Use Only

VOL_DOWN

CAMERA

9

(2007.12.20)

VOL_UP

7

(2007.12.20)

Change to NA

1

0

(2007.12.20)

SEND

Change to NA

MAIN KEYPAD

CLEAR

Change to NA

45

#

3

BGM_MP3

6

(2007.12.20)

*

Change to NA

2

8

CN400

1234

SHARP

R411 680

R413 680

diode

406

409

VA406

DNI_DIODE_1006

402

407

R404 680

DNI_DIODE_1006

diode

VA402

DNI_DIODE_1006

diode

VA404VA403

diode

DNI_DIODE_1006

680R406

408

R405 680

SEND

DNI_DIODE_1006

diodeVA407

401

405404

R412 680

CN404

1 2 3 4

403

DNI_DIODE_1006

diode

CLEAR

VA405

400

STAR

KEY_ROW1

KEY_ROW2

KEY_ROW3

KEY_ROW0

KEY_ROW5

KEY_ROW4

KEY_COL0

KEY_COL1

KEY_COL2

Figure 3-14-1 MAIN KEY STRUCTURE

Figure 3-14-2 HOT KEY STRUCTURE

10K

R400

VBAT

680R401

END

POWERKEY

OK

MENU UP

CONF

DOWN

RIGHT

KEY_ROW0

KEY_ROW1

KEY_ROW2

LEFT

KEY_ROW3

KEY_COL3

KEY_COL4

C104

NA

C105

NA

- 48 -

3. TECHNICAL BRIEF

The keypad interface supports a row/column decoding of a keyboard matrix of up to 8 rows and 8 columns. The interface generates an interrupt when any key is pressed, and the interrupt is routed through the system interrupt controller to the MCU. Software must scan the columns to determine which key was pressed. Debouncing must also be implemented in software. The keypad interface consists of eight tristateable KEYPADCOL outputs and eight KEYPADROW inputs. Pressing a key pulls the corresponding KEYPADROW input low. When all KEYPADCOL outputs are driven low, pulling any KEYPADROW input low generates an interrupt. In the interrupt service routine, the keypad must be scanned by setting only one column output low at a time and reading the row inputs. A zero is read anywhere a key is pressed on that column. The scan should be repeated at regular intervals until no key is being pressed. To implement debouncing, the software must require the same scan result for several scans. The keypad interrupt should not be cleared until no key has been pressed for several scans. The 8 by 8 matrix of rows and columns provides the possibility of up to 64 keys (with an additional 8 if a ghost column is used). Full flexibility in enabling and disabling individual rows and columns is provided. Any rows or columns not used should be disabled in the Keypad Control Register. The following figure shows the keypad interface and interrupt generation logic.

LGE Internal Use Only

Only for training and service purposes

Figure 3-14-3 keypad interface and interrupt generation logic

- 49 -

3. TECHNICAL BRIEF

3.15 Audio Interface

The AD6855 Audio Section supports communications and personal audio applications. The Audio Section provides an audio codec with two digital-to-analog converters and an analog-todigital converter, a microphone interface, and analog input and output channels.

Audio and Music Serial Ports

The AD6855 Audio Serial Port is described in detail in the Audio Serial Port (ASPORT) section below.

Audio Codec

The AD6855 audio codec supports communications applications with digital sample rates of 8 kHz or 16kHz. DAC 1 is used for receiving speech. An ADC is used for sending speech. The AD6855 audio codec supports personal audio applications with digital sample rates of 8 kHz, 11.025kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, or 48 kHz. DAC 1 and DAC 2 are used for monophonic audio. The channels are common in the digital section. DAC 1 and DAC 2 are used together for stereo audio, with DAC 1 decoding the left-channel digital input and DAC 2 decoding the right-channel digital input.

LGE Internal Use Only

Figure 3-15-1 ABB Internal Audio Block Diagram

- 50 -

3. TECHNICAL BRIEF

Audio codec operating modes can be controlled by writing 5 bit codes in the AudMode field of the AudControl1 register and in the AudMode_M field of the AudControl4 register. AudControl1 programs the sampling rate and stereo or monophonic operating mode for PCM audio samples input via the ASPORT. AudControl4 programs the sampling rate and stereo or monophonic operating mode for PCM audio samples input via the MSPORT. The AudControl1 and AudControl4 contain control bits that allow system software to turn on three audio loudness enhancement techniques meant for use when driving 8 ohm loudspeakers. These are high pass filter, dynamic range compressor, and x4 gain boost. These loudness enhancement techniques can be used with any AudMode or AudMode_M setting. And are programmed seperately and independently for the ASPORT and MSPORT PCM audio decoder data streams.

Analog Audio Output & Input Configurations

Output configurations are set by AudOS[4:0] bits in the AudControl2 register. Input configurations are set by AudIS[3:0] bits in the AudControl2 register. AudIn3LMute bit high in the AudMuteControl register (0x27). For configurations using “DAC2+AIN3R”, the AIN3R input may be muted by setting AudIn3RMute bit high in the AudMuteControl register. For configurations using “AIN3(L)”, the AIN3L and AIN3R inputs may be used as a differential input or the AIN3L input may be used as a single-ended input. Single ended configuration is chosen by setting AudIn3Cfg bit high in the AudControl3 register (0x32).

Audio DACs and Analog Filters

The Audio DACs are over-sampled switched-capacitor DACs. The analog filters are switchedcapacitor filters followed by active-RC filters.

LGE Internal Use Only

Only for training and service purposes

- 51 -

3. TECHNICAL BRIEF

Analog Audio Output Drivers

Audio Output 1

PGA gain for Audio Output 1 can be set by using bits AudOut1Gain[4:0] in the AudOut12Control (0x21) register. Output 1 is used for 32 Ω interface with differential output but can be used by single ended interface. And this model only uses passive filters between output port and Receiver.

Audio Output 2

PGA gain for Audio Output 2 can be set by using bits AudOut2Gain[4:0] in the AudOut12Control (0x21) register. Output 2 is used for 8 Ω. This port supports only a differential interface. And this model only uses passive filters and Class D audio amplifier between output port and speaker. Audio amplifier Gain is set by hardware component and gain is 6 times.

LGE Internal Use Only

Figure 3-15-2 ABB Audio OUTPUT1

Figure 3-15-3 ABB Audio OUTPUT2

- 52 -

3. TECHNICAL BRIEF

Audio Output 3

PGA gain for Audio Output 3 Stereo Configuration can be set by using bits AudOutLGain[4:0] and AudOutRGain[4:0] in the AudOutLRControl (0x22) register. When Audio Output 3 configured as monophonic differential output PGA gain can be set by using bits AudOut3Gain[4:0] in the AudOut3Control register (0x23). This port is used for headset speaker in stereo. This port must use DC-coupling capacitor as output DC. It uses two 100uF capacitor each other in left and right output.

Analog Audio Input

The AD6855 provides two analog input channels, AIN1 and AIN2, that may be used for both microphone and line inputs. The AIN1 and AIN2 channels are identical. One of the two channels is typically used with microphone built into a handset. The other channel is typically used with an external microphone or external line input.

LGE Internal Use Only

Only for training and service purposes

Figure 3-15-3 ABB Audio OUTPUT3

Figure 3-15-4 Audio Input Block Diagram

- 53 -

3. TECHNICAL BRIEF

Analog Input AIN1, AIN2 and VMIC configurations can be chosen by setting bits AudIS[3:0] in the AudControl2 register (0x1E). Additional gain of 9dB can be inserted into Analog Audio Input signal chain by setting AudPreampGainSel bit high in the AudControl3 register (0x32).

Microphone Interface

The microphone pre-amplifier and associated integrated resistors support electret microphones. An internal (Configuration 11) or external (Configuration 01 or 10) load resistor converts the current input of the microphone to a voltage signal which is amplified using a low-noise pre-amplifier. The Microphone signal path also includes an additional programmable gain of +9 dB gain directly after the pre-amplifier. Different microphones require different DC bias currents for optimum sensitivity.

Audio ADC and PGA

The Audio ADC is a high-order single-bit sigma-delta ADC that includes a switchedcapacitor PGA at the input.

Digital Filters

The AD6855 Audio Section provides two digital filters. The voiceband filter is used for applications with a 8 kHz digital sample rate. The high-quality audio filter is used for applications with higher digital sample rates.

Audio Accessory Detection

The AD6855 provides for detection of audio headset accessory insertion, extraction, and hookswitch events. The detector circuit is designed to operate with minimum power in standby mode. There are two pins dedicated to the accessory detector. AccDet is intended to interface to the external microphone and monitor its bias voltage. The ACCDET terminal is used to sense hookswitch events while a headset accessory is inserted. The JackSense terminal is interfaced to the switch pin of the Jack socket or a Jack Sense terminal on a handset system connector.

LGE Internal Use Only

- 54 -

3. TECHNICAL BRIEF

Use of the AccDet Terminal for Hookswitch Event Detection

The AccDet terminal may be connected directly to the Ain2P pin in the case of a DC coupling of the accessory microphone. If the accessory microphone is connected via a capacitor then the AccDet pin may be connected to the microphone side of the coupling capacitor. The AccDet terminal is used to detect hookswitch events. Hookswitch events cause the system to answer an incoming phone call or hang up on an active phone call. The detector circuit is in operation only if an accessory is inserted. It monitors the voltage at the AccDet terminal using a comparator as shown Figure below. Associated logic then provides the AudAccInt interrupt and updates the contents of the Detector Control register as follows on each comparator transition

LGE Internal Use Only

Only for training and service purposes

Figure 3-15-5 Audio Accessory Detection Block Diagram

- 55 -

3. TECHNICAL BRIEF

Use of the JackSense Terminal for Accessory Insertion and Removal Detection

Accessory insertion and removal is detected using the JackSense terminal. The JackSense terminal is connected to a signal produced by a mechanical connection that indicates the presence or absence of the headset accessory. The insertion/removal sense circuit fed by JackSense is flexible as far as the characteristics of the mechanical connection are concerned. The mechanical connection will often times be pulled down in one state and floating in the other. In such cases a 1uA on chip current source is used to pull JsckSense to VBAT when the mechanical connection is floating. To avoid false interrupts the Accessory detect logic has a hardware polling loop which will prevent Interrupt generation from comparator transitions with a duration of no less than 10 mSec.

LGE Internal Use Only

Figure 3-15-6 Accessory Insertion/Removal Detector Block Diagram

- 56 -

3. TECHNICAL BRIEF

3.16 Camera Interface(2M Fixed Focus Camera)

3.16.1 AD6900 Camera Interface (PPI Block)

AD6900 provides a Parallel Peripheral Interface (PPI) that can connect directly to camera modules. The PPI is an input-only parallel external port that accommodates up to 10 bits of data, in a variety of RGB and YUV color formats. In addition, ITU-656 (CCIR656) and ITU-601 (CCIR601) compatible data transfers are supported.

The PPI feature set includes:

Eight dedicated data pins and two data pins muxed with GPIOs Parallel data transfer rates up to 32.5 MB/s Two frame syncs (horizontal and vertical), with programmable polarity A bidirectional clock pin, with programmable output clock rate up to 65 MHz Synchronization by detection of embedded preamble codes or by using frame synchronization pins ITU standard and counter controlled data transfers 8-bit data packing to reduce DMA bandwidth for image data Data re-ordering to reduce DMA bandwidth for YUV 4:2:2 data A 32 word by 16 bit input FIFO

The PPI offers specific configurations to support still image and video data inputs. The PPI supports ITU-601 and ITU-656 standards. It also provides Active Video Only and Entire Field operational modes. In all modes, data packing options optimize DMA transfer bandwidth for YUV 4:2:2 and other data formats. The PPI pins are listed in the following table.

LGE Internal Use Only

Only for training and service purposes

- 57 -

3. TECHNICAL BRIEF

PPI Architecture

A simplified PPI block diagram is shown in the following figure. The PPI contains a 32 word by 16 bit FIFO, interrupt request (IRQ) generation logic, clock dividers, and memory mapped registers(MMRs). The PPI provides a parallel interface to camera modules.

LGE Internal Use Only

Bi-Directional Input Clock PPI_CLK

Input Frame Sync PPI_VSYNC

Input Frame Sync PPI_HSYNC

Input Optional Data PPI_DATA_10B_LSB[0]

Input Optional Data PPI_DATA_10B_LSB[1]

Input Data PPI_DATA[0]

Input Data PPI_DATA[1]

Input Data PPI_DATA[2]

Input Data PPI_DATA[3]

Input Data PPI_DATA[4]

Input Data PPI_DATA[5]

Input Data PPI_DATA[6]

Input Data PPI_DATA[7]

Direction Default Function Signal Name

Figure 3-16-1 PPI Block Diagram

- 58 -

3. TECHNICAL BRIEF

FIFO Operation

The PPI FIFO is 32 words by 16 bits. Received data is stored in the FIFO either as 16- bit words or as 8-bit words. The data is only stored a 8-bit words when the DLEN and PACK_EN bits in the PPI Control register are cleared. The data in the FIFO may be read whenever the FIFO is not empty. The DMA controllers may burst read the FIFO data whenever at least four words are contained in the FIFO. These FIFO status conditions are reported in the PPI Status register and can be unmasked in the PPI DMA Interrupt Mask register to generate interrupts.

Interrupt Request Generation

The PPI generates interrupt requests for the DMA controllers, MCU, and DSP. An interrupt can be generated for the following conditions:

Start of a frame FIFO overflow FIFO underflow Incorrect number of data words in a line or lines in a frame Preamble code error (in ITU-656 mode)

PPI Clock Frequency

The PPI transfer clock may be provided either by an external source or internally by the PPI. BCLK is the source for the PPI clock divider. The clock may be divided by 1, 2, 3, 4, 5, 6, 7,8, 16, 32 or 64 from BCLK. However, the maximum frequency supported is 32.5 MHz for packed 8-bit transfers and 16.25 MHz for 10-bit or unpacked 8-bit transfers. At higher clock frequencies, the APPDMA does not support the incoming data bandwidth. A PPI FIFO (32 words deep, 16-bits wide) is provided to compensate for arbitration latency encountered by APP DMA accessing system resources.

LGE Internal Use Only

Only for training and service purposes

- 59 -

3. TECHNICAL BRIEF

3.17 KEY BACLKLIGHT LED Interface

The AD6855 Auxiliary Section provides three independent PWM light controllers. The PWM output controllers regulate the average current through active lights.

The output frequencies of the LIGHTx PWM output controllers are set by the Light12Period (0x2F) and Light3Period (0x31) control registers.

With fMCLK = 13 MHz, frequencies ranging from 50.781 kHz to 49.591 Hz may be specified.

fLIGHT1 = ( fMCLK / 256 ) / ( Light12Period[9:0] + 1) fLIGHT2 = ( fMCLK / 256 ) / ( Light12Period[9:0] + 1) fLIGHT3 = ( fMCLK / 256 ) / ( Light3Period[9:0] + 1)

he output duty cycles of the PWM output controllers are set by the LightxDutyCycle[7:0] control registers - Light1DutyCycle (0x2D), Light2DutyCycle (0x2E) and Light3DutyCycle (0x30).

This model use Light3 port for main key LED and Light1 port for slide LED.

LGE Internal Use Only

Figure 3-17 ABB Light Controller Block Diagram

- 60 -

3. TECHNICAL BRIEF

3.18 Vibrator Interface

Vibrator is driven by switch relay(SUY98005LT1G). Switch relay is controlled by VIBRATOR signal of DBB for only ON/OFF function.

LGE Internal Use Only

Only for training and service purposes

Figure 3-18 Vibrator Driver

VIBRATOR

R407

1K

R410

100K

Change the connection from GND to between pad (2007.10.30)

U400 SUY98005LT1G

1

VIN

VOUT

2

GND

EUSY0160401

3

R408

R409 10

10

L400

100nH

C400 1u

VIB_P

VIB_N

VBAT

CN402

ENEY0003801 24-8000-002-000-829

Eliminate Vib. pads

1

2

2008.01.03

4.1 RF Component

U600 Power Amp Module (SKY77318)

U601 (AD6548) RF Main Chip (Transceiver)

X600 Crystal, 26MHz Clock

FL600 FEM

- 61 -

4. TROUBLE SHOOTING

LGE Internal Use Only

TEST POINT

Figure 4-1

FL600

U600

U601

X600

LGE Internal Use Only

Only for training and service purposes

- 62 -

4. TROUBLE SHOOTING

4.2 RX Trouble

CHECKING FLOW

START

HP8960 : Test mode

62 CH, 7 level setting (TCH)

62CH, -60dBm setting (BCCH)

Spectrum analyzer setting

Oscilloscope se

tting

(1) Check

Crystal Circuit

(2) Check

Mobile SW &FE

(3) Check

RX I/Q Signa

Re-download SW or

Do calibration again

M

l

LGE Internal Use Only

4. TROUBLE SHOOTING

- 63 -

(1) Checking Crystal Circuit

TP1

TP2

26 MHzO.K?

No

Crystal Circuit is OK See next Page to check Mobile SW

See next Page to check Mobile SW

Yes

Change X600

1u

C622

0.1u

C636

C618

82p

27p

C632

C621

47p

VLDO1

C633

0.1u

VAFC_NC

VBAT

14

VCC_BBI

4

24

VCC_BBQ

1

VCC_FE

VCC_REF

17

VCC_TXVCO

12

13

VDD

15

VLDO1

VLDO2

16

9

VLDO3

2V75_VCXO

REFIN

REFINB

19

REF_OP

21

RX1800

28

27

RX1800B

RX1900

26

25

RX1900B

RX850

32

31

RX850B

RX900

30

29

RX900B

SCLK

6

5

SDATA7SEN

11

TXOP_HI

TXOP_LO

10

18

EUSY0280101

AD6548

U601

GND

33

I

2

3

IB

NC

8

Q

23

22QB20

34

X600

TSX-3225_26MHZ

EXXY0024401

12

C624 220n

10

R607

VLDO1

QN

QP

TEST POINT CHECKING FLOW

CIRCUIT

Graph 4-2-1(a)

Graph 4-2-1(b)

Figure 4-2-1

TP1

TP2

WAVEFORM

KEY_ROW0 KEY_ROW1 KEY_ROW2 KEY_ROW3 KEY_ROW4

SIM_DATA

SIM_CLK

MC_CLK

MC_CMD

MC_D0 MC_D1 MC_D2 MC_D3

nSLIDE_DET

nLCD_RD

nLCD_WE

CAM_LDO_EN

LCD_RS

LCD_VSYNC CAM_PWDN BT_LDO_EN

LOUD_SPK_EN

SPK_RCV_SEL

nLCD_RESET

nCAM_RESET

nBT_RESET

CAM_I2C_DATA

CAM_I2C_CLK

CAM_HSYNC CAM_VSYNC

CAM_PCLK

C122

1000p

U14 AA13 AB12

W13 AA12

N17

W17

R19

U22

R17

N22

U19

W18

AB21 AA22

M22

L19 K19

B14

F22

J19

J17 E21 F21 K17

P4

P19

P21 P17

T19

K21 L21 P22

T17

Y21 L22

KEYPADROW_0 KEYPADROW_1 KEYPADROW_2 KEYPADROW_3 KEYPADROW_4

SIMDATAIO SIMCLK

CLKIN26M

MC_CLK MC_CMD MC_DAT_0 MC_DAT_1 MC_DAT_2 MC_DAT_3

GPIO_010

EB2_NRD EB2_NWE EB2_NWAIT

EB2_ADDR_00 EB2_ADDR_01 EB2_ADDR_02 EB2_ADDR_03 EB2_ADDR_04 EB2_ADDR_05 EB2_ADDR_06 EB2_ADDR_07 EB2_ADDR_08 EB2_ADDR_09 EB2_ADDR_10 EB2_ADDR_11 EB2_ADDR_12

PPI_HSYNC PPI_VSYNC PPI_CLK PPI_DATA_0

LGE Internal Use Only

Only for training and service purposes

4. TROUBLE SHOOTING

- 64 -

(2) Checking Mobile SW & FEM

C645

100p

2V75_VCXO

R608

10

39p

C628

13

VDD

12

GND2

16

GND3

GND4

18

19

GND5

GND6

20

10

GSM1800_1900_TX

5

GSM1800_RX1

6

GSM1800_RX2

GSM1900_RX1

7

8

GSM1900_RX2

15

GSM850_900_TX

GSM850_RX1

1

2

GSM850_RX2

GSM900_RX1

3

GSM900_RX2

4

VC1

14

VC2

SFAY0011101

FL600

DGM1110M014

ANT

17

9

GND1

11

47p

C620

C626

0.1u

C644

100p

ANT_SW2

ANT_SW1

TEST POINT

CIRCUIT

Figure 4-2-2

WAVEFORM

Graph 4-2-2 FEM Control Signal

TP2

TP1

2V75_VCXO

TP1 TP2

LGE Internal Use Only

4. TROUBLE SHOOTING

- 65 -

CHECKING FLOW

Table 4.2.1

Switch Mode Vc1 Vc2

GSM850/900 Tx 0 1

GSM1800/1900 Tx 1 1

GSM850/900 Rx 0 0

GSM1800/1900 Rx 1 0

For these 2 test case,

No Call connection is needed

Check SW600 Pin ANT,RF

with RF Cable connected.

Check SW600 Pin ANT,RF

with No RF Cable Connected

Check C644,C645,C626

Check whether Ant SW

Set as RX mode

Refer to Table 4.2.2

Check RF Level of

FL600.3(for EGSM) &

FL600.5&7(for DCS&PCS)

Open

Yes

Short

Yes

Check Vctrl 1,2 & Vcxo

Yes

Pin 16 : ~ -62dBm

Pin 14 & 12 : ~ -63dBm

Yes

Ant SW & Mobile SW is OK

See next Page to check

Rx I/Q Signal

No

Changing SW

Changing the Board.

Chang

600

ing FL600

For this RF Level test case,

RX Stand alone Mode is needed

refer to chapter

10

(3) Checking RX I/Q

LGE Internal Use Only

Only for training and service purposes

4. TROUBLE SHOOTING

- 66 -

TEST POINT

TP1 &TP4

TP2 & TP3

WAVEFORM

CIRCUIT

Graph 4-2-3

Figure 4-2-3

CHECKING FLOW

TP1

TP2

TP3

TP4

TP3

TP4

SW600

U601

TP2

TP1

QN

C618

QP

VLDO1

82p

C621

47p

25

RX1900B

26

RX1900

27

RX1800B

28

RX1800

29

RX900B

30

RX900

31

RX850B

32

RX850

33

GND

VLDO1

IP

C640

82p

IN

24

23

22QB20

Q

VCC_BBQ

AD6548

U601

EUSY0280101

VCC_FE

I

IB

1

2

3

21

REF_OP

VCC_BBI

4

5

TSX-3225_26MHZ

19

18

REFIN

REFINB

VAFC_NC

VCC_TXVCO

SCLK

SDATA7SEN

6

34

X600

EXXY0024401

17

VCC_REF

VLDO2 VLDO1

VBAT

VDD

TXOP_HI

TXOP_LO

VLDO3

NC

8

12

2V75_VCXO

R607

10

C622

1u

C624 220n

16 15 14 13 12 11 10 9

C636

0.1u

C632

C633

0.1u

27p

C641 C643

C642

100p 100p

100p

Check C618, C640.

Check if there is any

Major difference

Refer to graph 4.

2.3

No

Similar?

Yes

Redownload software and calibration again

Replace U60

1

LGE Internal Use Only

4. TROUBLE SHOOTING

- 67 -

4.3 TX Trouble

CHECKING FLOW

START

HP8960 : Test mode

62 CH, 7 level setting (TCH)

62CH, -60dBm setting (BCCH)

Spectrum analyzer setting

Oscilloscope se

tting

(1)Check

Crystal Circuit

(2)Check

Mobile SW

& FEM

(3)Check

PAM control

al

sign

(4)Check

TX I/Q Signal

Redownload SW or Do calibration again

(1) Checking Crystal Circuit

- 68 -

LGE Internal Use Only

Only for training and service purposes

26 MHzO.K?

No

Crystal Circuit is OK See next Page to check Mobile

SW

See next Page to check Mobile SW

Yes

Change X60

0

TEST POINT CHECKING FLOW

CIRCUIT

Graph 4-3-1(a)

Graph 4-3-1(b)

Figure 4-3-1

WAVEFORM

TP1

TP2

TP1

TP2

QN

C618

82p

QP

VLDO1

C621

47p

24

25

RX1900B

26

RX1900

VCC_BBQ

27

RX1800B

28

RX1800

29

RX900B

30

EUSY0280101

RX900

31

RX850B

32

RX850

33

GND

VCC_FE

1

VLDO1

23

2

22QB20

Q

AD6548

U601

I

IB

3

21

REF_OP

VCC_BBI

4

19

REFIN

SDATA7SEN

6

5

REFINB

SCLK

TSX-3225_26MHZ

34

X600

EXXY0024401

17

18

VCC_REF

VAFC_NC

VLDO2 VLDO1

VBAT

VDD

VCC_TXVCO

TXOP_HI

TXOP_LO

VLDO3

NC

8

12

2V75_VCXO

R607

10

C622

1u

C624 220n

16 15 14 13 12 11 10 9

C632 27p

C636

0.1u

C633

0.1u

KEY_ROW0 KEY_ROW1 KEY_ROW2 KEY_ROW3 KEY_ROW4

SIM_DATA

SIM_CLK

MC_CLK

MC_CMD

MC_D0 MC_D1 MC_D2 MC_D3

nSLIDE_DET

nLCD_RD nLCD_WE

CAM_LDO_EN

LCD_RS LCD_VSYNC CAM_PWDN BT_LDO_EN

LOUD_SPK_EN

SPK_RCV_SEL

nLCD_RESET

nCAM_RESET

nBT_RESET

CAM_I2C_DATA

CAM_I2C_CLK

CAM_HSYNC CAM_VSYNC

CAM_PCLK

C122

1000p

AA13 AB12

W13

AA12

W17

W18

AB21 AA22

U14

L19 K19

B14

F22

J19

J17 E21 F21 K17

P4

P19 N17

P21 P17 R19 T19 U22 R17 K21 L21 P22 N22 U19 T17

Y21 L22 M22

KEYPADROW_0 KEYPADROW_1 KEYPADROW_2 KEYPADROW_3 KEYPADROW_4

SIMDATAIO SIMCLK

CLKIN26M

MC_CLK MC_CMD MC_DAT_0 MC_DAT_1 MC_DAT_2 MC_DAT_3

GPIO_010

EB2_NRD EB2_NWE EB2_NWAIT

EB2_ADDR_00 EB2_ADDR_01 EB2_ADDR_02 EB2_ADDR_03 EB2_ADDR_04 EB2_ADDR_05 EB2_ADDR_06 EB2_ADDR_07 EB2_ADDR_08 EB2_ADDR_09 EB2_ADDR_10 EB2_ADDR_11 EB2_ADDR_12

PPI_HSYNC PPI_VSYNC PPI_CLK PPI_DATA_0

- 69 -

LGE Internal Use Only

(2) Checking Mobile SW & FEM

C645

100p

2V75_VCXO

R608

10

39p

C628

13

VDD

12

GND2

16

GND3

GND4

18

19

GND5

GND6

20

10

GSM1800_1900_TX

5

GSM1800_RX1

6

GSM1800_RX2

GSM1900_RX1

7

8

GSM1900_RX2

15

GSM850_900_TX

GSM850_RX1

1

2

GSM850_RX2

GSM900_RX1

3

GSM900_RX2

4

VC1

14

VC2

SFAY0011101

FL600

DGM1110M014

ANT

17

9

GND1

11

47p

C620

C626

0.1u

C644

100p

ANT_SW2

ANT_SW1

TEST POINT

CIRCUIT

Figure 4-2-2

WAVEFORM

Graph 4-2-2 FEM Control Signal

TP2

TP1

2V75_VCXO

TP1 TP2

Figure 4.3.2

LGE Internal Use Only

Only for training and service purposes

4. TROUBLE SHOOTING

- 70 -

CHECKING FLOW

Table 4-3-1

Switch Mode Vc1 Vc2

GSM850/900 Tx 0 1

GSM1800/1900 Tx 1 1

GSM850/900 Rx 0 0

GSM1800/1900 Rx 1 0

Check C644,C645,C626

Check whether Ant SW

Set as TX mode

Refer to Graph 4.3.2

Refer to Table 4.3.2

For the test,

TX Stand alone Mode is needed. Refer to

chapter 10 (PL=7 for EGSM, PL=2 for

Check Vctrl 1,2 & Vcxo

DCS&PCS)

No

Yes

Changing boar

d

Check RF Level of

FL600.15(for EGSM) & FL600.10(for

DCS&PCS)

Check SW600.ANT, RF with RF

Cable connected.

Check SW600.ANT,RF

with RF Cable disconnected

Pin15 : ~29.5dBm

Pin10 : ~26.5dBm

Yes

Open

Yes

Short

Yes

END

No

Go to 4.3.3 Checking PAM

control sign

Changing SW600

Changing SW

600

al

LGE Internal Use Only

4. TROUBLE SHOOTING

- 71 -

(3) Checking PAM Control Signal

Similar?

Yes

No

Check TX_RAMP and PAM_EN

Any Major Difference or

not

Similar?

Yes

No

Go to Next Step

Similar?

Yes

No

Re-download S/W

Check if there is

Any Major Difference or not

Refer to Graph 4.3.3

(GPIO_060)

(GPIO_070)

0.01u

C605

10nH

L601

C604

0.01u

C616 27p

C610

0.5p

C603

39p

18pC607

PA_BAND

GND9

16

P_GND

21

19

RSVD_GND

VAPC

20

VBATT

17

2

VCC1A

6

VCC1B

BS

1

3

DCS_PCS_INDCS_PCS_OUT

15

4

EGSM_IN

11

EGSM_OUT

ENABLE

18

GND1

5

7

GND2

GND38GND4

9

10

GND512GND613GND7

GND8

14

U600

SKY77318

SMPY0014001

L602 33nH

8p

C615

1KR600

L603

39nH

PA_EN

PA_BAND

TX_RAMP

TEST POINT

CHECKING FLOW

WAVEFORM

CIRCUIT

Graph 4-3-3

Figure 4-3-3

TP2

TP1

TP2

TP1

LGE Internal Use Only

Only for training and service purposes

4. TROUBLE SHOOTING

- 72 -

(4) Checking TX I/Q

Re-download the Software And calibrate

Check if there is Any

Major Difference

Refer to Graph4.3.4

Similar?

Yes

No

Replace U60

1

U601

C618

C640

SW600

TEST POINT

WAVEFORM

CIRCUIT

Graph 4-3-4

Figure 4-3-4

CHECKING FLOW

QN

QP

VLDO1

IP

IN

C621

47p

C618

82p

24

23

25

RX1900B

26

RX1900

VCC_BBQ

27

RX1800B

28

RX1800

29

RX900B

30

EUSY0280101

RX900

31

RX850B

32

RX850

33

GND

VCC_FE

1

2

VLDO1

C640

82p

22QB20

Q

AD6548

U601

I

3

21

IB

4

19

REFIN

REF_OP

VCC_BBI

SDATA7SEN

6

5

TSX-3225_26MHZ

34

EXXY0024401

17

18

REFINB

VCC_REF

VAFC_NC

VLDO2 VLDO1

VBAT

VDD

VCC_TXVCO

TXOP_HI

TXOP_LO

VLDO3

SCLK

NC

8

X600

12

2V75_VCXO

R607

10

C622

1u

C624 220n

16 15 14 13 12 11 10 9

C636

0.1u

C632

C633

0.1u

27p

C642

C641 C643

100p

100p 100p

4.4 Power On Trouble

LGE Internal Use Only

4. TROUBLE SHOOTING

- 73 -

TEST POINT

Figure 4-4

CIRCUIT

TP2

TP1

2V93_VEXT

2V75_VCXO

1V5_VPLL

U501

VCORE

2V85_VSI

1V82_VINT

1V88_VMEM

A3

VEXT1

B3

VEXT2

L4

VMEMOUT1

M4

VMEMOUT2

G12

VABB

F12

VPLL

F2

VCOREPWR2

F1

VCOREPWR1

E1

VCORESW1

E2

VCORESW2

K1

VINTOUT

K2

VINT

D12

VAPPGATE

C11

VUSB

M6

VSIM

J12

VMIC

C12

VRF

M5

VGP

A8

PA

A9

IP

A10

IN

A12

QP

A11

QN

J9

SPWR1

J10

SPWR2

B7

REFBB

2V5_VMIC

M

U100

1V8_VRT

1V8_VG

C

P

TP1

TP2

2V5_VAB

D101

B

3

R101

100K

R400

10K

680R401

RPWRON

VBAT

END

ELCP0008001

TX_RAMP

IP IN

QP QN

1uC139

2V93_VEXT

1V88_VMEM

2V5_VABB

1V5_VPLL

VBAT

VCORE

1V82_VINT

22u

C134

2125, 0.85T

C127 1u

VUSB

1u

C128

2V85_VSIM

C129 1u

4.7uHL100

1uC124

VBAT

C138

1u

FB100

SFBH0008101

2.2uC133

(1608)

C126 33u

C123 1u

C125 1u

Change the value for

Board noise(2007.11.01)

EXT_PWRON

2V5_VMIC

2V75_VCXO

C130 1u

PWRON

1V8_VGP

1uC131

C132 1u

POWERKEY

20070918

Change for BT

D101

1

2

KDR331V

EDSY0017301

LGE Internal Use Only

Only for training and service purposes

4. TROUBLE SHOOTING

- 74 -

CHECKING FLOW

START

Check Battery Voltage

> 3.35V

YES

Push power-on key

And check the level change

into low of POWERKEY

Check the voltage of

The LDO outputs at U

Logic level at RPWRON

(DBBON) of D101(TP2)

= HIGH(above1.2V)

(TP1

)

YES

100

YES

?

YES

NO

VCORE=1.2V~1.5V 2V75_VCXO=2.75V 1V88_VMEM=1.88V 2V85_VSIM= 2.85V 2V93_VEXT=2.93V 1V5_VPLL=1.5V 2V5_VMIC=2.5V 2V5_VABB=2.5V

NO

Charge or Change Battery

Check the contact of power key

Or dome-switc

Replace U100

Re-download software

h

Is the phone power on?

YES

The phone will

Properly operati

ng.

NO

Replace U100 and Re-download software

Does it work properly?

NO

Replace the main board

- 75 -

4. TROUBLE SHOOTING

LGE Internal Use Only

4.5 Charging Trouble

TEST POINT

CIRCUIT

Figure 4-5

TP2

TP1

C312

(GPIO_037) USB_DET

nCHG_EN

(GPIO_059)

R210

R212

39K

100K

(1%)

TP1 TP2

U301

VCHARGE

VUSBIN

R209

R208

1

10K

R213

10K

C210

1u

C211

1u

FL300

R211

100K

1

CRDL

2

USB

6

IMIN

9

ICDL

7

USBON

5

_EN

EUSY0254701

ISL6299U202

10

BAT

3

_PPR

4

_CHG

8

GND

11

PGND

VBAT

C212

1u

VCHARGE_OVP

1uC322

1

IN1

4

IN2

5

IN3

3

_FLAG

2

GND

11

NC1

12

NC2

EUSY0319201

SFEY0007101

ICVFP10181E301FR

NCP348MTR2GU301

GND1 GND2

IN OUT

_EN

GATE_OUT

GATE

OUT2

OUT1

FL300

VCHARGE_OVPVCHARGE_IO

10

9

8

7

6

VCHARGE

CN300

U202

R210

C304 10u ECTH0005601

R311 30K

R312 30K

CHG_DET

LGE Internal Use Only

Only for training and service purposes

4. TROUBLE SHOOTING

- 76 -

CHECKING FLOW

START

Change the battery

Battery is charged?

NO

Is I/O Connector(CN300)

at pin6 of U301 = 5.1V?

soldered ?

well-

YES

Check the voltage at

C312 = 5.

Is the voltage

of R311 = 5.1V?

(TP1

(TP2

1V ?

YES

)

YES

)

YES

NO

Charging is

properly operati

Resolder the CN300

(Pin 12,13 : VCHARGE)

The TA is out of order

Change the TA

Replace the

U301

Replace the

F

ng

L300

Is Voltage across R210

about 1.2V

Battery is charged?

Charging is

properly operati

?

YES

ng

NO

Replace the

U202

Replace the main board

LGE Internal Use Only

4. TROUBLE SHOOTING

- 77 -

4.6 Vibrator Trouble

TEST POINT

CIRCUIT

Figure 4-6

TP2

TP1

C400

L400 R408,R409

TP1

U400

VIBRATOR

R407

1K

R410

100K

U400 SUY98005LT1G

1

VIN

3

VOUT

2

GND

EUSY0160401

R408

R409 10

Change the connection from GND to between pad (2007.10.30)

10

L400

100nH

C400 1u

VIB_P

VIB_N

VBAT

CN402

1

2

ENEY0003801 24-8000-002-000-829

Eliminate Vib. pads

TP2

2008.01.03

- 78 -

4. TROUBLE SHOOTING

LGE Internal Use Only

Only for training and service purposes

CHECKING FLOW

SETTING : Enter the engineering mode, and set vibrator on at vibration of BB test menu

START

Check the soldering of

C400, L400, R407, R408

, R409

Is the voltage at pin 3

of U400 toggled?

YE

Is the voltage

of R407 toggled?

YES

Connection of vibrator

Replace vibrator

Working well !

(TP1

S

(TP2

Is good

Vibrator

)

?

YES

NO

Check the soldering

or replace U400

Replace the main board.

NO

Reconnect vibrator

- 79 -

4. TROUBLE SHOOTING

LGE Internal Use Only

4.7 LCD Trouble

TEST POINT

Figure 4-7

CN500

CN101

FL501FL500 FL503 FL504

FL502

TP1

CN101

U501

R505

CN102

C508, C509,

R501, R502

CN100

LGE Internal Use Only

Only for training and service purposes

4. TROUBLE SHOOTING

- 80 -

CIRCUIT

TP1

2V8_AVDD

LCD_ID_L

MLED3 MLED1 MLED2

MLED

SPK_RCV_N

SPK_RCV_P

KEY_COL4 KEY_COL3 KEY_ROW3 KEY_ROW2 KEY_ROW1 KEY_ROW0

KEY_BACKLIGHT

CAM_I2C_CLK

CAM_I2C_DATA

CAM_VSYNC

CAM_HSYNC

CAM_MCLK CAM_PWDN

nCAM_RESET

CAM_PCLK

2V8_IOVDD

R503

R504

FL505

4.7K

4.7K ICVE10184E150R500FR

9

8

7

6

R506

Eliminated C513, C514, C523, C524 by Lee_071105

C507

47p

1

INOUT_A1

INOUT_B1

2

INOUT_A2

INOUT_B2

3

INOUT_A3

INOUT_B3

4

INOUT_A4

INOUT_B4

G15G2

10

SFEY0011601

20K

5G210

G1

INOUT_B4

INOUT_A4

4

INOUT_B3

INOUT_A3

3

INOUT_B2

INOUT_A2

2

INOUT_B1

INOUT_A1

1

FL507

ICVE10184E150R500FR

6

7

8

9

FL500

INOUT_A1

INOUT_A2

INOUT_A3

INOUT_A4

G15G2

10

ICVE10184E150R101FR

1

9

INOUT_A1

INOUT_B1

8

INOUT_A2

INOUT_B2

7

INOUT_A3

INOUT_B3

6

INOUT_A4

INOUT_B4

G15G2

10

SFEY0010501

FL502 ICVE10184E150R101FR

9

INOUT_A1

INOUT_B1

8

INOUT_A2

INOUT_B2

7

INOUT_B3

INOUT_A3

6

INOUT_B4

INOUT_A4

G110G2

5

1

2

3

4

FL504

ICVE10184E150R101FR

9

INOUT_A1

INOUT_B1

8

INOUT_A2

INOUT_B2

7

INOUT_A3

INOUT_B3

6

INOUT_B4

INOUT_A4

G110G2

100ohmR501

5

100ohmR502

C509

C508 15p

15p

ICVE10184E150R500FR

10

G15G2

INOUT_B4

INOUT_A4

4

INOUT_B3

INOUT_A3

3

INOUT_B2

INOUT_A2

2

INOUT_B1

INOUT_A1

1

LCD_DATA15

2

LCD_DATA14

3

LCD_DATA13

4

LCD_DATA12

LCD_DATA11 LCD_DATA10 LCD_DATA09 LCD_DATA08

1

LCD_DATA07

2

LCD_DATA06

3

LCD_DATA05

4

LCD_DATA04

LCD_DATA03 LCD_DATA02 LCD_DATA01 LCD_DATA00

1

nLCD_RD

2

nLCD_WE

3

LCD_RS

4

nLCD_MAIN_CS

LCD_VSYNC

nLCD_RESET

CAM_DATA7 CAM_DATA6 CAM_DATA5 CAM_DATA4

FL508

CAM_DATA3

6

CAM_DATA2

7

CAM_DATA1

8

CAM_DATA0

9

VBAT

2V8_IOVDD

1V8_DVDD

C516

C515

1u

2V93_VEXT

FL501 ICVE10184E150R101FR

C502

C500

1u

C517 1u

C503

C501

0.1u

47p

CN500

G3 G4

40 41 39

42

38

43 44

37

45

36

46

35

47

34

48

33

49

32

50

31

51

30 29

52

28

53

27

54

26

55

25

56

24

57

23

58 59

22

60

21

61

20

62

19

63

18

64

17

65

16

66

15 14

67

13

68

12

69

11

70

10

71

9

72 73

8

74

7

75

6

76

5

77

4

78

3

79

2

80

1

G1 G2 AXK7L80227G ENBY0026001

10

G15G2

INOUT_A4

INOUT_B4

4

INOUT_A3

INOUT_B3

3

INOUT_A2

INOUT_B2

2

INOUT_B1

INOUT_A1

1

FL506 ICVE10184E150R500FR

9

INOUT_A1

INOUT_B1

8

INOUT_A2

INOUT_B2

7

INOUT_A3

INOUT_B3

6

INOUT_A4

INOUT_B4

G110G2

5

6

7

8

9

ICVE10184E150R101FR

9

INOUT_B1

8

INOUT_B2

7

INOUT_B3

6

INOUT_B4

1

2

3

4

FL503

LCD CONNECTOR

04-6293-035-000-829 (ELCO 35 pin ZIF connector)

2V93_VEXT

CN101

1

IF2 IF1

ENQY0013901 04-6293-035-000-829

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

MLED MLED1 MLED2 MLED3

LCD_ID1 LCD_DATA15 LCD_DATA14 LCD_DATA13 LCD_DATA12 LCD_DATA11 LCD_DATA10 LCD_DATA09 LCD_DATA08 LCD_DATA07 LCD_DATA06 LCD_DATA05 LCD_DATA04 LCD_DATA03 LCD_DATA02 LCD_DATA01 LCD_DATA00

nLCD_RD

nLCD_WE

LCD_RS

nLCD_MAIN_CS

LCD_VSYNC

Eliminated Pull down resistor by Lee 071105

nLCD_RESET

C102 C103 18p

0.1u

MLED

LCD_BACKLIGHT_CTRL

FB501 SFBH0007102 BLM15AG100PN1

C519

C518 47p

VBAT

AAT3157ITP-T1U501

5

R505

100K

IN

8

CP

11

EN_SET

4

GND

EUSY0238702

C510

1u

C1+

C2+

10

C511

1u

9

C1-

7

C512

1u

6

C2-

1

D1

2

D2

3

D3

12

NC

C521C520 47p47p

C522 47p

MLED1 MLED2 MLED3

LGE Internal Use Only

4. TROUBLE SHOOTING

- 81 -

WAVEFORM

Graph 4-7-1. LCD Backlight Control Signal Waveform

Graph 4-7-2. LCD Data Waveform

- 82 -

4. TROUBLE SHOOTING

LGE Internal Use Only

Only for training and service purposes

CHECKING FLOW

START

Check the Waveform of

EMI filter

S

YE

Check the Waveform of

Data pins on CN500

YES

Check the connection of

FPCB and CN500

YE

S

Check the Waveform of

Data pins on FPCBís CN101

S

YE

Check the Waveform of

Data pins on Key PCBís CN101

YE

S

Check

the Voltage Level of

FB501 (TP1) is about Batt.

voltage ?

(LCD_BACKLIGHT_CTRT

Signal is high

Level)

NO

Resoldering or replace EMI filter.

(FL501~FL504)

Replace Main board.

Reassemble FPCB to CN500

Replace FPCB.

Replace Key PCB or

check the soldering condition

of Key PCBís CN100 and CN101

Resoldering or Replace U501

4. TROUBLE SHOOTING

.

Is the connection of LCD

And Key PCBís CN101 ok ?

S

YE

S

YE

Does LCD work

properly ?

YES

LCD working well !

NO

Reassemble LCD to LCD conn.

Replace LCD module

- 83 -

4. TROUBLE SHOOTING

LGE Internal Use Only

4.8 Camera Trouble

TEST POINT

Figure 4-8

CN500

FL505

FB500

R500

U500

2.8V

TP1

1.8V

FL506

CN100

CN102

FL508

FL507

LGE Internal Use Only

Only for training and service purposes

4. TROUBLE SHOOTING

- 84 -

CIRCUIT

TP1

2V8_AVDD

LCD_ID_L

MLED3 MLED1 MLED2

MLED

SPK_RCV_N

SPK_RCV_P

KEY_COL4 KEY_COL3 KEY_ROW3 KEY_ROW2 KEY_ROW1 KEY_ROW0

KEY_BACKLIGHT

CAM_I2C_CLK

CAM_I2C_DATA

CAM_VSYNC

CAM_HSYNC

CAM_MCLK CAM_PWDN

nCAM_RESET

CAM_PCLK

2V8_IOVDD

R503

R504

FL505

4.7K

4.7K ICVE10184E150R500FR

9

8

7

6

R506

Eliminated C513, C514, C523, C524 by Lee_071105

C507

47p

1

INOUT_A1

INOUT_B1

2

INOUT_A2

INOUT_B2

3

INOUT_A3

INOUT_B3

4

INOUT_A4

INOUT_B4

G15G2

10

SFEY0011601

20K

5G210

G1

INOUT_B4

INOUT_A4

4

INOUT_B3

INOUT_A3

3

INOUT_B2

INOUT_A2

2

INOUT_B1

INOUT_A1

1

FL507

ICVE10184E150R500FR

6

7

8

9

FL500

INOUT_A1

INOUT_A2

INOUT_A3

INOUT_A4

G15G2

10

ICVE10184E150R101FR

1

9

INOUT_A1

INOUT_B1

8

INOUT_A2

INOUT_B2

7

INOUT_A3

INOUT_B3

6

INOUT_A4

INOUT_B4

G15G2

10

SFEY0010501

FL502 ICVE10184E150R101FR

9

INOUT_A1

INOUT_B1

8

INOUT_A2

INOUT_B2

7

INOUT_B3

INOUT_A3

6

INOUT_B4

INOUT_A4

G110G2

5

1

2

3

4

FL504

ICVE10184E150R101FR

9

INOUT_A1

INOUT_B1

8

INOUT_A2

INOUT_B2

7

INOUT_A3

INOUT_B3

6

INOUT_B4

INOUT_A4

G110G2

100ohmR501

5

100ohmR502

C509

C508 15p

15p

ICVE10184E150R500FR

10

G15G2

INOUT_B4

INOUT_A4

4

INOUT_B3

INOUT_A3

3

INOUT_B2

INOUT_A2

2

INOUT_B1

INOUT_A1

1

LCD_DATA15

2

LCD_DATA14

3

LCD_DATA13

4

LCD_DATA12

LCD_DATA11 LCD_DATA10 LCD_DATA09 LCD_DATA08

1

LCD_DATA07

2

LCD_DATA06

3

LCD_DATA05

4

LCD_DATA04

LCD_DATA03 LCD_DATA02 LCD_DATA01 LCD_DATA00

1

nLCD_RD

2

nLCD_WE

3

LCD_RS

4

nLCD_MAIN_CS

LCD_VSYNC

nLCD_RESET

CAM_DATA7 CAM_DATA6 CAM_DATA5 CAM_DATA4

FL508

CAM_DATA3

6

CAM_DATA2

7

CAM_DATA1

8

CAM_DATA0

9

VBAT

2V8_IOVDD

1V8_DVDD

C516

C515

1u

2V93_VEXT

FL501 ICVE10184E150R101FR

C502

C500

1u

C517 1u

C503

C501

0.1u

47p

CN500

G3 G4

40 41 39

42

38

43 44

37

45

36

46

35

47

34

48

33

49

32

50

31

51

30 29

52

28

53

27

54

26

55

25

56

24

57

23

58 59

22

60

21

61

20

62

19

63

18

64

17

65

16

66

15 14

67

13

68

12

69

11

70

10

71

9

72 73

8

74

7

75

6

76

5

77

4

78

3

79

2

80

1

G1 G2 AXK7L80227G ENBY0026001

10

G15G2

INOUT_A4

INOUT_B4

4

INOUT_A3

INOUT_B3

3

INOUT_A2

INOUT_B2

2

INOUT_B1

INOUT_A1

1

FL506 ICVE10184E150R500FR

9

INOUT_A1

INOUT_B1

8

INOUT_A2

INOUT_B2

7

INOUT_A3

INOUT_B3

6

INOUT_A4

INOUT_B4

G110G2

5

6

7

8

9

ICVE10184E150R101FR

9

INOUT_B1

8

INOUT_B2

7

INOUT_B3

6

INOUT_B4

1

2

3

4

FL503

CAM_LDO_EN

(EB2_ADDR_00)

R500 330

VBAT

U500

18

VIN

2

EN1

3

EN2

C504

1u

NC1

RT9011-MGPQW

VOUT1 VOUT2

NC2

PGND

GND

9

EUSY0319001

7 6 54

1V8_DVDD

C505 C506

2.2u

2V8_IOVDD

FB500 BLM15AB601SN1 SFBH0008101

2.2u

2V8_AVDD

CAM_I2C_CLK

CAM_I2C_DATA

CAM_VSYNC CAM_HSYNC

CAM_MCLK

CAMERA CONNECTOR

(ENBY0020401,24PIN,0.9T,SOCKET,AXK7L24227G)

2V8_AVDD

1V8_DVDD

2V8_IOVDD

CN100

ENBY0020401 AXK7L24227G

G1G2

1

24

2

23 22

3

21

4

20

5

19

6

18

7

17

8

16

9 10

15

11

14

1213

NA

RSB6.8CST2R

ZD101

RSB6.8CST2R

ZD100

Add for ESD 071024

=>Change to NA 071218

C100 470n

C101 1u

G3G4

RSB6.8CST2R

NA

ZD102

ZD103

Add for ESD 071123

=>Change to NA 071218

CAM_DATA7 CAM_DATA6 CAM_DATA5 CAM_DATA4 CAM_DATA3 CAM_DATA2 CAM_DATA1 CAM_DATA0 CAM_PCLK nCAM_RESET CAM_PWDN

RSB6.8CST2R

LGE Internal Use Only

4. TROUBLE SHOOTING

- 85 -

WAVEFORM

Graph 4-8-1 I2C Data Waveform Graph 4-8-2 MCLK Waveform

Graph 4-8-3 CAM_VSYNC vs.

CAM_HSYNC Waveform

Graph 4-8-4 CAM_HSYNC vs.

CAM_PCLK Waveform

CAM_RESET

I2C_DATA

CAM_MCLK

13MHz

CAM_VSYNC

CAM_HSYNC

CAM_PCLK

20.8MHz

LGE Internal Use Only

Only for training and service purposes

4. TROUBLE SHOOTING

- 86 -

CHECKING FLOW

START

Check the Waveform of

EMI filter

S

YE

Check the Waveform of

Data pins on CN500

YES

Check the

voltages at pin 7, 8(TP1)

of U500 when CAM_LDO_EN

is high

YE

S

Check the connection of

FPCB and CN500

YE

S

Check the Waveform of

all pins on FPCBís CN100

YE

S

NO

Resoldering or replace EMI filter.

(FL505~FL508)

Replace Main board.

Replace U500 and resolder FB500

Reassemble FPCB to CN500

Replace FPCB.

Check the connection of

FPCB and Camera

Does Camera work

Camera working well !

YE

S

properly ?

YES

NO

Reassemble Camera to FPCB

Replace Camera

LGE Internal Use Only

4. TROUBLE SHOOTING

- 87 -

4.9 Speaker/Receiver (1810 one way dual speaker) Trouble

TEST POINT

VBAT

1V8_DVDD

2V93_VEXT

2V8_AVDD

2V8_IOVDD

76

77

78

79

8

80

9

G1G2

63

64

65

66

67

68

69

7

70

71

72

73

74

75

5 6

4

18

2 3

ENBY0025901

AXK8L80125BG

CN102

1

10 11 12 13 14 15 16 17

MLED2 MLED1

MLED

MLED3

SPK_RCV_N SPK_RCV_P

LCD_ID1

CIRCUIT

Figure 4-9

TP1

SPK Pad

SPK_RCV_P

SPK_RCV_N

CN102

SPEAKER/RECEIVER

Change to 071218

by RF eng. Lee

C102 39p

C103

VA102 DNI

C104

39p39p

ERHZ0000401

MCR01MZSJ000

VA103

DNI

L100 L101

0L100

0L101

SPK_P

SPK_N

FB305

CN500

SPK_O_P

RCV_P

VBAT

C329

1u

FB305 BLM15AB601SN1 SFBH0008101

U306

1

VCC

2

NO1

3

COM1

4

IN1

5

NC1

EUSY0300101

NLAS5223BMNR2G

NO2

COM2

NC2

GND

IN2

U306

10

9

8

7

6

RCV_N

SPK_RCV_N

SPK_RCV_SELSPK_RCV_P

SPK_O_N

R316

100K

LCD_ID_L

SPK_RCV_N

SPK_RCV_P

VBAT

1V8_DVDD

2V93_VEXT

C502

C500

C501

C503

0.1u

1u

47p

CN500

G3 G4

40 41 39

42

38

43 44

37

45

36

46

35

47

34

48

33

49

32

50

31

51

30 29

52

28

53

27

54

26

55

25

56

24

57

23

58 59

22

2V8_IOVDD

2V8_AVDD

MLED3 MLED1 MLED2

MLED

- 88 -

4. TROUBLE SHOOTING

LGE Internal Use Only

Only for training and service purposes

R313

R314

U100

U305

TEST POINT WAVEFORM

CIRCUIT

RCV or SPK_P

RCV or SPK_N

Figure 4-9

TP2

Receiver path

Speaker path

Speaker

AMP

AOUT1N AOUT1P

AOUT2N_1 AOUT2N_2 AOUT2P_1 AOUT2P_2

AOUT3R

AOUT3L

SPEAKER

SPK_N

SPK_P

F11 E11

L8 M8 L9 M9

G10 F10

C2

TDO

C1

TMS

B1

TDI

D1

TCK

C323 0.01u R313 47K

LOUD_SPK_EN

0.01uC324

(GAIN x6)

47KR314

R315

100K

D1

C1

A1

C153 39p

U305

IN-

IN+

_SD

GND1

A2

A3

C154 C156

C155

39p

EUSY0160001

TPA2005D1ZQYR

GND2

GND3

GND4C3GND5D2GND6

B3

C2

39p

VDD1 VDD2

VO-

VO+

D3

NC

GND7

39p

B4 C4 B1

A4

D4

VBAT

C325 C326 10u

C157 C158

DNIDNI

FB306

SFBH0007101

FB307

BLM15AG121PN1

DNI

RCV_N RCV_P SPK_N

SPK_P

HP_ROUT HP_LOUT

1000p

C328

1000p

C327

SPK_O_N

SPK_O_P

- 89 -

4. TROUBLE SHOOTING

LGE Internal Use Only

CHECKING FLOW

START

Check the state of contact of spea

Yes

Check the Audio signal

L100, L101 ,R313, R314

Yes

Check the Audio signal

CN102, CN500

Yes

Check the Power Voltage

U305,U306 = VBAT

(TP1,2)

Yes

ker

No

Replace/Change speaker

Resolder L100, L101, R313,

Resolder CN102, CN500

Change the U305, U306

R314

Or

Change the U100

Or

Change the U100

Check VBAT or

Speaker

Working well !

!

LGE Internal Use Only

Only for training and service purposes

4. TROUBLE SHOOTING

- 90 -

4.10 Earphone Trouble

TEST POINT

CIRCUIT

Figure 4-10

TP2 TP1

HP_MIC_N

HP_MIC_P

CN300

2V5_VMIC

R300

1.5K

C300 39p

MULTI_PORT_TX

MULTI_PORT_RX

JACK_DETECT

C302

39p

C303 39p

EXT_PWRON

nDSR_DET

UART_TX UART_RX

C301

10u

HP_EN

2V93_VEXT

R306

100K

TP1

R305 ,R308

R302

2.2K

2V93_VEXT

ECTH0005202

C306 100u

C307

R303

1u

100K

R307

100K

EXT_PWRON

nDSR_DET

UART_TX R309 47

C305 ,C306

R300 R302

U302 NLAS5223BMNR2G

1

NO210VCC

2

9

NO1

COM2

8

3

IN2

COM1

7

4

NC2

IN1

5

6

NC1

GND

EUSY0300101

100u

C305

ECTH0005202

R305 4.7 R308 4.7

R310 47UART_RX

C144

U100

0R301

HP_LOUT

HP_ENHP_ROUT

diode

diodeVA301

39pC314

DNI_DIODE_1006

VA300

Change to NA for Ear-rcv TDMA

(2007.12.18)

VUSBIN_IO

39pC315

1u

C316

(1608, 25V, X5R)

VA302

VBAT

33uC311

RSB6.8CST2R

ECTH0005501

HOOK_DET

SFBH0008105

FB300

FB301 FB302

FB303

47p

C317

FB301 FB302

VCHARGE_IO

1800

BLM15BD182SN1D

VA303

82pC318

ICVN0505X150FR

1u

ECZH0003503

C312

(1608, 25V, X5R)

FB300

CN300

21 19

1 2 3

L301

4

270nH

5 6 7 8

9 10 11 12 13 14 15 16 17 18

20 22

GU041-18P-E1000 ENRY0006801

TP2

C308 10p

FM_ANT

L300

1nH

LGE Internal Use Only

4. TROUBLE SHOOTING

- 91 -

CHECKING FLOW

START

Resolder CN300

Check the

pin(#8) in CN300(TP1)

is LOW?

YE

S

Is FB303

(JACK DETECT : TP2)

LOW?

YES

Set the audio part of the test

equipment to PRBS or

Continuous wave m

Can you hear the sound from the earphone?

YE

S

Set the audio part of the test

Equipment to echo m

Can you hear your

voice from

the earphone?

ode

NO

Change the earphone

and try again

NO

Change the earphone

and try again

Resolder pin8 in CN300

Resolder FB303

Can you hear the sound from the earphone?

YE

S

Can you hear your

voice from

the ea

rphone?

NO

Resolder C305, C306,

R305 & R308

Resolder C144,FB300, R300 & R302

, FB301&FB302

Or Change the U100

Earphone will work properly

YES

4.11 Microphone Trouble

LGE Internal Use Only

Only for training and service purposes

4. TROUBLE SHOOTING

- 92 -

TEST POINT

Figure 4-11

CIRCUIT

TP1

MIC

TP1

R323

R325

2V5_VMIC

MIC300

MIC_P

MIC_N

C339 39p

R323

100ohm

R325

100ohm

R318

R319

1K

2.2K

C332 39p

R326

C330 10u ECTH0005601

MIC300

2 1

OB4-15L42-C33L

VA305

VA304

EVLC14S02050 SEVY0001001

LGE Internal Use Only

4. TROUBLE SHOOTING

- 93 -

CHECKING FLOW

SETTING : After initialize Agilent 8960, Test GSM900, PCS mode

START

Check microphone sound hole

Make a phone call,

then check R318 mic bias signal

comes from U100?

(TP1)

YES

Check the

Signal Level at each

Side of MIC300.

Is it a few tens

mV AC?

YE

S

Check the soldering of

R323, R325

YES

Microphone will work

properly.

NO

1. Check mic Bias signal line

2. Change the U100

Change the microphone

NO

Resolder component

LGE Internal Use Only

Only for training and service purposes

4. TROUBLE SHOOTING

- 94 -

4.12 SIM Card Interface Trouble

TEST POINT

CIRCUIT

Figure 4-12

PIN 6 PIN 4

J300

SIM CONNECTOR

2V85_VSIM

R317

15K

SIM_DATA

C333

DNI

PIN 1 PIN 3

J300

5000-6P-1.8SL

4

C5

5

C6

6

C7

10

GND4

9

ENSY0018701

GND1 GND2GND3

C1 C2 C3

1 2 3 7 8

2V85_VSIM

220n

DNI

C331

DNI

(GPIO_100)

nSIM_RST SIM_CLK

1000p

C335

20071029

C336

C337 22p

C338

C334

C331

Add for China ESD

LGE Internal Use Only

4. TROUBLE SHOOTING

- 95 -

CHECKING FLOW

START

Does the SIM card

support 3V or 1.8V

YES

Is Voltage at the pin1

of J300 2.85V or 1.8V

YE

S

Change the SIM Card

And try again.

Does it work

Properly?

S

YE

?

NO

This phone supports 3V or 1.8V SIM card

NO

?

NO

Change the SIM Card.

Voltage output of VSIM LDO is

2.85V or 1.8V?

YES

Resolder J300

Redownload SW.

Does it work

YES

Properly

?

NO

.

Change the U100

Change the main board

SIM card is properly working

SIM card is properly working.

LGE Internal Use Only

Only for training and service purposes

4. TROUBLE SHOOTING

- 96 -

4.13 Main key backlight Trouble

TEST POINT

Figure 4-13

Test point

Main

R402

KEY BACKLIGHT

LD400

VBAT

LD400

LEBBS47AAZ

EDLH0013406

LD401

LEBBS47AAZ

R402

R403

47

R403

LD401

KEY_BACKLIGHT3

VA400

VA401

Change to N/A

2007.10.30

DNI_VARISTER_1005

LGE Internal Use Only

4. TROUBLE SHOOTING

- 97 -

CHECKING FLOW

START

Power save mode?

YES

Is the Duty cycle of LED

(40%

YES

Are all LEDs

Working?

YES

)?

NO

Check U100

Check the soldering

each R and LED

NO

Replace or resolder

component

Backlight will work properly.

If on, R402,R403=0~500mV?

S

YE

NO

- 98 -

4. TROUBLE SHOOTING

LGE Internal Use Only

Only for training and service purposes

4.14 Slide key backlight Trouble

TEST POINT

Figure 4-14

TP1

TP2

TP4

TP3

TP5

- 99 -

4. TROUBLE SHOOTING

LGE Internal Use Only

(ENBY0025901, 80PIN,0.9T, HEADER, AXK8L80125BG)

MAIN BORAD CONNECTOR

VBAT

1V8_DVDD

2V93_VEXT

2V8_AVDD

TP101

2V8_IOVDD

TP100

76

77

78

79

8

80

9

G1G2

G3G4

60

61

62

63

64

65

66

67

68

69

7

70

71

72

73

74

75

47

48

49

5

50

51

52

53

54

55

56

57

58

59

6

31 32 33 34 35 36 37 38 39

4

4041

42

43

44

45

46

18 19

2

20 21 22 23 24 25 26 27 28 29

3

30

ENBY0025901

AXK8L80125BG

CN102

1

10 11 12 13 14 15 16 17

LCD_DATA03

LCD_DATA04

LCD_DATA05

LCD_DATA06

LCD_DATA07

CAM_DATA3

CAM_DATA4

CAM_DATA5

LCD_DATA14

CAM_DATA6

CAM_DATA7

nLCD_RESET

LCD_VSYNC

nLCD_MAIN_CS

LCD_RS

nLCD_WE

LCD_DATA15

nLCD_RD

LCD_DATA00

LCD_DATA01

LCD_DATA02

CAM_HSYNC

CAM_MCLK

KEY_COL3

LCD_DATA08

LCD_DATA09

LCD_DATA10

LCD_DATA11

LCD_DATA12

LCD_DATA13

CAM_PWDN

nCAM_RESET

CAM_PCLK

CAM_DATA0

CAM_DATA1

CAM_DATA2

MLED2 MLED1

MLED

MLED3

KEY_BACKLIGHT

SPK_RCV_N SPK_RCV_P

LCD_ID1

KEY_COL4

KEY_ROW0

KEY_ROW1

KEY_ROW2

KEY_ROW3

CAM_I2C_DATA

CAM_I2C_CLK

CAM_VSYNC

Eliminated capacitors 20070917

(ENBY0036701,60PIN,1.0T,HEADER GB042-60P-H10-E3000)

KEY PCB CONNECTOR

2V93_VEXT

56

57

58

59

6

60

7 8 9

42

43

44

45

46

47

48

49

5

50

51

52

53

54

55

27 28 29

3

30 31

32

33

34

35

36

37

38

39

4

40

41

12 13 14 15 16 17 18 19

2

20 21 22 23 24 25 26

VBAT

ENBY0036701 GB042-60P-H10-E3000

CN101

1

10 11

MLED2 MLED3

MLED

MLED1

KEY_COL3

KEY_COL4

KEY_ROW0

KEY_ROW3 KEY_ROW2 KEY_ROW1

LCD_ID1

KEY_BACKLIGHT

nLCD_RESET

LCD_DATA00

LCD_DATA01

LCD_DATA02

LCD_DATA03

LCD_DATA04

LCD_DATA05

LCD_DATA06

LCD_DATA07

LCD_DATA08

LCD_DATA09

LCD_DATA10

LCD_DATA11

LCD_DATA12

LCD_DATA13

LCD_DATA14

LCD_DATA15

nLCD_RD

LCD_RS

nLCD_WE

nLCD_MAIN_CS

LCD_VSYNC

CIRCUIT

LED (Slide PCB) Connector (Slide PCB)

Main connector (FPCB) Key connector (FPCB)

TP1

TP2

TP3

TP4

VA100

SEVY0004101

SLIDE KEY BACKLIGHT

VBAT

47

VA101

R100 47

ICVN0505X150FR

LD100

KEY_BACKLIGHT

R101 47

LD101

R102

LD102

R103

LD103

LEBB-S14E

EDLH0004501

47

R104

LD104

47

R105

LD105

VA102

VA103

SEVY0004101

ICVN0505X150FR

2V93_VEXT

MLED MLED1 MLED2 MLED3

KEY_COL4

KEY_COL3 KEY_ROW3 KEY_ROW2 KEY_ROW1 KEY_ROW0

nLCD_RESET

KEY_BACKLIGHT

LCD_ID1

C101

VBAT

47p

KEY PCB CONNECTOR

C100

1u

CN100

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

ENBY0036801 GB042-60S-H10-E3000

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

LCD_DATA15 LCD_DATA14 LCD_DATA13 LCD_DATA12

LCD_DATA11 LCD_DATA10 LCD_DATA09 LCD_DATA08

LCD_DATA07 LCD_DATA06 LCD_DATA05 LCD_DATA04

LCD_DATA03 LCD_DATA02 LCD_DATA01 LCD_DATA00

LCD_VSYNC nLCD_MAIN_CS nLCD_WE LCD_RS nLCD_RD

- 100 -

4. TROUBLE SHOOTING

LGE Internal Use Only

Only for training and service purposes

CHECK FLOW

Connector (Main PCB) ABB (Main PCB)

TP5

2V8_AVDD

LCD_ID_L

MLED3 MLED1 MLED2

MLED

SPK_RCV_N

SPK_RCV_P

KEY_COL4 KEY_COL3 KEY_ROW3 KEY_ROW2 KEY_ROW1 KEY_ROW0

KEY_BACKLIGHT

C507

47p

2V8_IOVDD

1V8_DVDD

VBAT

2V93_VEXT

C502

C500

C501

1u

C503

0.1u

47p

CN500

G3 G4

40 41 39

42

38

43 44

37

45

36

46

35

47

34

48

33

49

32

50

31

51

30

52

29

53

28

54

27

55

26

56

25

57

24

58

23

59

22

60

21

61

20

62

19

63

18

64

17

65

16

66

15

67

14

68

13

VCHARGE

VUSBIN

VBAT

BATT_TEMP

R106

(1%)

120K

C152

KEY_BACKLIGHT

0.1u

KEY_BACKLIGHT3

KEY_ROW4

POWERKEY

(USE GHOST FUNC. OF ROW4 ON POWER-UP)

C151 0.1u

Add R(20071121)

R113 DNI

A5

GATEDRIVE

A6

ISENSE

(1%)

68KR105

B12

REFCHG

A1

VCHG

A4

VUSBCHG

B6

VBATSENSE

B5

BATTYPE

K8

CHGLIGHT

H11

LIGHT1

G11

LIGHT2

H12

LIGHT3

L10

KEYOUT

M10

KEYON

START

Power save mode?

YES

Is the level Period of LED

(Duty=40%)?

YES

Are all LEDs

Working?

YES

NO

Check Key PCB connector

FPCB, Main PCB connector

ABB(U100)

Check the soldering

each R and LED

NO

Replace or resolder

component

If on, TP1 :3~3.5V

The other side of LEDís

:0~500mV?

S

YE

NO

Backlight will work properly.

- 101 -

4. TROUBLE SHOOTING

LGE Internal Use Only

4.15 RTC Trouble

TEST POINT WAVEFORM

TP1

X100

TP2

TP1

TP2

CIRCUIT

Figure 4-15

TP1

TP2

X100

32.768KHz

12

3

EXXY0016001

SSP-T7-F_7PF_20PPM

4

C137

10p

R103

10M

C143

10p

CAM_DATA0 CAM_DATA1 CAM_DATA2 CAM_DATA3 CAM_DATA4 CAM_DATA5 CAM_DATA6 CAM_DATA7

BT_UART_TX

BT_UART_RX

BT_UART_CTS BT_UART_RTS

HP_EN

N21 M21

V22

V21 W22 W21

V19

Y22

A17

A16

L1 M4 M1 M2

N6 N1 P2

PPI_DATA_1 PPI_DATA_2 PPI_DATA_3 PPI_DATA_4 PPI_DATA_5 PPI_DATA_6 PPI_DATA_7 PPI_DATA_8 PPI_DATA_9

OSCIN OSCOUT

GPIO_000 GPIO_001 GPIO_002 GPIO_003 GPIO_004 GPIO_005 GPIO_009

LG KF240 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual