Lenovo YOGA 370 Schematic

1

2

3

4

5

Model Name : CILL1 (Lenovo)

A A

CILL2 (NEC)

File Name : LA-C422P

B B

Compal Confidential

Lin-2 M/B Schematics Document

Intel Kabylake U Processor with DDR4

C C

Rev. 1.0

D D

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D
DEPARTMENT EXCEPTAS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE I NFORMATION IT CONTAINS

DEPARTMENT EXCEPTAS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE I NFORMATION IT CONTAINS

DEPARTMENT EXCEPTAS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE I NFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/03/21 2017/03/01

2016/03/21 2017/03/01

2016/03/21 2017/03/01

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

4

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Cover_Page

Cover_Page

Cover_Page

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

LA-C422P

LA-C422P

LA-C422P

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

5

1 58Tuesday, November 15, 2016

1 58Tuesday, November 15, 2016

1 58Tuesday, November 15, 2016

1.0

1.0

1.0

A

www.schematic-x.blogspot.com

B

C

D

E

A-ch DDR4-SO-DIMM X1

P.32

eDP

DDI 1

DDI 2

PCIE3

PCIE9

PCIE2

SATA0

PCIE5

PCIE6

SATA1

HD Audio

SPI

I2C

KabyLake U

+

KabyLake PCH-LP

ULT (15W)

BGA

P.5~P .16

LPC BUS

EC

nuvoton NPCE388N

P.45

Memory Bus

DDR4 2133MHz (2.5V)

USB 3.0

USB 2.0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 2 Port 2

Port 6

Port 7

Port 8

Port 10

B-ch DDR4-SO-DIMM X1

USB Board

USB 3.0 CONN

USB 3.0 CONN

USB 3.0 CONN

USB 3.0 CONN

USB 3.0 CONN (AOU)

Docking (Lenovo)

FPR

NFC (FeliCa)

CAM Module

PCIE4

M.2 WLAN / BT

USB 2.0 HUB

Genesys_GL850G

Function Board

RS232 CONN(NEC)

1 1

eDP CONN

P.19

Function Board

mDP CONN (Lenovo)

HDMI CONN (NEC)

VGA CONN

Docking

(Lenovo)

P.47

Function Board

RJ45 CONN

2 2

P.42

DP to VGA

NXP_PTN3355

Docking

LAN Switch

Pericom_PI3L720ZHEX

(Lenovo)

P.21P.22

P.47

P.23

(NEC)

P.27

DP

DP

DeMux

Parade_PS8338 B

LAN

Intel_Jacksonville

Card Reader

O2_BH611FJ1LN

PCI Bridge

O2_OZ600

HDD CONN

2 Channel Speaker

P.39

SATA Express

ODD CONN

CAM Module

DMIC *2

P.19

Audio Codec

ALC3245

Audio Board

3 3

Docking

Combo Jack

P.43

(Lenovo)

P.47

I2S

SPI ROM

16M

TPM

Nuvoton_NP CT650LA0YX

P.42

P.20

P.23

.24

P

(NEC)PCMCIA CONN

P.26

DMUX

P.32

P.37

P.38

P.41

PCIE/SATA

P.7

(NEC)

P.42

P.33

P.34

P.35

P.47

(Lenovo)

(NEC)

P.36

P.19

P.28

(Lenovo)

P.36

P.42

P.17

P.18

Port 1

Port 2

Port 3

Port 4

Port 5

PCIE11
PCIE12 /

USB 2.0

SATA2

M.2 WWAN/Optane/SSD

PCIE10

ExpressCard

Smart Card

(Lenovo)

P.25

(Lenovo)

P.36

P.29

Accelerometer

Kionix_KX023-1025

4 4

A

P.37

B

Click Pad

Int.KBD

P.40

P.40

C

Thermal Sensor

Fintek F75303M

Lid Board

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUTPRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUTPRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUTPRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

P.40

P.19

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

2016/03/21 2017/03/01

2016/03/21 2017/03/01

2016/03/21 2017/03/01

D

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Block_Diagram

Block_Diagram

Block_Diagram

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

LA-C422P

LA-C422P

LA-C422P

Date: Sheet of

Date: Sheet of

Date: Sheet of

E

2 58Tuesday, November 15, 2016

2 58Tuesday, November 15, 2016

2 58Tuesday, November 15, 2016

1.0

1.0

1.0

5

[CILL1 PWR Sequence_KBL-U_DDR4_Non-Deep Sx]

4

3

2

1

D D

C C

[AC Mode]

AC_IN

B+

+3VLP/+VL

EN_3V

+3VALW

+1.0V_PRIM

PCH_PWR_EN

+1.8V_PRIM

ON/OFFBTN#

PBTN_ OUT#

EC_RSMRST#

SUSPWRDNACK

AC_PRES ENT

moniter AC_I N (51_ON)

Moniter ON/OFFBTN# rising e dge

20ms

PM_SLP_ S5#

PM_SLP_ S4#

PM_SLP_ S3#

SYSON

+2.5V_VDD Q

+1.2V_VDD Q

DDR_P G_CTRL

+0.6VS_VT T

SUSP# After PM_SLP_S3# moniter SYSON rising edge.

+5VS

+3VS

Montier PBTN_OUT# falling edge.

T=20m s

[DC Mode]

BATT+

AC_PRES ENT

B+

+3VLP/+VL

ON/OFFBTN#

EN_5V/EN_3V

+5VALW/+3VALW

+1.0V_PRIM

PCH_PWR_EN

+1.8V_PRIM

EC_RSMRST#

SUSPWRDNACK

PBTN_ OUT#

T=10m s

Moniter ON/OFFBTN#

T=10m s

oniter ON/OFFBTN# and EN_3/5V both of ri sgin edge

M

T=110m s

20ms

immediately, After PM_SLP_S4# falling e dge

immediately, After PM_SLP_S3# falling e dge

Moniter ON/OFFBTN# rising e dge

+1.5VS

B B

VCCST_PG_EC (ALL_SYS_PWRGD,non CPU code VR)

VR_ON

+VCC_CORE

VGATE

H_CPUPWRGD_R

SYS_PWROK

PLT_RST#

T=20m s

After SUSP# risign edge

immediately, VCCST_PG_PWR & VCCST_PG_EC risign edge

Vboot

T=10m s

After VCCST_PG_EC rising edgePCH_PWROK

T=99m s

After VCCST _PG_EC assertion

After CPUPWRGD/PCH_PWRGD/SYS_PWROK assertion

immediately, After SUSP# falling edge

immediately, After SUSP# falling edge

immediately, After SUSP# falling edge

A A

Security C lassification

Security C lassification

Security C lassification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRETINFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENTDIVISION OF R&D

AND TRADE SECRETINFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENTDIVISION OF R&D

AND TRADE SECRETINFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENTDIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZEDBY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZEDBY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZEDBY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUTPRIOR WRITTEN CONSENTOF COMPAL ELECTRONICS,INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUTPRIOR WRITTEN CONSENTOF COMPAL ELECTRONICS,INC.

5

4

3

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUTPRIOR WRITTEN CONSENTOF COMPAL ELECTRONICS,INC.

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

2016/03/21 2017/03/01

2016/03/21 2017/03/01

2016/03/21 2017/03/01

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Power Sequence

Power Sequence

Power Sequence

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

D

D

D

LA-C422P

LA-C422P

LA-C422P

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

3 58Tuesday, Novem ber 15, 2 016

3 58Tuesday, Novem ber 15, 2 016

3 58Tuesday, Novem ber 15, 2 016

1.0

1.0

1.0

1

H8

H_4P4

1

Screw

H6

H30

Screw

H_2P5N

H26

H_3P0X3P5N

H_4P4

1

Screw

H_2P3

1

H31

1

H12

Screw

1

Screw

H18

1

Screw

H27

H_3P0X2P5N

1

Screw

H15

H_2P7

1

Screw

Screw

1

H17

H_3P4

1

Screw

H13

H_3P4X3P6

1

Screw

H_3P0

H_3P0

H24

H_3P0

1

Screw

A A

B B

H_2P2N

2

H5

H_2P5

1

Screw

H14

H_3P4X3P6

1

Screw

H16

H_3P6

1

Screw

H32

1

Screw

H22

H_3P0

1

Screw

H9

Screw

H19

H_2P7

1

Screw

H28

H_3P0

1

Screw

3

H29

1

Screw

H_3P2

1

H10

H_3P2

1

Screw

H2

Screw

H3

H_3P0

1

H_3P0N

1

Screw

H_3P0

4

H33

H34

H_1P5N

H_1P5N

1

1

Screw

Screw

H11

H_3P3

1

Screw

H23

H_4P4

1

Screw

H25

H_4P4

1

H1

Screw

H_3P0

1

Screw

5

FD1

1

FIDUCIAL_C40M80

FD3

1

FIDUCIAL_C40M80

FD2

@

@

1

FIDUCIAL_C40M80

FD4

@

@

1

FIDUCIAL_C40M80

Shielding Clip

Larger

CLIP1

CLIP2

HOLEA

HOLEA

@

@

1

1

Smaller

CLIP7

CLIP6

HOLEA

HOLEA

@

@

1

1

Voltage Rails

S

3 S4/S5Power Plane Descript i on

S0ix

S0

ON

PCB

ZZZ

PCB

DAZ1SS00100

C C

X4E

ZZZ1

EMC_LNV

Lenovo@

ZZZ2

EMC_NEC

NECPremium@

ZZZ3

EMC_NEC

NECBase@

D D

CPU

U1

CPU13@
SA0000ADM30

FJ8067702739934 SR34A H0 2.2G

U1

CPU14@
SA0000A38G0

FJ8067702739738 SR2ZW H0 2.4G

U1

CPU15@
SA0000A37G0

FJ8067702739739 SR2ZU H0 2.5G

U1

CPU16@
SA0000ADO30

FJ8067702739633 SR340 H0 2.6G

U1

CPU17@
SA0000A34E0

FJ8067702739740 SR2ZV H0 2.7G

U1

CPU18@
SA0000ADP30

FJ8067702739628 SR33Z H0 2.8G

1

U1

CPU19@
SA0000ADL40

FJ8067702739933 SR349 H0 1.8G

+3VL_RTC RTC power
+3VLP +19VB to +3VLP power rail
+5VALW
+3VALW System +3VALW always on power rail
+3VALW_DSW +3VALW power for PCH DSW rails
+3V_PRIM +3VALW power for PCH suspend rails
+1.8V_PRIM

1.0V_PRIM

+
+1.0V_MPHYPLL +1.0V power for PCH MODPHY rails
+2.5V DDR4 +2.5V power rail

+0.6VS_VTT
+VCC_CO RE
+1.0VS_VCCIO +1.0VS IO power rail
+VCC_GT Sliced graphics power rail
+VCC_SA System Agent power rail

+5VS System +5VS power rail
+3VS

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF

System +5VALW power rail

System +1.8V power rail
System +1.0V power rail

DDR4 +1.2V power rail+1.2V_VDDQ

DDR +0.6VS power rail for DDR terminator

Core voltage for CPU

System +3VS power rail

SIT BOM Structure Table

BTO Item

vPRO
non vPRO
FPR/Do cking
USB Hub/WWAN/

Express/Smart card

PCMCI A/NFC
TPM_In fineon
TPM_S T
APS_K ionix
APS_S T
Premi un-U
ESD requirement
ESD reserve
EMI requirement
EMI reserve
RF requirement
RF reserve
XDP

2

BOM Structure

M3@
NOM3 @
Lenov o@

LNVHU B@ LNV Premium-U

NEC@
TPMi @
TPMs @
APSk @
APSs @
Premi um@
ESD@
@ESD @
EMI@
@EMI @
RF@
@RF@
XDP@

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON
ON

ON

ON/OFF

ON/OFF

ON

ON

OFF

ON

OFF

ON

OFF

ON

OFF

ON
ON

ON

ON

ON

ON

Remar k

vPRO sku

non vPRO sku

LNV

NEC

LNV N EC

NECLNV

LNV

NEC

NA

Premiun-U Sku

NECLNV

NA

NECLNV

NA

NECLNV

NA

NECLNV

ON
ON
ON
ON
ON
ON
ON
ON

ON/OFF

ONONON
ON

OFF
OFF
OFF

FF

O

OFF
OFF

ON/OFF

3

ON
ON
ON*
ON*
ON*
ON*
ON*
ON*

OFF
OFF
OFF
OFF
OFF
O
OFFOFFOFF
OFF
OFF

FF

I/O mapping

Define.

USB3# 1

1

2

USB3# 2

USB3# 3

3

USB3# 4

4

USB3#5/P CIE#1

5

6

USB3#6/P CIE#2

PCIE#3/ Gbe

7

PCIE#4/ Gbe

8

PCIE#5/ Gbe

9

PCIE# 6

10

PCIE#7/S ATA#0

11

PCIE#8/S ATA#1

12

PCIE#9/ Gbe

13

PCIE#10/ Gbe

14

PCIE#11/ SATA#1

15

PCIE#12/ SATA#2

16

USB 2.0

LIN

USB3_Re ar

1

USB3_Doc king

2

USB3_Rig ht-1

USB3_Rig ht-2

3

USB3_Rig ht-3

4

USB3_Le ft

5

FPR

6

CAM

7

BT

8

X

9

USB 2.0 HUB

10

LIN-2

USB3#1_R ear

USB3#2_D ocking
USB3#2_R ight-1
USB3#3_R ight-2

USB3#4_R ight-3

USB3#5_L eft

PCIE2_PCMCIA Bridge

PCIE#3_ GBE

PCIE#4_W LAN

PCIE#5_ L0

PCIE#5_ L1

SATA#0_ HDD

SATA#1_ ODD

PCIE#5_Card Reader

PCIE#6_Express Card

PCIE#11 _L1

PCIE#11_ L0/SATA #2

USB 2.0 HUB (LNV)

1

(LNV)

2

(NEC)

3

4

(LNV)

(LNV)

EC SM Bus1 address

(LNV)

(NEC)

(NEC)

M.2
2

280 SSD

Optane /

242 SSD

2

Device

Smart Battery 0001 011X b

Charger 0001 011X b

EC SM Bus2 address

Device

Thermal Sensor Fintek F75303M

Thermal Sensor ON-semi ADM1032

CPU Intel KBL-U

APS Kionix KX023-1025

APS ST LIS3DHTR

(LNV)

Address

Address

1001_101xb

0100_110xb

0011_110xb

0011_100xb

PCH SM Bus address

Device

DDR DIMM1

LIN

WWAN

(LNV)

Express Card

(LNV)

Smart Card

(LNV)

X

Security Classification Compal Secret Data

Security Classification Compal Secret Data

Security Classification Compal Secret Data

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRI ETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRI ETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRI ETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPALELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPALELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPALELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED T O ANYT HIRD PARTY WITHOUT PRIO R WRITTEN CONSENT O F COMPAL ELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED T O ANYT HIRD PARTY WITHOUT PRIO R WRITTEN CONSENT O F COMPAL ELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED T O ANYT HIRD PARTY WITHOUT PRIO R WRITTEN CONSENT O F COMPAL ELECTRONICS, INC.

4

DDR DIMM2

Synaptics Inter Touch Click Pad

PCH SM Link0 address

Device

LAN Intel WGI219

Deciphered Date

Deciphered Date

2016/03/21 2017/03/01

2016/03/21 2017/03/01

2016/03/21 2017/03/01

Deciphered Date

Address

1001 000Xb

TBD TBD

Address

HEX

16H

12H

HEX

9AH

4CH

3Ch/3Dh

30h/31h

HEX

A0H/A1H

A3H/A4H1001 001Xb

HEX

C8H

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Notes_List

Notes_List

Notes_List

Size

Size

Size

Document N umber Rev

Document N umber Rev

Document N umber Rev

Custom

Custom

Custom

LA-C422P

LA-C422P

LA-C422P

Date: Sheet of

Date: Sheet of

Date: Sheet of

5

4 58Tuesday, November 15, 2016

4 58Tuesday, November 15, 2016

4 58Tuesday, November 15, 2016

1.0

1.0

1.0

5

4

3

2

1

+3VS

Function Board

D D

C C

RP1

DDIP1_CTRL_CLK

1 8

DDIP1_CTRL_DATA

2 7

DDIP2_CTRLCLK

3 6

DDIP2_CTRLDATA

4 5

2.2K_0804_8P4R_5%

DDPB_CTRLDATA: Port B Detected
DDPC_CTRLDATA:

1: Port B or C is detected

0: Port B or C is not detected

Port have internal PD

COMPENSATION PU FOR eDP

+1.0VS_VCCIO

R3

CAD note:
Trace width=20 mils,Spacing=25 mil,Max length=100mils

+1.0V_VCCST

1 2

R6 1K_0402_5%

R9 100K_0402_5%

R12

1 2

100K_0402_5%

Port C Detected

EDP_COMP

24.9_0402_1%

H_THERMTRIP#

DDIP1_mDP_HDMI_HPD

12

DDIP2_HPD

12

MUX

DDC for HDMI

H_PROCHOT#[45]

DDIP1_CTRL_CLK[42]
DDIP1_CTRL_DATA[42]

DDIP2_CTRLCLK[20]
DDIP2_CTRLDATA[20]

+1.0VS_VCCSTG

12

R4
1K_0402_5%

CPU_DP1_N0[42]
CPU_DP1_P0[42]
CPU_DP1_N1[42]
CPU_DP1_P1[42]
CPU_DP1_N2[42]
CPU_DP1_P2[42]
CPU_DP1_N3[42]
CPU_DP1_P3[42]

DDIP2_0N[20]
DDIP2_0P[20]
DDIP2_1N[20]
DDIP2_1P[20]
DDIP2_2N[20]
DDIP2_2P[20]
DDIP2_3N[20]
DDIP2_3P[20]

ODD_DA#_R[10,37]

T9 TP@

H_PECI[45]

12

R5 499_0402_1%

T10 TP@

T21 TP@
T29 TP@

T13 TP@

12

R7 49.9_0402_1%

12

R8 49.9_0402_1%

12

R10 49.9_0402_1%

12

R11 49.9_0402_1%

DDIP2_0N
DDIP2_0P
DDIP2_1N
DDIP2_1P
DDIP2_2N
DDIP2_2P
DDIP2_3N
DDIP2_3P

DDIP1_CTRL_CLK
DDIP1_CTRL_DATA

DDIP2_CTRLCLK
DDIP2_CTRLDATA

ODD_DA#_R

EDP_COMP

H_PECI
H_PROCHOT#_R
H_THERMTRIP#
SOC_OCC#

XDP_BPM#0
XDP_BPM#1

SOC_GPIOE3

CPU_POPIRCOMP
PCH_OPIRCOMP
EDRAM_OPIO_RCOMP
EOPIO_RCOMP

U1A

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

N7

GPP_E20/DDPC_CTRLCLK

N8

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22/DDPD_CTRLCLK

N12

GPP_E23/DDPD_CTRLDATA

E52

EDP_RCOMP

K

BL-U_BGA1356

U1D

D63

CATERR#

A54

PECI

C65

PROCHOT#

C63

THERMTRIP#

A65

SKTOCC#

C55

BPM#[0]

D55

BPM#[1]

B54

BPM#[2]

C56

BPM#[3]

A6

GPP_E3/CPU_GP0

A7

GPP_E7/CPU_GP1

BA5

GPP_B3/CPU_GP2

AY5

GPP_B4/CPU_GP3

AT16

PROC_POPIRCOMP

AU16

PCH_OPIRCOMP

H66

OPCE_RCOMP

H65

OPC_RCOMP

KBL-U_BGA1356

DDI

DISPLAY SIDEBANDS

CPU MISC

1 OF 20

4 OF 20

EDP

JTAG

PROC_TCK

PROC_TDI
PROC_TDO
PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS

PCH_TRST#

EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]

EDP_AUXN
EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP
DDI3_AUXN
DDI3_AUXP

GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3

GPP_E17/EDP_HPD

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

B61
D60
A61
C60
B59

B56
D59
A56
C59
C61
A59

JTAGX

C47
C46
D46
C45
A45
B45
A47
B47

E45
F45

B52

G50
F50
E48
F48
G46
F46

L9
L7

SOC_GPIOE9

L6

EC_SCI#

N9

EDP_HPD

L10

R12

EDP_BKCTL

R11
U13

XDP_TCK0
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#

PCH_TCK
PCH_TDI
PCH_TDO
PCH_TMS
PCH_TRST#

JTAGX

1 2

R2 0_0402_5%@

EDP_TXN0 [19]
EDP_TXP0 [19]
EDP_TXN1 [19]
EDP_TXP1 [19]

EDP_AUXN [19]

T5TP@

T8TP@

EDP_AUXP [19]

DDI1_AUXN [42]
DDI1_AUXP [42]

DDIP2_AUXN [20]
DDIP2_AUXP [20]

DDIP1_mDP_HDMI_HPD [42]
DDIP2_HPD [20]

EC_SCI# [10,45]
EDP_HPD [19]

ENBKL [45]

INVPWM [19]
PCH_ENVDD [19]

<eDP> 2 Lane for FHD LCD

mDP or HDMI

MUX

XDP CONN

APS CONN

B B

PM_SLP_S3#[9,25,45,46]

PM_SLP_S5#[9,45]
PM_SLP_S4#[9,12,45,46,52]
PM_SLP_A#[9,28,45,54]

SOC_RTCRST#[9]

PBTN_OUT#[9,45]

SYS_RESET#[9]

PM_SLP_S0#[9]

A A

+3V_PRIM+3VALW

JAPS1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

GND

20

GND

ACES_50506-01841-P01

ME@

+1.0V_VCCST

+1.0V_XDP

+1.0VS_VCCSTG

JTAGX
PCH_TCK

PCH_TMS
PCH_TDI

PCH_TRST#
PCH_TDO

@

1 2

XDP@

RPC1

1 8
2 7
3 6
4 5

0_0804_8P4R_5%

XDP@

RPC2

1 8
2 7
3 6
4 5

0_0804_8P4R_5%

XDP@

RP9

1 8
2 7
3 6
4 5

51_0804_8P4R_5%

XDP@

RP13

1 8
2 7
3 6
4 5

51_0804_8P4R_5%

R191K_0402_5%

XDP_ITP_PMODE

XDP_TCK0
XDP_TCK1
XDP_TMS
XDP_TDI

XDP_TRST#
XDP_TDO

PCH_TDI
PCH_TMS
PCH_TDO

XDP_TCK0
XDP_TRST#
PCH_TCK

+1.0V_XDP+1.0V_PRIM

1 2

R14 0_0603_5%@

XDP_TCK0

XDP_TCK1
XDP_TMS
XDP_TDI
XDP_TRST#
XDP_TDO

SYS_RESET#

XDP_ITP_PMODE[16]

EC_RSMRST#[9,45]

CFG3[16]

XDP_PRDY#[11]

XDP_PREQ#[11]

XDP_ITP_PMODE

EC_RSMRST#

CFG3

XDP_PRDY#
XDP_PREQ#

@

1

0.1U_0201_10V6K
C258

2

JXDP1

28

GND

27

GND

26

26

25

25

24

24

23

23

22

22

21

21

20

20

19

19

18

18

17

17

16

16

15

15

14

14

13

13

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

ACES_51522-02601-001

ME@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/03/21 2017/03/01

2016/03/21 2017/03/01

2016/03/21 2017/03/01

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

KBL ULT(1/12) DDI,MSIC,XDP

KBL ULT(1/12) DDI,MSIC,XDP

KBL ULT(1/12) DDI,MSIC,XDP

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

C

C

C

LA-C422P

LA-C422P

LA-C422P

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

5 58Tuesday, November 15, 2016

5 58Tuesday, November 15, 2016

5 58Tuesday, November 15, 2016

1.0

1.0

1.0

5

4

3

2

1

Interleaved

LIN-2

Memory

D D

DDR_A_D[0..15][17]

DDR_A_D[16..31][17]

C C

B B

DDR_A_D[32..47][17]

DDR_A_D[48..63][17]

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

U1B

AL71

DDR0_DQ[0]

AL68

DDR0_DQ[1]

AN68

DDR0_DQ[2]

AN69

DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]

AN70

DDR0_DQ[6]

AN71

DDR0_DQ[7]

AR70

DDR0_DQ[8]

AR68

DDR0_DQ[9]

AU71

DDR0_DQ[10]

AU68

DDR0_DQ[11]

AR71

DDR0_DQ[12]

AR69

DDR0_DQ[13]

AU70

DDR0_DQ[14]

AU69

DDR0_DQ[15]

BB65

DDR0_DQ[16]/DDR0_DQ[32]

AW65

DDR0_DQ[17]/DDR0_DQ[33]

AW63

DDR0_DQ[18]/DDR0_DQ[34]

AY63

DDR0_DQ[19]/DDR0_DQ[35]

BA65

DDR0_DQ[20]/DDR0_DQ[36]

AY65

DDR0_DQ[21]/DDR0_DQ[37]

BA63

DDR0_DQ[22]/DDR0_DQ[38]

BB63

DDR0_DQ[23]/DDR0_DQ[39]

BA61

DDR0_DQ[24]/DDR0_DQ[40]

AW61

DDR0_DQ[25]/DDR0_DQ[41]

BB59

DDR0_DQ[26]/DDR0_DQ[42]

AW59

DDR0_DQ[27]/DDR0_DQ[43]

BB61

DDR0_DQ[28]/DDR0_DQ[44]

AY61

DDR0_DQ[29]/DDR0_DQ[45]

BA59

DDR0_DQ[30]/DDR0_DQ[46]

AY59

DDR0_DQ[31]/DDR0_DQ[47]

AY39

DDR0_DQ[32]/DDR1_DQ[0]

AW39

DDR0_DQ[33]/DDR1_DQ[1]

AY37

DDR0_DQ[34]/DDR1_DQ[2]

AW37

DDR0_DQ[35]/DDR1_DQ[3]

BB39

DDR0_DQ[36]/DDR1_DQ[4]

BA39

DDR0_DQ[37]/DDR1_DQ[5]

BA37

DDR0_DQ[38]/DDR1_DQ[6]

BB37

DDR0_DQ[39]/DDR1_DQ[7]

AY35

DDR0_DQ[40]/DDR1_DQ[8]

AW35

DDR0_DQ[41]/DDR1_DQ[9]

AY33

DDR0_DQ[42]/DDR1_DQ[10]

AW33

DDR0_DQ[43]/DDR1_DQ[11]

BB35

DDR0_DQ[44]/DDR1_DQ[12]

BA35

DDR0_DQ[45]/DDR1_DQ[13]

BA33

DDR0_DQ[46]/DDR1_DQ[14]

BB33

DDR0_DQ[47]/DDR1_DQ[15]

AY31

DDR0_DQ[48]/DDR1_DQ[32]

AW31

DDR0_DQ[49]/DDR1_DQ[33]

AY29

DDR0_DQ[50]/DDR1_DQ[34]

AW29

DDR0_DQ[51]/DDR1_DQ[35]

BB31

DDR0_DQ[52]/DDR1_DQ[36]

BA31

DDR0_DQ[53]/DDR1_DQ[37]

BA29

DDR0_DQ[54]/DDR1_DQ[38]

BB29

DDR0_DQ[55]/DDR1_DQ[39]

AY27

DDR0_DQ[56]/DDR1_DQ[40]

AW27

DDR0_DQ[57]/DDR1_DQ[41]

AY25

DDR0_DQ[58]/DDR1_DQ[42]

AW25

DDR0_DQ[59]/DDR1_DQ[43]

BB27

DDR0_DQ[60]/DDR1_DQ[44]

BA27

DDR0_DQ[61]/DDR1_DQ[45]

BA25

DDR0_DQ[62]/DDR1_DQ[46]

BB25

DDR0_DQ[63]/DDR1_DQ[47]

K

BL-U_BGA1356

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]

DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

DDR0_DQSN[0]
DDR0_DQSP[0]
DDR0_DQSN[1]

DDR0_DQSP[1]
DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
DDR0_DQSP[7]/DDR1_DQSP[5]

DDR_VREF_CA

DDR CH - A

2 OF 20

DDR0_VREF_DQ
DDR1_VREF_DQ

DDR_VTT_CNTL

DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]

DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]

DDR0_CS#[0]
DDR0_CS#[1]
DDR0_ODT[0]
DDR0_ODT[1]

DDR0_MA[3]
DDR0_MA[4]

DDR0_ALERT#

DDR0_PAR

AU53
AT53
AU55
AT55

BA56
BB56
AW56
AY56

AU45
AU43
AT45
AT43

BA51
BB54
BA52
AY52
AW52
AY55
AW54
BA54
BA55
AY54

AU46
AU48
AT46
AU50
AU52
AY51
AT48
AT50
BB50
AY50
BA50
BB52

AM70
AM69
AT69
AT70
BA64
AY64
AY60
BA60
BA38
AY38
AY34
BA34
BA30
AY30
AY26
BA26

AW50
AT52

AY67
AY68
BA67

AW67

DDR_A_CLK#0
DDR_A_CLK0
DDR_A_CLK#1
DDR_A_CLK1

DDR_A_CKE0
DDR_A_CKE1

DDR_A_CS#0
DDR_A_CS#1
DDR_A_ODT0
DDR_A_ODT1

DDR_A_MA5
DDR_A_MA9
DDR_A_MA6
DDR_A_MA8
DDR_A_MA7
DDR_A_BG0
DDR_A_MA12
DDR_A_MA11
DDR_A_ACT#
DDR_A_BG1

DDR_A_MA13
DDR_A_MA15
DDR_A_MA14
DDR_A_MA16
DDR_A_BA0
DDR_A_MA2
DDR_A_BA1
DDR_A_MA10
DDR_A_MA1
DDR_A_MA0
DDR_A_MA3
DDR_A_MA4

DDR_A_DQS#0
DDR_A_DQS0
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_DQS#7
DDR_A_DQS7

DDR_A_ALERT#
DDR_A_PARITY

DDR_PG_CTRL

T14TP@
T15TP@

+0.6V_VREFCA

T233TP@

+0.6V_B_VREFDQ

DDR_A_CLK#0 [17]
DDR_A_CLK0 [17]
DDR_A_CLK#1 [17]
DDR_A_CLK1 [17]

DDR_A_CKE0 [17]
DDR_A_CKE1 [17]

DDR_A_CS#0 [17]
DDR_A_CS#1 [17]
DDR_A_ODT0 [17]
DDR_A_ODT1 [17]

DDR_A_MA5 [17]
DDR_A_MA9 [17]
DDR_A_MA6 [17]
DDR_A_MA8 [17]
DDR_A_MA7 [17]
DDR_A_BG0 [17]
DDR_A_MA12 [17]
DDR_A_MA11 [17]
DDR_A_ACT# [ 17]
DDR_A_BG1 [17]

DDR_A_MA13 [17]
DDR_A_MA15 [17]
DDR_A_MA14 [17]
DDR_A_MA16 [17]
DDR_A_BA0 [17]
DDR_A_MA2 [17]
DDR_A_BA1 [17]
DDR_A_MA10 [17]
DDR_A_MA1 [17]
DDR_A_MA0 [17]
DDR_A_MA3 [17]
DDR_A_MA4 [17]

DDR_A_DQS#0 [17]
DDR_A_DQS0 [17]
DDR_A_DQS#1 [17]
DDR_A_DQS1 [17]
DDR_A_DQS#2 [17]
DDR_A_DQS2 [17]
DDR_A_DQS#3 [17]
DDR_A_DQS3 [17]
DDR_A_DQS#4 [17]
DDR_A_DQS4 [17]
DDR_A_DQS#5 [17]
DDR_A_DQS5 [17]
DDR_A_DQS#6 [17]
DDR_A_DQS6 [17]
DDR_A_DQS#7 [17]
DDR_A_DQS7 [17]

DDR_A_ALERT# [17]
DDR_A_PARITY [17] DDR_B_ALERT# [18]

DDR_B_D[0..15][18]

DDR_B_D[16..31][18]

DDR_B_D[32..47][18]

DDR_B_D[48..63][18]

Trace width/Spacing >= 20mils

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

U1C

AF65

DDR1_DQ[0]/DDR0_DQ[16]

AF64

DDR1_DQ[1]/DDR0_DQ[17]

AK65

DDR1_DQ[2]/DDR0_DQ[18]

AK64

DDR1_DQ[3]/DDR0_DQ[19]

AF66

DDR1_DQ[4]/DDR0_DQ[20]

AF67

DDR1_DQ[5]/DDR0_DQ[21]

AK67

DDR1_DQ[6]/DDR0_DQ[22]

AK66

DDR1_DQ[7]/DDR0_DQ[23]

AF70

DDR1_DQ[8]/DDR0_DQ[24]

AF68

DDR1_DQ[9]/DDR0_DQ[25]

AH71

DDR1_DQ[10]/DDR0_DQ[26]

AH68

DDR1_DQ[11]/DDR0_DQ[27]

AF71

DDR1_DQ[12]/DDR0_DQ[28]

AF69

DDR1_DQ[13]/DDR0_DQ[29]

AH70

DDR1_DQ[14]/DDR0_DQ[30]

AH69

DDR1_DQ[15]/DDR0_DQ[31]

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DDR1_DQ[17]/DDR0_DQ[49]

AP65

DDR1_DQ[18]/DDR0_DQ[50]

AN65

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DDR1_DQ[20]/DDR0_DQ[52]

AP66

DDR1_DQ[21]/DDR0_DQ[53]

AT65

DDR1_DQ[22]/DDR0_DQ[54]

AU65

DDR1_DQ[23]/DDR0_DQ[55]

AT61

DDR1_DQ[24]/DDR0_DQ[56]

AU61

DDR1_DQ[25]/DDR0_DQ[57]

AP60

DDR1_DQ[26]/DDR0_DQ[58]

AN60

DDR1_DQ[27]/DDR0_DQ[59]

AN61

DDR1_DQ[28]/DDR0_DQ[60]

AP61

DDR1_DQ[29]/DDR0_DQ[61]

AT60

DDR1_DQ[30]/DDR0_DQ[62]

AU60

DDR1_DQ[31]/DDR0_DQ[63]

AU40

DDR1_DQ[32]/DDR1_DQ[16]

AT40

DDR1_DQ[33]/DDR1_DQ[17]

AT37

DDR1_DQ[34]/DDR1_DQ[18]

AU37

DDR1_DQ[35]/DDR1_DQ[19]

AR40

DDR1_DQ[36]/DDR1_DQ[20]

AP40

DDR1_DQ[37]/DDR1_DQ[21]

AP37

DDR1_DQ[38]/DDR1_DQ[22]

AR37

DDR1_DQ[39]/DDR1_DQ[23]

AT33

DDR1_DQ[40]/DDR1_DQ[24]

AU33

DDR1_DQ[41]/DDR1_DQ[25]

AU30

DDR1_DQ[42]/DDR1_DQ[26]

AT30

DDR1_DQ[43]/DDR1_DQ[27]

AR33

DDR1_DQ[44]/DDR1_DQ[28]

AP33

DDR1_DQ[45]/DDR1_DQ[29]

AR30

DDR1_DQ[46]/DDR1_DQ[30]

AP30

DDR1_DQ[47]/DDR1_DQ[31]

AU27

DDR1_DQ[48]

AT27

DDR1_DQ[49]

AT25

DDR1_DQ[50]

AU25

DDR1_DQ[51]

AP27

DDR1_DQ[52]

AN27

DDR1_DQ[53]

AN25

DDR1_DQ[54]

AP25

DDR1_DQ[55]

AT22

DDR1_DQ[56]

AU22

DDR1_DQ[57]

AU21

DDR1_DQ[58]

AT21

DDR1_DQ[59]

AN22

DDR1_DQ[60]

AP22

DDR1_DQ[61]

AP21

DDR1_DQ[62]

AN21

DDR1_DQ[63]

K

BL-U_BGA1356

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSP[3]/DDR0_DQSP[7]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSN[5]/DDR1_DQSN[3]
DDR1_DQSP[5]/DDR1_DQSP[3]

DDR CH - B

3 OF 20

DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[0]
DDR1_CKP[1]

DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]

DDR1_CS#[0]
DDR1_CS#[1]
DDR1_ODT[0]
DDR1_ODT[1]

DDR1_MA[3]
DDR1_MA[4]

DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]

DDR1_ALERT#

DDR1_PAR

DRAM_RESET#
DDR_RCOMP[0]
DDR_RCOMP[1]
DDR_RCOMP[2]

AN45
AN46
AP45
AP46

AN56
AP55
AN55
AP53

BB42
AY42
BA42
AW42

AY48
AP50
BA48
BB48
AP48
AP52
AN50
AN48
AN53
AN52

BA43
AY43
AY44
AW44
BB44
AY47
BA44
AW46
AY46
BA46
BB46
BA47

AH66
AH65
AG69
AG70
AR66
AR65
AR61
AR60
AT38
AR38
AT32
AR32
AR25
AR27
AR22
AR21

AN43
AP43
AT13
AR18
AT18
AU18

DDR_B_CLK#0
DDR_B_CLK#1
DDR_B_CLK0
DDR_B_CLK1

DDR_B_CKE0
DDR_B_CKE1

DDR_B_CS#0
DDR_B_CS#1
DDR_B_ODT0
DDR_B_ODT1

DDR_B_MA5
DDR_B_MA9
DDR_B_MA6
DDR_B_MA8
DDR_B_MA7
DDR_B_BG0
DDR_B_MA12
DDR_B_MA11
DDR_B_ACT#
DDR_B_BG1

DDR_B_MA13
DDR_B_MA15
DDR_B_MA14
DDR_B_MA16
DDR_B_BA0
DDR_B_MA2
DDR_B_BA1
DDR_B_MA10
DDR_B_MA1
DDR_B_MA0
DDR_B_MA3
DDR_B_MA4

DDR_B_DQS#0
DDR_B_DQS0
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_DQS#7
DDR_B_DQS7

DDR_B_ALERT#
DDR_B_PARITY
DDR_DRAMRST#

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

DDR_B_CLK#0 [18]
DDR_B_CLK#1 [18]
DDR_B_CLK0 [18]
DDR_B_CLK1 [18]

DDR_B_CKE0 [18]

DDR_B_CKE1 [18]

T16TP@
T17TP@

DDR_B_CS#0 [18]

DDR_B_CS#1 [18]

DDR_B_ODT0 [18]

DDR_B_ODT1 [18]

DDR_B_MA5 [18]

DDR_B_MA9 [18]

DDR_B_MA6 [18]

DDR_B_MA8 [18]

DDR_B_MA7 [18]

DDR_B_BG0 [ 18]

DDR_B_MA12 [18]

DDR_B_MA11 [18]

DDR_B_ACT# [18]

DDR_B_BG1 [ 18]

DDR_B_MA13 [18]

DDR_B_MA15 [18]

DDR_B_MA14 [18]

DDR_B_MA16 [18]

DDR_B_BA0 [18]

DDR_B_MA2 [18]

DDR_B_BA1 [18]

DDR_B_MA10 [18]

DDR_B_MA1 [18]

DDR_B_MA0 [18]

DDR_B_MA3 [18]

DDR_B_MA4 [18]

DDR_B_DQS#0 [18]

DDR_B_DQS0 [18]

DDR_B_DQS#1 [18]

DDR_B_DQS1 [18]

DDR_B_DQS#2 [18]

DDR_B_DQS2 [18]

DDR_B_DQS#3 [18]

DDR_B_DQS3 [18]

DDR_B_DQS#4 [18]

DDR_B_DQS4 [18]

DDR_B_DQS#5 [18]

DDR_B_DQS5 [18]

DDR_B_DQS#6 [18]

DDR_B_DQS6 [18]

DDR_B_DQS#7 [18]

DDR_B_DQS7 [18]

DDR_B_PARITY [18]

DDR_DRAMRST# [17,18]

1 2

RC1 121_0402_1%

1 2

RC2 80.6_0402_1%

1 2

RC3 100_0402_1%

+1.2V_VDDQ

0.1U_0201_10V6K

DDR_PG_CTRL

Buffer with Open Drain Output

For VTT power control

A A

5

4

2

3

74AUP1G07GW_TSSOP5

12

NC1VCC

A

GND

CC1

UC1

5

4

Y

+5VALW

1 2

R92
10K_0402_5%

DDR_VTT_PG_CTRL [ 52]

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/03/21 2017/03/01

2016/03/21 2017/03/01

2016/03/21 2017/03/01

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

+1.2V_VDDQ

R163 470_0402_5%

100P_0402_50V8J

1 2

ESD@

DDR_DRAMRST#

DDR_DRAMRST#

12

C3

ESD request

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

KBL ULT(2/12) DDR4

KBL ULT(2/12) DDR4

KBL ULT(2/12) DDR4

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

C

C

C

LA-C422P

LA-C422P

LA-C422P

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

1.0

1.0

6 58Tuesday, November 15, 2016

6 58Tuesday, November 15, 2016

1

6 58Tuesday, November 15, 2016

1.0

5

U1E

AV2

AW3

AV3

AW2

AU4
AU3
AU2
AU1

M2
M3

J4
V1
V2
M1

G3
G2
G1

AW13

AY11

22P_0402_50V8J

SPI - FLASH

SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_IO2
SPI0_IO3
SPI0_CS0#
SPI0_CS1#
SPI0_CS2#

SPI - TOUCH

GPP_D1/SPI1_CLK
GPP_D2/SPI1_MISO
GPP_D3/SPI1_MOSI
GPP_D21/SPI1_IO2
GPP_D22/SPI1_IO3
GPP_D0/SPI1_CS#

C LINK

CL_CLK
CL_DATA
CL_RST#

GPP_A0/RCIN#

GPP_A6/SERIRQ

BL-U_BGA1356

K

C5

@EMI@

33_0804_8P4R_5%

33_0804_8P4R_5% @

68P_0402_50V8J

RP3

18
27
36
45

RP4

18
27
36
45

C6

@EMI@

SOC_SPI_HOLD#_R0
SOC_SPI_WP#_R0
SOC_SPI_MISO_R0
SOC_SPI_MOSI_R0

SOC_SPI_HOLD#_R1
SOC_SPI_WP#_R1
SOC_SPI_MISO_R1
SOC_SPI_MOSI_R1

SERIRQ[26,37,45]

SOC_SPI_CLK

SOC_SPI_CLK
SOC_SPI_SO
SOC_SPI_SI
SOC_SPI_WP#
SOC_SPI_HOLD#
SOC_SPI_CS#0
SOC_SPI_CS#1
SOC_SPI_CS#2

TCH_SPI_CLK

CL_CK
CL_DAT
CL_RST#

SERIRQ

1 2

R42 33_0402_5%

1 2

R44 33_0402_5%@

1 2

R45 33_0402_5%@EMI@

SOC_SPI_HOLD#
SOC_SPI_WP#
SOC_SPI_SO
SOC_SPI_SI

SOC_SPI_CLK[41]
SOC_SPI_SO[41]

D D

C C

SOC_SPI_SI[41]

SOC_SPI_CS#2[ 41]

T20 TP@

CL_CLK[28]
CL_DAT[28]

CL_RST#[28]

KB_RST#[45]

SPI Signals

SOC side

B B

4

SMBUS, SMLINK

LPC

GPP_A14/SUS_STAT#/ESPI_RESET#

5 OF 20

SOC_SPI_CLK_R0

SOC_SPI_CLK_R1

1

1

C7
68P_0402_50V8J

@EMI@

2

2

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

EMIEMI

SOC_SMBCLK

R7

SOC_SMBDATA

R8

SOC_SMBALERT#

R10

SOC_SML0CLK

R9

SOC_SML0DATA

W2

SOC_SML0ALERT#

W1

SOC_SML1CLK

W3

SOC_SML1DATA

V3

SOC_SML1ALERT#

AM7

LPC_AD0

AY13

LPC_AD1

BA13

LPC_AD2

BB13

LPC_AD3

AY12

LPC_FRAME#

BA12

SUS_STAT#

BA11

CLKOUT_LPC0

AW9

CLKOUT_LPC1

AY9
AW11

CLKRUN#

SOC_SPI_CS#0

SOC_SPI_WP#_R0

SOC_SPI_CS#1
SOC_SPI_MISO_R1
SOC_SPI_WP#_R1

R37 22_0402_1%
R38 22_0402_1%

R590 0_0402_5%@

3

SOC_SML0CLK [23]
SOC_SML0DATA [23]

SOC_SML0ALERT# [10]

1 2
1 2

NEC@

1 2

12

R400_0402_5% @

SPI ROM ( 16MByte )

U2

1

/CS

2

DO(IO1)

3

/WP(IO2)
GND4DI(IO0)

W25Q128FVSIQ_SO8

/HOLD(IO3)

VCC

CLK

SPI ROM (Reserve)

U3

@

1

/CS

2

DO/IO1

3

/WP/IO2

4

GND

W25Q32FVSSIQ_SO8

VCC

/HOLD/IO3

CLK

DI/IO0

U3

@

SMB

(DDR, CP)

SML0

(GBE)

SML1

(EC, Thermal Sensor, APS)

LPC_AD0 [ 37,45]
LPC_AD1 [ 37,45]
LPC_AD2 [ 37,45]

LPC_AD3 [ 37,45]
LPC_FRAME# [37,45]
SUS_STAT# [37]

CLK_LPC_EC [ 45]
PCMCIA_CLK_24 [26]

LPCCLK_DEBUG_24M [37]

PCMCIA_CLKRUN# [26]

CLKRUN# [37]

8

SOC_SPI_HOLD#_R0SOC_SPI_MISO_R0

7

SOC_SPI_CLK_R0

6

SOC_SPI_MOSI_R0

5

C8

68P_0402_50V8J

@EMI@

EMI

8

SOC_SPI_HOLD#_R1

7

SOC_SPI_CLK_R1

6

SOC_SPI_MOSI_R1

5

2

SOC_SPI_SO

SOC_SPI_SI

SOC_SPI_WP#

SOC_SPI_HOLD#

SOC_SPI_CS#0

SOC_SPI_HOLD#

1 2

R346 1K_0402_1%@

1 2

R345 1K_0402_1%@

1 2

R31 1K_0402_1%@

1 2

R32 1K_0402_1%@

1 2

R33 1K_0402_1%@

1 2

R34 1K_0402_1%@

1

+3V_SPI

From WW36 MOW for SKL-U ES sample

+3VALW

RP2

SOC_SML1CLK
SOC_SML1DATA
SOC_SMBCLK
SOC_SMBDATA

LPC Bus

SOC_SMBALERT#

SMBALERT# / GPP_C2

TLS CONFIDENTIALITY

H

ENABLE

DISABLE

L

+3V_SPI

1

C4

0.1U_0201_10V6K

2

1

2

+3V_SPI

1

C9

@

0.1U_0201_10V6K

2

The R87 need s tuf f If use PCHHOT# fr o m WW52 MO W

SOC_SML1ALERT#

SERIRQ

CLKRUN#

SOC_SML0CLK

SOC_SML0DATA

@
1 8
2 7
3 6
4 5

1K_0804_8P4R_5%

1 2

R46 1K_0402_5%M3@

1 2

R87 150K_0402_1%@

+3VS_PGPPA

1 2

R41 10K_0402_5%

1 2

R348 8.2K_0402_5%

1 2

R334 499_0402_1%

1 2

R331 499_0402_1%

+3VALW

+3VALW

VCC3GBE

SPI ROM ( 8MByte )

ROM side

SPI ROM

1st

2nd

Vendor

Winbond

W25Q64FVSSIQ_SO8

16MB

SA00005VV10

8MB

SA000039A30

4MB

SA00003K820

PCH_SMB_DATA

PCH_SMB_CLK

R210 2.2K_0402_5%

R211 2.2K_0402_5%

+3VS

12

12

SOC_SMB (+3VALW) EC_SMB (+3VS)

+3VS

RF request

PCH_SMB_CLK

A A

5

EC_SMB_CK2

CLKOUT_LPC0

C10 22P_0402_50V8J

@RF@

C11 22P_0402_50V8J

@RF@

1 2

C556 33P_0402_50V8J

RF@

4

SOC_SMBDATA

NX7002BKS 2N SOT363-6

SOC_SMBCLK

2

@

Q9A

16

NX7002BKS 2N SOT363-6
Q9B

PCH_SMB (+3VS)
DIMM1/DIMM2/Clic kPad

SOC_SMBDATA PCH_SMB_DATA

SOC_SMBCLK PCH_SMB_CLK

PCH_SMB_DATA

5

PCH_SMB_CLK

43

@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1 2

@

R47 0_0402_5%

1 2

@

R49 0_0402_5%

PCH_SMB_DATA [17,18,40]

PCH_SMB_CLK [ 17,18,40] EC_SMB_DA2 [37,40,45]

Compal Secret Data

Compal Secret Data

2016/03/21 2017/03/01

2016/03/21 2017/03/01

2016/03/21 2017/03/01

Compal Secret Data

SOC_SML1 (+3VALW)

Deciphered Date

Deciphered Date

Deciphered Date

2

SOC_SML1CLK

SOC_SML1DATA

+3VS

NX7002BKS 2N SOT363-6

Q10A

EC, Thermal Sensor, APS

SOC_SML1CLK EC_SMB_CK2

SOC_SML1DATA EC_SMB_DA2

2

16

@

5

43

NX7002BKS 2N SOT363-6

@

Q10B

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

KBL ULT(3/12) SPI,ESPI,SMB

KBL ULT(3/12) SPI,ESPI,SMB

KBL ULT(3/12) SPI,ESPI,SMB

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

C

C

C

LA-C422P

LA-C422P

LA-C422P

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

R48 0_0402_5%

R50 0_0402_5%

EC_SMB_CK2

EC_SMB_DA2

1 2

1 2

@

@

EC_SMB_CK2 [37,40,45]

1

1.0

1.0

7 58Tuesday, November 15, 2016

7 58Tuesday, November 15, 2016

7 58Tuesday, November 15, 2016

1.0

5

D D

HDA_SDIN0[38]

SC_OFF#[36]

SPKR[10,38]

T28 TP@

T38 TP@

HDA_SYNC
HDA_BIT_CLK
HDA_SDOUT
HDA_SDIN0

HDA_RST#

SOC_GPIOF0

SC_OFF#

4

BA22

HDA_SYNC/I2S0_SFRM

AY22

HDA_BLK/I2S0_SCLK

BB22

HDA_SDO/I2S0_TXD

BA21

HDA_SDI0/I2S0_RXD

AY21

HDA_SDI1/I2S1_RXD

AW22

HDA_RST#/I2S1_SCLK

J5

GPP_D23/I2S_MCLK

AY20

I2S1_SFRM

AW20

I2S1_TXD

AK7

GPP_F1/I2S2_SFRM

AK6

GPP_F0/I2S2_SCLK

AK9

GPP_F2/I2S2_TXD

AK10

GPP_F3/I2S2_RXD

H5

GPP_D19/DMIC_CLK0

D7

GPP_D20/DMIC_DATA0

D8

GPP_D17/DMIC_CLK1

C8

GPP_D18/DMIC_DATA1

AW5

GPP_B14/SPKR

K

BL-U_BGA1356

3

U1G

AUDIO

7 OF 20

SDIO/SDXC

GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3

GPP_G5/SD_CD#

GPP_G6/SD_CLK

GPP_G7/SD_WP

GPP_A17/SD_PWR_EN#/ISH_GP7

GPP_A16/SD_1P8_SEL

SD_RCOMP

GPP_F23

AB11
AB13
AB12
W12
W11
W10
W8
W7

BA9
BB9

AB7

AF13

SDIO_RCOMP

12

R52 200_0402_1%

2

1

C C

B B

A A

+3VALW

1 2

@

R54 1K_0402_5%

HDA_SDOU T

ME debug mode,this signal has a weak internal PD
Low = Disabled (Default)

*

High = Enabled [Flash Descriptor Security Overide]

HDA_SDOUT

HDA for AUDIO

ME_FLASH[45]

HDA_SDOUT_AUDIO[38]
HDA_SYNC_AUDIO[38]
HDA_RST_AUDIO#[38]
HDA_BITCLK_AUDIO[38]

A36
B36
C38
D38
C36
D36
A38
B38

C31
D31
C33
D33
A31
B31
A33
B33

A29
B29
C28
D28
A27
B27
C27
D27

KBL-U_BGA1356

U1I

CSI-2

CSI2_DN0
CSI2_DP0
CSI2_DN1
CSI2_DP1
CSI2_DN2
CSI2_DP2
CSI2_DN3
CSI2_DP3

CSI2_DN4
CSI2_DP4
CSI2_DN5
CSI2_DP5
CSI2_DN6
CSI2_DP6
CSI2_DN7
CSI2_DP7

CSI2_DN8
CSI2_DP8
CSI2_DN9
CSI2_DP9
CSI2_DN10
CSI2_DP10
CSI2_DN11
CSI2_DP11

Closed to CPU

33P_0402_50V8J

C12

RF@

9 OF 20

1 2

R53 0_0402_5%@

RP5

1 8
2 7
3 6
4 5

33_8P4R_5%

EMI@

1

2

CSI2_CLKN0

CSI2_CLKP0

CSI2_CLKN1

CSI2_CLKP1

CSI2_CLKN2

CSI2_CLKP2

CSI2_CLKN3

CSI2_CLKP3

CSI2_COMP

GPP_D4/FLASHTRIG

EMMC

GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F22/EMMC_CLK

GPP_F12/EMMC_CMD

EMMC_RCOMP

EMI

C37
D37
C32
D32
C29
D29
B26
A26

E13
B7

AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1

AM2
AM3
AP4

AT1

HDA_SDOUT
HDA_SYNC
HDA_RST#
HDA_BIT_CLK

C13

1

33P_0402_50V8J

RF@

2

12

R55

0_0402_5%

@

CSI2_COMP

R58 100_0402_1%

TAMPER_SW_DTCT#

EMMC_RCOMP

12

12

R67 200_0402_1%

TAMPER_SW_DTCT# [9]

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/03/21 2017/03/01

2016/03/21 2017/03/01

2016/03/21 2017/03/01

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

KBL ULT(4/12) HDA,EMMC,SDIO

KBL ULT(4/12) HDA,EMMC,SDIO

KBL ULT(4/12) HDA,EMMC,SDIO

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

C

C

C

LA-C422P

LA-C422P

LA-C422P

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

1

8 58Tuesday, November 15, 2016

8 58Tuesday, November 15, 2016

8 58Tuesday, November 15, 2016

1.0

1.0

1.0

5

+3VL_RTC

1 2

R69 20K_0402_5%

1 2

D D

C14 1U_0402_6.3V6K

1 2

CLRP1 SHORT PADS

SOC_SRTCRST#

CLR ME

GLAN

1 2

R71 20K_0402_5%

1 2

C15 1U_0402_6.3V6K

1 2

CLRP2 SHORT PADS

1 2

R72 1M_0402_5%

SOC_RTCRST#

CLR CMOS

SM_INTRUDER#

WLAN

Card Reader

M.2_Optane

+3VS

RP6

10K_0804_8P4R_5%

Premium@

1 2

R77 10K_0402_5%

1 2

C C

+3VALW_DSW

B B

+3V_PRIM

+3VALW_DSW

R78 10K_0402_5%

+3VALW_DSW+3V_PRIM

RP7

10K_0804_8P4R_5%

CXDP1 SHORT PADS

1 2

@

R81 1K_0402_5%

R82 100K_0402_5%

1 2

R83 8.2K_0402_5%

1 2

R85 1K_0402_5%

1 2

@

R86 10K_0402_5%

1 2

@

R88 10K_0402_5%

1 2

@

R90 100K_0402_5%

12

From EC(open-drain)

A A

VCCST_PG_EC[45,46]

CLKREQ_WLAN#

18

CLKREQ_LAN#

27

CLKREQ_CR#

36

CLKREQ_PCI#

45

CLKREQ_2242#

CLKREQ_SATAex#

PCH_PWROK

18

LAN_WAKE#

27

EC_RSMRST#

36

SYS_RESET#

45

SYS_RESET#

SUSCLK

PCH_DPWROK

12

PM_BATLOW#

PCIE_WAKE#

AC_PRESENT_R

SOC_VRALERT#

PBTN_OUT#_R

+1.0V_VCCST

12

R96 60.4_0402_1%

LIN-2

R95
1K_0402_5%

1 2

PCMCIA / Express Card

SATA-EX

LIN-2

ESD request

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

T84 TP@

EC_VCCST_PG

CLKREQ_SATAex#[32]

ESD@

ESD@

ESD@

ESD@

R84 10K_0402_5%@

SUSPWRDNACK[45]

4

CLK_PCIE_LAN#[23]
CLK_PCIE_LAN[23]

CLKREQ_LAN#[23]

CLK_PCIE_WLAN#[28]
CLK_PCIE_WLAN[28]
CLKREQ_WLAN#[28]

CLK_PCIE_CR#[24]
CLK_PCIE_CR[24]

CLKREQ_CR#[24]

CLK_PCIE_2242#[29]
CLK_PCIE_2242[29]

CLKREQ_2242#[29]

CLK_PCIE_PCI#[26]
CLK_PCIE_PCI[ 26]
CLKREQ_PCI#[25,26]

CLK_PCIE_SATAex#[32]
CLK_PCIE_SATAex[32]

12

C20

12

C22

12

C23

12

C24

SYS_RESET#[5]

SYS_PWROK[45]
PCH_PWROK[45]

PCIE_WAKE#[25,28]
LAN_WAKE#[23]
LANPHYPC[23]

+1.0V_VCCST

C341

RF@

68P_0402_50V8J

SOC_PLTRST#

H_CPUPWRGD_R

SYS_PWROK

PCH_PWROK

12

T114 TP@

1

2

CLK_PCIE_LAN#
CLK_PCIE_LAN
CLKREQ_LAN#

CLK_PCIE_WLAN#
CLK_PCIE_WLAN
CLKREQ_WLAN#

CLK_PCIE_CR#
CLK_PCIE_CR
CLKREQ_CR#

CLK_PCIE_2242#
CLK_PCIE_2242
CLKREQ_2242#

CLK_PCIE_PCI#
CLK_PCIE_PCI
CLKREQ_PCI#

CLK_PCIE_SATAex#
CLK_PCIE_SATAex
CLKREQ_SATAex#

SOC_PLTRST#
SYS_RESET#
EC_RSMRST#

H_CPUPWRGD_R
EC_VCCST_PG

SYS_PWROK
PCH_PWROK
PCH_DPWROK

SUSPWRDNACK
SUSACK#

PCIE_WAKE#
LAN_WAKE#

LANPHYPC

TAMPER_SW_DTCT#[8]

U1J

D42

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

AR10

GPP_B5/SRCCLKREQ0#

B42

CLKOUT_PCIE_N1

A42

CLKOUT_PCIE_P1

AT7

GPP_B6/SRCCLKREQ1#

D41

CLKOUT_PCIE_N2

C41

CLKOUT_PCIE_P2

AT8

GPP_B7/SRCCLKREQ2#

D40

CLKOUT_PCIE_N3

C40

CLKOUT_PCIE_P3

AT10

GPP_B8/SRCCLKREQ3#

B40

CLKOUT_PCIE_N4

A40

CLKOUT_PCIE_P4

AU8

GPP_B9/SRCCLKREQ4#

E40

CLKOUT_PCIE_N5

E38

CLKOUT_PCIE_P5

AU7

GPP_B10/SRCCLKREQ5#

K

BL-U_BGA1356

PCH PLTRST Buf f er

SOC_PLTRST#

TC7SH08FU_SSOP 5P

U1K

AN10

GPP_B13/PLTRST#

B5

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

B6

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWROK

AR13

GPP_A13/SUSWARN#/SUSPWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/RSVD

K

BL-U_BGA1356

TAMPER_SW_DTCT#

AC_PRESENT[45]

PBTN_OUT#[5,45]

EC_RSMRST#[5,45]

3

CLOCK SIGNALS

10 OF 20

R79 0_0402_5%@

+3VALW

1

IN1

2

IN2

SYSTEM POWER MANAGEMENT

1 2

R89 0_0402_5%@

1 2

R91 0_0402_5%@

1 2

R94 0_0402_5%@

1 2

5

U5

P

O

G

3

11 OF 20

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

XCLK_BIASREF

C21

1 2

0.1U_0201_10V6K

4

GPP_B11/EXT_PWR_GATE#

SW1

1

2

SPVR310100_4P

Lenovo@

GPD8/SUSCLK

XTAL24_IN

XTAL24_OUT

RTCX1
RTCX2

SRTCRST#

RTCRST#

12

R80
100K_0402_5%

GPP_B12/SLP_S0#

GPD4/SLP_S3#
GPD5/SLP_S4#

GPD10/SLP_S5#

SLP_SUS#
SLP_LAN#

GPD9/SLP_WLAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_A11/PME#

INTRUDER#

GPP_B2/VRALERT#

3

4

AC_PRESENT_R

PBTN_OUT#_R

PCH_DPWROK

2

CLK_CPU_ITP#

F43

CLK_CPU_ITP

E43

BA17

SUSCLK

SOC_XTAL24_IN

E37

SOC_XTAL24_OUT

E35

XCLK_BIASREF

E42

SOC_RTCX1 SOC_RTCX1

AM18

SOC_RTCX2

AM20

SOC_SRTCRST#

AN18
AM16

PLT_RST#

PLT_RST# [23,24,25,26,28,29,32,37,41,45]

PM_SLP_S0#

AT11

PM_SLP_S3#

AP15

PM_SLP_S4#

BA16

PM_SLP_S5#

AY16

SLP_SUS#

AN15

SLP_LAN#

AW15

SLP_WLAN#

BB17

PM_SLP_A#

AN16

PBTN_OUT#_R

BA15

AC_PRESENT_R

AY15

PM_BATLOW#

AU13

AU11

SM_INTRUDER#

AP16

EXT_PWR_GATE#

AM10

SOC_VRALERT#

AM11

T85TP@
T86TP@

SUSCLK [28,29]

1 2

R605 33_0402_5%

1 2

R73 33_0402_5%

1 2

R74 2.7K_0402_1%

1 2

R75 0_0402_5%@

SOC_RTCRST# [ 5]

PM_SLP_S0# [5]
PM_SLP_S3# [5,25, 45,46]
PM_SLP_S4# [5,12, 45,46,52]
PM_SLP_S5# [5,45]

SLP_SUS# [13,53]
SLP_LAN# [12]
SLP_WLAN# [28]
PM_SLP_A# [5,28,45,54]

EXT_PWR_GATE# [13]

1 2

R62 0_0402_5%@

1000P_0402_50V7K

0_0402_5%

C119

@

SOC_XTAL24_IN_R
SOC_XTAL24_OUT_R

+1.0V_CLK5_F24NS

SOC_RTCX2_R

R595

@

1 2

2

1

D27
RB751V40_SOD-323

Lenovo@

1 2

SOC_RTCX2_RSOC_RTCRST#

5.6P_0402_50V8D

C16

C18

1

1 2

R70 1M_0402_5%

Y1
24MHZ_12PF_7V24000020

3

3

GND

4

22P_0402_50V8J

1 2

R76 10M_0402_5%

32.768KHZ_9PF_9H03280012

1

2

1

1

GND

2

Y2

12

C19

5.6P_0402_50V8D

SM_INTRUDER_D# [50]

1

C17

2

6.8P_0402_50V8C

1

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/03/21 2017/03/01

2016/03/21 2017/03/01

2016/03/21 2017/03/01

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

KBL ULT(5/12) CLK,GPIO

KBL ULT(5/12) CLK,GPIO

KBL ULT(5/12) CLK,GPIO

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

C

C

C

LA-C422P

LA-C422P

LA-C422P

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

1

9 58Tuesday, November 15, 2016

9 58Tuesday, November 15, 2016

9 58Tuesday, November 15, 2016

1.0

1.0

1.0

5

4

3

2

1

U1F

GSPI0_CS#

D D

HDD_I FDe t#

SEL

(PCIE)

L
H (SATA)

HDD_I/F (reserve)

PTN33 55(re serv e)

C C

WWAN_PWROFF#[29]

3G_OFF#[29]

HDD_IFDet_SOC#[32]

BT_ON[28]

EXTPWRG[47]

PWRON_DOCK#[47]

I2C_1_SDA[21]
I2C_1_SCL[21]

WWAN_RST#[29]

WWAN_CFG0[29]
WWAN_CFG1[29]

GSPI0_CLK
GSPI0_MISO
GSPI0_MOSI

WWAN_PWROFF#
3G_OFF#
DDI1_Config
GSPI1_MOSI

HDD_IFDet_SOC#
SOC_SPI_IRQ#
BT_ON

EXTPWRG
PWRON_DOCK#

I2C_0_SDA
I2C_0_SCL

I2C_1_SDA
I2C_1_SCL

WWAN_RST#

WWAN_CFG0
WWAN_CFG1

AH10

AH11
AH12

AF11
AF12

AN8
AP7
AP8
AR7

AM5
AN7
AP5
AN5

AB1
AB2

W4

AB3

AD1
AD2
AD3
AD4

U7
U6

U8
U9

AH9

LPSS ISH

GPP_B15/GSPI0_CS#
GPP_B16/GSPI0_CLK
GPP_B17/GSPI0_MISO
GPP_B18/GSPI0_MOSI

GPP_B19/GSPI1_CS#
GPP_B20/GSPI1_CLK
GPP_B21/GSPI1_MISO
GPP_B22/GSPI1_MOSI

GPP_C8/UART0_RXD
GPP_C9/UART0_TXD
GPP_C10/UART0_RTS#
GPP_C11/UART0_CTS#

GPP_C20/UART2_RXD
GPP_C21/UART2_TXD
GPP_C22/UART2_RTS#
GPP_C23/UART2_CTS#

GPP_C16/I2C0_SDA
GPP_C17/I2C0_SCL

GPP_C18/I2C1_SDA
GPP_C19/I2C1_SCL

GPP_F4/I2C2_SDA
GPP_F5/I2C2_SCL

GPP_F6/I2C3_SDA
GPP_F7/I2C3_SCL

GPP_F8/I2C4_SDA
GPP_F9/I2C4_SCL

BL-U_BGA1356

K

6 OF 20

GPP_D9
GPP_D10
GPP_D11
GPP_D12

GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL

GPP_F10/I2C5_SDA/ISH_I2C2_SDA
GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

GPP_D15/ISH_UART0_RTS#

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_C15/UART1_CTS#/ISH_UART1_CTS#

GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5

GPP_A12/BM_BUSY#/ISH_GP6

P2
P3
P4
P1

M4
N3

N1
N2

AD11
AD12

U1
U2
U3
U4

AC1
AC2
AC3
AB4

AY8
BA8
BB7
BA7
AY7
AW7
AP13

DOCKID3
DOCKID2
DOCKID1
DOCKID0

Exp_SHDN#

BTN_ECO#

WWAN_CFG2
WWAN_CFG3

ODD_EN

vPRO_detec

DOCKID3 [47]
DOCKID2 [47]
DOCKID1 [47]
DOCKID0 [47]

Exp_SHDN# [25]

1 2

R51 0_0402_5%@

WWAN_CFG2 [29]
WWAN_CFG3 [29]

ODD_EN [37]

BTN_ECO# [43]
EC_WAKE# [45]

LIN-2

PTN3 355

ODD_DA#_R[5,37]

EC_SCI#[5,45]
SATA_GP1[11,37]
SATA_GP0[11]

WWAN_PE_DTCT#[11,29]

I2C_0_SCL
I2C_0_SDA
I2C_1_SDA
I2C_1_SCL

DOCKID1
DOCKID3
DOCKID0
DOCKID2

ODD_DA#_R
ODD_EN

EC_SCI#
SATA_GP1
SATA_GP0
WWAN_PE_DTCT#

RP8

1 8
2 7
3 6
4 5

2.2K_0804_8P4R_5%

@

RP10

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

RP11

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

RP12

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

+3VS

Prod uctDock _ID3 D ock_I D2 Dock _ID 1 D ock_I D0

0 0 0 1
0 0 01
0 0 1
0 001

1

Functional Strap Definitions

SPKR (Internal Pull Down):

TOP Swap Override

0 = Disable TOP Swap mode.

1 = Enable TOP Swap Mode.

B B

GSPI0_MOSI (Internal Pull Down):

No Reboot

0 = Disable No Reboot mode.

1 = Enable No Reboot Mode. (PCH will disable the TCO

Timer system reboot feature). T his function is useful

when running ITP/ XDP.

GSPI1_MOSI (Internal Pull Down):

Boot BIOS Strap Bit

0 = SPI Mode

1 = LPC Mode

SML0ALERT# (Internal Pu ll Down):

eSPI or LPC

A A

0 = LPC is selected for EC --> For KB9022/9032 Use

1 = eSPI is selected fo r EC --> For KB9032 On ly.

Strap Pin

+3VS

R99 2.2K_0402_5%@

R100 2.2K_0402_5%@

R101 2.2K_0402_5%@

+3V_PRIM

R102 4.7K_0402_5%

1 2

1 2

1 2

@

1 2

SPKR

GSPI0_MOSI

GSPI1_MOSI

SOC_SML0ALERT#

SPKR [8,38]

(RESERVE for NO DOCK)

GIDO RAH
GODZ ILLA
MOTH RA

SOC_SML0ALERT# [7]

WWAN_PWROFF#

GSPI0_CS#

GSPI0_CLK

GSPI0_MISO

SOC_SPI_IRQ#

vPRO_detec

DDI1_Config

1 2

@

R534 47K_0402_5%

1 2

@

R338 49.9K_0402_1%

1 2

@

R339 49.9K_0402_1%

1 2

@

R340 49.9K_0402_1%

1 2

@

R532 10K_0402_5%

1 2

M3@

R535 10K_0402_5%

1 2

NOM3@

R536 10K_0402_5%

1 2

@

R342 10K_0402_5%

1 2

@

R343 10K_0402_5%

+3VALW

+3VALW

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/03/21 2017/03/01

2016/03/21 2017/03/01

2016/03/21 2017/03/01

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

KBL ULT(6/12) GPIO,LPIO

KBL ULT(6/12) GPIO,LPIO

KBL ULT(6/12) GPIO,LPIO

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

C

C

C

LA-C422P

LA-C422P

LA-C422P

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

1

10 58Tuesday, November 15, 2016

10 58Tuesday, November 15, 2016

10 58Tuesday, November 15, 2016

1.0

1.0

1.0

5

4

3

2

1

U1H

D D

USB3_CONN (Left)

PCI_PCMCIA (NEC)

LIN-2

PCIE_GLAN

PCIE_WLAN

2280

PCIE*2_SATA-Express

LIN-2

SATA_HDD

C C

SATA_ODD

PCIE_Card Reader

PCIE_Express Card (LNV)

LIN-2

2242

PCIE*2_Optane

LIN-2

B B

USB3_PRX_DTX_N5[35]
USB3_PRX_DTX_P5[35]
USB3_PTX_DRX_N5[35]
USB3_PTX_DRX_P5[35]

PCIE_PRX_DTX_N2[26]
PCIE_PRX_DTX_P2[26]

PCIE_PTX_C_DRX_N2[26]
PCIE_PTX_C_DRX_P2[26]

PCIE_PRX_DTX_N3[23]
PCIE_PRX_DTX_P3[23]
PCIE_PTX_C_DRX_N3[23]
PCIE_PTX_C_DRX_P3[23]

PCIE_PRX_DTX_N4[28]
PCIE_PRX_DTX_P4[28]
PCIE_PTX_C_DRX_N4[28]
PCIE_PTX_C_DRX_P4[28]

PCIE_PRX_DTX_N5_L0[32]
PCIE_PRX_DTX_P5_L0[32]
PCIE_PTX_C_DRX_N5_L0[32]
PCIE_PTX_C_DRX_P5_L0[32]

PCIE_PRX_DTX_N5_L1[32]
PCIE_PRX_DTX_P5_L1[32]
PCIE_PTX_C_DRX_N5_L1[32]
PCIE_PTX_C_DRX_P5_L1[32]

SATA_PRX_DTX_N0[32]
SATA_PRX_DTX_P0[32]
SATA_PTX_DRX_N0[32]
SATA_PTX_DRX_P0[32]

SATA_PRX_DTX_N1[37]
SATA_PRX_DTX_P1[37]
SATA_PTX_DRX_N1[37]
SATA_PTX_DRX_P1[37]

PCIE_PRX_DTX_N9[24]
PCIE_PRX_DTX_P9[24]
PCIE_PTX_C_DRX_N9[24]
PCIE_PTX_C_DRX_P9[24]

PCIE_PRX_DTX_N10[25]
PCIE_PRX_DTX_P10[25]
PCIE_PTX_C_DRX_N10[25]
PCIE_PTX_C_DRX_P10[25]

XDP_PRDY#[5]
XDP_PREQ#[5]
TPM_IRQ#[41]

PCIE_PRX_DTX_N11_L1[29]

PCIE_PRX_DTX_P11_L1[29]
PCIE_PTX_C_DRX_N11_L1[29]
PCIE_PTX_C_DRX_P11_L1[29]

PCIE_PRX_DTX_N11_L0[29]

PCIE_PRX_DTX_P11_L0[29]
PCIE_PTX_C_DRX_N11_L0[29]
PCIE_PTX_C_DRX_P11_L0[29]

1 2

C33 0.1U_0201_10V6K

1 2

C34

0.1U_0201_10V6K

NEC@
NEC@

1 2

C25 0.1U_0201_10V6K

1 2

C26

0.1U_0201_10V6K

1 2

C27 0.1U_0201_10V6K

1 2

C28

0.1U_0201_10V6K

1 2

C511 0. 22U_0201_6.3V6K

1 2

C512 0. 22U_0201_6.3V6K

1 2

C513 0. 22U_0201_6.3V6K

1 2

C514 0. 22U_0201_6.3V6K

1 2

C29 0.1U_0201_10V6K

1 2

C30

0.1U_0201_10V6K

1 2

C31 0.1U_0201_10V6K

1 2

C32

0.1U_0201_10V6K

LNVHUB@

1 2

R106 100_0402_1%

LNVHUB@

XDP_PRDY#
XDP_PREQ#
TPM_IRQ#

1 2

C515 0. 22U_0201_6.3V6K

1 2

C516 0. 22U_0201_6.3V6K

Premium@
Premium@

1 2

C517 0. 22U_0201_6.3V6K

1 2

C518 0. 22U_0201_6.3V6K

Premium@
Premium@

PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P2

PCIE_PTX_DRX_N3
PCIE_PTX_DRX_P3

PCIE_PTX_DRX_N4
PCIE_PTX_DRX_P4

PCIE_PTX_DRX_N5_L0
PCIE_PTX_DRX_P5_L0

PCIE_PTX_DRX_N5_L1
PCIE_PTX_DRX_P5_L1

PCIE_PTX_DRX_N9
PCIE_PTX_DRX_P9

PCIE_PTX_DRX_N10
PCIE_PTX_DRX_P10

PCIE_RCOMPN
PCIE_RCOMPP

PCIE_PTX_DRX_N11_L1
PCIE_PTX_DRX_P11_L1

PCIE_PTX_DRX_N11_L0
PCIE_PTX_DRX_P11_L0

PCIE/US B3/S ATA

H13

PCIE1_RXN/USB3_5_RXN

G13

PCIE1_RXP/USB3_5_RXP

B17

PCIE1_TXN/USB3_5_TXN

A17

PCIE1_TXP/USB3_5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_RXP

D16

PCIE2_TXN/USB3_6_TXN

C16

PCIE2_TXP/USB3_6_TXP

H16

PCIE3_RXN

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

PCIE4_RXN

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE4_TXP

F16

PCIE5_RXN

E16

PCIE5_RXP

C19

PCIE5_TXN

D19

PCIE5_TXP

G18

PCIE6_RXN

F18

PCIE6_RXP

D20

PCIE6_TXN

C20

PCIE6_TXP

F20

PCIE7_RXN/SATA0_RXN

E20

PCIE7_RXP/SATA0_RXP

B21

PCIE7_TXN/SATA0_TXN

A21

PCIE7_TXP/SATA0_TXP

G21

PCIE8_RXN/SATA1A_RXN

F21

PCIE8_RXP/SATA1A_RXP

D21

PCIE8_TXN/SATA1A_TXN

C21

PCIE8_TXP/SATA1A_TXP

E22

PCIE9_RXN

E23

PCIE9_RXP

B23

PCIE9_TXN

A23

PCIE9_TXP

F25

PCIE10_RXN

E25

PCIE10_RXP

D23

PCIE10_TXN

C23

PCIE10_TXP

F5

PCIE_RCOMPN

E5

PCIE_RCOMPP

D56

PROC_PRDY#

D61

PROC_PREQ#

BB11

GPP_A7/PIRQA#

E28

PCIE11_RXN/SATA1B_RXN

E27

PCIE11_RXP/SATA1B_RXP

D24

PCIE11_TXN/SATA1B_TXN

C24

PCIE11_TXP/SATA1B_TXP

E30

PCIE12_RXN/SATA2_RXN

F30

PCIE12_RXP/SATA2_RXP

A25

PCIE12_TXN/SATA2_TXN

B25

PCIE12_TXP/SATA2_TXP

BLL-U_BGA1356

K

8 OF 20

SSIC / USB3

USB3_2_RXN/SSIC_1_RXN
USB3_2_RXP/SSIC_1_RXP
USB3_2_TXN/SSIC_1_TXN

USB3_2_TXP/SSIC_1_TXP

USB3_3_RXN/SSIC_2_RXN
USB3_3_RXP/SSIC_2_RXP
USB3_3_TXN/SSIC_2_TXN

USB3_3_TXP/SSIC_2_TXP

USB2

USB2_VBUSSENSE

GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2

GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2

GPP_E8/SATALED#

USB3_1_RXN
USB3_1_RXP
USB3_1_TXN
USB3_1_TXP

USB3_4_RXN
USB3_4_RXP
USB3_4_TXN
USB3_4_TXP

USB2N_1
USB2P_1

USB2N_2
USB2P_2

USB2N_3
USB2P_3

USB2N_4
USB2P_4

USB2N_5
USB2P_5

USB2N_6
USB2P_6

USB2N_7
USB2P_7

USB2N_8
USB2P_8

USB2N_9
USB2P_9

USB2N_10
USB2P_10

USB2_COMP

USB2_ID

H8
G8
C13
D13

J6
H6
B13
A13

J10
H10
B15
A15

E10
F10
C15
D15

AB9
AB10

AD6
AD7

AH3
AJ3

AD9
AD10

AJ1
AJ2

AF6
AF7

AH1
AH2

AF8
AF9

USB20_N9

AG1

USB20_P9

AG2

AH7
AH8

USB2_COMP

AB6

USB2_ID

AG3

USB2_VBUSSENSE

AG4

USB_OC0#

A9

USB_OC1#

C9

USB_OC2#

D9

USB_OC3#

B9

HDD_DEVSLP0

J1
J2

DEVSLP1
SSD_DEVSLP2

J3

SATA_GP0

H2

SATA_GP1

H3

WWAN_PE_DTCT#

G4

SOC_SATALED#

H1

WWAN_ PE_D TCT#

L

PCI E

H SAT A

USB3_PRX_DTX_N1 [ 42]
USB3_PRX_DTX_P1 [42]
USB3_PTX_DRX_N1 [ 42]
USB3_PTX_DRX_P1 [42]

USB3_PRX_DTX_N2 [ 47]
USB3_PRX_DTX_P2 [47]
USB3_PTX_DRX_N2 [ 47]
USB3_PTX_DRX_P2 [47]

USB3_PRX_DTX_N3 [ 33]

USB3_PRX_DTX_P3 [33]
USB3_PTX_DRX_N3 [ 33]
USB3_PTX_DRX_P3 [33]

USB3_PRX_DTX_N4 [ 34]
USB3_PRX_DTX_P4 [34]
USB3_PTX_DRX_N4 [ 34]
USB3_PTX_DRX_P4 [34]

USB20_N1 [42]

USB20_P1 [42]

USB20_N2 [47]

USB20_P2 [47]

USB20_N3 [33]

USB20_P3 [33]

USB20_N4 [34]

USB20_P4 [34]

USB20_N5 [35]

USB20_P5 [35]

USB20_N6 [36]

USB20_P6 [36]

USB20_N7 [19]

USB20_P7 [19]

USB20_N8 [28]

USB20_P8 [28]

T219 T P@
T220 T P@

USB20_N10 [36]

USB20_P10 [36]

1 2

R105 113_0402_1%

1 2

R56 0_0402_5%@

1 2

R57 1K_0402_5%

USB_OC0# [42]

USB_OC1# [33,34]

USB_OC2# [35]

HDD_DEVSLP0 [32]

T99 TP@

SSD_DEVSLP2 [ 29]

SATA_GP0 [10]

SATA_GP1 [10,37]

WWAN_PE_DTCT# [ 10,29]

SOC_SATALED# [32,43]

USB3_CONN (Rear)

USB3_Docking (LNV) / USB3_CONN (Right-1) (NEC)

USB3_CONN (Right-2)

USB3_CONN (Right-3)

USB3_CONN (Rear)

Docking (Lenovo) / U SB3_CONN (Right-1) (NEC)

USB3_CONN (Right-2)

USB3_CONN (Right-3)

USB3_CONN (Left)

FPR (Lenovo) / NFC FeliCa (NEC)

CAM

BT

NC

HUB

WWAN (Lenovo)

Express Card (Lenovo)

Smart Card (Lenovo)

USB_OC3#

USB_OC0#
USB_OC1#
USB_OC2#
SOC_SATALED#

HDD_DEVSLP0

X

1 2

R108 10K_0402_5%@

RP21

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

@

1 2

R113 10K_0402_5%

HDD

SSD

ODD

LIN-2

LIN-2

+3V_PRIM

+3V_PRIM

+3VS

+3VS

GPI O

USB_ OC0#

USB_ OC1#

USB_ OC2#

USB_ OC3#

DEVS LP0

DEVS LP1

DEVS LP2

A A

SATA _GP0

SATA _GP1

SATA _GP2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/03/21 2017/03/01

2016/03/21 2017/03/01

2016/03/21 2017/03/01

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Title

Title

Title

Size

Size

Size

C

C

C

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

DEVICE CONTROL

USB3#1 ,2

USB3#3 ,4

USB 3#5

NA

HDD

X

SSD

NA

ODD

WWAN_ PE_D TCT#

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

KBL ULT(7/12) PCIE,USB

KBL ULT(7/12) PCIE,USB

KBL ULT(7/12) PCIE,USB

Document Number Re v

Document Number Re v

Document Number Re v

LA-C422P

LA-C422P

LA-C422P

1

11 58Tuesday, November 15, 2016

11 58Tuesday, November 15, 2016

11 58Tuesday, November 15, 2016

1.0

1.0

1.0

5

4

3

2

1

+1.0V_PRIM TO +1.0V_VCCSTU

+5VALW +1.0V_PRIM

1U_0402_6.3V6K

1U_0402_6.3V6K

C37

C35

1

D D

1 2

EN_1.0V_VCCSTU

R114 30K_0402_5%

1 2

R115 0_0402_5%@

1 2

R255 0_0402_5%@

1

C328

0.1U_0201_10V6K

2

SYSON[45,46,50,52]

PM_SLP_S4#[5,9,45,46,52]

SLP_LAN#[9]

delay EN_1.0V_VCCSTU

C C

1

@

2

2

U6

1

VIN1

2

EN_1.0V_VCCSTU

+3VALW

1

C259

2

0.01U_0402_16V7K

1U_0402_6.3V6K

C41

1

@

2

VIN1

3

ON1

4

VBIAS

5

ON2

6

VIN2

7

VIN2

RT9740AGQW_TDFN14-11_2X3

VOUT1
VOUT1

VOUT2
VOUT2

GPAD

GND

CT1

CT2

14
13

12

11

10P_0402_50V8J

10

9

1000P_0402_50V7K

8

15

C38

C39

1 2

1 2

R578 0_0805_5%@

1 2

+3VALW TO VCC3GBE

0.5 A

+3VALW

@

1 2

0.1U_0201_10V6K

0.1U_0201_10V6K

1

1

C255

C254

2

2

R254 0_0805_5%

VCC3GBE

20 mil

22U_0603_6.3V6M

1

2

+1.0V_VCCSTU

JUMP6

@

2

112

JUMP_43X79

Follow 543977_SKL_PDDG_Rev0_91
CC95 10PF ->22us(Spec:<= 65us)

0.1U_0201_10V6K

1

C256

C257

2

Close to LAN chip

For Power consumption
M

easuremen t

+1.0V_PRIM +1.0V_PRIM_JP

B B

JUMP3

@

112

JUMP_43X79

Imax : 2.77 A

0.1U_0201_10V6K

SUSP#[37,45,46,52,53,54]

2

+5VALW

+1.0V_PRIM_JP

1U_0402_6.3V6K

1 2

1

C46

2

SUSP#

C45

@

R123 0_0402_5%@

2

1

+1.0V_PRIM

1

RF@

C343

2

U7

1

VIN1

2

VIN2

7

VIN thermal

3

VBIAS

4

ON

TPS22961DNYR_WSON8

68P_0402_50V8J

RF@

C344

VOUT

1

2

6

5

GND

1

RF@

C342

2

82P_0402_50V8J

RF request

+1.0VS_VCCSTG_IO

2.2U_0402_6.3V6M

1 2

R120 0_0402_5%@

1 2

R121 0_0805_5%@

0.04A

20 mil

3A

120 mil

+1.0VS_VCCSTG

+1.0VS_VCCIO

0.16 A

20 mil

0.1U_0201_10V6K

C36

1

2

VCC3GBE

0.5 A

20 mil

1

C40

0.1U_0201_10V6K

2

@

1 2

C42 0.1U_0201_10V6K

@

1 2

C47 0.1U_0201_10V6K

+1.2V_VDDQ

JUMP2

For Power consumption
Measuremen t

JUMP_43X79

+1.0VS_VCCSTG

+1.2V_VCCSFR_OC

+1.0V_VCCSFR

+1.2V_VDDQ_CPU

@

2

112

+1.2V_VDDQC

+1.0V_VCCST

+1.0V_VCCSTU +1.0V_VCCST

1 2

R118 0_0402_5%@

1 2

R122 0_0402_5%@

AU23
AU28
AU35
AU42

BB23
BB32
BB41
BB47
BB51

AM40

AL23

A18

A22

K20
K21

U1N

VDDQ_AU23
VDDQ_AU28
VDDQ_AU35
VDDQ_AU42
VDDQ_BB23
VDDQ_BB32
VDDQ_BB41
VDDQ_BB47
VDDQ_BB51

VDDQC

VCCST

VCCSTG_A22

VCCPLL_OC

VCCPLL_K20
VCCPLL_K21

K

BL-U_BGA1356

CPU POWER 3 OF 4

14 OF 20

PSC Side

1U_0402_6.3V6K

1

C43

2

1U_0402_6.3V6K

1

C48

2

VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO

VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA

VCCIO_SENSE
VSSIO_SENSE

VSSSA_SENSE
VCCSA_SENSE

+1.2V_VDDQ_CPU

+1.0VS_VCCIO

AK28
AK30
AL30
AL42
AM28
AM30
AM42

AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25
K27
K28
K30

AM23
AM22

H21
H20

VCCIO_SENSE
VSSIO_SENSE

VSSSA_SENSE
VCCSA_SENSE

1 2

R119 0_0402_5%@

+VCC_SA

+1.2V_VCCSFR_OC

BSC Side

1

C44

2

0.1U_0201_10V6K

+1.0VS_VCCSTG+1.0V_VCCSFR

BSC SidePSC Side

1U_0402_6.3V6K

1

2

T101TP@
T102TP@

VSSSA_SENSE [55]
VCCSA_SENSE [55]

C49

+1.0V_PRIM to +1.0VS_VCCSTG / +1.0VS_VCCIO

+1.0VS_VCCIO

1

2

A A

@

BSC Side PSC Side

10U_0603_6.3V6M

10U_0603_6.3V6M

1

C62

C61

2

@

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C63

2

@

1U_0402_6.3V6K

1

1

C64

C65

2

2

@

@

@

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

C66

C67

2

2

1U_0402_6.3V6K

1

C68

2

1U_0402_6.3V6K

1

1

C69

2

2

+1.2V_VDDQ_CPU

1 2

R124 0_0805_5%@

C70

+1.2V_VDDQC

BSC Side

1U_0402_6.3V6K

1

2

C50

68P_0402_50V8J

RF@

+1.2V_VDDQ_CPU

C444

+1.2V_VDDQ_CPU

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

68P_0402_50V8J
C468

RF@

2

2

1

C51

2

10U_0603_6.3V6M

1

1

C52

C53

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

C54

2

1

C55

2

2

BSC SidePSC Side

1U_0402_6.3V6K

10U_0603_6.3V6M

C56

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

C58

C57

2

2

1U_0402_6.3V6K

1

1

C59

C60

2

2

C58 Follow 543016_SKL_U_Y_PDG_0_9

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/03/21 2017/03/01

2016/03/21 2017/03/01

2016/03/21 2017/03/01

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

KBL ULT(8/12) Power

KBL ULT(8/12) Power

KBL ULT(8/12) Power

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

C

C

C

LA-C422P

LA-C422P

LA-C422P

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

1

12 58Tuesday, November 15, 2016

12 58Tuesday, November 15, 2016

12 58Tuesday, November 15, 2016

1.0

1.0

1.0

5

4

3

2

1

+1.0V_PRIM

1 2

R125 0_0603_5%@

D D

1 2

R130 0_0603_5%@

1 2

R135 0_0603_5%@

C C

1 2

R138 0_0805_5%@

Imax : 2.57A

1 2

R141 0_0402_5%@

1 2

B B

R144 0_0603_5%@

1 2

R148 0_0402_5%@

Follow 543016_SKL_U_Y_PDG_0_9

+1.0V_PRIM +3V_PRIM +1.8V_PRIM

22U_0603_6.3V6M

22U_0603_6.3V6M

C111

C112

1

1

A A

2

2

@

@

C113

1

2
@

+1.0V_CLK4_F100OC

1

@

2

22U_0603_6.3V6M

C114

1

2

@

+1.0V_APLL

22U_0603_6.3V6M

C72

C71

1

1

2

2

@

@

+1.0V_CLK5_F24NS

22U_0603_6.3V6M

C79

C78

1

1

2

2

@

@

22U_0603_6.3V6M

C84

C83

1

1

2

2

@

@

+1.0V_PRIM_CORE

1U_0402_6.3V6K

1

@

2

+1.0V_MPHYAON

1U_0402_6.3V6K

1

2

+1.0V_CLK6_24TBT

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C99

@

2

+1.0V_DTS

22U_0603_6.3V6M

1

2

@

+1.8V_PRIM

0.1U_0201_10V6K

22U_0603_6.3V6M

C510

1

+3V_PRIM

2

22U_0603_6.3V6M

22U_0603_6.3V6M

C89

C93

@

1 2

R126 0_0402_5%

1 2

R131 0_0603_5%@

1 2

R132 0_0402_5%@

1 2

R134 0_0402_5%@

1 2

R136 0_0402_5%@

1 2

R139 0_0402_5%@

1 2

R142 0_0402_5%@

+3V_1.8V_HDA

+3V_1.8V_PGPPA

+3V_SPI

+3V_PGPPB

1

@

2

+3V_PGPPC

1

@

2

1

2

1U_0402_6.3V6K

C85

1U_0402_6.3V6K

C90

R143 0_0402_5%@

1U_0402_6.3V6K

C94

C76

1

2

@

1 2

1 2

+3V_1.8V_PGPPA

1

RF@

C499

2

68P_0402_50V8J

R127 0_0603_5%@

1 2

R129 0_0402_5%@

1 2

R133 0_0603_5%@

1 2

R137 0_0603_5%@

RF@

C498

1

2

1

RF@

C497

2

82P_0402_50V8J

0.1U_0201_10V6K

2

C77
1U_0402_6.3V6K

1

@

+1.8V_PRIM

12

R1280_0402_5%

+1.8V_PRIM+3V_1.8V_PGPPD

RF request

+3V_PGPPE

22U_0603_6.3V6M

22U_0603_6.3V6M

C101

C102

1

1

C100

2

2

@

@

22U_0603_6.3V6M

22U_0603_6.3V6M

C115

C118

1

2

@

1 2

R145 0_0402_5%@

1 2

R526 0_0402_5%@

1 2

R147 0_0402_5%@

1U_0402_6.3V6K

1

@

2

1U_0402_6.3V6K

1

2

+3V_PRIM_RTC

1U_0402_6.3V6K

1

2

C103

1 2

R527 0_0402_5%@

C486

C110

1

C109

2

+3VS

1 2

R152 0_0402_5%@

+1.8V_PRIM+3V_1.8V_PGPPG

+3VALW

1 2

R153 0_0603_5%@

+3VS_PGPPA

+3VALW_DSW

Follow 543016_SKL_U_Y_PDG_0_9

+1.0V_PRIM +1.0V_PRIM

1

RF@

C390

0.1U_0201_10V6K

2

1

RF@

C346

2

68P_0402_50V8J

1

RF@

C345

2

82P_0402_50V8J

2.2U_0402_6.3V6M

RF request RF request

+1.0V_PRIM

1

RF@

C495

2

1

RF@

C496

2

68P_0402_50V8J

1

RF@

C488

2

82P_0402_50V8J

2.2U_0402_6.3V6M

RF request

5

4

3

+1.0V_AMPHYPLL+1.0V_MPHYPLL

0.088A

22U_0603_6.3V6M

22U_0603_6.3V6M

1U_0402_6.3V6K

1

C73

@

2

1U_0402_6.3V6K

1

2

+1.0VO_DSW +1.8V_PRIM

2.2U_0402_6.3V6M

RF@

C469

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C74

1

2

@

1

C86

2

@

1U_0402_6.3V6K

1

2

1

2

68P_0402_50V8J

1

2

@

+1.0V_APLLEBB

1

2

+1.0V_SRAM

1

@

2

+1.0V_MPHYGT

22U_0603_6.3V6M

C87

1

2

@

C95

PCH_PWR_EN[45,53]

SLP_SUS#[9,53]

EXT_PWR_GATE#[9]

RF@

C392

C75

1U_0402_6.3V6K

0.642A

1U_0402_6.3V6K

0.154A

C88

+1.0V_PRIM_CORE

+1.0VO_DSW

0.033A

1

2

+1.0V_MPHYAON

+1.0V_MPHYGT

C80

+1.0V_AMPHYPLL

+1.0V_APLL

+1.0V_PRIM

+3VALW_DSW

C82

22U_0603_6.3V6M

1

2

+3V_1.8V_HDA

+3V_SPI

+1.0V_SRAM

+3V_PRIM

+1.0V_PRIM

+1.0V_APLLEBB

+3V_PRIM +1.0V_PRIM

1U_0402_6.3V6K

82P_0402_50V8J

1U_0402_6.3V6K

1

C96

@

2

RC5 0_0402_5%@

RC4 0_0402_5%

R149 0_0402_5%

1

RF@

C391

2

2.2U_0402_6.3V6M

2016/03/21 2017/03/01

2016/03/21 2017/03/01

2016/03/21 2017/03/01

1U_0402_6.3V6K

1

C97

@

2

1 2

1 2

@

1 2

@

Compal Secret Data

Compal Secret Data

Compal Secret Data

+1.0V_PRIM

AB19
AB20

P18

AF18
AF19

V20
V21

AL1

K17

N15
N16
N17
P15
P16

K15
L15

V15

AB17

Y18

AD17
AD18

AJ17

AJ19

AJ16

AF20
AF21

T19
T20

AJ21

AK20

N18

C98

C104

1

@

2

Deciphered Date

Deciphered Date

Deciphered Date

2

U1O

VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0

VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE

DCPDSW_1P0

VCCMPHYAON_1P0

L1

VCCMPHYAON_1P0

VCCMPHYGT_1P0_N15
VCCMPHYGT_1P0_N16
VCCMPHYGT_1P0_N17
VCCMPHYGT_1P0_P15
VCCMPHYGT_1P0_P16

VCCAMPHYPLL_1P0
VCCAMPHYPLL_1P0

VCCAPLL_1P0

VCCPRIM_1P0_AB17
VCCPRIM_1P0_Y18

VCCDSW_3P3_AD17
VCCDSW_3P3_AD18
VCCDSW_3P3_AJ17

VCCHDA

VCCSPI

VCCSRAM_1P0
VCCSRAM_1P0
VCCSRAM_1P0
VCCSRAM_1P0

VCCPRIM_3P3_AJ21

VCCPRIM_1P0_AK20

VCCAPLLEBB

BL-U_BGA1356

K

RTC Battery

MAX. 8000mil

+RTCBATT

1U_0402_6.3V6K

@

EN_3V_PRIM

EXT_PWR_GATE#_R

+1.0V_PRIM

1

@

2

CPU POWER 4 OF 4

+3VALW TO +3V_PRIM

1U_0402_6.3V6K

C105

1

2

1U_0402_6.3V6K

C116

For Power consumption
Measuremen t

+1.0V_PRIM TO +1.0V_MPHYPLL

VCCPRIM_3P3_V19

VCCPRIM_1P0_T1

VCCATS_1P8

VCCRTCPRIM_3P3

VCCRTC_AK19
VCCRTC_BB14

GPP_B0/CORE_VID0
GPP_B1/CORE_VID1

15 OF 20

1 2

R140 0_0402_5%@

For Power consumption
Measuremen t

JUMP4

@

2

112

JUMP_43X79

U8

1

VOUT1

VIN1

2

VOUT1

VIN1

3

4

5

6
7

CT1

ON1

GND

VBIAS

ON2

CT2

VIN2

VOUT2

VIN2

VOUT2

GPAD

RT9740AGQW_TDFN14-11_2X3

@

JUMP5

@

112

JUMP_43X79

@

JUMP11

112

JUMP_43X39

Title

Title

Title

Size

Size

Size

C

C

C

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

AK15

VCCPGPPA

AG15

VCCPGPPB

Y16

VCCPGPPC

Y15

VCCPGPPD

T16

VCCPGPPE

AF16

VCCPGPPF

AD15

VCCPGPPG

V19

T1

AA1

AK17

AK19
BB14

BB10

DCPRTC

A14

VCCCLK1

K19

VCCCLK2

L21

VCCCLK3

N20

VCCCLK4

L19

VCCCLK5

A10

VCCCLK6

AN11
AN13

W=20 mils

1

C91

2

1U_0402_6.3V6K

+3V_PRIMJP

14
13

12

C107

11

1000P_0402_50V7K

10

C108

9

1000P_0402_50V7K

8

15

+1.0V_MPHYJP

2

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

KBL ULT(9/12) Power

KBL ULT(9/12) Power

KBL ULT(9/12) Power

Document Number Re v

Document Number Re v

Document Number Re v

LA-C422P

LA-C422P

LA-C422P

+3V_1.8V_PGPPA
+3V_PGPPB
+3V_PGPPC
+3V_1.8V_PGPPD
+3V_PGPPE
+1.8V_PRIM
+3V_1.8V_PGPPG

+3V_PRIM

+1.0V_DTS

+1.8V_PRIM

+3V_PRIM_RTC

+3VL_RTC

1 2

C81 0.1U_0201_10V6K

+1.0V_CLK6_24TBT

+1.0V_APLL

+1.0V_CLK4_F100OC

+1.0V_CLK5_F24NS

+1.0V_CLK6_24TBT

PRIMCORE_VID0
PRIMCORE_VID1

+3VL_RTC

0.1U_0201_10V6K

C92

1

2

0.5 A

20 mil

R146
0_0805_5%

1 2

@

1 2

@

1 2

@

R150
0_0805_5%

1 2

@

1 A

40 mil

1

T103TP@
T104TP@

+3V_PRIM+3VALW+5VALW

0.1U_0201_10V6K

C106

1

@

2

+1.0V_MPHYPLL

1

C117

@

0.1U_0201_10V6K

2

13 58Tuesday, November 15, 2016

13 58Tuesday, November 15, 2016

13 58Tuesday, November 15, 2016

1.0

1.0

1.0

5

D D

4

3

2

1

U1L

A30
A34
A39

A44
AK33
AK35
AK37
AK38
AK40

AL33
AL37

AL40
AM32
AM33
AM35
AM37
AM38

G30

K32

AK32

AB62

C C

For CPU2+3e SKU

SVID ALERT

B B

SOC_SVID_ALERT#

R156 220_0402_5%

SVID DATA

SOC_SVID_DAT

A A

P62
V62

H63

G61

AC63
AE63

AE62
AG62

AL63

AJ62

+1.0V_VCCST

12

12

CRB : 43 ohm, PDG : 220 ohm?

+1.0V_VCCST

1 2

CPU POWER 1 OF 4

VCC_A30
VCC_A34
VCC_A39
VCC_A44
VCC_AK33
VCC_AK35
VCC_AK37
VCC_AK38
VCC_AK40
VCC_AL33
VCC_AL37
VCC_AL40
VCC_AM32
VCC_AM33
VCC_AM35
VCC_AM37
VCC_AM38
VCC_G30

RSVD_K32

RSVD_AK32

VCCOPC_AB62
VCCOPC_P62
VCCOPC_V62

VCC_OPC_1P8_H63

VCC_OPC_1P8_G61

VCCOPC_SENSE
VSSOPC_SENSE

VCCEOPIO
VCCEOPIO

VCCEOPIO_SENSE
VSSEOPIO_SENSE

K

BL-U_BGA1356

Place the PU
resistors close to CPU

R155
56_0402_5%

Place the PU
resistors close to CPU

R157

100_0402_1%

12 OF 20

SOC_SVID_ALERT#_R [55]

CRB : 110 ohm, PDG : NA

SOC_SVID_DAT [55]

VCC_G32
VCC_G33
VCC_G35
VCC_G37
VCC_G38
VCC_G40
VCC_G42

VCC_J30
VCC_J33
VCC_J37

VCC_J40
VCC_K33
VCC_K35
VCC_K37
VCC_K38
VCC_K40
VCC_K42
VCC_K43

VCC_SENSE

VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

VCCSTG_G20

G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43

E32
E33

B63
A63
D64

G20

(To VR)

(To VR)

SOC_SVID_ALERT#
SOC_SVID_CLK
SOC_SVID_DAT

PH at PWR side
Place close to CPU

Trace Length < 25 mils

VCCSENSE [55]

VSSSENSE [55]

SOC_SVID_CLK [55]

+1.0VS_VCCSTG

PH at PWR side
Place close to CPU

VCCGT_SENSE[55]
VSSGT_SENSE[55]

Trace Length < 25 mils

VCCGT_SENSE
VSSGT_SENSE

+VCC_GT +VCC_GT+VCC_CORE +VCC_CORE

+3VS +VCC_GT

+VCC_CORE +VCC_GT

+VCC_CORE +VCC_SA

+VCC_SA +1.0V_PRI M

AC64
AC65
AC66
AC67
AC68
AC69
AC70
AC71

AA63
AA64
AA66
AA67
AA69
AA70
AA71

A48
A53
A58
A62
A66

J43
J45
J46
J48
J50
J52
J53
J55
J56
J58
J60
K48
K50
K52
K53
K55
K56
K58
K60
L62
L63
L64
L65
L66
L67
L68
L69
L70

L71
M62
N63
N64
N66
N67
N69

J70

J69

U1M

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

VCCGT_SENSE
VSSGT_SENSE

K

BL-U_BGA1356

C502
33P_0402_50V8J@RF@

1 2

C503
33P_0402_50V8J@RF@

1 2

C504
33P_0402_50V8J@RF@

1 2

C505
33P_0402_50V8J@RF@

1 2

CPU POWER 2 OF 4

VCCGTX_AK42
VCCGTX_AK43
VCCGTX_AK45
VCCGTX_AK46
VCCGTX_AK48
VCCGTX_AK50
VCCGTX_AK52
VCCGTX_AK53
VCCGTX_AK55
VCCGTX_AK56
VCCGTX_AK58
VCCGTX_AK60
VCCGTX_AK70
VCCGTX_AL43
VCCGTX_AL46
VCCGTX_AL50
VCCGTX_AL53
VCCGTX_AL56

VCCGTX_AL60
VCCGTX_AM48
VCCGTX_AM50
VCCGTX_AM52
VCCGTX_AM53
VCCGTX_AM56
VCCGTX_AM58

VCCGTX_AU58

VCCGTX_AU63

VCCGTX_BB57

VCCGTX_BB66

VCCGTX_SENSE
VSSGTX_SENSE

13 OF 20

RF request

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62

AK42
AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL43
AL46
AL50
AL53
AL56
AL60
AM48
AM50
AM52
AM53
AM56
AM58
AU58
AU63
BB57
BB66

AK62
AL61

For CPU2+3e SKU

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/03/21 2017/03/01

2016/03/21 2017/03/01

2016/03/21 2017/03/01

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

KBL ULT(10/12) Power

KBL ULT(10/12) Power

KBL ULT(10/12) Power

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

C

C

C

LA-C422P

LA-C422P

LA-C422P

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

1

14 58Tuesday, November 15, 2016

14 58Tuesday, November 15, 2016

14 58Tuesday, November 15, 2016

1.0

1.0

1.0

5

D D

4

3

2

1

AT63
AT68
AT71
AU10
AU15
AU20
AU32
AU38

AV68
AV69
AV70

AV71
AW10
AW12
AW14
AW16
AW18
AW21
AW23
AW26
AW28
AW30
AW32
AW34
AW36
AW38
AW41
AW43
AW45
AW47
AW49
AW51
AW53
AW55
AW57

AW60
AW62
AW64
AW66

AY66

BA10

BA14

BA18

BA23

BA28

BA32

BA36

BA45

AV1

AW6

AW8

B10
B14
B18
B22
B30
B34
B39
B44
B48
B53
B58
B62
B66
B71
BA1

BA2

F68

U1Q

GND 2 OF 3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

K

BL-U_BGA1356

17 OF 20

U1R

GND 3 OF 3

BA49

VSS

BA53

VSS

BA57

VSS

BA6

VSS

BA62

VSS

BA66

VSS

BA71

VSS

BB18

VSS

BB26

VSS

BB30

VSS

BB34

VSS

BB38

VSS

BB43

VSS

BB55

VSS

BB6

VSS

BB60

VSS

BB64

VSS

BB67

VSS

BB70

VSS

C1

VSS

C25

VSS

C5

VSS

D10

VSS

D11

VSS

D14

VSS

D18

VSS

D22

VSS

D25

VSS

D26

VSS

D30

VSS

D34

VSS

D39

VSS

D44

VSS

D45

VSS

D47

VSS

D48

VSS

D53

VSS

D58

VSS

D6

VSS

D62

VSS

D66

VSS

D69

VSS

E11

VSS

E15

VSS

E18

VSS

E21

VSS

E46

VSS

E50

VSS

E53

VSS

E56

VSS

E6

VSS

E65

VSS

E71

VSS

F1

VSS

F13

VSS

F2

VSS

F22

VSS

F23

VSS

F27

VSS

F28

VSS

F32

VSS

F33

VSS

F35

VSS

F37

VSS

F38

VSS

F4

VSS

F40

VSS

F42

VSS

BA41

VSS

F8
G10
G22
G43
G45
G48

G5
G52
G55
G58

G6
G60
G63
G66
H15
H18
H71
J11
J13
J25
J28
J32
J35
J38
J42

J8
K16
K18
K22
K61
K63
K64
K65
K66
K67
K68
K70
K71
L11
L16
L17

KBL-U_BGA1356

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

18 OF 20

L18

VSS

L2

VSS

L20

VSS

L4

VSS

L8

VSS

N10

VSS

N13

VSS

N19

VSS

N21

VSS

N6

VSS

N65

VSS

N68

VSS

P17

VSS

P19

VSS

P20

VSS

P21

VSS

R13

VSS

R6

VSS

T15

VSS

T17

VSS

T18

VSS

T2

VSS

T21

VSS

T4

VSS

U10

VSS

U63

VSS

U64

VSS

U66

VSS

U67

VSS

U69

VSS

U70

VSS

V16

VSS

V17

VSS

V18

VSS

W13

VSS

W6

VSS

W9

VSS

Y17

VSS

Y19

VSS

Y20

VSS

Y21

VSS

U1P

GND 1 OF 3

A5

VSS

A67

VSS

A70

VSS

AA2

VSS

AA4

VSS

AA65

VSS

AA68

VSS

AB15

VSS

AB16

VSS

AB18

VSS

AB21

VSS

AB8

VSS

AD13

VSS

AD16

VSS

AD19

VSS

AD20

VSS

AD21

VSS

AD62

VSS

AD8

VSS

AE64

VSS

AE65

VSS

C C

B B

AE66
AE67
AE68
AE69

AF10
AF15
AF17

AF63
AG16
AG17
AG18
AG19
AG20
AG21
AG71
AH13

AH63
AH64
AH67

AJ15

AJ18

AJ20

AK11
AK16
AK18
AK21
AK22
AK27
AK63
AK68
AK69

AL28

AL32

AL35

AL38

AL45

AL48

AL52

AL55

AL58

AL64

AF1

AF2
AF4

AH6

AJ4

AK8

AL2

AL4

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

K

BL-U_BGA1356

16 OF 20

AL65

VSS

AL66

VSS

AM13

VSS

AM21

VSS

AM25

VSS

AM27

VSS

AM43

VSS

AM45

VSS

AM46

VSS

AM55

VSS

AM60

VSS

AM61

VSS

AM68

VSS

AM71

VSS

AM8

VSS

AN20

VSS

AN23

VSS

AN28

VSS

AN30

VSS

AN32

VSS

AN33

VSS

AN35

VSS

AN37

VSS

AN38

VSS

AN40

VSS

AN42

VSS

AN58

VSS

AN63

VSS

AP10

VSS

AP18

VSS

AP20

VSS

AP23

VSS

AP28

VSS

AP32

VSS

AP35

VSS

AP38

VSS

AP42

VSS

AP58

VSS

AP63

VSS

AP68

VSS

AP70

VSS

AR11

VSS

AR15

VSS

AR16

VSS

AR20

VSS

AR23

VSS

AR28

VSS

AR35

VSS

AR42

VSS

AR43

VSS

AR45

VSS

AR46

VSS

AR48

VSS

AR5

VSS

AR50

VSS

AR52

VSS

AR53

VSS

AR55

VSS

AR58

VSS

AR63

VSS

AR8

VSS

AT2

VSS

AT20

VSS

AT23

VSS

AT28

VSS

AT35

VSS

AT4

VSS

AT42

VSS

AT56

VSS

AT58

VSS

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/03/21 2017/03/01

2016/03/21 2017/03/01

2016/03/21 2017/03/01

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

KBL ULT(11/12) GND

KBL ULT(11/12) GND

KBL ULT(11/12) GND

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

C

C

C

LA-C422P

LA-C422P

LA-C422P

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

1

15 58Tuesday, November 15, 2016

15 58Tuesday, November 15, 2016

15 58Tuesday, November 15, 2016

1.0

1.0

1.0

5

D D

T222 TP@

CFG3[5]

T223 TP@
T224 TP@
T234 TP@

C C

XDP_ITP_PMODE[5]

T161 TP@

B B

@

1 2

CFG3

R529 1K_0402_1%

@

1 2

CFG9

R344 1K_0402_1%

CFG_RCOMP

1 2

R161 49.9_0402_1%

1 2

CFG4

R162 1K_0402_1%

4

CFG2
CFG3
CFG4
CFG5
CFG6
CFG7

CFG9

CFG_RCOMP

XDP_ITP_PMODE

AL25
AL27

BA70
BA68

E68
B67
D65
D67
E70
C68
D68
C67
F71
G69
F70
G68
H70
G71
H69
G70

E63
F63

E66
F66

E60

E8

AY2
AY1

D1
D3

K46
K45

C71
B70

F60

A52

J71
J68

F65
G65

F61
E61

U1S

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]

CFG[16]
CFG[17]

CFG[18]
CFG[19]

CFG_RCOMP

ITP_PMODE

RSVD_AY2
RSVD_AY1

RSVD_D1
RSVD_D3

RSVD_K46
RSVD_K45

RSVD_AL25
RSVD_AL27

RSVD_C71
RSVD_B70

RSVD_F60

RSVD_A52

RSVD_TP_BA70
RSVD_TP_BA68

RSVD_J71
RSVD_J68

VSS_F65
VSS_G65

RSVD_F61
RSVD_E61

K

BL-U_BGA1356

RESERVED SIGNALS-1

19 OF 20

RSVD_TP_BB68
RSVD_TP_BB69

RSVD_TP_AK13
RSVD_TP_AK12

RSVD_BB2
RSVD_BA3

RSVD_D5
RSVD_D4
RSVD_B2
RSVD_C2

RSVD_B3
RSVD_A3

RSVD_AW1

RSVD_E1
RSVD_E2

RSVD_BA4
RSVD_BB4

RSVD_A4
RSVD_C4

RSVD_A69
RSVD_B69

RSVD_AY3

RSVD_D71
RSVD_C70

RSVD_C54
RSVD_D54

VSS_AY71

ZVM#

RSVD_TP_AW71
RSVD_TP_AW70

MSM#

PROC_SELECT#

3

BB68
BB69

AK13
AK12

BB2
BA3

AU5

TP5

AT5

TP6

D5
D4
B2
C2

B3
A3

AW1

E1
E2

BA4
BB4

A4
C4

BB5

TP4

A69
B69

AY3

D71
C70

C54
D54

AY4

TP1

BB3

TP2

AY71
AR56

AW71
AW70

AP56
C64

CNL_N

1 2

R158 0_0402_5%@

1 2

R159 0_0402_5%@

R160 100K_0402_5%@

1 2

T117 T P@

T131 T P@

T157 T P@

+1.0V_VCCST

+1.0V_VCCST

1

C340

2

RF@

68P_0402_50V8J

For 2+3e Solution
P

M_ZVM#

PM_MSM#

AW69
AW68

AU56

AW48

C7
U12
U11
H11

2

U1T

RSVD_AW69
RSVD_AW68
RSVD_AU56
RSVD_AW48
RSVD_C7
RSVD_U12
RSVD_U11
RSVD_H11

KBL-U_BGA1356

SPARE

20 OF 20

RSVD_F6

RSVD_E3
RSVD_C11
RSVD_B11
RSVD_A11
RSVD_D12
RSVD_C12
RSVD_F52

1

F6
E3
C11
B11
A11
D12
C12
F52

Display Port Presence Strap

1 : Disabled; No Physical Display Port

CFG4

attached to Embedded Display Port

0 : Enabled; An external Display Port device is
connected to the Embedded Display Port

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION.THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS S HEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUTPRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2016/03/21 2017/03/01

2016/03/21 2017/03/01

2016/03/21 2017/03/01

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

KBL ULT(12/12) RSVD

KBL ULT(12/12) RSVD

KBL ULT(12/12) RSVD

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

C

C

C

LA-C422P

LA-C422P

LA-C422P

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

1

16 58Tuesday, November 15, 2016

16 58Tuesday, November 15, 2016

16 58Tuesday, November 15, 2016

1.0

1.0

1.0

5

Interleaved Memory

DDR_A_DQS#[0..7][6]

DDR_A_D[0..63][6]

DDR_A_DQS[0..7][6]

DDR_A_MA[0..16][6]

DDR_A_BA0[6]
DDR_A_BA1[6]
DDR_A_BG0[6]
DDR_A_BG1[6]
DDR_A_ACT#[6]
DDR_A_PARITY[6]

D D

C C

B B

DDR_A_ALERT#[6]

DDR_A_CLK0[6]
DDR_A_CLK#0[6]
DDR_A_CLK1[6]
DDR_A_CLK#1[6]

DDR_A_CKE0[6]
DDR_A_CKE1[6]
DDR_A_CS#0[6]
DDR_A_CS#1[6]

PCH_SMB_DATA[7,18,40]
PCH_SMB_CLK[7,18,40 ]

DDR_A_ODT0[6]
DDR_A_ODT1[6]

Layout Not e:
Place near JDIMM1

+1.2V_VDDQ

+1.2V_VDDQ

Layout Not e:
Place near JDIMM1.203,204

+0.6VS_VTT

+2.5V

DDR_A_BA0
DDR_A_BA1
DDR_A_BG0
DDR_A_BG1
DDR_A_ACT#
DDR_A_PARITY
DDR_A_ALERT#

DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1
DDR_A_CLK#1

DDR_A_CKE0
DDR_A_CKE1
DDR_A_CS#0
DDR_A_CS#1

PCH_SMB_DATA
PCH_SMB_CLK

DDR_A_ODT0
DDR_A_ODT1

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

C133

C132

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

@

C138

C139

1

1

1

2

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

C150

C151

@

2

2

Layout Not e:
Place near JDIMM1

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

1

C530

C531

2

2

2

@

@

1U_0402_6.3V6K

1

2

10U_0603_6.3V6M

C140

1U_0402_6.3V6K

1

2

1

C533

2

LIN-2

D/DQ Signals link to CPU

CMD Signals from CPU

Clock Signals from CPU

CTL Signals from CPU

SMBUS Signals link to CPU

ODT Signals to CH A

Note:
Check voltag e tolerance o f
VREF_DQ at the DIMM socke t

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C134

2

10U_0603_6.3V6M

C141

1

2

1

C152

@

2

1U_0402_6.3V6K

C532

@

1U_0402_6.3V6K

1

1

C135

C136

C137

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

@

C147

C146

C145

1

1

1

2

1U_0402_6.3V6K

C153

1

2

2

2

Layout Not e:
Place near JDIMM1

+3VS

2.2U_0402_6.3V6M

1

@

2

Layout Not e:
PLACE THE CAP WITHIN 200 MILS
FROM THE JDIMM1

+0.6V_DDRA_VREFCA

2.2U_0402_6.3V6M

1

2

1

2

C148

C154

C128

1U_0402_6.3V6K

1U_0402_6.3V6K

1

@

C529

C528

2

330U_D3_2.5VY_R6M

@

1

C142

+

2

0.1U_0201_10V6K

1

C155

2

0.1U_0201_10V6K

C129

1

2

4

+1.2V_VDDQ +1.2V_VDDQ

DDR_A_D5

DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D7

DDR_A_D3

DDR_A_D13

DDR_A_D9

DDR_A_D15

DDR_A_D10

DDR_A_D17 DDR_A_D16

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D23

DDR_A_D19

DDR_A_D29

DDR_A_D25

DDR_A_D26

DDR_A_CKE0

DDR_A_BG1 DDR_A_ACT#
DDR_A_BG0

DDR_A_MA12
DDR_A_MA9

DDR_A_MA3
DDR_A_MA1

DDR_A_CLK0
DDR_A_CLK#0

DDR_A_PARITY
DDR_A_BA1

DDR_A_CS#0
DDR_A_MA14

DDR_A_ODT0
DDR_A_CS#1

DDR_A_ODT1

DDR_A_D37

DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D38

DDR_A_D34

DDR_A_D44

DDR_A_D40

DDR_A_D46

DDR_A_D42 DDR_A_D43

DDR_A_D52

DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D55

DDR_A_D51

DDR_A_D61

DDR_A_D56

DDR_A_D58 DDR_A_D59

+3VS
+2.5V +0.6VS_VTT

JDIMM1

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99

101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
207
209
211
213
215
217
219
221
223
225
227
229
231
233
235
237
239
241
243
245
247
249
251
253
255
257
259
261

VSS1
DQ5
VSS3
DQ1
VSS5
DQS0_c
DQS0_t
VSS8
DQ7
VSS10
DQ3
VSS12
DQ13
VSS14
DQ9
VSS16
DM1_n/DBI_n
VSS17
DQ15
VSS19
DQ10
VSS21
DQ21
VSS23
DQ17
VSS25
DQS2_c
DQS2_t
VSS28
DQ23
VSS30
DQ19
VSS32
DQ29
VSS34
DQ25
VSS36
DM3_n/DBI3_n
VSS37
DQ30
VSS39
DQ26
VSS41
CB5/NC
VSS43
CB1/NC
VSS45
DQS8_c
DQS8_t
VSS48
CB2/NC
VSS50
CB3/NC
VSS52
CKE0
VDD1
BG1
BG0
VDD3
A12
A9
VDD5
A8
A6
VDD7
A3
A1
VDD9
CK0_t
CK0_c
VDD11
PARITY
BA1
VDD13
CS0_n
WE_n/A14
VDD15
ODT0
CS1_n
VDD17
ODT1
VDD19
C1, CS3_n,NC
VSS53
DQ37
VSS55
DQ33
VSS57
DQS4_c
DQS4_t
VSS60
DQ38
VSS62
DQ34
VSS64
DQ44
VSS66
DQ40
VSS68
DM5_n/DBI5_n
VSS69
DQ46
VSS71
DQ42
VSS73
DQ52
VSS75
DQ49
VSS77
DQS6_c
DQS6_t
VSS80
DQ55
VSS82
DQ51
VSS84
DQ61
VSS86
DQ56
VSS88
DM7_n/DBI7_n
VSS89
DQ62
VSS91
DQ58
VSS93
SCL
VDDSPD
VPP1
VPP2
GND1

3

DM0_n/DBI0_n

DQS1_c

DQS1_t

DM2_n/DBI2_n

DQS3_c

DQS3_t

CB4/NC

CB0/NC

DM8_n/DBI_n/NC

CB6/NC

CB7/NC

RESET_n

ALERT_n

EVENT_n/NF

VDD10

CK1_t/NF

CK1_c/NF

VDD12

A10/AP
VDD14

RAS_n/A16

VDD16

CAS_n/A15

VDD18

C0/CS2_n/NC

VREFCA

DM4_n/DBI4_n

DQS5_c

DQS5_t

DM6_n/DBI6_n

DQS7_c

DQS7_t

VSS11

VSS13

VSS15

VSS18

VSS20

VSS22

VSS24

VSS26

VSS27

VSS29

VSS31

VSS33

VSS35

VSS38

VSS40

VSS42

VSS44

VSS46

VSS47

VSS49

VSS51

ACT_n

VSS54

VSS56

VSS58

VSS59

VSS61

VSS63

VSS65

VSS67

VSS70

VSS72

VSS74

VSS76

VSS78

VSS79

VSS81

VSS83

VSS85

VSS87

VSS90

VSS92

VSS94

2

VSS2

4

DQ4

6

VSS4

8

DQ0

10

VSS6

12
14

VSS7

16

DQ6

18

VSS9

20

DQ2

22
24

DQ12

26
28

DQ8

30
32
34
36
38

DQ14

40
42

DQ11

44
46

DQ20

48
50

DQ16

52
54
56
58

DQ22

60
62

DQ18

64
66

DQ28

68
70

DQ24

72
74
76
78
80

DQ31

82
84

DQ27

86
88
90
92
94
96
98
100
102
104
106
108
110

CKE1

112

VDD2

114
116
118

VDD4

120

A11

122

A7

124

VDD6

126

A5

128

A4

130

VDD8

132

A2

134
136
138
140
142
144

A0

146
148
150

BA0

152
154
156
158

A13

160
162
164
166

SA2

168
170

DQ36

172
174

DQ32

176
178
180
182

DQ39

184
186

DQ35

188
190

DQ45

192
194

DQ41

196
198
200
202
204

DQ47

206
208

DQ43

210
212

DQ53

214
216

DQ48

218
220
222
224

DQ54

226
228

DQ50

230
232

DQ60

234
236

DQ57

238
240
242
244
246

DQ63

248
250

DQ59

252
254

SDA

256

SA0

258

VTT

260

SA1

262

GND2

DDR_A_D4

DDR_A_D0

DDR_A_D6

DDR_A_D2

DDR_A_D12

DDR_A_D8

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D14

DDR_A_D11

DDR_A_D20DDR_A_D21

DDR_A_D22

DDR_A_D18

DDR_A_D28

DDR_A_D24

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D31DDR_A_D30

DDR_A_D27

DDR_DRAMRST#
DDR_A_CKE1

DDR_A_ALERT#

DDR_A_MA11
DDR_A_MA7

DDR_A_MA5DDR_A_MA8
DDR_A_MA4DDR_A_MA6

DDR_A_MA2

DDR_A_CLK1
DDR_A_CLK#1

DDR_A_MA0
DDR_A_MA10

DDR_A_BA0
DDR_A_MA16

DDR_A_MA15
DDR_A_MA13

SA2_CHA_DIM1

DDR_A_D36

DDR_A_D32

DDR_A_D39

DDR_A_D35

DDR_A_D45

DDR_A_D41

DDR_A_DQS#5
DDR_A_DQS5

DDR_A_D47

DDR_A_D53

DDR_A_D48

DDR_A_D54

DDR_A_D50

DDR_A_D60

DDR_A_D57

DDR_A_DQS#7
DDR_A_DQS7

DDR_A_D63DDR_A_D62

PCH_SMB_DATAPCH_SMB_CLK
SA0_CHA_DIM1

SA1_CHA_DIM1

T225TP@

DDR_DRAMRST# [6,1 8]

1

C130
100P_0402 _50V8J

2

ESD@

CAD NOTE
PLACE THE CAP NEAR TO
DIMM RESET PIN

+0.6V_DDRA_VREFCA

2

1

Reverse Type

2-3A to 1 DIMMs/channel

+3VS +3VS +3 VS

12

@

12

CLOSE TO SODIMM

SPD ADDRESS FOR CHANNEL A :
WRITE ADDRESS: 0XA0
READ ADDRESS: 0XA1
SA0 = 0; SA1 = 0; SA2 = 0.
DDR4 POR OPERATING SPEED: 1867 MT/S
STRETCH GOAL IS 2133 MT/S

+1.2V_VDDQ

1

2

@

C527

0.1U_0201_1 0V6K

12

12

12

R554
0_0402_5%

R555
0_0402_5%

@

SA2_CHA_DIM1 SA1_CHA_DIM1 SA0_ CHA_DIM1

12

@

R553
0_0402_5%

R556
0_0402_5%

12

R558

@

0_0402_5%

12

R557
0_0402_5%

@

@

+1.2V_VDDQ

1

1

C560

C561

RF@

RF@

2

68P_0402_50V8J

1

C562

C563

RF@

RF@

2

2

68P_0402_50V8J

68P_0402_50V8J

68P_0402_50V8J

+1.2V_VDDQ

1

1

C564

C565

RF@

RF@

2

68P_0402_50V8J

DIMM1 Side CPU Side

1K_0402_1 %

+0.6V_DDRA_VREFCA +0 .6V_VREFCA

R169

1K_0402_1 %
R171

2

68P_0402_50V8J

1

2

C566

RF@

68P_0402_50V8J

1 2

R170
2_0402_1%

C526

0.1U_0201_1 0V6K

1

C567

RF@

2

68P_0402_50V8J

Place near to SO-DIMM connector.

1

2

1

2

1

C149

0.022U_0402 _16V7K

2

12

R172

24.9_0402 _1%

DEREN_40-4227 5-26002RHF

A A

Security Classification Compal Secret Data

Security Classification Compal Secret Data

Security Classification Compal Secret Data

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED T O ANY T HIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED T O ANY T HIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED T O ANY T HIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

2016/03/21 2017/03/01

2016/03/21 2017/03/01

2016/03/21 2017/03/01

2

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

DDR4_DIMMA

DDR4_DIMMA

DDR4_DIMMA

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

LA-C422P

LA-C422P

LA-C422P

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

17 58Tuesday, November 15, 2016

17 58Tuesday, November 15, 2016

17 58Tuesday, November 15, 2016

1.0

1.0

1.0

5

Interleaved Memory

DDR_B_DQS#[0..7][6]

DDR_B_D[0..63][6]

DDR_B_DQS[0..7][6]

DDR_B_MA[0..16][6]

DDR_B_BA0[6]
DDR_B_BA1[6]
DDR_B_BG0[6]
DDR_B_BG1[6]
DDR_B_ACT#[6]

D D

C C

B B

DDR_B_PARITY[6]
DDR_B_ALERT#[6]

DDR_B_CLK0[6]
DDR_B_CLK#0[ 6]
DDR_B_CLK1[6]
DDR_B_CLK#1[ 6]

DDR_B_CKE0[6]
DDR_B_CKE1[6]
DDR_B_CS#0[6]
DDR_B_CS#1[6]

PCH_SMB_DATA[7,17,40]
PCH_SMB_CLK[7,17,40]

DDR_B_ODT0[6]
DDR_B_ODT1[6]

Layout Note:
Place near JDIMM2

+1.2V_VDDQ

+1.2V_VDDQ

Layout Note:
Place near JDIMM2

+0.6VS_VTT

Layout Note:
Place near JDIMM1

+2.5V

DDR_B_BA0
DDR_B_BA1
DDR_B_BG0
DDR_B_BG1
DDR_B_ACT#
DDR_B_PARITY
DDR_B_ALERT#

DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK1
DDR_B_CLK#1

DDR_B_CKE0
DDR_B_CKE1
DDR_B_CS#0
DDR_B_CS#1

PCH_SMB_DATA
PCH_SMB_CLK

DDR_B_ODT0
DDR_B_ODT1

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

1

C160

2

10U_0603_6.3V6M

1

2

10U_0603_6.3V6M

1

2

10U_0603_6.3V6M

1

2

C162

C161

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

@

C166

C167

C168

1

1

2

2

1U_0402_6.3V6K

10U_0603_6.3V6M

1

C541

C542

1

C179

@

2

2

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

1

C543

C544

C546

2

2

2

LIN-2

D/DQ Signals link to CPU

CMD Signals from CPU

Clock Signals from CPU

CTL Signals from CPU

SMBUS Signals link to CPU

ODT Signals to CH B

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

C164

C163

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

@

C170

C169

1

1

2

2

Layout Note:
Place near JDIMM2

1U_0402_6.3V6K

1

C180

@

2

Layout Note:
PLACE T HE CAP WITHIN 20 0 MILS
FROM THE JDI MM2

C545

1U_0402_6.3V6K

1

1

C165

2

2

10U_0603_6.3V6M

C171

1

1

2

2

+3VS

1

2

+0.6V_DDRB_VREFCA

2.2U_0402_6.3V6M

1

C156

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C539

C540

2

10U_0603_6.3V6M

10U_0603_6.3V6M

330U_D3_2.5VY_R6M

1

@

C174

C172

C173

1

+

2

2

2.2U_0402_6.3V6M

0.1U_0201_10V6K

C181

1

@

C182

2

0.1U_0201_10V6K

1

C157

2

4

+1.2V_VDDQ +1.2V_VDDQ

DDR_B_D13

DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D15

DDR_B_D11

DDR_B_D5

DDR_B_D1

DDR_B_D7

DDR_B_D2

DDR_B_D21

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D23

DDR_B_D19

DDR_B_D29

DDR_B_D25

DDR_B_D30 DDR_B_D31

DDR_B_D26

DDR_B_CKE0

DDR_B_BG0

DDR_B_MA12
DDR_B_MA9

DDR_B_MA8
DDR_B_MA6 DDR_B_MA4

DDR_B_MA3
DDR_B_MA1

DDR_B_CLK0
DDR_B_CLK#0

DDR_B_PARITY
DDR_B_BA1

DDR_B_CS#0
DDR_B_MA14

DDR_B_ODT0
DDR_B_CS#1

DDR_B_ODT1

DDR_B_D37

DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D38

DDR_B_D34

DDR_B_D44

DDR_B_D40

DDR_B_D52

DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D55

DDR_B_D51

DDR_B_D61

DDR_B_D56

DDR_B_D62 DDR_B_D63

PCH_SMB_CLK

+3VS
+2.5V +0.6VS_VTT

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99

101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
207
209
211
213
215
217
219
221
223
225
227
229
231
233
235
237
239
241
243
245
247
249
251
253
255
257
259
261

JDIMM2

VSS1
DQ5
VSS3
DQ1
VSS5
DQS0_c
DQS0_t
VSS8
DQ7
VSS10
DQ3
VSS12
DQ13
VSS14
DQ9
VSS16
DM1_n/DBI_n
VSS17
DQ15
VSS19
DQ10
VSS21
DQ21
VSS23
DQ17
VSS25
DQS2_c
DQS2_t
VSS28
DQ23
VSS30
DQ19
VSS32
DQ29
VSS34
DQ25
VSS36
DM3_n/DBI3_n
VSS37
DQ30
VSS39
DQ26
VSS41
CB5/NC
VSS43
CB1/NC
VSS45
DQS8_c
DQS8_t
VSS48
CB2/NC
VSS50
CB3/NC
VSS52
CKE0
VDD1
BG1
BG0
VDD3
A12
A9
VDD5
A8
A6
VDD7
A3
A1
VDD9
CK0_t
CK0_c
VDD11
PARITY
BA1
VDD13
CS0_n
WE_n/A14
VDD15
ODT0
CS1_n
VDD17
ODT1
VDD19
C1, CS3_n,NC
VSS53
DQ37
VSS55
DQ33
VSS57
DQS4_c
DQS4_t
VSS60
DQ38
VSS62
DQ34
VSS64
DQ44
VSS66
DQ40
VSS68
DM5_n/DBI5_n
VSS69
DQ46
VSS71
DQ42
VSS73
DQ52
VSS75
DQ49
VSS77
DQS6_c
DQS6_t
VSS80
DQ55
VSS82
DQ51
VSS84
DQ61
VSS86
DQ56
VSS88
DM7_n/DBI7_n
VSS89
DQ62
VSS91
DQ58
VSS93
SCL
VDDSPD
VPP1
VPP2
GND1

3

DM0_n/DBI0_n

DQS1_c
DQS1_t

DM2_n/DBI2_n

DQS3_c
DQS3_t

CB4/NC

CB0/NC

DM8_n/DBI_n/NC

CB6/NC

CB7/NC

RESET_n

ALERT_n

EVENT_n/NF

VDD10
CK1_t/NF
CK1_c/NF

VDD12

A10/AP

VDD14

RAS_n/A16

VDD16

CAS_n/A15

VDD18

C0/CS2_n/NC

VREFCA

DM4_n/DBI4_n

DQS5_c
DQS5_t

DM6_n/DBI6_n

DQS7_c
DQS7_t

VSS11

VSS13

VSS15

VSS18

VSS20

VSS22

VSS24

VSS26

VSS27

VSS29

VSS31

VSS33

VSS35

VSS38

VSS40

VSS42

VSS44

VSS46

VSS47

VSS49

VSS51

ACT_n

VSS54

VSS56

VSS58

VSS59

VSS61

VSS63

VSS65

VSS67

VSS70

VSS72

VSS74

VSS76

VSS78

VSS79

VSS81

VSS83

VSS85

VSS87

VSS90

VSS92

VSS94

2

VSS2

4

DQ4

6

VSS4

8

DQ0

10

VSS6

12
14

VSS7

16

DQ6

18

VSS9

20

DQ2

22
24

DQ12

26
28

DQ8

30
32
34
36
38

DQ14

40
42

DQ11

44
46

DQ20

48
50

DQ16

52
54
56
58

DQ22

60
62

DQ18

64
66

DQ28

68
70

DQ24

72
74
76
78
80

DQ31

82
84

DQ27

86
88
90
92
94
96
98
100
102
104
106
108
110

CKE1

112

VDD2

114
116
118

VDD4

120

A11

122

A7

124

VDD6

126

A5

128

A4

130

VDD8

132

A2

134
136
138
140
142
144

A0

146
148
150

BA0

152
154
156
158

A13

160
162
164
166

SA2

168
170

DQ36

172
174

DQ32

176
178
180
182

DQ39

184
186

DQ35

188
190

DQ45

192
194

DQ41

196
198
200
202
204

DQ47

206
208

DQ43

210
212

DQ53

214
216

DQ48

218
220
222
224

DQ54

226
228

DQ50

230
232

DQ60

234
236

DQ57

238
240
242
244
246

DQ63

248
250

DQ59

252
254

SDA

256

SA0

258

VTT

260

SA1

262

GND2

DDR_B_D12

DDR_B_D8

DDR_B_D14

DDR_B_D10

DDR_B_D4

DDR_B_D0

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D6

DDR_B_D3

DDR_B_D20

DDR_B_D16DDR_B_D17

DDR_B_D22

DDR_B_D18

DDR_B_D28

DDR_B_D24

DDR_B_DQS#3
DDR_B_DQS3

DDR_B_D27

DDR_DRAMRST#
DDR_B_CKE1

DDR_B_ACT#DDR_B_BG1
DDR_B_ALERT#

DDR_B_MA11
DDR_B_MA7

DDR_B_MA5

DDR_B_MA2

DDR_B_CLK1
DDR_B_CLK#1

DDR_B_MA0
DDR_B_MA10

DDR_B_BA0
DDR_B_MA16

DDR_B_MA15
DDR_B_MA13

SA2_CHB_DIM2

DDR_B_D36

DDR_B_D32

DDR_B_D39

DDR_B_D35

DDR_B_D45

DDR_B_D41

DDR_B_DQS#5
DDR_B_DQS5

DDR_B_D47DDR_B_D46

DDR_B_D43DDR_B_D42

DDR_B_D53

DDR_B_D48

DDR_B_D54

DDR_B_D50

DDR_B_D60

DDR_B_D57

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D59DDR_B_D58

PCH_SMB_DATA
SA0_CHB_DIM2

SA1_CHB_DIM2

T226TP@

DDR_DRAMRST# [6,17]

1

C158
100P_0402_50V8J

2

ESD@

CAD NOTE
PLACE THE CAP NEAR TO
DIMM RESET PIN

+0.6V_DDRB_VREFCA

2

1

Reverse Type

2-3A to 1 DIMMs/channel

+3VS +3VS +3VS

12

@

SA2_CHB_DIM2 SA1_CHB_DIM2 SA0_CHB_DIM2

12

R560
0_0402_5%

R562
0_0402_5%

12

12

@

@

CLOSE TO SODIMM

SPD ADDRESS F OR CHANNEL B :
WRITE ADDRESS: 0 XA4
READ ADDRESS: 0XA3
SA0 = 0; SA1 = 1; SA2 = 0.
DDR4 POR OPERATING SPEED: 1867 MT/S
STRETCH GOAL IS 2133 MT/ S

+1.2V_VDDQ

1

2

@

1

2

C537

0.1U_0201_10V6K

C538

0.1U_0201_10V6K

12

1K_0402_1%

DIMM2 Side CPU Side

R175

+0.6V_DDRB_VREFCA

12

1K_0402_1%
R177

Place near to SO-DIMM connector.

R561
0_0402_5%

R559
0_0402_5%

@

1

C536

0.1U_0201_10V6K

2

R176
2_0402_1%

12

R564

@

0_0402_5%

12

R563
0_0402_5%

1 2

@

+0.6V_B_VREFDQ

1

C159

0.022U_0402_16V7K

2

12

R178

24.9_0402_1%

DEREN_40-42271-26002RHF

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRI ETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRI ETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRI ETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPALELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPALELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPALELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBE USED BY OR DISCLOSED T O ANYT HIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.

MAYBE USED BY OR DISCLOSED T O ANYT HIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.

5

4

3

MAYBE USED BY OR DISCLOSED T O ANYT HIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

2016/03/21 2017/03/01

2016/03/21 2017/03/01

2016/03/21 2017/03/01

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

DDR4_DIMMB

DDR4_DIMMB

DDR4_DIMMB

Size

Size

Size

Document N umber Rev

Document N umber Rev

Document N umber Rev

Custom

Custom

Custom

LA-C422P

LA-C422P

LA-C422P

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

18 58Tuesday, November 15, 2016

18 58Tuesday, November 15, 2016

18 58Tuesday, November 15, 2016

1.0

1.0

1.0