Lenovo Y720-15ACZ Schematic

A

1 1

B

C

D

E

LCFC Confidential

Allsparks 5B Project M/B Schematics Document

2 2

AMD FP4 Carrizo SOC with DDRIIIL

AMD Exo Pro A10/FX

2015-04-23

3 3

4 4

REV:0.3

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

A

B

2014/10/22

2014/10/22

2014/10/22

C

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2014/10/22

2014/10/22

2014/10/22

D

Title

Cover Page

Cover Page

Cover Page

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet of

Wednesday, April 29, 2015

Allsparks 5B

Allsparks 5B

Allsparks 5B

E

1 51

1 51

1 51

0.3

0.3

0.3

A

B

C

D

E

LCFC confidential

AMD Strato XT
M3 Package: 29mmX29mm

Page 18~24

1 1

VRAM 256*16

GDDR5*4/8 4GB/2GB

Page 14~22

PCI-Express
8x Gen3

PEG 0~7

Memory BUS (DDR3L)

1.35V DDR3L 1600 MT/s

DDR3L-SO-DIMM X2

Page 12,13

UP TO 8G x 2

HDMI Conn.

Page 26

eDP Conn

FHD

Page 25

Int. Camera

USB2.0 Port1

HDMI x4 Lane Port1

DP x2 Lane Port0

USB2.0 2x

AMD FP4 APU
Carrizo 35W

(Integrated FCH)

Int. Mic Conn

2 2

Page 23

USB 3.0 2x

USB 2.0 2x

USB2.0 1x

USB3.0 1x

SATA HDD

Page 33

SATA Port0

SATA Gen3

USB2.0 1x

USB Right

USB 2.0 Port5
USB 3.0 Port1

USB 2.0 Port6
USB 3.0 Port2

USB charger

TPS2546RTER

JUSB1

Page 32

JUSB2

USB Left

USB2.0 Port0

(Debug Port)

Cardreader Genesys
GL3215

USB3.0 Port0
USB2.0 Port4

JUSB3

SD/MMC SD4.0 Conn.

IO Board

BGA-968

SATA SSD

Page 30

RJ45 Conn.

3 3

Page 29

Subwoofer Conn

Page 27

Amplifiers

TPA3113D2PWPR

Page 27

LAN Realtek

RTL8111H-CG

Page 28

Realtek ALC3248

Page 34

SATA Port1

PCIe Port2/3

PCIe Port1

Codec

SATA Gen3

PCIe 2x

PCIe 1x

HD Audio

SPK Conn.

Page 34

Page 4~11

HP&Mic Combo Conn.

37mm*29mm

ITE IT8371-LQFP

Page 35

EC

USB 2.0 1x

PCIe 1x

SPI BUS

TPM
Z32H320TC

for reserve

Page 36

NGFF Card
WLAN&BT

Page 31

SPI ROM
8MB

Page 08

PCIe Port1
USB2.0 Port3

Sub-board

LED BOARD

IO Board

IO Board

4 4

A

B

Touch Pad Int.KBD

Page 36

Page 36

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

Thermal Sensor
F75303M

Page 31

LC Future Center Secret Data

LC Future Center Secret Data

2014/10/22

2014/10/22

2014/10/22

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

2014/10/22

2014/10/22

2014/10/22

Title

Title

Title

Block Diagram

Block Diagram

Block Diagram

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet of

Wednesday, April 29, 2015

Allsparks 5B

Allsparks 5B

Allsparks 5B

E

2 51

2 51

2 51

0.3

0.3

0.3

A

B

C

D

E

Voltage Rails

power
plane

1 1

State

S0

S3

2 2

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

( O --> Means ON , X --> Means OFF )

B+
(+20VSB)

+3VL

+5VLP

O

O

O

O

X

+5VALW

+3VALW
(+3VALW_APU)

+1.8VALW

+0.95VALW

+0.775VALW

+1.35V
(+VSYSMEM_APU)

O

O

O

X

O

X X

X

X X X

+5VS

+3VS

+1.8VS

+1.5VS

+0.95VS

+0.675VS

+APU_CORE

+APU_CORE_NB

+APU_GFX

+VGA_CORE

+3VGS

+1.8VGS

+1.35VGS

+0.95VGS

OO

X

X

STATE

S0 (Full ON)

S1 (Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

SLP_S3# SLP_S5# +VALW +V +VS Clock

HIGH HIGH

LOW

LOW LOW

USB Port Table for Carrzio

USB 3.0USB 2.0 Port

0

EHCI

xHCI

1
2
3
4
5
6
7

ON

ONONON ON

ON

HIGHHIGH

ON

HIGHLOW

LOW

3 External
USB Port

ON

ON

OFF

ON

OFF

LEFT USB (2.0) charge
Camera
N/A
Blue Tooth
Card Reader
Right USB (3.0)
Right USB (3.0)
N/A

ON

LOW

OFF

OFF

OFF

OFF

OFF

OFF

BOM Structure Table

PCIE PORT LIST

SMBUS Control Table

SOURCE

EC_SMB_CK1

EC_SMB_DA1

3 3

EC_SMB_CK2

EC_SMB_DA2

APU_SMB_CLK
APU_SMB_DATA

IT8371D

+3VALW

IT8371D

+3VS

APU

+3VS

EC SM Bus1 address

Device

Battery

Charger

GPU BATT SODIMM WLAN Thermal

X

V

+3VS_VGA

X

X X X X

X

X

V V

EC SM Bus2 address

Address

0X16 1001_100xb

0001 0010 b

Device

Thermal Sensor

GPU

APU Thermal Diode

Address

0x41(default)

TBU

Sensor

X

X

APUIT8371DX

Charger

XV

V

X

V

APU_SIC
APU_SID

1.8VS for CZ
3VS for CZL

TP

V

X

X

X

X

V

Port Device

0

GPP

1
2
3
0

GFX

1
2
3
4
5
6
7

LAN
WLAN

SSD

STRATO
GPU

VRAM

Board ID need to be update!

BOARD
Config.

@
ME@
EMC@
RF@
PX@
PSSD@
SSD@
CHA@
CHB@
DXMIRROR@
NOMIRROR@
8586@
NOBACO@
BACO@
CD@
REV@
TPM@
EMC_NS@
RF_NS@
AOAC@
HDT@
8371@

S2G@
M2G@
H2G@
S1G@
M1G@
H1G@

GPIOxx GPIOxx Function

0 0

BTO ItemBOM Structure

Not stuff

Connector

EMC Part

RF Part

Discrete GPU SKU part

PCIE BUS NGFF SSD

SATA BUS NGFF SSD

VRAM channel A

VRAM channel B

IT8371DX for MIRROR

IT8371/8586 for noMIRROR

IT8586

GPU WITHOUT BACO FUNCTION

GPU WITH BACO FUNCTION

COST DOWN PROPOSAL

RESERVE FOR DEBUG

RESERVE FOR TPM FUNCTION

EMC reserve Part

RF reserve Part

AOAC support part

HDT Debug part

IT8371

X76 SAMSUNG 2G

X76 MICRON 2G

X76 HYNIX 2G

X76 SAMSUNG 1G

X76 MICRON 1G

X76 HYNIX 2G

GPIOxx

0

APU SM Bus address

4 4

Device Address

DDR DIMMA

DDR DIMMB

WLAN

TP

1001 000Xb

1001 010Xb

RSVD

RSVD

A

B

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

2014/10/22

2014/10/22

2014/10/22

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

2014/10/22

2014/10/22

2014/10/22

Title

Title

Title

Notes List

Notes List

Notes List

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet of

Wednesday, April 29, 2015

Allsparks 5B

Allsparks 5B

Allsparks 5B

E

3 51

3 51

3 51

0.3

0.3

0.3

5

D D

PCIE_PRX_DTX_P028

LAN

WLAN

C C

+0.95VS

GPU

B B

PCIE_PRX_DTX_N028

PCIE_PRX_DTX_P130
PCIE_PRX_DTX_N130

PCIE_PRX_DTX_P230
PCIE_PRX_DTX_N230

PCIE_PRX_DTX_P330
PCIE_PRX_DTX_N330

1 2

RC1 196_0402_1%

PCIE_CRX_GTX_P015
PCIE_CRX_GTX_N015

PCIE_CRX_GTX_P115
PCIE_CRX_GTX_N115

PCIE_CRX_GTX_P215
PCIE_CRX_GTX_N215

PCIE_CRX_GTX_P315
PCIE_CRX_GTX_N315

PCIE_CRX_GTX_P415
PCIE_CRX_GTX_N415

PCIE_CRX_GTX_P515
PCIE_CRX_GTX_N515

PCIE_CRX_GTX_P615
PCIE_CRX_GTX_N615

PCIE_CRX_GTX_P715
PCIE_CRX_GTX_N715

4

PCIE_PRX_DTX_P0
PCIE_PRX_DTX_N0

PCIE_PRX_DTX_P1
PCIE_PRX_DTX_N1

PCIE_PRX_DTX_P2
PCIE_PRX_DTX_N2

PCIE_PRX_DTX_N3

P_TX_ZVDD

PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0

PCIE_CRX_GTX_P1
PCIE_CRX_GTX_N1

PCIE_CRX_GTX_P2
PCIE_CRX_GTX_N2

PCIE_CRX_GTX_P3
PCIE_CRX_GTX_N3

PCIE_CRX_GTX_P4
PCIE_CRX_GTX_N4

PCIE_CRX_GTX_P5
PCIE_CRX_GTX_N5

PCIE_CRX_GTX_P6
PCIE_CRX_GTX_N6

PCIE_CRX_GTX_P7
PCIE_CRX_GTX_N7

U10

P10

L10

U9

T6
T5

T9
T8

P7
P6

U7

P9

N6
N5

N9
N8

L7
L6

L9

K6
K5

K9
K8

J7
J6

P_GPP_RXP0
P_GPP_RXN0

P_GPP_RXP1
P_GPP_RXN1

P_GPP_RXP2
P_GPP_RXN2

P_GPP_RXP3
P_GPP_RXN3

P_ZVDDP

P_GFX_RXP0
P_GFX_RXN0

P_GFX_RXP1
P_GFX_RXN1

P_GFX_RXP2
P_GFX_RXN2

P_GFX_RXP3
P_GFX_RXN3

P_GFX_RXP4
P_GFX_RXN4

P_GFX_RXP5
P_GFX_RXN5

P_GFX_RXP6
P_GFX_RXN6

P_GFX_RXP7
P_GFX_RXN7

CPU@

UC1B

PCIE

P_GPP_TXP0
P_GPP_TXN0

P_GPP_TXP1
P_GPP_TXN1

P_GPP_TXP2
P_GPP_TXN2

P_GPP_TXP3
P_GPP_TXN3

P_ZVSS/P_RX_ZVDDP

P_GFX_TXP0
P_GFX_TXN0

P_GFX_TXP1
P_GFX_TXN1

P_GFX_TXP2
P_GFX_TXN2

P_GFX_TXP3
P_GFX_TXN3

P_GFX_TXP4
P_GFX_TXN4

P_GFX_TXP5
P_GFX_TXN5

P_GFX_TXP6
P_GFX_TXN6

P_GFX_TXP7
P_GFX_TXN7

FP4 REV 0.93

AMD-CARRIZO_FP4-BGA968

3

R1
R2

R4
R3

N1
N2

N4
N3

U6

M2
M1

L1
L2

L4
L3

J1
J2

J4
J3

H2
H1

G1
G2

G4
G3

PCIE_PTX_DRX_P0
PCIE_PTX_DRX_N0

PCIE_PTX_DRX_P1
PCIE_PTX_DRX_N1

PCIE_PTX_DRX_P2
PCIE_PTX_DRX_N2

PCIE_PTX_DRX_P3
PCIE_PTX_DRX_N3

P_RX_ZVDD

PCIE_CTX_GRX_P0
PCIE_CTX_GRX_N0

PCIE_CTX_GRX_P1
PCIE_CTX_GRX_N1

PCIE_CTX_GRX_P2
PCIE_CTX_GRX_N2

PCIE_CTX_GRX_P3
PCIE_CTX_GRX_N3

PCIE_CTX_GRX_P4
PCIE_CTX_GRX_N4

PCIE_CTX_GRX_P5
PCIE_CTX_GRX_N5

PCIE_CTX_GRX_P6
PCIE_CTX_GRX_N6

PCIE_CTX_GRX_P7
PCIE_CTX_GRX_N7

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

2

CC130.1U_0402_10V6-K
CC131.1U_0402_10V6-K

CC1.1U_0402_10V6-K
CC2.1U_0402_10V6-K

CC1320.22U_0402_16V6-K PSSD@
CC1330.22U_0402_16V6-K PSSD@

CC1340.22U_0402_16V6-K PSSD@
CC1350.22U_0402_16V6-K PSSD@

RC3196_0402_1%

CC1360.22U_0402_16V6-K PX@
CC1370.22U_0402_16V6-K PX@

CC1380.22U_0402_16V6-K PX@
CC1390.22U_0402_16V6-K PX@

CC1400.22U_0402_16V6-K PX@
CC1410.22U_0402_16V6-K PX@

CC1420.22U_0402_16V6-K PX@
CC1430.22U_0402_16V6-K PX@

CC1440.22U_0402_16V6-K PX@
CC1450.22U_0402_16V6-K PX@

CC1460.22U_0402_16V6-K PX@
CC1470.22U_0402_16V6-K PX@

CC1480.22U_0402_16V6-K PX@
CC1490.22U_0402_16V6-K PX@

CC1500.22U_0402_16V6-K PX@
CC1510.22U_0402_16V6-K PX@

PCIE_PTX_C_DRX_P0
PCIE_PTX_C_DRX_N0

PCIE_PTX_C_DRX_P1
PCIE_PTX_C_DRX_N1

PCIE_PTX_C_DRX_P2
PCIE_PTX_C_DRX_N2

PCIE_PTX_C_DRX_P3PCIE_PRX_DTX_P3
PCIE_PTX_C_DRX_N3

PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_N0

PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_N1

PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_N2

PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_N3

PCIE_CTX_C_GRX_P4
PCIE_CTX_C_GRX_N4

PCIE_CTX_C_GRX_P5
PCIE_CTX_C_GRX_N5

PCIE_CTX_C_GRX_P6
PCIE_CTX_C_GRX_N6

PCIE_CTX_C_GRX_P7
PCIE_CTX_C_GRX_N7

PCIE_PTX_C_DRX_P0 28
PCIE_PTX_C_DRX_N0 28

PCIE_PTX_C_DRX_P1 30
PCIE_PTX_C_DRX_N1 30

PCIE_PTX_C_DRX_P2 30
PCIE_PTX_C_DRX_N2 30

PCIE_PTX_C_DRX_P3 30
PCIE_PTX_C_DRX_N3 30

For SSD PCIE GEN3,Coupling CAP need 220nF

PCIE_CTX_C_GRX_P0 15
PCIE_CTX_C_GRX_N0 15

PCIE_CTX_C_GRX_P1 15
PCIE_CTX_C_GRX_N1 15

PCIE_CTX_C_GRX_P2 15
PCIE_CTX_C_GRX_N2 15

PCIE_CTX_C_GRX_P3 15
PCIE_CTX_C_GRX_N3 15

PCIE_CTX_C_GRX_P4 15
PCIE_CTX_C_GRX_N4 15

PCIE_CTX_C_GRX_P5 15
PCIE_CTX_C_GRX_N5 15

PCIE_CTX_C_GRX_P6 15
PCIE_CTX_C_GRX_N6 15

PCIE_CTX_C_GRX_P7 15
PCIE_CTX_C_GRX_N7 15

1

LAN

WLAN

SSDSSD

GPU

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2013/08/15

2013/08/15

2013/08/15

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2013/08/15

2013/08/15

2013/08/15

2

Title

FP4 (PCIE I/F)

FP4 (PCIE I/F)

FP4 (PCIE I/F)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Allsparks 5B

Allsparks 5B

Allsparks 5B

4 51

4 51

4 51

1

0.3

0.3

0.3

5

4

3

2

1

DDRA_DQ[0..63]

DDRA_DQS[0..7]

DDRA_DQS#[0..7]

DDRA_MA[0..15]

DDRA_DM[0..7]

D D

DDRA_MA0

AE28

DDRA_MA1
DDRA_MA2
DDRA_MA3
DDRA_MA4
DDRA_MA5
DDRA_MA6
DDRA_MA7
DDRA_MA8
DDRA_MA9
DDRA_MA10
DDRA_MA11
DDRA_MA12
DDRA_MA13
DDRA_MA14
DDRA_MA15

DDRA_BS0#12
DDRA_BS1#12
DDRA_BS2#12

C C

DDRA_CLK012
DDRA_CLK0#12
DDRA_CLK112
DDRA_CLK1#12

MEM_MA_RST#12
MEM_MA_EVENT#12

DDRA_CKE012
DDRA_CKE112

DDRA_ODT012

B B

DDRA_ODT112

DDRA_CS0#12
DDRA_CS1#12

DDRA_RAS#12
DDRA_CAS#12
DDRA_WE#12

APU_MA_VREFDQ12

DDRA_BS0#
DDRA_BS1#
DDRA_BS2#

DDRA_DM0
DDRA_DM1
DDRA_DM2
DDRA_DM3
DDRA_DM4
DDRA_DM5
DDRA_DM6
DDRA_DM7

DDRA_DQS0
DDRA_DQS#0
DDRA_DQS1
DDRA_DQS#1
DDRA_DQS2
DDRA_DQS#2
DDRA_DQS3
DDRA_DQS#3
DDRA_DQS4
DDRA_DQS#4
DDRA_DQS5
DDRA_DQS#5
DDRA_DQS6
DDRA_DQS#6
DDRA_DQS7
DDRA_DQS#7

DDRA_CLK0
DDRA_CLK0#
DDRA_CLK1
DDRA_CLK1#

MEM_MA_RST#
MEM_MA_EVENT#

DDRA_CKE0
DDRA_CKE1

DDRA_ODT0
DDRA_ODT1

DDRA_CS0#
DDRA_CS1#

DDRA_RAS#
DDRA_CAS#
DDRA_WE#

APU_MA_VREFDQ
+MEM_VREF

MA_ADD0

Y27

MA_ADD1

Y29

MA_ADD2

Y26

MA_ADD3

W28

MA_ADD4

W29

MA_ADD5

W26

MA_ADD6

U29

MA_ADD7

W25

MA_ADD8

U26

MA_ADD9

AG29

MA_ADD10

U27

MA_ADD11

T28

MA_ADD12

AK26

MA_ADD13

T26

MA_ADD14/MA_BG1

T25

MA_ADD15/MA_ACT_L

AG26

MA_BANK0

AG27

MA_BANK1

T29

MA_BANK2/MA_BG0

E19

MA_DM0

D21

MA_DM1

K21

MA_DM2

F29

MA_DM3

AP28

MA_DM4

AV26

MA_DM5

AR22

MA_DM6

BC22

MA_DM7

K29

MA_DM8

H19

MA_DQS_H0

G19

MA_DQS_L0

B22

MA_DQS_H1

A22

MA_DQS_L1

F23

MA_DQS_H2

E23

MA_DQS_L2

G27

MA_DQS_H3

F27

MA_DQS_L3

AP25

MA_DQS_H4

AP26

MA_DQS_L4

AW27

MA_DQS_H5

AV27

MA_DQS_L5

AV22

MA_DQS_H6

AU22

MA_DQS_L6

BA21

MA_DQS_H7

AY21

MA_DQS_L7

L27

MA_DQS_H8

L26

MA_DQS_L8

AE25

MA_CLK_H0

AE26

MA_CLK_L0

AD26

MA_CLK_H1

AD27

MA_CLK_L1

AB28

MA_CLK_H2

AB29

MA_CLK_L2

AB25

MA_CLK_H3

AB26

MA_CLK_L3

N29

MA_RESET_L

AE29

MA_EVENT_L

P27

MA_CKE0

P29

MA_CKE1

AK27

MA0_ODT0

AL26

MA0_ODT1

AH25

MA1_ODT0

AL25

MA1_ODT1

AH26

MA0_CS_L0

AL29

MA0_CS_L1

AH29

MA1_CS_L0

AL28

MA1_CS_L1

AG24

MA_RAS_L/MA_RAS_L_ADD16

AK29

MA_CAS_L/MA_CAS_L_ADD15

AH28

MA_WE_L/MA_WE_L_ADD14

B19

MA_VREFDQ

T32

M_VREF

CPU@

UC1A

MEMORY A

MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15

MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23

MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31

MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39

MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47

MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55

MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63

MA_CHECK0
MA_CHECK1
MA_CHECK2
MA_CHECK3
MA_CHECK4
MA_CHECK5
MA_CHECK6
MA_CHECK7

MA_ZVDDIO_MEM_S

FP4 REV 0.93

AMD-CARRIZO_FP4-BGA968

MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7

MA_DATA8
MA_DATA9

H17
J17
F20
H20
E17
F17
K18
E20

A21
C21
C23
D23
B20
B21
B23
A23

G22
H22
E25
G25
J20
E22
H23
J23

F26
E27
J26
J27
H25
E26
G28
G29

AN26
AP29
AR26
AP24
AN29
AN27
AR29
AR27

AU26
AV29
AU25
AW25
AU29
AU28
AW26
AT25

AV23
AW23
AV20
AW20
AR23
AT23
AR20
AT20

BB23
BB22
BB20
AY19
BA23
BC23
BC21
BB21

K26
K28
N26
N28
J29
K25
L29
N25

AD29

DDRA_DQ0
DDRA_DQ1
DDRA_DQ2
DDRA_DQ3
DDRA_DQ4
DDRA_DQ5
DDRA_DQ6
DDRA_DQ7

DDRA_DQ8
DDRA_DQ9
DDRA_DQ10
DDRA_DQ11
DDRA_DQ12
DDRA_DQ13
DDRA_DQ14
DDRA_DQ15

DDRA_DQ16
DDRA_DQ17
DDRA_DQ18
DDRA_DQ19
DDRA_DQ20
DDRA_DQ21
DDRA_DQ22
DDRA_DQ23

DDRA_DQ24
DDRA_DQ25
DDRA_DQ26
DDRA_DQ27
DDRA_DQ28
DDRA_DQ29
DDRA_DQ30
DDRA_DQ31

DDRA_DQ32
DDRA_DQ33
DDRA_DQ34
DDRA_DQ35
DDRA_DQ36
DDRA_DQ37
DDRA_DQ38
DDRA_DQ39

DDRA_DQ40
DDRA_DQ41
DDRA_DQ42
DDRA_DQ43
DDRA_DQ44
DDRA_DQ45
DDRA_DQ46
DDRA_DQ47

DDRA_DQ48
DDRA_DQ49
DDRA_DQ50
DDRA_DQ51
DDRA_DQ52
DDRA_DQ53
DDRA_DQ54
DDRA_DQ55

DDRA_DQ56
DDRA_DQ57
DDRA_DQ58
DDRA_DQ59
DDRA_DQ60
DDRA_DQ61
DDRA_DQ62
DDRA_DQ63

MA_ZVDDIO

1 2

RC4 39.2_0402_1%

DDRA_DQ[0..63] 12

DDRA_DQS[0..7] 12

DDRA_DQS#[0..7] 12

DDRA_MA[0..15] 12

DDRA_DM[0..7] 12

+1.35V

DDRB_MA[15..0]13

DDRB_BS0#13
DDRB_BS1#13
DDRB_BS2#13

DDRB_DM[7..0]13

DDRB_CLK013
DDRB_CLK0#13
DDRB_CLK113
DDRB_CLK1#13

MEM_MB_RST#13

MEM_MB_EVENT#13

DDRB_CKE013
DDRB_CKE113

DDRB_ODT013
DDRB_ODT113

DDRB_CS0#13
DDRB_CS1#13

DDRB_RAS#13
DDRB_CAS#13
DDRB_WE#13

APU_MB_VREFDQ13

DDRB_MA0
DDRB_MA1
DDRB_MA2
DDRB_MA3
DDRB_MA4
DDRB_MA5
DDRB_MA6
DDRB_MA7
DDRB_MA8
DDRB_MA9
DDRB_MA10
DDRB_MA11
DDRB_MA12
DDRB_MA13
DDRB_MA14
DDRB_MA15

DDRB_BS0#
DDRB_BS1#
DDRB_BS2#

DDRB_DM0
DDRB_DM1
DDRB_DM2
DDRB_DM3
DDRB_DM4
DDRB_DM5
DDRB_DM6
DDRB_DM7

DDRB_DQS0
DDRB_DQS#0
DDRB_DQS1
DDRB_DQS#1
DDRB_DQS2
DDRB_DQS#2
DDRB_DQS3
DDRB_DQS#3
DDRB_DQS4
DDRB_DQS#4
DDRB_DQS5
DDRB_DQS#5
DDRB_DQS6
DDRB_DQS#6
DDRB_DQS7
DDRB_DQS#7

DDRB_CLK0
DDRB_CLK0#
DDRB_CLK1
DDRB_CLK1#

MEM_MB_RST#
MEM_MB_EVENT#

DDRB_CKE0
DDRB_CKE1

DDRB_ODT0
DDRB_ODT1

DDRB_CS0#
DDRB_CS1#

DDRB_RAS#
DDRB_CAS#
DDRB_WE#

APU_MB_VREFDQ

AG31
AC30
AC31
AB32
AA32
AA33
AA31

AA30

AG32

AL31

AH32
AG33

AR30

AW30

BC30
BC26

AR32

AR33
AW32
AW33

BA29

AY29

BA25

AY25

AE33

AE32

AE30

AE31

AD32

AD33

AC33

AC32

AG30

AL30

AM32

AJ32

AM33

AJ33

AL32

AJ30

AL33

AH33

AK32

W32

W33

W30

W31

AJ31

DDRB_DQS[0..7]

DDRB_DQS#[0..7]

MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6

Y33

MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10

Y32

MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14/MB_BG1

V32

MB_ADD15/MB_ACT_L

MB_BANK0
MB_BANK1
MB_BANK2/MB_BG0

D25

MB_DM0

D29

MB_DM1

E33

MB_DM2

J33

MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7

N33

MB_DM8

B26

MB_DQS_H0

A26

MB_DQS_L0

B30

MB_DQS_H1

A30

MB_DQS_L1

F32

MB_DQS_H2

E32

MB_DQS_L2

K32

MB_DQS_H3

J32

MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7

P32

MB_DQS_H8

N32

MB_DQS_L8

MB_CLK_H0
MB_CLK_L0
MB_CLK_H1
MB_CLK_L1
MB_CLK_H2
MB_CLK_L2
MB_CLK_H3
MB_CLK_L3

T33

MB_RESET_L
MB_EVENT_L

U32

MB_CKE0

U33

MB_CKE1

MB0_ODT0
MB0_ODT1
MB1_ODT0
MB1_ODT1

MB0_CS_L0
MB0_CS_L1
MB1_CS_L0
MB1_CS_L1

MB_RAS_L/MB_RAS_L_ADD16
MB_CAS_L/MB_CAS_L_ADD15
MB_WE_L/MB_WE_L_ADD14

A19

MB_VREFDQ

CPU@

UC1I

MEMORY B

MB_ZVDDIO_MEM_S

FP4 REV 0.93

AMD-CARRIZO_FP4-BGA968

MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7

MB_DATA8

MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15

MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23

MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31

MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39

MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47

MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55

MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63

MB_CHECK0
MB_CHECK1
MB_CHECK2
MB_CHECK3
MB_CHECK4
MB_CHECK5
MB_CHECK6
MB_CHECK7

DDRB_DQS[0..7] 13

DDRB_DQS#[0..7] 13

DDRB_DQ0

A25

DDRB_DQ1

C25

DDRB_DQ2

C27

DDRB_DQ3

D27

DDRB_DQ4

B24

DDRB_DQ5

B25

DDRB_DQ6

B27

DDRB_DQ7

A27

DDRB_DQ8

A29

DDRB_DQ9

C29

DDRB_DQ10

B32

DDRB_DQ11

D32

DDRB_DQ12

B28

DDRB_DQ13

B29

DDRB_DQ14

A31

DDRB_DQ15

C31

DDRB_DQ16

E30

DDRB_DQ17

E31

DDRB_DQ22

G33

DDRB_DQ23

G32

DDRB_DQ20

C33

DDRB_DQ21

D33

DDRB_DQ19

G30

DDRB_DQ18

G31

DDRB_DQ24

J30

DDRB_DQ25

J31

DDRB_DQ26

L33

DDRB_DQ27

L32

DDRB_DQ29

H32

DDRB_DQ28

H33

DDRB_DQ30

L30

DDRB_DQ31

L31

DDRB_DQ36

AN31

DDRB_DQ32

AP32

DDRB_DQ39

AT32

DDRB_DQ35

AU32

DDRB_DQ33

AN33

DDRB_DQ37

AN32

DDRB_DQ34

AR31

DDRB_DQ38

AT33

DDRB_DQ41

AU30

DDRB_DQ44

AV32

DDRB_DQ43

BA33

DDRB_DQ47

AY32

DDRB_DQ45

AU33

DDRB_DQ40

AU31

DDRB_DQ46

AW31

DDRB_DQ42

AY33

DDRB_DQ54

BC31

DDRB_DQ53

BB30

DDRB_DQ50

BB28

DDRB_DQ52

AY27

DDRB_DQ49

BB32

DDRB_DQ48

BA31

DDRB_DQ51

BC29

DDRB_DQ55

BB29

DDRB_DQ60

BB27

DDRB_DQ57

BB26

DDRB_DQ58

BB24

DDRB_DQ59

AY23

DDRB_DQ61

BA27

DDRB_DQ56

BC27

DDRB_DQ63

BC25

DDRB_DQ62

BB25

N30
N31
R33
R32
M32
M33
R30
R31

MB_ZVDDIO

AF32

DDRB_DQ[63..0] 13

DATA16--DATA23 Byte internal swap

DATA24--DATA31 Byte internal swap

DATA32--DATA39 Byte internal swap

DATA40--DATA47 Byte internal swap

DATA48--DATA55 Byte internal swap

DATA56--DATA63 Byte internal swap

+1.35V

1 2

RC5 39.2_0402_1%

+1.35V

12

RC6

1K_0402_1%

A A

1K_0402_1%

RC8

@

12

1

1

2

2

.47U_0402_6.3V6K

CC21

CC22

5

+MEM_VREF

1

2

.1U_0402_10V6-K

1000P_0402_50V7K

CC23

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2013/08/15

2013/08/15

2013/08/15

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2013/08/15

2013/08/15

2013/08/15

Title

FP4 (MEM)

FP4 (MEM)

FP4 (MEM)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

Allsparks 5B

Allsparks 5B

Allsparks 5B

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

5 51

5 51

1

5 51

0.3

0.3

0.3

5

+1.8VS

12

RC14
300_0402_5%

EC_SMB_CK216,31,35

EC_SMB_DA216,31,35

+1.8VS

+1.8VS

RC45
1K_0402_5%

HDT@

1 2

HDT@

12

APU_RST#

1

CC24
150P_0402_50V8-J

@

2

RC15
300_0402_5%

PWROK

1

CC25
150P_0402_50V8-J

@

2

RC48 33_0402_5%HDT@

2

CC27
.01U_0402_16V7-K

1

+1.8VS

6 1

1 2

5

2

1K_0404_4P2R_5%

G

S

D

QC23A

5

DMN5L06DWK-7 2N SOT363-6

G

3 4

D

QC23B
DMN5L06DWK-7 2N SOT363-6

APU_TRST#_R

RPC18
10K_0804_8P4R_5%

HDT@

1 8

2 7

3 6

4 5

APU_HDMI_TX2+26
APU_HDMI_TX2-26

APU_HDMI_TX1+26

HDMI eDP

eDP

+1.8VS

RPC4

1 4

2 3

APU_SIC

S

APU_SID

APU_HDMI_TX1-26

APU_HDMI_TX0+26
APU_HDMI_TX0-26

APU_HDMI_CLK+26
APU_HDMI_CLK-26

APU_EDP_TX0+25
APU_EDP_TX0-25

APU_EDP_TX1+25
APU_EDP_TX1-25

APU_SVT51
APU_SVC51
APU_SVD51

GFX_SVT50
GFX_SVC50
GFX_SVD50

APU_PWROK50,51

H_PROCHOT#35,43

With HDT+ Header

JHDT1

@

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

RC2544 33_0402_5%

18

18

20

20

APU_TCK

APU_TMS

APU_TDI

APU_TDO

APU_PWROK_BUF

APU_RST#_BUF

APU_DBRDY

HDT@

1 2

APU_TEST19_PLLTEST0

APU_TEST18_PLLTEST1

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

SAMTE_ASP-136446-07-B

D D

PLACE CC24 CAPS CLOSE TO APU,CRB reserve 27pf

PLACE CC25 CAPS CLOSE TO APU,CRB reserve 27pf

C C

B B

APU_TRST#

A A

4

APU_HDMI_TX2+
APU_HDMI_TX2-

APU_HDMI_TX1+
APU_HDMI_TX1-

APU_HDMI_TX0+
APU_HDMI_TX0-

APU_HDMI_CLK+
APU_HDMI_CLK-

APU_EDP_TX0+
APU_EDP_TX0-

APU_EDP_TX1+
APU_EDP_TX1-

RC22 0_0402_5%

1 2
1 2

RC23 0_0402_5%
RC24 0_0402_5%

1 2

1 2

RC25 0_0402_5%
RC26 0_0402_5%

1 2
1 2

RC28 0_0402_5%

RC186 0_0402_5%

1 2

1 2

RC184 0_0402_5%

+1.8VS+1.8VS

RPC6

18
27
36
45

1K_0804_8P4R_5%

HDT@

HDT@

4

APU_SVT_R
APU_SVC_R
APU_SVD_R

APU_GFX_SVT_R
APU_GFX_SVC_R
APU_GFX_SVD_R

APU_SIC
APU_SID

APU_RST#
PWROK

APU_PROCHOT#_R
ALERT#

APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_TRST#
APU_DBRDY
APU_DBREQ#

2

CC176
.01U_0402_16V7-K

1

APU_PWROK

APU_RST#

APU_TDIAPU_DBREQ# APU_DBREQ#

2

CC175

@

.01U_0402_16V7-K

1

C15
D17
D19

B15
B16
A18

B18
C17

D15
C19

A15
B17

H15
H14
D13
G15
J14
C13
A11

B6
A6

D7
C7

A7
B7

D9
C9

A2
A3

B4
A4

D5
C5

A5
B5

E2
E1

E3
E4

D1
D2

C1
B1

DP2_TXP0
DP2_TXN0

DP2_TXP1
DP2_TXN1

DP2_TXP2
DP2_TXN2

DP2_TXP3
DP2_TXN3

DP1_TXP0
DP1_TXN0

DP1_TXP1
DP1_TXN1

DP1_TXP2
DP1_TXN2

DP1_TXP3
DP1_TXN3

DP0_TXP0
DP0_TXN0

DP0_TXP1
DP0_TXN1

DP0_TXP2
DP0_TXN2

DP0_TXP3
DP0_TXN3

SVT0
SVC0
SVD0

SVT1
SVC1
SVD1

SIC
SID

RESET_L
PWROK

PROCHOT_L
ALERT_L

TDI
TDO
TCK
TMS
TRST_L
DBRDY
DBREQ_L

CPU@

UC1C

DISPLAY/SVI2/JTAG/TEST

DP_AUX_ZVSS

TEMPINRETURN

DP_STEREOSYNC/TEST36

VDDCR_GFX_SENSE

VDDCR_NB_SENSE

VDDCR_CPU_SENSE

VDDP_SENSE

FP4 REV 0.93

AMD-CARRIZO_FP4-BGA968

1

CC26

.1U_0402_10V6-K HDT@

2

UC2

3

2A

2

GND

1

1A

SN74LVC2G07YZPR_WCSP6HDT@

DP_ZVSS

DP_BLON

DP_DIGON

DP_VARY_BL

DP2_AUXP
DP2_AUXN

DP2_HPD

DP1_AUXP
DP1_AUXN

DP1_HPD

DP0_AUXP
DP0_AUXN

DP0_HPD

RSVD_1
TEMPIN0
TEMPIN1
TEMPIN2

TEST410
TEST411

TEST4
TEST5
TEST6

TEST9
TEST10
TEST14
TEST15
TEST16
TEST17
TEST11
TEST18
TEST19

TEST28_H
TEST28_L

TEST31

TEST37

VSS_SENSE

4

2Y

5

VCC

6

1Y

3

DP_2K_ZVSS

A9

DP_150_ZVSS

B9

DP_ENBKL

G5

DP_ENVDD

G6

DP_EDP_PWM

F11

H9
G9
E9

APU_DDC_CLK

F7

APU_DDC_DATA

E7

APU_HDMI_HPD

F5

APU_EDP_AUX

F8

APU_EDP_AUX#

E8

APU_EDP_HPD

G8

K24

CORETYPE

E15
E14
E12
F14
AK24

TEST410

AL24

TEST411

P24

TEST4

N24

TEST5

AN24
AB8
Y9

APU_TEST14_BP0

B10

APU_TEST15_BP1

D11

APU_TEST16_BP2

A10

APU_TEST17_BP3

C11

APU_TEST11_BP4

B11

APU_TEST18_PLLTEST1

A14

APU_TEST19_PLLTEST0

B14

APU_TEST28_H_PLLCHARZ

A13

APU_TEST28_L_PLLCHARZ

B13

APU_TEST31_MEM_TEST

P26

APU_TEST36_STEREOSYNC

E11

APU_TEST37

A17

GFX_CORE_SEN

H11

APU_VDDNB_SEN_H

J12

APU_VDD_SEN_H

G12

VDD_095_FB_H

AY18

APU_VSS_SEN_L

H12

+1.8VS+1.8VS

3

RC11 2K_0402_1%
RC12 150_0402_1%

RPC26
1K_0404_4P2R_5%

HDT@

1 4

2 3

APU_PWROK_BUF

APU_RST#_BUF

2

For Carrzio
DisplayPort Auxiliary Channel pins are dual-mode pins and are 3.3V tolerant.
In I2C mode AUXP pins change to SCL, and AUXN pins change to SDA.
During this operation the pin type is B-IO33-OD. FDS

1 2
1 2

For Carrzio,
Hot Plug Detect pins is I-IO18-S,but 3.3V tolerant.
DP_VARY_BL, DP_BLON, DP_DIGON signals are VDD_18 level at the APU

APU_DDC_CLK 26
APU_DDC_DATA 26
APU_HDMI_HPD 26

APU_EDP_AUX 25
APU_EDP_AUX# 25
APU_EDP_HPD 25

TC7@

1

TC8@

1
1

TC9@
TC10@

1
1

TC11@

RC17 1K_0402_5%@

1 2

1

TC12@

RC19 1K_0402_5%@

1 2

RC20 1K_0402_5%@

1 2
1 2

RC21 1K_0402_5%@

1

TC13@
TC14@

1
1

TC15@

GFX_CORE_SEN 50
APU_VDDNB_SEN_H 51
APU_VDD_SEN_H 51

1

@

TC16

1 2

RC36 0_0402_5%

RC2538 0_0402_5%

1 2

RC37 0_0402_5%

1 2

HDMI

23
14

RPC3 1K_0404_4P2R_5%

1 2

RC29 1K_0402_5%@
RC30 1K_0402_5%

1 2

RC31 1K_0402_5%@

1 2
1 2

RC32 1K_0402_5%@

APU_VDD_SEN_L 51

APU_VDDNB_SEN_L 51

GFX_VSS_SEN 50

APU_VDDNB_SEN_H

APU_VDD_SEN_H

APU_VDD_SEN_L

GFX_CORE_SEN

GFX_VSS_SEN

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

1

1

1

1

1

+1.8VS

TC17@

TC18@

TC19@

TC20@

TC21@

2013/08/15

2013/08/15

2013/08/15

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

2

DP_EDP_PWM

Follow CRB @

Deciphered Date

Deciphered Date

Deciphered Date

1

APU_DDC_CLK
APU_DDC_DATA

APU_EDP_HPD

ALERT#
APU_PROCHOT#_R

CORETYPE

To EDP panel

+3VALW

2

G

12

DP_ENVDD

12

RC33

4.7K_0402_5%

@

RC43
100K_0402_5%

S

+3VALW

QC25A

DMN5L06DWK-7 2N SOT363-6

2

G

S

@

LCD Power IC can reserve,as IC EN VIH>=1.5V

+3VALW

QC26A

DMN5L06DWK-7 2N SOT363-6

DP_ENBKL

2

G

12

RC49
100K_0402_5%

@

S

@

PCH_ENBKL can to con EC ADC pin for CZ cost down because 1.8V level

2013/08/15

2013/08/15

2013/08/15

RC9 2K_0402_5%
RC10 2K_0402_5%

RC13 100K_0402_5%

+3VS

RC18
10K_0402_5%

1 2

5

G

61

D

QC24A
DMN5L06DWK-7 2N SOT363-6

1 2

RC34 0_0402_5%@

+3VS

RC39
10K_0402_5%

@

1 2

5

G

61

@

D

RC44 0_0402_5%

1 2

+3VS

1 2

RC47
10K_0402_5%

@

1 2

34

D

5

G

S

61

@

D

RC50 0_0402_5%

1 2

FP4 (DISPLAY/CLK/MISC)

FP4 (DISPLAY/CLK/MISC)

FP4 (DISPLAY/CLK/MISC)

Custom

Custom

Custom

1 2
1 2

1 2

RPC1

23
14

1K_0404_4P2R_5%

RC2537 100K_0402_5%

1 2

@

12

RC16

4.7K_0402_5%

QC24B

34

DMN5L06DWK-7 2N SOT363-6

D

S

12

RC38

4.7K_0402_5%

@

34

D

QC25B

S

DMN5L06DWK-7 2N SOT363-6

RC46

2.2K_0402_5%

@

PCH_ENBKL 25

QC26B
DMN5L06DWK-7 2N SOT363-6

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet

Allsparks 5B

Allsparks 5B

Allsparks 5B

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

1

+3VS_APU

+1.8VS

+3VALW_APU

PCH_EDP_PWM 25

PCH_ENVDD 25

6 51

6 51

6 51

0.3

0.3

0.3

of

5

1 2

RC56 33_0402_5%

RB751V-40_SOD323-2@

12

10K_0402_5%

DC2

12

DC4

SYS_PWRGD_RSYS_RESET#

@

RC51 33_0402_5%

1

CC28
150P_0402_50V8-J

2

1 2

1

CC29
150P_0402_50V8-J

2

+1.8VALW

RC63
1K_0402_5%

1 2

RSMRST#_R

2

CC30
.1U_0402_10V6-K

1

+1.8VS

12

RC68

@

SYS_PWRGD_R

1

CC31
1U_0402_6.3V6K

@

2

PCIE_WAKE# 30,35

APU_LPC_RST#35,36

PLT_RST#15,28,30

D D

EC_RSMRST#35

RSMRST# VDD_18_S5 power rail
Connected to 10-ms RC-delay circuit on VDD_18_S5 power rail.
(CRB PWR Dealy: 22K/0.1uF)

C C

EC_SYS_PWRGD35

I2C Bus, CZ have, 1.8V ;
CZL only have GPIO function, 3.3V.
so for common design, it's should not be GPIO setting

PCIE_WAKE#_RA

RC70 0_0402_5%

AGPIO5

B B

+3VALW_APU

12

RC2542
100K_0402_5%@

12

RC57
100K_0402_5%@

1 2

DC1

RC187 0_0402_5%

@

1 2

RB751V-40_SOD323-2

RC69 0_0402_5%

1 2

RB751V-40_SOD323-2

12

12

RC71

@

0_0402_5%

DC3

12

RB751V-40_SOD323-2

@

LPC_RST#_R

PCIE_RST#_R

PBTN_OUT#35

SYS_RESET#11

PM_SLP_S3#35
PM_SLP_S5#35

4

3

2

1

04/23 For TP SMBUS channel change

Q178A

APU_SMB_CLK2

UC1D

LPC_RST#_R
PCIE_RST#_R

RSMRST#_R

PWRBTN#_RPBTN_OUT#

12

RC64 0_0402_5%

PM_SLP_S3#

RC65 0_0402_5%

PM_SLP_S5#

RC66 0_0402_5%

APU_S5_MUX_CTRL9

KBRST#35
GATEA2035
EC_SCI#35

1 2

RC2551

AC_PRESENT16,35

HDA_SDIN034

SUSCLK11,30

@

0_0402_5%

LAN_CLKREQ0#28

WLAN_CLKREQ1#30

SSD_CLKREQ2#30

PCH_BT_OFF#30

GPU_CLKREQ#16

USB_OC1#32
USB_OC2#36

RC76 0_0402_5%

RPC11

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

1

CC32

2

12
12

TC47 @

AC_PRES

12

RC84

1 2

20M_0402_5%

YC1

1 2

202983-PG14

Max ESR < 65K ohm !!

18P_0402_50V8J

SYS_PWRGD_R
SYS_RESET#
PCIE_WAKE#_RA

PM_SLP_S3#_R
PM_SLP_S5#_R

AGPIO10
APU_S5_MUX_CTRL

TEST0
TEST1
TEST2

KBRST#

1

BOARD_ID1

IR_LED_L
LAN_CLKREQ0#
WLAN_CLKREQ1#
SSD_CLKREQ2#
PCH_BT_OFF#
GPU_CLKREQ#
BOARD_ID0
USB_OC1#
USB_OC2#

HDA_BITCLK
HDA_SDIN0_R
HDA_SDIN1
HDA_SDIN2
HDA_RST#
HDA_SYNC
HDA_SDOUT

I2C0SCl
I2C0SDA
I2C1SCL
I2C1SDA

BB12

LPC_RST_L

AN7

PCIE_RST_L/EGPIO26

AE4

RSMRST_L

AE1

PWR_BTN_L/AGPIO0

BC9

PWR_GOOD

AF2

SYS_RESET_L/AGPIO1

AG2

WAKE_L/AGPIO2

AK7

SLP_S3_L

AH5

SLP_S5_L

AE8

S0A3_GPIO/AGPIO10

AH8

S5_MUX_CTRL/EGPIO42

AH6

TEST0

AK8

TEST1/TMS

AE3

TEST2

AY15

ESPI_RESET_L/KBRST_L/AGPIO129

BC19

GA20IN/AGPIO126

AD7

LPC_PME_L/AGPIO22

BB13

LPC_SMI_L/AGPIO86

AG3

AC_PRES/USB_OC4_L/IR_RX0/AGPIO23

AD5

IR_TX0/USB_OC5_L/AGPIO13

AL8

IR_TX1/USB_OC6_L/AGPIO14

AN8

IR_RX1/AGPIO15

AE2

IR_LED_L/LLB_L/AGPIO12

BC15

CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92

BB17

CLK_REQ1_L/AGPIO115

BC17

CLK_REQ2_L/AGPIO116

BB18

CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131

BB16

CLK_REQG_L/OSCIN/EGPIO132

AH9

USB_OC0_L/TRST_L/AGPIO16

AG1

USB_OC1_L/TDI/AGPIO17

AH2

USB_OC2_L/TCK/AGPIO18

AL9

USB_OC3_L/TDO/AGPIO24

AU6

AZ_BITCLK/I2S_BCLK_MIC

AR8

AZ_SDIN0/I2S_DATA_MIC0

AP6

AZ_SDIN1/I2S_LR_PLAYBACK

AR5

AZ_SDIN2/I2S_DATA_MIC1

AU9

AZ_RST_L/I2S_LR_MIC

AT9

AZ_SYNC/I2S_BCLK_PLAYBACK

AR7

AZ_SDOUT/I2S_DATA_PLAYBACK

BB10

I2C0_SCL/EGPIO145

BB9

I2C0_SDA/EGPIO146

BB7

I2C1_SCL/EGPIO147

BC7

I2C1_SDA/EGPIO148

AG7

32K_X1

32K_X2

RTCCLK

AT1

X32K_X1

AT2

X32K_X2

CPU@

1

CC33

2

18P_0402_50V8J

ACPI/SD/AZ/GPIO/RTC/I2C/UART/MISC

UART1_CTS_L/BT_I2S_BCLK/EGPIO140

UART1_RXD/BT_I2S_SDI/EGPIO141

UART1_TXD/BT_I2S_SDO/EGPIO143

UART1_INTR/BT_I2S_LRCLK/AGPIO144

FP4 REV 0.93

AMD-CARRIZO_FP4-BGA968

SD0_WP/EGPIO101

SD0_PWR_CTRL/AGPIO102

SD0_CD/AGPIO25

SD0_CLK/EGPIO95

SD0_CMD/EGPIO96

SD0_DATA0/EGPIO97
SD0_DATA1/EGPIO98
SD0_DATA2/EGPIO99

SD0_DATA3/EGPIO100

SD0_LED/EGPIO93

SCL0/I2C2_SCL/EGPIO113
SDA0/I2C2_SDA/EGPIO114

SCL1/I2C3_SCL/AGPIO19
SDA1/I2C3_SDA/AGPIO20

AGPIO3
AGPIO4
AGPIO5

AGPIO6/LDT_RST_L

AGPIO7/LDT_PWROK

AGPIO8
AGPIO9

VDDGFX_PD/AGPIO39

AGPIO40
AGPIO64
AGPIO65

AGPIO66/SHUTDOWN_L

AGPIO68/SGPIO_CLK

AGPIO69/SGPIO_LOAD

AGPIO71/SGPIO_DATAOUT

AGPIO72/SGPIO_DATAIN

SPKR/AGPIO91

BLINK/USB_OC7_L/AGPIO11

GENINT1_L/AGPIO89
GENINT2_L/AGPIO90

FANIN0/AGPIO84

FANOUT0/AGPIO85

UART0_CTS_L/EGPIO135

UART0_RXD/EGPIO136

UART0_RTS_L/EGPIO137

UART0_TXD/EGPIO138

UART0_INTR/AGPIO139

UART1_RTS_L/EGPIO142

BB2
BB5
BC2
BB4
AY5

BC3
BA3
BC5
BA5
BB6

BA15
AY17

AG5
AG4

AL5
AL6
AJ1
AJ3
AH1
AJ4
AK5
AD8
AG8
AW15
AU15

AT15
AU12
AT14
AR14
BC13

BA17

AN5

BB14
BA19

BC18
BB19

AY9
AW8
AV5
AV8
AW9

AV11
AU7
AT11
AR11
AP9

@

SD_WP
SD_PWR_CNTL
SD_CD#
SD_CLK_R
SD_CMD_R

SD_DATA0_R
SD_DATA1_R
SD_DATA2_R
SD_DATA3_R
SD_LED

APU_SMB_CLK
APU_SMB_DATA

APU_SMB_CLK2
APU_SMB_DATA2

AGPIO3

AGPIO5
LDT_RST_L
LDT_PWROK

AGPIO8

VDDGFX_PD
AGPIO40

VR_GFX_PWRGD

APU_SHUTDOWN#

PXS_RST#_R

HVB_EN
VR_VGA_PWRGD

PXS_PWREN_R
PCH_WLAN_OFF#

1

TC22

@

1

TC23

1

@

TC24

@

1

TC25

1

@

TC26

1

TC27@

1

TC28@

1

TC29@

1

TC30@

1

TC31@

APU_SMB_CLK 12,13,30
APU_SMB_DATA 12,13,30

AGPIO3 11

1

TC32@

1

TC33@

VDDGFX_PD 35

VR_GFX_PWRGD 35,50
PEDET 30

APU_SHUTDOWN# 16

1 2

RC74 0_0402_5%PX@

1 2

RC2539 0_0402_5%BOAC@

PCH_BEEP 34

BLINK 11

HVB_EN 11
VR_VGA_PWRGD 15,49

1 2

RC75 1K_0402_5%PX@

PCH_WLAN_OFF# 30

UART Bus:

1.8V CZ, no signla for CZL
it's should not be GPIO setting

APU_SMB_DATA2

DIMM1, DIMM2, WLAN,TP
SCL0/SDA0 is the SMBus port in the S0 power domain
SCL1/SDA1 is the SMBus port in the S5 power domain

2N7002KDWH_SOT363-6

6 1

D

3 4

D

2N7002KDWH_SOT363-6

Q178B

PXS_RST# 15

PX_EN 15,19

PXS_PWREN 19,48,49

G

2

5

G

S

S

PM_SLP_S3#
PM_SLP_S5#

USB_OC1#
USB_OC2#

APU_SMB_CLK2
APU_SMB_DATA2

APU_SMB_CLK
APU_SMB_DATA

KBRST#

PCH_BT_OFF#
PCH_WLAN_OFF#

LAN_CLKREQ0#
WLAN_CLKREQ1#
SSD_CLKREQ2#

GPU_CLKREQ#
APU_SHUTDOWN#

PCIE_WAKE#_RA
AC_PRES
AGPIO5
PBTN_OUT#

VDDGFX_PD
IR_LED_L

RPC28

14
23

2.2K_0404_4P2R_5%

APU_SMB_CLK2
APU_SMB_DATA2

RC89 2.2K_0402_5%@
RC90 2.2K_0402_5%@

RC2533 10K_0402_5%
RC2534 10K_0402_5%
RC2535 10K_0402_5%

RC79 10K_0402_5%@
RC80 100K_0402_5%@

RC88 10K_0402_5%@
RC2530 10K_0402_5%

TP_SMB_CLK 36

+3VS+3VS

TP_SMB_DAT 36

RPC7

1 4
2 3

@

10K_0404_4P2R_5%

1 2
1 2

RPC13

1 4
2 3

10K_0404_4P2R_5%

RPC27

23
14

2.2K_0404_4P2R_5%

RPC8

23
14

2.2K_0404_4P2R_5%
RPC9

18
27
36
45

10K_0804_8P4R_5%

1 2
1 2
1 2

PSSD@

1 2
1 2

RPC12

1 8
2 7
3 6
4 5

10K_0804_8P4R_5%

1 2
1 2

+3VALW

+3VALW_APU

+3VS_APU

+3VALW_APU

5

RC83

2.2K_0402_5%

@

1 2

TEST0
TEST1
TEST2

RC87
15K_0402_5%

1 2

PXS_PWREN_R
PXS_RST#_R

VR_VGA_PWRGD

PXS_PWREN_R
PXS_RST#_R

VR_VGA_PWRGD

SYS_RESET#

2

CC184
.1U_0402_10V6-K

1

EMC@

HDA_RST#
HDA_SYNC
HDA_SDOUT

RC2552

1K_0402_5%

RC2553

1K_0402_5%

RC2554

1K_0402_5%

1 2

1 2

1 2

0303 ADD for AMD HDA sequence workround

4

+3VALW_APU

HDA_SDIN1
HDA_SDIN2

AGPIO8
AGPIO40

AGPIO10

GPU_CLKREQ#

HDA_BITCLK
HDA_SDIN0_R

RSMRST#_R
SYS_PWRGD_R
VDDGFX_PD

Title

Title

Title

FP4 (GEVENT/GPIO/SD/AZ)

FP4 (GEVENT/GPIO/SD/AZ)

FP4 (GEVENT/GPIO/SD/AZ)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet

1 2

1 2

Deciphered Date

Deciphered Date

Deciphered Date

RC53
10K_0402_5%

128@

RC59
10K_0402_5%

256@

2013/08/15

2013/08/15

2013/08/15

RPC15

HDA_RST_AUDIO#34
HDA_SYNC_AUDIO34
HDA_BITCLK_AUDIO34
HDA_SDOUT_AUDIO34

1 8
2 7
3 6
4 5

33_0804_8P4R_5%

3

HDA_RST#
HDA_SYNC
HDA_BITCLK
HDA_SDOUT

Only Cz pin(AGPIO66/ShutDown_L )have ShutDown_L function,
inter pull down for Cz,pull high for Czl

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

BOARD_ID0
BOARD_ID1

2013/08/15

2013/08/15

2013/08/15

RC52
10K_0402_5%

PSSD@

1 2

RC58
10K_0402_5%

SSD@

1 2

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

2

RPC24

1 4
2 3

10K_0404_4P2R_5%
RPC23

1 4
2 3

10K_0404_4P2R_5%

1 2

RC97 10K_0402_5%

1 2

RC100 10K_0402_5%

RC102 1K_0402_5%
RC103 10K_0402_5%@

RC106 100K_0402_5%
RC107 100K_0402_5%
RC2536 100K_0402_5%

12

1 2

1 2
1 2
1 2

@

Allsparks 5B

Allsparks 5B

Allsparks 5B

1

7 51

7 51

7 51

0.3

0.3

0.3

of

RC81

2.2K_0402_5%

@

1 2

RC85
15K_0402_5%

1 2

+3VS_APU

RC91 10K_0402_5%PX@
RC92 10K_0402_5%@

A A

RC94 10K_0402_5%@

RC95 100K_0402_5%@
RC96 100K_0402_5%PX@
RC98 2K_0402_5%@

1 2
1 2
1 2

1 2
1 2
1 2

RC82

2.2K_0402_5%

@

1 2

RC86
15K_0402_5%

1 2

5

SATA_PTX_DRX_P033
SATA_PTX_DRX_N033

HDD

SATA_PRX_DTX_N033
SATA_PRX_DTX_P033

SATA_PTX_DRX_P130
SATA_PTX_DRX_N130

SSD

SATA_PRX_DTX_N130

CLK0_PCI_EC11,35

CLK1_PCI_TPM11,36

SPI_CLK35
SPI_CS0#35

SPI_SO35

SPI_SI35

48M_X1

48M_X2

1

CC37
10P_0402_50V8J

2

LPC_PD

SATA1_DEVSLP_R

SATA0_DEVSLP_R
AGPIO76

SATA_PRX_DTX_P130

+0.95VS

SSD_DEVSLP_R30

+3VS_APU

SATA_LED#36

CLK_PCIE_GPU CLK_PCIE_GPU_R
CLK_PCIE_GPU# CLK_PCIE_GPU#_R

CLK_PCIE_LAN CLK_PCIE_LAN_R

CLK_PCIE_WLAN CLK_PCIE_WLAN_R

SPI_CLK
SPI_CS0#

SPI_SO
SPI_SI
SPI_WP#
SPI_HOLD#

RC109 1K_0402_1%
RC110 1K_0402_1%

RC180 10K_0402_5%@
RC112 10K_0402_5%@
RC2545 0_0402_5%

1 2

RC113 0_0402_5%PX@

1 2

RC114 0_0402_5%PX@

1 2

RC117 0_0402_5%

1 2

RC118 0_0402_5%

1 2

RC115 0_0402_5%

1 2

RC116 0_0402_5%

1 2

RC176 0_0402_5%PSSD@

1 2

RC177 0_0402_5%PSSD@

1 2

RC122 0_0402_5%

1 2

RC181 22_0402_5%

LPC_AD035,36
LPC_AD135,36
LPC_AD235,36
LPC_AD335,36

LPC_FRAME#11,35,36

SERIRQ35,36

RC124 0_0402_5%
RC125 0_0402_5%
RC182 10K_0402_5%
RC126 0_0402_5%
RC127 0_0402_5%
RC128 0_0402_5%
RC129 0_0402_5%

SPI_CS0#
SPI_SO
SPI_WP#

+VCC_SPI

1 4
2 3

1 2

RC2543 10K_0402_5%

D D

RC109 RC110 place to cpu within 1000mil

GPU

LAN

WLAN

SSD

C C

B B

A A

48MHz/10pF Crystal

1 2

RC130 1M_0402_5%

YC2

1

OSC1

1

2

NC12OSC2

48MHZ_10PF_7V48000017
CC36
10P_0402_50V8J

1 2

RC2527 10K_0402_5%

1 2

RC2526 10K_0402_5%

RPC22

1 4
2 3

10K_0404_4P2R_5%

CLK_PCIE_GPU15
CLK_PCIE_GPU#15

CLK_PCIE_LAN28
CLK_PCIE_LAN#28

CLK_PCIE_WLAN30
CLK_PCIE_WLAN#30

CLK_PCIE_SSD30
CLK_PCIE_SSD#30

4

NC2

3

5

4

SATA_PTX_DRX_P0
SATA_PTX_DRX_N0

SATA_PRX_DTX_N0
SATA_PRX_DTX_P0

SATA_PTX_DRX_P1
SATA_PTX_DRX_N1

SATA_PRX_DTX_N1
SATA_PRX_DTX_P1

1 2
1 2

1 2
1 2

1 2

12

DC5

@

TC37 @

1 2
1 2
1 2
1 2
1 2
1 2
1 2

QUAD@
QUAD@

8MB ROM

UC4

1

/CS

2

DO(IO1)

3

/WP(IO2)

4

GND

W25Q64FWSSIQ_SO8

RPC25

SPI_WP#
SPI_HOLD#

10K_0404_4P2R_5%

SPI_CS0#

4

3

UC1E

AU3

SATA_TX0P

AU4

SATA_TX0N

AV1

SATA_RX0N

AV2

SATA_RX0P

AY2

SATA_TX1P

AY1

SATA_TX1N

AW4

SATA_RX1N

AW3

SATA_CALRN
SATA_CALRP
SATA0_DEVSLP_R USB20_N3
SATA1_DEVSLP_R
SATA_ACT_L

RB751V-40_SOD323-2

CLK_PCIE_LAN#_RCLK_PCIE_LAN#

CLK_PCIE_WLAN#_RCLK_PCIE_WLAN#

CLK_PCIE_SSD_RCLK_PCIE_SSD
CLK_PCIE_SSD#_RCLK_PCIE_SSD#

X14M_25M_48M_OSC

1

48M_X1

48M_X2

LPCCLK0
LPCCLK1

1

TC38 @

1

TC39 @

LPC_PD

SPI_CLK_R
SPI_CS0#_R
SPI_CS2#_R
SPI_SO_R
SPI_SI_R
SPI_WP#_R
SPI_HOLD#_R
AGPIO76

/HOLDor/RESET(IO3)

VCC

CLK

DI(IO0)

SATA_RX1P

AW1

SATA_ZVSS

AW2

SATA_ZVDDP

AT17

DEVSLP0/EGPIO67

AT12

DEVSLP1/EGPIO70

BB15

SATA_ACT_L/AGPIO130

AU2

SATA_X1

AU1

SATA_X2

U4

GFX_CLKP

U3

GFX_CLKN

U1

GPP_CLK0P

U2

GPP_CLK0N

W4

GPP_CLK1P

W3

GPP_CLK1N

W1

GPP_CLK2P

W2

GPP_CLK2N

Y2

GPP_CLK3P

Y1

GPP_CLK3N

BC10

X25M_48M_OSC

T2

X48M_X1

T1

X48M_X2

AW14

LPCCLK0/EGPIO74

AY13

LPCCLK1/EGPIO75

BB11

LAD0

BA11

LAD1

AY11

LAD2

BA13

LAD3

AV14

LFRAME_L

BA1

ESPI_ALERT_L/LDRQ0_L

BC14

SERIRQ/AGPIO87

BC11

LPC_CLKRUN_L/AGPIO88

AE9

LPC_PD_L/AGPIO21

BC6

SPI_CLK/ESPI_CLK/EGPIO117

BB8

SPI_CS1_L/EGPIO118

AW7

SPI_CS2_L/ESPI_CS_L/EGPIO119

BA9

SPI_DI/ESPI_DATA/EGPIO120

AY7

SPI_DO/EGPIO121

AW11

SPI_WP_L/EGPIO122

BA7

SPI_HOLD_L/EGPIO133

AW12

SPI_TPM_CS_L/AGPIO76

CPU@

+VCC_SPI

8

SPI_HOLD#

7

SPI_CLK

6

SPI_SI

5

1

2

CLK/SATA/USB/SPI/LPC

CC35
.1U_0402_10V6-K

+VCC_SPI

USBCLK/25M_48M_OSC

USB_HSD0P
USB_HSD0N

USB_HSD1P
USB_HSD1N

USB_HSD2P
USB_HSD2N

USB_HSD3P
USB_HSD3N

USB_HSD4P
USB_HSD4N

USB_HSD5P
USB_HSD5N

USB_HSD6P
USB_HSD6N

USB_HSD7P
USB_HSD7N

USB_SS_ZVSS

USB_SS_ZVDDP

USB_SS_0TXP
USB_SS_0TXN

USB_SS_0RXP
USB_SS_0RXN

USB_SS_1TXP
USB_SS_1TXN

USB_SS_1RXP
USB_SS_1RXN

USB_SS_2TXP
USB_SS_2TXN

USB_SS_2RXP
USB_SS_2RXN

USB_SS_3TXP
USB_SS_3TXN

USB_SS_3RXP
USB_SS_3RXN

FP4 REV 0.93

AMD-CARRIZO_FP4-BGA968

+VCC_SPI

40mil(25mA Max)

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

CLK_USB48M

AP8

USB_RCOMP

AP5

USB_ZVSS

RC132 0_0402_5%

RC133 0_0402_5%

AR2
AR1

AR3
AR4

AN2
AN1

AN3
AN4

AM1
AM2

AL2
AL1

AL3
AL4

AK2
AJ2

AD2
AD1

AA3
AA4

W9
W8

AA2
AA1

W5
W6

AC1
AC2

Y6
Y7

AC4
AC3

AB5
AB6

1 2

1 2

@

2013/08/15

2013/08/15

2013/08/15

USB20_P0
USB20_N0

USB20_P1
USB20_N1

USB20_P3

USB20_P4
USB20_N4

USB20_P5
USB20_N5

USB20_P6
USB20_N6

USBSS_CALRN
USBSS_CALRP

USB30_TX_P0
USB30_TX_N0

USB30_RX_P0
USB30_RX_N0

USB30_TX_P1
USB30_TX_N1

USB30_RX_P1
USB30_RX_N1

USB30_TX_P2
USB30_TX_N2

USB30_RX_P2
USB30_RX_N2

2

1

TC36@

1 2

RC108 11.8K_0402_1%

USB20_P0 36
USB20_N0 36

USB20_P1 25
USB20_N1 25

USB20_P3 30
USB20_N3 30

USB20_P4 36
USB20_N4 36

USB20_P5 32
USB20_N5 32

USB20_P6 32
USB20_N6 32

1 2

RC119 1K_0402_1%

1 2

RC120 1K_0402_1%

USB30_TX_P0 36
USB30_TX_N0 36

USB30_RX_P0 36
USB30_RX_N0 36

USB30_TX_P1 32
USB30_TX_N1 32

USB30_RX_P1 32
USB30_RX_N1 32

USB30_TX_P2 32
USB30_TX_N2 32

USB30_RX_P2 32
USB30_RX_N2 32

CarrzioL don't support USB_SS_[1:0]
Note: Route USB 3.0 ports starting from the lowest numbered port,
for example, Port0, Port1, Port2.
All unused ports should be the highest numbered ports.
For CZ and CZL Co-lay, can start from Port2

USB3.0 port0 must map to USB2.0 port4,
USB3.0 port1 must map to USB2.0 port5,
USB3.0 port2 must map to USB2.0 port6,
USB3.0 port3 must map to USB2.0 port7

+1.8VS

+1.8VALW

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

RC108 place to cpu within 1000mil

LEFT USB (2.0)

Camera

Blue Tooth

Card Reader

RIGHT USB (3.0) upper JUSB1

RIGHT USB (3.0) Lower JUSB2

+0.95VALW

Card Reader

RIGHT USB (3.0) upper JUSB1

RIGHT USB (3.0) Lower JUSB2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

2

2013/08/15

2013/08/15

2013/08/15

SPI_CLK

FP4 (SATA/USB/LPC/SPI)

FP4 (SATA/USB/LPC/SPI)

FP4 (SATA/USB/LPC/SPI)

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

1

RC134
10_0402_5%

EMC_NS@

1 2

2

CC38
10P_0402_50V8J

EMC_NS@

1

EMC

Allsparks 5B

Allsparks 5B

Allsparks 5B

1

8 51

8 51

8 51

0.3

0.3

0.3

5

+1.35V

+1.35V

1

1

1

CC45

CC44

CC63

2

2

D D

C C

+VCCRTC

B B

APU_S5_MUX_CTRL7

S5_MUX_CTRL:
Enable MUX(S0 to S3)-->LOW
Disable MUX(S3 to S0)-->HIGH
During S0 track VDDNB power
During S5/S4/S3 set to 0.775V

A A

2

22U_0603_6.3V6-M

22U_0603_6.3V6-M

+3VS_APU

+3VS

1 2

RC139

0_0603_5%

1

CC87

2

10U_0603_6.3V6M

+0.95VS

1

1

1

CC96

CC95

CC94

2

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

OK

+APU_CORE_NB

1

1

1

CC103

CC102

CC104

2

2

2

0.22U_0402_10V6K

0.22U_0402_10V6K

OK

RC141 10K_0402_5%

1 2

CC118

RC154

1 2

0_0402_5%

22U_0603_6.3V6-M

10U_0603_6.3V6M

0.22U_0402_10V6K

1

2

1

1

CC46

CC47

2

2

22U_0603_6.3V6-M

+1.8VS

1

CC97

CC98

2

10U_0603_6.3V6M

1

1

CC106

CC105

2

2

0.22U_0402_10V6K

AP2138N-1.5TRG1_SOT23-3

1U_0402_6.3V6K

+3VALW_APU

12

RC149
100K_0402_5%

@

1

CC48

CC64

2

22U_0603_6.3V6-M

22U_0603_6.3V6-M

1

1

CC89

CC88

2

2

@

22U_0603_6.3V6-M

1

1

CC152

2

2

0.22U_0402_10V6K

0.22U_0402_10V6K

1

CC108

CC107

2

0.22U_0402_10V6K

0.22U_0402_10V6K

UC5

1

Vin

Vout

2

GND

B+

2

G

QC16A

S

2N7002KDWH_SOT363-6

1

1

1

CC49

2

22U_0603_6.3V6-M

1

CC157

2

10U_0603_6.3V6M

1

CC153

2

0.22U_0402_10V6K

1

CC109

2

0.22U_0402_10V6K

3

+5VALW

12

RC150

1M_0402_5%

MUX_S5

61

D

+5VALW

1

CC65

CC50

2

2

2

@

@

22U_0603_6.3V6-M

22U_0603_6.3V6-M

+1.8VALW

1

0.22U_0402_10V6K

CC90

2

1

1

1

CC155

CC156

CC154

2

2

2

0.22U_0402_10V6K

0.22U_0402_10V6K

1

1

CC111

CC110

2

2

180P_0402_50V8-J

0.22U_0402_10V6K

follow CRB ACROSS VDDNB AND VSS SPLIT

+RTCBATT

1

CC119

2

1U_0402_6.3V6K

+5VALW

RC2547

10K_0402_5%

@

1 2

5

G

RC155

100K_0402_5%

+3VALW_APU

RC2555 0_0402_5%

RC2556 0_0402_5%@

1

CC52

2

1

0.22U_0402_10V6K

CC51

2

@

22U_0603_6.3V6-M

22U_0603_6.3V6-M

RC137 0_0805_5%PX@

CC91

10U_0603_6.3V6M

CC99

0.22U_0402_10V6K

1

2

1 2

MUX_S0

34

QC16B

D

2N7002KDWH_SOT363-6

S

12

1 2

1 2

Wake-on-Ring not supported:
+VDDIO_AZ_APU Connect to +1.5V S0 rail

+1.8VS

1 2

+3VALW_APU

1

2

0.22U_0402_10V6K

1

2

180P_0402_50V8-J

1

1

CC114

CC113

CC112

2

2

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

12

12

JCMOS1

RC142

SHORT PADS

470_0603_5%

@

13

D

S

RC2546
10K_0402_5%

+APU_CORE_NB

@

FCH_S5_POWER

RC2550

1 2

0_0402_5%

FCH_S5_POWER_COMP FCH_S5_POWER

1

180P_0402_50V8-J
CC127

@

2

+3VALW_APU_FCH

4

1

1

1

CC54

CC53

CC55

2

2

2

0.22U_0402_10V6K

0.22U_0402_10V6K

+0.95VS_GFX_APU+0.95VS

PX@

1

CC92

2

1

CC115

2

0.22U_0402_10V6K

@

EC_RTCRST#_ON

2

G

MUX_S0

1 2

1 2

@

1

CC79

2

1

CC93

2

10U_0603_6.3V6M

CC116

@

0.22U_0402_10V6K

1 2

0.22U_0402_10V6K

CC80

PX@

10U_0603_6.3V6M

0.22U_0402_10V6K

1

2

0.22U_0402_10V6K

12

RC143
100K_0402_5%

@

RC2549 0_0402_5%@

1

2

OK

RC136 0_0402_5%

RC2531 0_0402_5%

1

2

QC13

2N7002KW_SOT323-3

@

RC147 0_0402_5%

1

CC56

2

0.22U_0402_10V6K

1 2

0.22U_0402_10V6K

+VDDIO_AZ_APU+1.5VS

+0.95VALW

1

CC57

2

0.22U_0402_10V6K

1

CC76

CC77

2

1U_0402_6.3V6K

1

CC100

2

EDC 17A TDC 12A

+RTCBATT

RC140

EC_RTCRST#_ON 35

+3VALW_APU_FCH

8

UC6A

3

P

+_1

O1

2

-_1

G

AS393MTR-G1_SO8

4

FCH_S5_POWER_COMP

1

2

10U_0603_6.3V6M

CC58

1U_0402_6.3V6K

CC101

1 2

1

+1.35V

1

2

180P_0402_50V8-J

1

CC78

2

1U_0402_6.3V6K

+VDDCR_FCH_S5

1

+0.95VS

2

0.22U_0402_10V6K

+APU_CORE_NB

+RTCBATT_APU

1K_0402_5%

COMP_OUT1

+0.775VALW

+0.95VALW

MUX_S5

P25

3A

P28
T24
T27
U25
U28
V30
V33
W24
W27
Y25
Y28

Y30
AB24
AB27
AB30
AB33
AD25
AD28
AD30
AE24
AE27
AF30
AF33

AG25
AG28

AH24
AH27
AH30
AK25
AK28
AK30
AK33
AL27

AM30

AR19

0.2A

AE6

1.4A

AE5

AP19

0.2A

AP21

AP16

1.5A

AP18

AP10

0.5A

AR9

AP15

0.2A

AR15

AN12

0.8A

AP12

AP13

0.2A

AR12

AW19

7A

AU17
AU19
AV17
AV19

AW17

AL12
AL13
AL15
AL18
AL21
AN13
AN16
AN19
AN22

AR17

1

CC117

2

0.22U_0402_10V6K

+APU_CORE_NB

+5VALW

RC146
10K_0402_5%

1 2

RC148 1K_0402_5%

RC153

1 2

0_0603_5%

1 2

RC156

0_0603_5%@

+3VALW_APU_FCH

8

UC6B

5

P

+_2

COMP_OUT2

7

O2

6

-_2

G

AS393MTR-G1_SO8

4

RC2548 0_0402_5%@

1 2

POWER

VDDIO_MEM_S3_1
VDDIO_MEM_S3_2
VDDIO_MEM_S3_3
VDDIO_MEM_S3_4
VDDIO_MEM_S3_5
VDDIO_MEM_S3_6
VDDIO_MEM_S3_7
VDDIO_MEM_S3_8
VDDIO_MEM_S3_9
VDDIO_MEM_S3_10
VDDIO_MEM_S3_11
VDDIO_MEM_S3_12
VDDIO_MEM_S3_13
VDDIO_MEM_S3_14
VDDIO_MEM_S3_15
VDDIO_MEM_S3_16
VDDIO_MEM_S3_17
VDDIO_MEM_S3_18
VDDIO_MEM_S3_19
VDDIO_MEM_S3_20
VDDIO_MEM_S3_21
VDDIO_MEM_S3_22
VDDIO_MEM_S3_23
VDDIO_MEM_S3_24
VDDIO_MEM_S3_25
VDDIO_MEM_S3_26
VDDIO_MEM_S3_27
VDDIO_MEM_S3_28
VDDIO_MEM_S3_29
VDDIO_MEM_S3_30
VDDIO_MEM_S3_31
VDDIO_MEM_S3_32
VDDIO_MEM_S3_33
VDDIO_MEM_S3_34
VDDIO_MEM_S3_35

VDDIO_AUDIO

VDDP_GFX_2
VDDP_GFX_1

VDD_33_1
VDD_33_2

VDD_18_1
VDD_18_2

VDD_18_S5_1
VDD_18_S5_2

VDD_33_S5_1
VDD_33_S5_2

VDDP_S5_1
VDDP_S5_2

VDDCR_FCH_S5_1
VDDCR_FCH_S5_2

VDDP_6
VDDP_1
VDDP_2
VDDP_3
VDDP_4
VDDP_5

VDDCR_NB_1
VDDCR_NB_2
VDDCR_NB_3
VDDCR_NB_4
VDDCR_NB_5
VDDCR_NB_6
VDDCR_NB_7
VDDCR_NB_8
VDDCR_NB_9

VDDBT_RTC_G

FP4 REV 0.93

AMD-CARRIZO_FP4-BGA968

CPU@

QC14

AON6414AL_DFN8-5

5

4

12

+5VALW

RC157
10K_0402_5%

1 2

RC158 1K_0402_5%

UC1F

VDDCR_CPU_1
VDDCR_CPU_2
VDDCR_CPU_3
VDDCR_CPU_4
VDDCR_CPU_5
VDDCR_CPU_6
VDDCR_CPU_7
VDDCR_CPU_8

VDDCR_CPU_9
VDDCR_CPU_10
VDDCR_CPU_11
VDDCR_CPU_12
VDDCR_CPU_13
VDDCR_CPU_14
VDDCR_CPU_15
VDDCR_CPU_16
VDDCR_CPU_17
VDDCR_CPU_18
VDDCR_CPU_19
VDDCR_CPU_20
VDDCR_CPU_21
VDDCR_CPU_22
VDDCR_CPU_23
VDDCR_CPU_24
VDDCR_CPU_25
VDDCR_CPU_26
VDDCR_CPU_42
VDDCR_CPU_31
VDDCR_CPU_43
VDDCR_CPU_32
VDDCR_CPU_44
VDDCR_CPU_33
VDDCR_CPU_45
VDDCR_CPU_34
VDDCR_CPU_46
VDDCR_CPU_35
VDDCR_CPU_47
VDDCR_CPU_36
VDDCR_CPU_28
VDDCR_CPU_29
VDDCR_CPU_40
VDDCR_CPU_30
VDDCR_CPU_37
VDDCR_CPU_49
VDDCR_CPU_38
VDDCR_CPU_39
VDDCR_CPU_48
VDDCR_CPU_41
VDDCR_CPU_27

VDDCR_GFX_14
VDDCR_GFX_15
VDDCR_GFX_16
VDDCR_GFX_17
VDDCR_GFX_18
VDDCR_GFX_19
VDDCR_GFX_20
VDDCR_GFX_21
VDDCR_GFX_22
VDDCR_GFX_23
VDDCR_GFX_24
VDDCR_GFX_25
VDDCR_GFX_26
VDDCR_GFX_27
VDDCR_GFX_28
VDDCR_GFX_29

VDDCR_GFX_1

VDDCR_GFX_2

VDDCR_GFX_3

VDDCR_GFX_4

VDDCR_GFX_5

VDDCR_GFX_6

VDDCR_GFX_7

VDDCR_GFX_8

VDDCR_GFX_9
VDDCR_GFX_10
VDDCR_GFX_11
VDDCR_GFX_12
VDDCR_GFX_30
VDDCR_GFX_31
VDDCR_GFX_32
VDDCR_GFX_33
VDDCR_GFX_34
VDDCR_GFX_35
VDDCR_GFX_36
VDDCR_GFX_37
VDDCR_GFX_13

1
2
3

RC151

5

1 2

AON6414AL_DFN8-5

4

12

3

+APU_CORE

U8

EDC 55A TDC 39A

W7
W12
W15
W18
W21
Y8
Y10
Y13
Y16
Y19
Y22
AB7
AB9
AB12
AB15
AB18
AB21
AD6
AD10
AD13
AD16
AD19
AD22
AE7
AE12
AK9
AG10
AK10
AG13
AK13
AG16
AK16
AG19
AK19
AG22
AK22
AH7
AE18
AE21
AH21
AG6
AH12
AN6
AH15
AH18
AL7
AK6
AE15

+APU_GFX

L8
L13
L16
L19
L22
N7
N12
N15
N18
N21
P8
P13
P16
P19
P22
T7
F12
F15
G11
G14
J8
J9
J11
K7
K12
K13
K15
K16
T12
T15
T18
T21
U13
U16
U19
U22
K19

1 2

RC144

AON6414AL_DFN8-5

1
2
3

4

0_0603_5%@

1
2
3

QC17

+APU_CORE

1

CC59

2

+APU_GFX

1

CC66

2

+1.35V

EDC 45A TDC 30A

VDDCR_CPU

VDDCR_NB

VDDCR_GFX

VDDIO_MEM_S3

VDDCR_FCH_S5

VDDP

VDDP_GFX

VDDP_S5

VDD_18

VDD_18_S5

VDD_33

VDD_33_S5

VDDIO_AUDIO

VDDBT_RTC_G

0_0603_5%@

QC15

5

1 2

RC152

AON6414AL_DFN8-5

1
2
3

4

2

1

1

2

1

2

1

2

0.22U_0402_10V6K

CC70

0.22U_0402_10V6K

CC84

0.22U_0402_10V6K

1

CC60

CC42

2

0.22U_0402_10V6K

1

1

CC71

2

2

0.22U_0402_10V6K

1

2

0.22U_0402_10V6K

3*22uf 0603 NC

+VDDCR_FCH_S5

0_0603_5%

1

2

0.22U_0402_10V6K

CC72

0.22U_0402_10V6K

CC85

CC120

@

1

CC61

2

1

2

0.22U_0402_10V6K

1

2

180P_0402_50V8-J

1

CC62

CC43

2

2

0.22U_0402_10V6K

0.22U_0402_10V6K

1

1

CC74

CC73

2

2

0.22U_0402_10V6K

0.22U_0402_10V6K

1

CC86

2

180P_0402_50V8-J

9*22uf 0805
8*0.22uf 0402
1*180pf 0402
6*22uf 0805
8*0.22uf 0402
1*180pf 0402
9*22uf 0805
9*0.22uf 0402
1*180pf 0402
8*22uf 0603
6*0.22uf 0402 split*4
1*180pf 0402 split*2
2*10uf 0603
1*0.22uf 0402

4*10uf 0603
6*0.22uf 0402
1*180pf 0402
1*10uf 0603
1*0.22uf 0402

1*10uf 0603
1*0.22uf 0402

1*22uf 0603 NC
1*10uf 0402

1*0.22uf 0402

1*10uf 0603
1*0.22uf 0402

1*10uf 0603

1*10uf 0403
1*0.22uf 0402

180P_0402_50V8-J

3*1uf 0402

1*0.22uf 0402

1

1

2

1

CC121

@

4.7U_0603_6.3V6K

+APU_CORE_NB +APU_CORE

1

2

RF_NS@

CC123

CC122

2

2

@

@

22U_0805_6.3V6M

4.7U_0603_6.3V6K

CC159

33P_0402_50V8J

CC160

33P_0402_50V8J

1

2

RF_NS@

RF_NS@

1

CC75

2

180P_0402_50V8-J

1

2

22U_0805_6.3V6M

CC161

33P_0402_50V8J

1

2

1

CC124

2

Decoupling cap
near APU ball

1

2

RF_NS@

1

1

CC39

CC40

CC41

2

2

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

OK

1

1

CC67

CC69

CC68

2

2

0.22U_0402_10V6K

0.22U_0402_10V6K

0.22U_0402_10V6K

OK

1

1

CC82

CC83

CC81

2

2

0.22U_0402_10V6K

0.22U_0402_10V6K

DECOUPLING BETWEEN PROCESSOR AND DIMMs
ACROSS VDDIO AND VSS SPLIT

Design Guide CRBY51-75

8*22uf 0603
6*0.22uf 0402
1*180pf 0402
6*22uf 0603
8*0.22uf 0402
1*180pf 0402
9*22uf 0603
9*0.22uf 0402
1*180pf 0402
8*22uf 0603
6*0.22uf 0402 split*4
1*180pf 0402 split*2
2*10uf 0402
1*0.22uf 0402

4*10uf 0402
6*0.22uf 0402
1*180pf 0402
1*10uf 0402
1*0.22uf 0402

1*10uf 0402
1*0.22uf 0402

1*10uf 0402
1*0.22uf 0402

1*10uf 0402
1*0.22uf 0402

1*10uf 0603

1*10uf 0603
1*0.22uf 0402

3*1uf 0402

1*0.22uf 0402

QC1/QC2/QC3/QC4 Rds on should less possible, CRB is 11.8mohm,
there is no load swtich for 0.775V power, so it need mos

RC145

1 2

0_0603_5%@

5

QC18

For RF

+1.35V

1

1

CC165

.1U_0402_10V6-K

EMC_NS@

2

2

+0.95VS +APU_CORE_NB

1

1

CC169

.1U_0402_10V6-K

EMC_NS@

2

2

For EMC

9*22uf 0603
8*0.22uf 0402
1*180pf 0402
6*22uf 0603
8*0.22uf 0402 split *5
1*180pf 0402
13*22uf 0603
9*0.22uf 0402
1*180pf 0402
8*22uf 0603
8*0.22uf 0402 split*4
1*180pf 0402 split*2
2*10uf 0603
1*0.22uf 0402

4*10uf 0603
6*0.22uf 0402
1*180pf 0402
1*10uf 0603
1*0.22uf 0402

1*10uf 0603
1*0.22uf 0402

1*10uf 0603

1*10uf 0603
1*0.22uf 0402

1*10uf 0603

1*10uf 0603
1*0.22uf 0402

3*1uf 0402

1*0.22uf 0402

1

1

CC125

CC126

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

0.22U_0402_10V6K

+1.35V

CC163

33P_0402_50V8J

CC164

33P_0402_50V8J

CC162

33P_0402_50V8J

1

1

2

2

RF_NS@

RF_NS@

1

+APU_CORE

1

CC166

.1U_0402_10V6-K

EMC_NS@

CC170

.1U_0402_10V6-K

EMC_NS@

1

CC167

.1U_0402_10V6-K

EMC_NS@

CC168

.1U_0402_10V6-K

EMC_NS@

2

2

1

1

CC171

.1U_0402_10V6-K

EMC_NS@

CC172

.1U_0402_10V6-K

EMC_NS@

2

2

+0.95VS +APU_CORE

+APU_CORE_NB

+0.95VS

@

1 2

CC177 .1U_0402_10V6-K

@

CC178 .1U_0402_10V6-K

1 2

@

CC179 .1U_0402_10V6-K

1 2

@

CC180 .1U_0402_10V6-K

1 2

@

CC182 .1U_0402_10V6-K

1 2

@

1 2

CC183 .1U_0402_10V6-K

+APU_CORE+APU_GFX

+APU_CORE

+0.95VGS

RESERVE SPLIT CAP

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2013/08/15

2013/08/15

2013/08/15

2

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2013/08/15

2013/08/15

2013/08/15

Title

FP4 (POWER&DECOUPLING)

FP4 (POWER&DECOUPLING)

FP4 (POWER&DECOUPLING)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Allsparks 5B

Allsparks 5B

Allsparks 5B

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

1

9 51

9 51

9 51

0.3

0.3

0.3

5

4

3

2

1

UC1G

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62

GND

VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98

VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124

FP4 REV 0.93

AMD-CARRIZO_FP4-BGA968

L28
M4
M30
N10
N13
N16
N19
N22
N27
P1
P2
P4
P5
P12
P15
P18
P21
P30
P33
T4
T10
T13
T16
T19
T22
T30
U5
U12
U15
U18
U21
U24
V1
V2
V4
W10
W13
W16
W19
W22
Y4
Y5
Y12
Y15
Y18
Y21
Y24
AB1
AB2
AB4
AB10
AB13
AB16
AB19
AB22
AD4
AD9
AD12
AD15
AD18
AD21
AD24

A8
A12
A16
A20
A24

D D

C C

B B

A28
A32

B12
B33

D10
D12
D14
D16
D18
D20
D22
D24
D26
D28
D30

F19
F22
F25
F30
F33

G17
G20
G23
G26

H30

J15
J19
J22
J25
J28

K10
K22
K27
K30
K33

L12
L15
L18
L21
L25

B2

B8

C3
D4
D6
D8

F1

F2

F4

F9

G7

H4

J5

K1

K2

K4

L5

CPU@

AE10
AE13
AE16
AE19
AE22

AF1
AF4

AG9
AG12
AG15
AG18
AG21

AH4

AH10
AH13
AH16
AH19
AH22

AK1

AK4
AK12
AK15
AK18

AL16
AL19
AL22

AM4

AN9
AN10
AN15
AN18
AN21
AN25
AN28

AP1
AP2
AP4

AP7
AP22
AP27
AP30
AP33

AR6
AR25
AR28

AT4
AT19
AT22
AT30

AU5

AU8
AU11
AU14
AU20
AU23
AU27

AV4
AV7

AV9
AV12
AV15
AV25

VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186

CPU@

UC1H

GND

VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212

VSS_213
VSS_215
VSS_214

FP4 REV 0.93

AMD-CARRIZO_FP4-BGA968

AV30
AV33
AW22
AY4
AY6
AY8
AY10
AY12
AY14
AY16
AY20
AY22
AY24
AY26
AY28
AY30
BB1
BB33
BC4
BC8
BC12
BC16
BC20
BC24
BC28
BC32

L24
AL10
AK21

UC1J

1

TC41@

1

TC42@

1

TC43@

U30
U31

AN30

RSVD_2
RSVD_3
RSVD_4

CPU@

FP4 REV 0.93

AMD-CARRIZO_FP4-BGA968

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

2013/08/15

2013/08/15

2013/08/15

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

3

2013/08/15

2013/08/15

2013/08/15

Title

FP4 (VSS)

FP4 (VSS)

FP4 (VSS)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet of

2

Wednesday, April 29, 2015

Allsparks 5B

Allsparks 5B

Allsparks 5B

10 51

10 51

10 51

1

0.3

0.3

0.3

5

4

3

2

+3VALW_APU +3VALW_APU +3VALW_APU +3VALW_APU+3VALW_APU+3VALW_APU +3VALW_APU +3VS_APU+3VS_APU +3VS_APU +3VS_APU

1

RC173
2K_0402_5%

@

12

RC167
10K_0402_5%

12

RC174
2K_0402_5%

@

12

RC168
10K_0402_5%

12

RC175
2K_0402_5%

@

RC179
10K_0402_5%

1 2

12

RC178
2K_0402_5%

@

12

RC163
10K_0402_5%

@

12

12

RC164
10K_0402_5%

@

RC171
2K_0402_5%

12

12

RC160
10K_0402_5%

@

RC169
2K_0402_5%

@

12

RC159

D D

LPC_FRAME#8,35,36

CLK1_PCI_TPM8,36

CLK0_PCI_EC8,35

AGPIO37

SYS_RESET#7

SUSCLK7,30

BLINK7

Connect to VSS to enable. If not used, leave

C C

unconnected to disable AMD Hardware Validated Boot

HVB_EN7

10K_0402_5%

12

RC161
10K_0402_5%

12

12

RC162
10K_0402_5%

@

RC170
2K_0402_5%

@

12

RC165
10K_0402_5%

12

RC172
2K_0402_5%

@

12

RC166
10K_0402_5%

12

STRAP PINS

LFRAME_L LPCCLK1 LPCCLK0 GEVENT2_L/AGPIO3 SYS_RESET_L RTCCLK BLINK(for CZL strap)

Signal

Int pull-up Int pull-up Int pull-up Int pull-up

Type II II I I I

PULL
HIGH

B B

PULL
LOW

II

SPI ROM

LPC ROM

Internal
CLK Gen

DefaultDefault

Reserved

Boot Fail Timer
Enabled

Boot Fail Timer
Disabled

Default

CZL CZ

Enhanced reset

1.8V SPI

logic (for quicker
S5 resume)

Default

Default to

3.3VSPI

traditional
reset logic

Default

III

Normal Power Up
&Reset Timing

Default Default

Reserved

Coin Battery

Direct DC

PWROK and RST_L
pin routed to APU

Default

Reserved

HVB_EN

II

floating

Disable HVB
on FP4 platforms

Default

connected to VSS

Enable HVB
on FP4 platforms

Type I straps become valid immediately after capture with the rising edge of RSMRST_L,they are captured only once when power is first applied to the processor

Type II straps become valid after PWR_GOOD is asserted,straps are captured every time the systems powers up from the S5 state. A transition from S3 to S0 does not trigger capture.
Type II straps should be pulled up to S0 power rail to prevent leakage when the signal is connected to a device in S0 power domain.

If the LPC bus is connected to devices that are on S0 power rail, then a pull-up resistor to VDD_33 is implemented.

All Strap pins must be configured with either external pull-up or pull-down resistors.

Platforms that are designed for AOAC complaint are recommended to use the Alternate Reset by strapping this pin to ‘1’ for CZ AGPIO3

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2013/08/15

2013/08/15

2013/08/15

3

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2013/08/15

2013/08/15

2013/08/15

2

Title

FP4 (STRAPS)

FP4 (STRAPS)

FP4 (STRAPS)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Allsparks 5B

Allsparks 5B

Allsparks 5B

11 51

11 51

11 51

1

of

0.3

0.3

0.3

DDR3 SO-DIMM A

5

4

3

2

1

DDRA_DQ[0..63]

DDRA_DQS[0..7]

APU_MA_VREFDQ5

DDRA_DQS#[0..7]

DDRA_MA[0..15]

DDRA_DM[0..7]

3A@1.5V

+1.35V

CD5

+1.35V

CD17

CD26

1

2

1

2

+0.675VS

DDR3 SO-DIMM A

VSS_2

VSS_4

DQS0#

DQS0

VSS_6

VSS_8

DQ12
DQ13

VSS_10

VSS_12

DQ14
DQ15

VSS_14

DQ20
DQ21

VSS_16

VSS_18

DQ22
DQ23

VSS_20

DQ28
DQ29

VSS_22

DQS3#

DQS3

VSS_24

DQ30
DQ31

VSS_26

CKE1

VDD_2

VDD_4

VDD_6

VDD_8

CK1#

RAS#

ODT0

ODT1

NC_2

VSS_28

DQ36
DQ37

VSS_30

VSS_32

DQ38
DQ39

VSS_34

DQ44
DQ45

VSS_35

DQS5#

DQS5

VSS_38

DQ46
DQ47

VSS_40

DQ52
DQ53

VSS_42

VSS_44

DQ54
DQ55

VSS_46

DQ60
DQ61

VSS_48

DQS7#

DQS7

VSS_50

DQ62
DQ63

VSS_52

VTT_2

GND2

BOSS2

+1.35V+1.35V

2

DDRA_DQ4

4

DQ4
DQ5

DQ6
DQ7

DM1

DM2

A15
A14

A11

A7

A6
A4

A2
A0

CK1

BA1

S0#

DM4

DM6

SDA
SCL

6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206
208

DDRA_DQ5

DDRA_DQS#0
DDRA_DQS0

DDRA_DQ6
DDRA_DQ7

DDRA_DQ12
DDRA_DQ13

DDRA_DM1
MEM_MA_RST#_C

DDRA_DQ14
DDRA_DQ15

DDRA_DQ20
DDRA_DQ21

DDRA_DM2

DDRA_DQ22
DDRA_DQ23

DDRA_DQ28
DDRA_DQ29

DDRA_DQS#3
DDRA_DQS3

DDRA_DQ30
DDRA_DQ31

DDRA_CKE1

DDRA_MA15
DDRA_MA14

DDRA_MA11
DDRA_MA7

DDRA_MA6
DDRA_MA4

DDRA_MA2
DDRA_MA0

DDRA_CLK1
DDRA_CLK1#

DDRA_BS1#
DDRA_RAS#

DDRA_CS0#
DDRA_ODT0

DDRA_ODT1

DDRA_DQ36
DDRA_DQ37

DDRA_DM4

DDRA_DQ38
DDRA_DQ39

DDRA_DQ44
DDRA_DQ45

DDRA_DQS#5
DDRA_DQS5

DDRA_DQ46
DDRA_DQ47

DDRA_DQ52
DDRA_DQ53

DDRA_DM6

DDRA_DQ54
DDRA_DQ55

DDRA_DQ60
DDRA_DQ61

DDRA_DQS#7
DDRA_DQS7

DDRA_DQ62
DDRA_DQ63

MEM_MA_EVENT#
APU_SMB_DATA
APU_SMB_CLK

1

CD69
33P_0402_50V8J

RF_NS@

2

1 2

R895 0_0402_5%

DDRA_CKE1 5

DDRA_CLK1 5
DDRA_CLK1# 5

DDRA_BS1# 5
DDRA_RAS# 5

DDRA_CS0# 5
DDRA_ODT0 5

DDRA_ODT1 5

MEM_MA_EVENT# 5
APU_SMB_DATA 7,13,30
APU_SMB_CLK 7,13,30

+0.675VS

0.65A@0.675V

MEM_MA_RST# 5

+VREF_CA_A0

D D

C C

B B

1 2

RD22 0_0402_5%

1 2

RD23 0_0402_5%

+1.35V

1 2

RC183 1K_0402_5%

A A

SA0_DIM1

SA1_DIM1

MEM_MA_EVENT#

2.2U_0603_10V6-K

+3VS

+VREF_MA_DQ

DDRA_DQ0
DDRA_DQ1

DDRA_DM0

DDRA_DQ2
DDRA_DQ3

DDRA_DQ8
DDRA_DQ9

DDRA_DQS#1
DDRA_DQS1

DDRA_DQ10
DDRA_DQ11

DDRA_DQ16
DDRA_DQ17

DDRA_DQS#2
DDRA_DQS2

DDRA_DQ18
DDRA_DQ19

DDRA_DQ24
DDRA_DQ25

DDRA_DM3

DDRA_DQ26
DDRA_DQ27

1

CD68
.1U_0402_10V6-K

2

DDRA_CKE0

DDRA_BS2#

DDRA_MA12
DDRA_MA9

DDRA_MA8
DDRA_MA5

DDRA_MA3
DDRA_MA1

DDRA_CLK0
DDRA_CLK0#

DDRA_MA10
DDRA_BS0#

DDRA_WE#
DDRA_CAS#

DDRA_MA13
DDRA_CS1#

DDRA_DQ32
DDRA_DQ33

DDRA_DQS#4
DDRA_DQS4

DDRA_DQ34
DDRA_DQ35

DDRA_DQ40
DDRA_DQ41

DDRA_DM5

DDRA_DQ42
DDRA_DQ43

DDRA_DQ48
DDRA_DQ49

DDRA_DQS#6
DDRA_DQS6

DDRA_DQ50
DDRA_DQ51

DDRA_DQ56
DDRA_DQ57

DDRA_DM7

DDRA_DQ58
DDRA_DQ59

SA0_DIM1

SA1_DIM1

DDRA_CKE05

DDRA_BS2#5

DDRA_CLK05
DDRA_CLK0#5

DDRA_BS0#5

DDRA_WE#5
DDRA_CAS#5

DDRA_CS1#5

1

CD63

2

CD@

3A@1.5V

JDDRL1

1
3
5
7
9

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

73
75
77
79
81
83
85
87
89
91
93
95
97

99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

205
207

LCN_DAN06-K4406-0103

ME@

SMBUS ADD 0XA0h

VREF_DQ
VSS_1
DQ0
DQ1
VSS_3
DM0
VSS_5
DQ2
DQ3
VSS_7
DQ8
DQ9
VSS_9
DQS1#
DQS1
VSS_11
DQ10
DQ11
VSS_13
DQ16
DQ17
VSS_15
DQS2#
DQS2
VSS_17
DQ18
DQ19
VSS_19
DQ24
DQ25
VSS_21
DM3
VSS_23
DQ26
DQ27
VSS_25

CKE0
VDD_1
NC_1
BA2
VDD_3
A12/BC#
A9
VDD_5
A8
A5
VDD_7
A3
A1
VDD_9
CK0
CK0#
VDD_11
A10/AP
BA0
VDD_13
WE#
CAS#
VDD_15
A13
S1#
VDD_17
TEST
VSS_27
DQ32
DQ33
VSS_29
DQS4#
DQS4
VSS_31
DQ34
DQ35
VSS_33
DQ40
DQ41
VSS_36
DM5
VSS_37
DQ42
DQ43
VSS_39
DQ48
DQ49
VSS_41
DQS6#
DQS6
VSS_43
DQ50
DQ51
VSS_45
DQ56
DQ57
VSS_47
DM7
VSS_49
DQ58
DQ59
VSS_51
SA0
VDDSPD
SA1
VTT_1

GND1
BOSS1

RESET#

VDD_10

VDD_12

VDD_14

VDD_16

VDD_18

VREF_CA

EVENT#

DDRA_DQ[0..63] 5

DDRA_DQS[0..7] 5

DDRA_DQS#[0..7] 5

DDRA_MA[0..15] 5

DDRA_DM[0..7] 5

1 2

R1 0_0402_5%

Layout Note:
Place near DIMM1

.1U_0402_10V6-K

.1U_0402_10V6-K

CD7

CD6

1

@

2

10U_0805_10V6K

10U_0805_10V6K

1

CD19

CD18

2

Layout Note:
Place near DIMM1

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

CD28

CD27

@

2

2

+1.35V

12

RD1
1K_0402_1%

+VREF_MA_DQ

20mil 20mil

1

CD10

1

2

2

1

@

2

EMI

4.7U_0603_6.3V6K

CD22

1

CD1

2

.1U_0402_10V6-K

.1U_0402_10V6-K

CD11

4.7U_0603_6.3V6K

1

2

EMC@

MEM_MA_RST#_C

CD2

CD58

1000P_0402_50V7K

.1U_0402_10V6-K

.1U_0402_10V6-K

CD12

1

1

@

2

2

0.047U_0402_16V7K

1

CD23

@

2

.1U_0402_10V6-K

1

@

2

RD3
1K_0402_1%

1 2

.1U_0402_10V6-K

.1U_0402_10V6-K

CD8

1

2

22U_0805_6.3V6M

1

CD20

2

1U_0402_6.3V6K

1

CD29

2

.1U_0402_10V6-K

CD9

1

1

@

2

2

22U_0603_6.3V6-M

1

CD21

@

2

EMC@

4.7U_0603_6.3V6K

1

@

2

CD13

RD2

1K_0402_1%

RD4

1K_0402_1%

.1U_0402_10V6-K

CD14

1

2

1

CD24
33P_0402_50V8J

2

RF_NS@

+1.35V

EMC@

12

12

.1U_0402_10V6-K

CD15

1

2

1

2

1

CD3

2

.1U_0402_10V6-K

.1U_0402_10V6-K

CD16

1

@

2

CD25
33P_0402_50V8J

RF_NS@

1

2

1

2

EMC@

+VREF_CA_A0

CD4

1000P_0402_50V7K

.1U_0402_10V6-K

RF

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2014/10/22

2014/10/22

2014/10/22

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/10/22

2014/10/22

2014/10/22

Title

DDRIII SO-DIMM A

DDRIII SO-DIMM A

DDRIII SO-DIMM A

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet of

Allsparks 5B

Allsparks 5B

Allsparks 5B

1

12 51

12 51

12 51

0.3

0.3

0.3

DDR3 SO-DIMM B

5

4

3

2

1

DDRB_DQ[0..63]

DDR3 SO-DIMM B

D D

C C

B B

+3VS

RD20 4.7K_0402_5%

1 2

RD24 0_0402_5%

+1.35V

1 2

RC7 1K_0402_5%

A A

SA0_DIM2

12

SA1_DIM2

MEM_MB_EVENT#

+3VS

2.2U_0603_10V6-K

+VREF_MB_DQ

DDRB_DQ0
DDRB_DQ1

DDRB_DM0

DDRB_DQ2
DDRB_DQ3

DDRB_DQ8
DDRB_DQ9

DDRB_DQS#1
DDRB_DQS1

DDRB_DQ10
DDRB_DQ11

DDRB_DQ16
DDRB_DQ17

DDRB_DQS#2
DDRB_DQS2

DDRB_DQ18
DDRB_DQ19

DDRB_DQ24
DDRB_DQ25

DDRB_DM3

DDRB_DQ26

+1.35V +1.35V

DDRB_CKE05

DDRB_BS2#5

DDRB_CLK05
DDRB_CLK0#5

DDRB_BS0#5

DDRB_WE#5
DDRB_CAS#5

DDRB_CS1#5

1

1

2

CD137
.1U_0402_10V6-K

2

CD72

CD@

DDRB_DQ27

DDRB_CKE0

DDRB_BS2#

DDRB_MA12
DDRB_MA9

DDRB_MA8
DDRB_MA5

DDRB_MA3
DDRB_MA1

DDRB_CLK0
DDRB_CLK0#

DDRB_MA10
DDRB_BS0#

DDRB_WE#
DDRB_CAS#

DDRB_MA13
DDRB_CS1#

DDRB_DQ32
DDRB_DQ33

DDRB_DQS#4
DDRB_DQS4

DDRB_DQ34
DDRB_DQ35

DDRB_DQ40
DDRB_DQ41

DDRB_DM5

DDRB_DQ42
DDRB_DQ43

DDRB_DQ48
DDRB_DQ49

DDRB_DQS#6
DDRB_DQS6

DDRB_DQ50
DDRB_DQ51

DDRB_DQ56
DDRB_DQ57

DDRB_DM7

DDRB_DQ58
DDRB_DQ59

SA0_DIM2

SA1_DIM2

JDDRH1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1
VSS49DQS#0

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2
DQS247VSS17
VSS1849DQ22

51

DQ18
DQ1953VSS19
VSS2055DQ28

57

DQ24
DQ2559VSS21
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3
A12/BC#83A11

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1
VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

LCN_DAN06-K4806-0103

ME@

SMBUS ADD 0XA2h

DQ4
DQ5

VSS3

DQS0

VSS6

DQ6
DQ7

VSS8
DQ12
DQ13

VSS10

DM1

DQ14
DQ15

DQ20
DQ21

DM2

DQ23

DQ29

DQS3

DQ30
DQ31

CKE1
VDD2

VDD4

VDD6

VDD8

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

DM4

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

DM6

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

SDA

VTT2

2

DDRB_DQ4

4

DDRB_DQ5

6
8

DDRB_DQS#0

10

DDRB_DQS0

12
14

DDRB_DQ6

16

DDRB_DQ7

18
20

DDRB_DQ12

22

DDRB_DQ13

24
26

DDRB_DM1

28

MEM_MB_RST#_C

30
32

DDRB_DQ14

34

DDRB_DQ15

36
38

DDRB_DQ20

40

DDRB_DQ21

42
44

DDRB_DM2

46
48

DDRB_DQ22

50

DDRB_DQ23

52
54

DDRB_DQ28

56

DDRB_DQ29

58
60

DDRB_DQS#3

62

DDRB_DQS3

64
66

DDRB_DQ30

68

DDRB_DQ31

70
72

DDRB_CKE1

74
76

DDRB_MA15

78

A15
A14

A7

A6
A4

A2
A0

CK1

BA1

S0#

SCL

G2

80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

DDRB_MA14

DDRB_MA11
DDRB_MA7

DDRB_MA6
DDRB_MA4

DDRB_MA2
DDRB_MA0

DDRB_CLK1
DDRB_CLK1#

DDRB_BS1#
DDRB_RAS#

DDRB_CS0#
DDRB_ODT0

DDRB_ODT1

DDRB_DQ36
DDRB_DQ37

DDRB_DM4

DDRB_DQ38
DDRB_DQ39

DDRB_DQ44
DDRB_DQ45

DDRB_DQS#5
DDRB_DQS5

DDRB_DQ46
DDRB_DQ47

DDRB_DQ52
DDRB_DQ53

DDRB_DM6

DDRB_DQ54
DDRB_DQ55

DDRB_DQ60
DDRB_DQ61

DDRB_DQS#7
DDRB_DQS7

DDRB_DQ62
DDRB_DQ63

MEM_MB_EVENT#
APU_SMB_DATA
APU_SMB_CLK

1

CD142
33P_0402_50V8J

RF_NS@

2

1 2

R896 0_0402_5%

DDRB_CKE1 5

DDRB_CLK1 5
DDRB_CLK1# 5

DDRB_BS1# 5
DDRB_RAS# 5

DDRB_CS0# 5
DDRB_ODT0 5

DDRB_ODT1 5

+VREF_CA_B0

MEM_MB_EVENT# 5
APU_SMB_DATA 7,12,30
APU_SMB_CLK 7,12,30

+0.675VS

0.65A@0.75V

RF

MEM_MB_RST# 5

APU_MB_VREFDQ5

DDRB_DQS[0..7]

DDRB_DQS#[0..7]

DDRB_MA[0..15]

DDRB_DM[0..7]

1 2

R176 0_0402_5%

3A@1.5V

+1.35V

Layout Note:
Place near DIMM2

.1U_0402_10V6-K

CD136

+1.35V

CD62

.1U_0402_10V6-K

CD138

1

1

@

2

2

10U_0805_10V6K

10U_0805_10V6K

1

1

CD129

2

2

CD130

CD126

CD66

+0.675VS

1

2

DDRB_DQ[0..63] 5

DDRB_DQS[0..7] 5

DDRB_DQS#[0..7] 5

DDRB_MA[0..15] 5

DDRB_DM[0..7] 5

+1.35V

12

RD18
1K_0402_1%

RD19
1K_0402_1%

1 2

.1U_0402_10V6-K

CD140

1

2

1

2

22U_0805_6.3V6M

Layout Note:
Place near DIMM2

1U_0402_6.3V6K

1

CD133

@

2

+VREF_MB_DQ

20mil 20mil

.1U_0402_10V6-K

CD33

1

1

2

2

.1U_0402_10V6-K

.1U_0402_10V6-K

CD125

CD135

1

2

1

2

22U_0603_6.3V6-M

1U_0402_6.3V6K

1

1

CD123

@

2

2

CD67

1

@

2

@

1U_0402_6.3V6K

CD124

+VREF_CA_A0

1 2

CD134

@

.1U_0402_10V6-K

1

2

0.047U_0402_16V7K

1

2

MEM_MB_RST#_C

R180 0_0402_5%

.1U_0402_10V6-K

CD141

CD127

1

@

2

0.047U_0402_16V7K

1

@

CD139

CD128

2

1

2

CD120

.1U_0402_10V6-K

@

1000P_0402_50V7K

CD34

.1U_0402_10V6-K

1

@

2

0.047U_0402_16V7K

1

@

CD71

2

4.7U_0603_6.3V6K

for MEM_MB_RST# overshoot issue

1K_0402_1%

1K_0402_1%

.1U_0402_10V6-K

1

2

+1.35V

RD25

RD26

CD122

1

2

12

@

12

@

.1U_0402_10V6-K

CD70

1

2

CD131
33P_0402_50V8J

RF_NS@

@

1

2

1

2

CD60

.1U_0402_10V6-K

.1U_0402_10V6-K

CD132

1

CD121
33P_0402_50V8J

2

RF_NS@

+VREF_CA_B0

1

CD61

2

1000P_0402_50V7K

.1U_0402_10V6-K

1

2

RF

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2014/10/22

2014/10/22

2014/10/22

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/10/22

2014/10/22

2014/10/22

Title

DDRIII SO-DIMM B

DDRIII SO-DIMM B

DDRIII SO-DIMM B

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet of

Allsparks 5B

Allsparks 5B

Allsparks 5B

1

13 51

13 51

13 51

0.3

0.3

0.3

5

4

3

2

1

Power-Up/Down Sequence

Multi-level Pin Straps

"Strato" has the following requirements with regards to power-supply
sequencing to avoid damaging the ASIC:

D D

C C

All the ASIC supplies must reach their respective nominal voltages within 20 ms
of the start of the ramp-up sequence, though a shorter ramp-up duration is
preferred. The maximum slew rate on all rails is 50 mV/µs.

It is recommended that the 3.3-V rail ramps up first.

The 3.3-V, 1.8-V, and 0.95-V rails must reach their ready states at least 10 µs
before VDDC and VDDCI start to ramp up.

The external pull ups on the DDC/AUX signals (if applicable) should ramp up
before or after both VDDC and VDD_CT have ramped up.

The power rails that are shared with other components on the system should be
gated for the dGPU so that when the dGPU is powered down (for example,
AMD PowerXpress idle state), all the power rails are removed from the dGPU.
The gate circuits must meet the slew rate requirement (such as ≤ 50 mV/µs).

For power down, reversing the ramp-up sequence is recommended.

0 ~ 20 ms

0 ~ 20 ms

MLPS Bit DescriptionStrap Name

PS_0[1]

ROM_CONFIG[0]

PS_0[2]

ROM_CONFIG[1]

PS_0[3]

ROM_CONFIG[2]

PS_0[4] N/A

AUD_PORT_CONN_
PINSTRAP[0]

PS_0[5]

PS_1[1]

STRAP_BIF_GEN3_EN_A

PS_1[2]

STRAP_BIF_CLK_PM_EN

PS_1[3]

PS_1[4]

PS_1[5]

PS_2[1]

PS_2[2]

PS_2[3]

PS_2[4]

PS_2[5]

PS_3[1]
PS_3[2]
PS_3[3]

PS_3[4]

PS_3[5]

N/A

STRAP_TX_CFG_DRV_
FULL_SWING

STRAP_TX_DEEMPH_EN

N/A

N/A

STRAP_BIOS_ROM_EN

STRAP_BIF_VGA_DIS

N/A Reserved 1

BOARD_CONFIG[0]
BOARD_CONFIG[1]
BOARD_CONFIG[2]

AUD_PORT_CONN_
PINSTRAP[1]

AUD_PORT_CONN_
PINSTRAP[2]

If STRAP_BIOS_ROM_EN = 1,ROM_CONFIG[2:0] define the ROM type.
If STRAP_BIOS_ROM_EN = 0,ROM_CONFIG[2:0] define the primary
memory-aperture size.
Reserved for internal use only.
Must be 1 at reset.

The LSB (least significant bit) of the strap option that indicates the number of
audio-capable display outputs.

PCIe GEN3 capability.
1 = PCIe GEN3 is supported.
0 = PCIe GEN3 is not supported.

0 = The CLKREQB power management capability is disabled
1 = The CLKREQB power management capability is enabled

0 = The transmitter half-swing is enabled
1 = The transmitter full-swing is enabled

0 = Tx deemphasis disabled.
1 = Tx deemphasis enabled.

Reserved.

Reserved.

0 = Disable the external BIOS ROM device.
1 = Enable the external BIOS ROM device.

0 = VGA controller capacity enabled.
1 = The device will not be recognized as the system’s VGA
controller.

Board configuration related strapping, such as for memory ID

Determines the maximum number of digital display audio endpoints
that will be presented to the OS and user.

111 = No usable endpoints.
110 = One usable endpoint.
101 = Two usable endpoints.
100 = Three usable endpoints.
011 = Four usable endpoints.
010 = Five usable endpoints.
001 = Six usable endpoints.
000 = All endpoints are usable.

RECOMMENDED
SETTINGS

Design dependent

1

Design dependent

Design dependent

0

0Reserved for internal use only. Must be 0 at reset.

1

Design dependent

0

0

Design dependent

0

Design dependent

Design dependent

VDDR3(+3VGS)

VDD_CT(+1.8VGS)

10us min

PCIE_VDDC(+0.95VGS)

B B

VDDR1(+1.35VGS)

VDDC(+GPU_VDDC)

VDDCI(+GPU_VDDCI)

PERSTb(GPU_RST#)

100 ms min

100 us min

REFCLK(CLK_PCIE_VGA)

A A

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2014/10/22

2014/10/22

2014/10/22

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/10/22

2014/10/22

2014/10/22

Title

VGA Notes List

VGA Notes List

VGA Notes List

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet of

Allsparks 5B

Allsparks 5B

Allsparks 5B

1

14 51

14 51

14 51

0.3

0.3

0.3

5

4

3

2

1

PCIE_CTX_C_GRX_P[7..0]

PCIE_CTX_C_GRX_N[7..0]

PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_N0

PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_N1

PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_N2

PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_N3

PCIE_CTX_C_GRX_P4
PCIE_CTX_C_GRX_N4

PCIE_CTX_C_GRX_P5
PCIE_CTX_C_GRX_N5

PCIE_CTX_C_GRX_P6
PCIE_CTX_C_GRX_N6

PCIE_CTX_C_GRX_P7
PCIE_CTX_C_GRX_N7

CLK_PCIE_GPU
CLK_PCIE_GPU#

(1.8V@100mA PCIE_PVDD)

(0.95V@1500mA BIF_VDDC)

(0.95V@2700mA PCIE_VDDC)

CV24

CV25

CV26

1

1

1

2

2

2

PX@

PX@

PX@

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

U1A

PART 2 OF 16

AH52

PCIE_RX0P

AH50

PCIE_RX0N

AG53

PCIE_RX1P

AG51

PCIE_RX1N

AF52

PCIE_RX2P

AF50

PCIE_RX2N

AE53

PCIE_RX3P

AE51

PCIE_RX3N

AD52

PCIE_RX4P

AD50

PCIE_RX4N

AC53

PCIE_RX5P

AC51

PCIE_RX5N

AA53

PCIE_RX6P

AA51

PCIE_RX6N

Y52

PCIE_RX7P

Y50

PCIE_RX7N

W53

PCIE_RX8P

W51

PCIE_RX8N

V52

PCIE_RX9P

V50

PCIE_RX9N

U53

PCIE_RX10P

U51

PCIE_RX10N

R53

PCIE_RX11P

R51

PCIE_RX11N

P52

PCIE_RX12P

P50

PCIE_RX12N

N53

PCIE_RX13P

N51

PCIE_RX13N

M52

PCIE_RX14P

M50

PCIE_RX14N

L53

PCIE_RX15P

L51

PCIE_RX15N

AJ51

PCIE_REFCLKP

AJ53

PCIE_REFCLKN

AU48

PCIE_PVDD_1

AR48

PCIE_PVDD_2

U43

BIF_VDDC_1

U44

BIF_VDDC_2

U42

BIF_VDDC_3

W43

BIF_VDDC_4

AA42

PCIE_VDDC_1

AA43

PCIE_VDDC_2

AC42

PCIE_VDDC_3

CV21

1

2

PX@

1U_0402_6.3V6K

AG43

AG42

AC43

AE42
AE43
AE44

AA44

W42

R42

N42
N43

L43

PCIE_VDDC_4
PCIE_VDDC_5
PCIE_VDDC_6
PCIE_VDDC_7
PCIE_VDDC_8
PCIE_VDDC_9
PCIE_VDDC_10
PCIE_VDDC_11

EVDDC

EVDDQ0
EVDDQ1
NC_EVDDQ2

GPU@

PCIE_TX0P
PCIE_TX0N

PCIE_TX1P
PCIE_TX1N

PCIE_TX2P
PCIE_TX2N

PCIE_TX3P
PCIE_TX3N

PCIE_TX4P
PCIE_TX4N

PCIE_TX5P
PCIE_TX5N

PCIE_TX6P
PCIE_TX6N

PCIE_TX7P
PCIE_TX7N

PCIE_TX8P
PCIE_TX8N

PCIE_TX9P
PCIE_TX9N

PCIE_TX10P
PCIE_TX10N

PCIE_TX11P
PCIE_TX11N

PCIE_TX12P
PCIE_TX12N

PCIEXPRESS

PCIE_TX13P
PCIE_TX13N

PCIE_TX14P
PCIE_TX14N

PCIE_TX15P
PCIE_TX15N

PCIE_CALR_RX
PCIE_CALR_TX

NC_PX_EN_1

PERSTB

+1.8VGS

PCIE_CTX_C_GRX_P[7..0]4

PCIE_CTX_C_GRX_N[7..0]4

CLK_PCIE_GPU8
CLK_PCIE_GPU#8

CV17

CV18

1

1

2

2

PX@

PX@

1U_0402_6.3V6K

10U_0603_6.3V6M

+0.95VGS

CV23

CV27

CV253

1

1

1

2

2

2

PX@

PX@

PX@

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

D D

C C

1 2

RV3 0_0402_5%@

B B

PXS_RST#7

PLT_RST#7,28,30

VR_VGA_PWRGD7,49

A A

+3VGS

5

1

VCC

IN1

2

IN2

GND

MC74VHC1G08DFT2G_SC70-5

3

PX@

GPU_RST#

VR_VGA_PWRGD

OUT

UV1

4

GPU_RST#

DV1

2

3

BAT54AW_SOT323-3

1 2

RV313

PX@

0_0402_5%@

1

GPU_RST# 16,19

VGA_PWROK

VGA_PWROK 49

PCIE_CRX_GTX_P[7..0]

PCIE_CRX_GTX_N[7..0]

PCIE_CRX_C_GTX_P0 PCIE_CRX_GTX_P0

AL48

PCIE_CRX_C_GTX_N0 PCIE_CRX_GTX_N0

AL47

PCIE_CRX_C_GTX_P1

AL45

PCIE_CRX_C_GTX_N1

AL44

PCIE_CRX_C_GTX_P2

AJ48

PCIE_CRX_C_GTX_N2 PCIE_CRX_GTX_N2

AJ47

PCIE_CRX_C_GTX_P3

AG48

PCIE_CRX_C_GTX_N3

AG47

PCIE_CRX_C_GTX_P4

AG45

PCIE_CRX_C_GTX_N4

AG44

PCIE_CRX_C_GTX_P5

AE48

PCIE_CRX_C_GTX_N5

AE47

PCIE_CRX_C_GTX_P6

AC48

PCIE_CRX_C_GTX_N6

AC47

AC45

PCIE_CRX_C_GTX_N7

AC44

AA48
AA47

W48
W47

W45
W44

U48
U47

R48
R47

R45
R44

N48
N47

L48
L47

AN47
AN48

AK50

J48

PX_EN

J45

STRATO-M3-XT_FCBGA1093

RV2 1K_0402_1%PX@
RV1 1.69K_0402_1%PX@

12

RV304

PX@

1K_0402_5%

1 2
1 2

PX_EN

PCIE_CRX_GTX_P[7..0] 4

PCIE_CRX_GTX_N[7..0] 4

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

+0.95VGS

PX_EN 7,19

RV4

CV10.22U_0402_16V6-K PX@
CV20.22U_0402_16V6-K PX@

CV30.22U_0402_16V6-K PX@
CV40.22U_0402_16V6-K PX@

CV50.22U_0402_16V6-K PX@
CV60.22U_0402_16V6-K PX@

CV70.22U_0402_16V6-K PX@
CV80.22U_0402_16V6-K PX@

CV90.22U_0402_16V6-K PX@
CV100.22U_0402_16V6-K PX@

CV110.22U_0402_16V6-K PX@
CV120.22U_0402_16V6-K PX@

CV130.22U_0402_16V6-K PX@
CV140.22U_0402_16V6-K PX@

CV150.22U_0402_16V6-K PX@
CV160.22U_0402_16V6-K PX@

GPU_RST#

12

PCIE_CRX_GTX_P1
PCIE_CRX_GTX_N1

PCIE_CRX_GTX_P2

PCIE_CRX_GTX_P3
PCIE_CRX_GTX_N3

PCIE_CRX_GTX_P4
PCIE_CRX_GTX_N4

PCIE_CRX_GTX_P5
PCIE_CRX_GTX_N5

PCIE_CRX_GTX_P6
PCIE_CRX_GTX_N6

PCIE_CRX_GTX_P7PCIE_CRX_C_GTX_P7
PCIE_CRX_GTX_N7

100K_0402_5%PX@

+0.95VGS

RF_NS@

33P_0402_50V8J

33P_0402_50V8J

CV488

CV489

1

1

2

2

RF_NS@

For RF

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2014/10/22

2014/10/22

2014/10/22

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2014/10/22

2014/10/22

2014/10/22

Title

ATI_STRATO_PCIE

ATI_STRATO_PCIE

ATI_STRATO_PCIE

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Date: Sheet of

Date: Sheet of

Date: Sheet of

Allsparks 5B

Allsparks 5B

Allsparks 5B

1

15 51

15 51

15 51

0.3

0.3

0.3

5

4

3

2

1

+3VGS

(3.3V@25mA VDDR3)

12

For EMC

+1.8VGS

1

2

GPU_RST#15,19

CV38

@

+0.95VGS

+1.8VGS

LV4

.1U_0402_16V7K

LV1 0_0402_5%PX@

(1.8V@13mA VDD_CT)

LV2 0_0402_5%PX@

GPU_SVC49
GPU_SVD49

GPU_SVT49

LV3

BLM15AG121SH1D_2P

CV37

1

2

@

.1U_0402_16V7K

PX@

1 2

BLM15AG121SH1D_2P

For EMC

LV5

CV43

1

For EMC

2

.1U_0402_16V7K

@

GPIO_19_CTF

12

+1.8VGS

PX@

1 2

(1.8V@250mA MPLL_PVDD)

10U_0603_6.3V6M

PX@

1 2

BLM15AG121SH1D_2P

GPU_RST#

RB751V-40_SOD323-2

Reserve

+3VGS

D D

10K_0404_4P2R_5%

GPIO21 can not be pull up, it will cause no-boot.

+3VGS

C C

12

PX@

10P_0402_50V8J

12

PX@

10P_0402_50V8J

B B

A A

1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2

PX@

RPV8

1 4

PX@

2 3

RPV6

PX@

10K_0804_8P4R_5%

1 2

1 2

1 2

1 2

CV34

2

YV1

PX@

GND1

OSC23GND2

CV41

18
27
36
45

RV25110K_0402_5% PX@

1

OSC1

4

GPU_GPIO5

RV1810K_0402_5% @

GPU_GPIO0

RV2110K_0402_5% @

GPU_GPIO8

RV2310K_0402_5% @

GPU_GPIO9

RV2410K_0402_5% @

GPU_GPIO10

RV2510K_0402_5% @

GPU_GPIO11

RV2710K_0402_5% @

GPU_GPIO12

RV2810K_0402_5% @

GPU_GPIO13

RV2910K_0402_5% @

GPU_GPIO22

RV3010K_0402_5% @

GPU_GPIO30

RV3110K_0402_5% @

GPU_GPIO6

RV3310K_0402_5% @

GPU_GPIO29

RV3410K_0402_5% @

GPU_GPIO1

RV24610K_0402_5% @

GPU_GPIO2

RV24710K_0402_5% @

GPU_GPIO3

RV24810K_0402_5% @

GPU_GPIO4

RV24910K_0402_5% @

GPU_GPIO20

RV25010K_0402_5% @

GPIO_7_BLON

RV25710K_0402_5% @

GPU_GPIO15

RV25910K_0402_5% @

GPU_GPIO16

RV25810K_0402_5% @

RV2604.7K_0402_5% PX@
RV2614.7K_0402_5%

GPU_HPD1
GPIO_14_HPD2

GPIO_18_HPD3
GENERICE_HPD4
GENERICF_HPD5
GENERICG_HPD6

GPU_GPIO21

JTAG_TRSTB

RV4610K_0402_5% PX@

RV2525.11K_0402_1% @

JTAG_TRSTB

RV25310K_0402_5% @

12

RV431K_0402_5% PX@

12

27MHZ_10PF_7V27000050

GPU_SCL
GPU_SDA

TESTEN

TESTEN

XTALIN

RV54
1M_0402_5%

PX@

XTALOUT

CV28

1

2

PX@

1U_0402_6.3V6K

CV29

1

2

PX@

1U_0402_6.3V6K

1 2

@

1K_0402_1%

PX@

(1.8V@75mA SPLL_PVDD)

1

1

CV35

CV36

2

2

PX@

PX@

1U_0402_6.3V6K

10U_0603_6.3V6M

CV39

CV40

CV42

1

1

1

2

2

2

1U_0402_6.3V6K

10U_0603_6.3V6M

PX@

PX@

PX@

(0.95V@100mA SPLL_VDDC)

10U_0603_6.3V6M

DV3

1 2

PX@
PX@

1 2

RV76

47K_0402_5%

+VDDR3

+VDD_CT+1.8VGS

VGA_SMB_CLK
VGA_SMB_DATA

GPU_SCL
GPU_SDA

12

RV150_0402_5% PX@

12

RV160_0402_5% PX@

12

RV170_0402_5% PX@

RV244

RV22
1K_0402_1%

1 2

1

CV254

2

PX@

.1U_0402_10V6-K

+MPLL_PVDD

1

CV256

2

PX@

.1U_0402_10V6-K

CV44

1

1

CV255

2

2

PX@

1U_0402_6.3V6K

PX@

FOR ONE TIME CTF USE 47K
FOR RESETABLE CTF USE 2K

PS_0
PS_1
PS_2
PS_3

GPU_SVC_R
GPU_SVD_R
GPU_SVT_R

+SPLL_VDDC

.1U_0402_10V6-K

PX@

RV77

+SPLL_VDDC

1

CV45

2

1 2

47K_0402_5%

BC37
BC39
BD37
BD39

AV34
AV36
AW34
AW36

BE43
BC41
BE41
BG41

AL51
AL53

BD21
BC21

BD17
BD19
BC17

BC49
BC48

BM20

BE19
BE39
BE15
BH43
BH27
BE23
BE17
BH25
BH29
BE21

AW23

AV23

AW25

AV21
AV20

@

MMBT3906_SOT23-3

100K_0402_5%

PART 5 OF 16

VDDR3_1
VDDR3_2
VDDR3_3
VDDR3_4

GPIO_5_REGHOT_AC_BATT

VDD_CT_1
VDD_CT_2
VDD_CT_3
VDD_CT_4

MLPS_0
MLPS_1
MLPS_2
MLPS_3

SMBCLK
SMBDAT

SCL
SDA

GPIO_SVC
GPIO_SVD
GPIO_SVT

DDCVGACLK
DDCVGADATA

TEST_PG

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9

GPU@

NC_10

PART 7 OF 16

SPLL_PVDD

SPLL_PVSS

SPLL_VDDC

PLLS XTAL

MPLL_PVDD_1
MPLL_PVDD_2

SPLL_CLKTESTA
SPLL_CLKTESTB

PLL_ANALOG_IN

GPU@

PLL_ANALOG_OUT

QV1

@

RV69

20K_0402_5%

@

12

@

RV78

@

PX@

1 2

RV68 0_0402_5%

U1D

GPIO_7_BLON

GPIO_8_ROMSO

GPIO_9_ROMSI

GPIO_10_ROMSCK

GPIO_14_HPD2

GPIO_17_THERMAL_INT

GPIO_18_HPD3

GPIO_19_CTF

GPIO_22_ROMCSB

GPIO

GENERICE_HPD4
GENERICF_HPD5

GENERICG_HPD6

NC_IDSC_ANALOGOUT

NC_IDSC_IL0
NC_IDSC_PWM0
NC_IDSC_PWM1
NC_IDSC_CMON

U1G

XO_IN2

XO_IN

XTALIN

XTALOUT

STRATO-M3-XT_FCBGA1093

+3VGS

E

3

B

2

C

1

12

2

B

CV48

.1U_0402_10V6-K

1

2

GPIO_11
GPIO_12
GPIO_13

GPIO_15
GPIO_16

GPIO_20
GPIO_21

GPIO_29

GPIO_30
GENERICA
GENERICB
GENERICC
GENERICD

VARY_BL

CLKREQB

NC_DSM_0
NC_DSM_1

NC_PS_4

BH50

BH52

BJ53

BJ51

BD15
BC15

BD23
BC23

12

12

13

C

E

GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4

GPIO_6

WAKEB

DIGON

HPD1

CLKTESTA
CLKTESTB

PLL_ANALOG_IN

RV66
20K_0402_5%

@

RV70
20K_0402_5%

@

QV11
MMBT3904_SOT23-3

@

BG27
BH23
BN19
BG29
BE27
BH35
BC29
BA45
BG39
BH37
BH39
BE29
BC31
BD31
BK28
BG31
BG37
BD29
BK36
BC27
BH33
BH31
BH41
BE25
BG25
BE45
BC45
BG23
BL19
BK42
BA53
AW49

BM44

AW45
AW47

BK44

CEC

J47
AK52

G48
F47
F45
G45
F43
BG33
BG35
BC43

STRATO-M3-XT_FCBGA1093

XO_IN2+SPLL_PVDD

XO_IN

10K_0404_4P2R_5%

XTALIN

XTALOUT

PAD

1
1

PAD

PLL_ANALOG_OUT

GPU_GPIO0
GPU_GPIO1
GPU_GPIO2
GPU_GPIO3
GPU_GPIO4
GPU_GPIO5
GPU_GPIO6
GPIO_7_BLON
GPU_GPIO8
GPU_GPIO9
GPU_GPIO10
GPU_GPIO11
GPU_GPIO12
GPU_GPIO13
GPIO_14_HPD2
GPU_GPIO15
GPU_GPIO16
GPU_GPIO17
GPIO_18_HPD3
GPIO_19_CTF
GPU_GPIO20
GPU_GPIO21
GPU_GPIO22
GPU_GPIO29
GPU_GPIO30

GENERICE_HPD4
GENERICF_HPD5
GENERICG_HPD6

GPU_HPD1

CEC_1

1

GPU_CLKREQ#_R

PX@

1 2

4.7K_0402_5%

RPV9

PX@
1 4
2 3

TV11

@

TV10

@

PAD

1

TV8

@

1 2

RV55

16.2K_0402_1%

keep out to noisy area.

RV79

12

RV71

PX@

100K_0402_5%

RB751V-40_SOD323-2

RV8 10K_0402_5%@

RV9 0_0402_5%@

RV10

TV2

@

PAD

RV26 0_0402_5%@

RV321

PX@

PX@

1 2

2.2K_0402_5%

12

DV2

@

12
12

PX@

12

10K_0402_5%

GPU_PROCHOT#

12

RV60_0402_5% PX@

12

+3VGS

@

RV268

1 2

4.7K_0402_5%

+1.8VGS

(1.8V@300mA VDDR4)

+3VGS

1 2

+1.8VGS

RV300

Place VREF divider and CAP close to ASIC

C

2

B

CV47

.1U_0402_10V6-K

E

3 1

PX@

1

2

AC_PRESENT 7,35

GPU_PROCHOT# 35

GPU_CLKREQ# 7

PART 1 OF 16

GPU@

1

1

CV258

CV257

2

2

PX@

PX@

1U_0402_6.3V6K

1U_0402_6.3V6K

RV254

@

10K_0402_5%

221_0402_1%

1 2

PX@

12

PX@

RV255

110_0402_1%

1 2

1 2

QV2
MMBT3904WH_SOT323-3

PX@

U1E

JTAG_TDO

JTAG_TMS

JTAG

JTAG_TCK

JTAG_TRSTB

AV38
AV39
AW38
AW39

BD33
BC33
BC35
BD35

BH9
BM18
BK18

BG9

BL11
BN11

BK20

1

CV259

2

PX@

.1U_0402_10V6-K

JTAG_TDI

TESTEN

RV620_0402_5% PX@

RV2430_0402_5% @

VDDR4_1
VDDR4_2
VDDR4_3
VDDR4_4

SWAPLOCKA
SWAPLOCKB
GENLK_CLK
GENLK_VSYNC

DVPCLK
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
MVP_DVOCNTL_0
MVP_DVOCNTL_1

VREFG

JTAG_TDO

BH47

JTAG_TDI

BG48

JTAG_TMS

BE47

JTAG_TCK

BG45

BH45

TESTEN
JTAG_TRSTB

BG49

STRATO-M3-XT_FCBGA1093

U1C

PART 6 OF 16

DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9

DVPDATA_10

DVP

DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23

GPU@

WRST# 35

APU_SHUTDOWN# 7

1

TV3 PAD@

1

TV12 PAD@

1

TV13 PAD@

1

TV14 PAD@

BH11
BG11
BH13
BG13
BH15
BG15
BH17
BG17
BH19
BG19
BH21
BG21
BM12
BK12
BN13
BL13
BM14
BK14
BN15
BL15
BM16
BK16
BN17
BL17

STRATO-M3-XT_FCBGA1093

+1.8VGS

+1.8VGS

RV316

RV315

+1.8VGS

SVC SVD

0

110

PX@

0_0402_5%

(1.8V@70mA AVDD)

PX@

0_0402_5%

RV319

0_0402_5%

Output Voltage (V)

00

1

1

(1.8V@117mA VDD1DI)

12

+VDD1DI

1

CV260

2

PX@

1U_0402_6.3V6K

.1U_0402_16V7K

12

+AVDD

1

1

CV262

@

2

2

PX@

1U_0402_6.3V6K

.1U_0402_16V7K

(1.8V@13mA TSVDD)

12

PX@

1U_0402_6.3V6K

GPU Internal Thermal Sensor

1.1

1.0

0.9

0.8

1

@

2

CV261

PX@

CV263

+TSVDD

1

CV46

2

PX@

PAD @

47K_0402_5%

VGA_SMB_CLK

VGA_SMB_DATA

GPU_SVD
GPU_SVC
GPU_SVT

+AVDD

DAC1_RSET

RV256

499_0402_1%

1 2

TV9

BC47

BA47

AR47

AM52

AM50

AW21

AW20

BC19

1

12

RV73

PX@

1 2

RV57

PX@

0_0402_5%

RV58
10K_0402_5%

@

1 2

1 2

RV63
10K_0402_5%

PX@

1 2

1 2

U1F

PART 8 OF 16

VDD1DI

VSS1DI

DAC1

AVDD

AVSSQ

RSET

STRATO-M3-XT_FCBGA1093

GPU@

U1B

PART 16 OF 16

TSVDD

TSS FDO

TSVSS

GPIO_28_FDO

TS_A

GPU@

+3VGS

12

RV74
47K_0402_5%

PX@

QV10A

2N7002KDWH_SOT363-6

+VDDIO_GPU+1.8VGS

RV61
10K_0402_5%

PX@

RV64
10K_0402_5%@

R

G

B

AVSSN

VSYNC
HSYNC

DPLUS

DMINUS

STRATO-M3-XT_FCBGA1093

G

2

S

RV59
10K_0402_5%

@

1 2

RV65
10K_0402_5%

@

1 2

AP50

AN51

AN53

AP52

GPU_VSYNC

AR49

GPU_HSYNC

AU49

BD25

BC25

BD27

61

PX@

D

QV10B

2N7002KDWH_SOT363-6

1

@

2

CV490

.1U_0402_16V7K

RPV10

1 4
2 3

PX@

10K_0404_4P2R_5%

GPU_DPLUS

1

TV4 PAD@

GPU_DMINUS

1

TV5 PAD@

GPIO_28_FDO

Must be held low before PCIe reset deassertion

RV75
10K_0402_5%

PX@

1 2

+3VGS

EC_SMB_CK2 6,31,35

G

5

S

34

PX@

D

EC_SMB_DA2 6,31,35

Multi-level Pin Straps

MLPS Bit DescriptionStrap Name

ROM_CONFIG[0]

PS_0[1]
PS_0[2]
PS_0[3]

PS_0[4] N/A

PS_0[5]

PS_1[1]

STRAP_BIF_GEN3_EN_A

PS_1[2]

STRAP_BIF_CLK_PM_EN

PS_1[3]

STRAP_TX_CFG_DRV_
FULL_SWING

PS_1[4]

PS_1[5]

STRAP_TX_DEEMPH_EN

PS_2[1]

PS_2[2]

PS_2[3]

STRAP_BIOS_ROM_EN

PS_2[4]

PS_2[5]

PS_3[1]
PS_3[2]
PS_3[3]

PS_3[4]

PS_3[5]

If STRAP_BIOS_ROM_EN = 1,ROM_CONFIG[2:0] define the ROM type.

ROM_CONFIG[1]

If STRAP_BIOS_ROM_EN = 0,ROM_CONFIG[2:0] define the primary

ROM_CONFIG[2]

memory-aperture size.
Reserved for internal use only.
Must be 1 at reset.

AUD_PORT_CONN_

The LSB (least significant bit) of the strap option that indicates the number of

PINSTRAP[0]

audio-capable display outputs.

PCIe GEN3 capability.
1 = PCIe GEN3 is supported.
0 = PCIe GEN3 is not supported.

0 = The CLKREQB power management capability is disabled
1 = The CLKREQB power management capability is enabled

N/A

0 = The transmitter half-swing is enabled
1 = The transmitter full-swing is enabled

0 = Tx deemphasis disabled.
1 = Tx deemphasis enabled.

N/A

Reserved.

N/A

Reserved.

0 = Disable the external BIOS ROM device.
1 = Enable the external BIOS ROM device.

0 = VGA controller capacity enabled.
1 = The device will not be recognized as the system’s VGA

STRAP_BIF_VGA_DIS

controller.

N/A Reserved 1

Board configuration related strapping, such as for memory ID

BOARD_CONFIG[0]
BOARD_CONFIG[1]
BOARD_CONFIG[2]

AUD_PORT_CONN_
PINSTRAP[1]
AUD_PORT_CONN_
PINSTRAP[2]

GDDR5 VRAM auto detect , no need memory ID.
config as 000

Determines the maximum number of digital display audio endpoints
that will be presented to the OS and user.

111 = No usable endpoints.
110 = One usable endpoint.
101 = Two usable endpoints.
100 = Three usable endpoints.
011 = Four usable endpoints.
010 = Five usable endpoints.
001 = Six usable endpoints.
000 = All endpoints are usable.

Capacitor Value (nF) Bits [5:4]

680

00

82

01

10

10

NC

11

Bit

MLPS

5 4 3 2 1

1 1

PS_0[5:1]

PS_1[5:1]

PS_2[5:1]

PS_3[5:1]

8.45K_0402_1%

00 1

1 1

00001

1 1

0

1 1

0 0 0

+1.8VGS +1.8VGS

12

RV37

PX@

PS_0

12

1

CV30

RV41

2K_0402_1%

PS_2

4.75K_0402_1%

.01U_0402_16V7-K

@

PX@

2

+1.8VGS +1.8VGS

12

RV44
10K_0402_5%

@

12

1

RV51

CV32
.01U_0402_16V7-K

PX@

@

2

RECOMMENDED
SETTINGS

Design dependent

256M=001

BOM

RV314

PX@

disable =1

R_pd (Ω)

RV49

PX@

4750

2000

2000

4990

4990

5620

10000

NC

12

RV38

8.45K_0402_1%PX@

12

12

RV45
10K_0402_5%

@

12

Design dependent

Design dependent

Design dependent

Design dependent

Design dependent

Design dependent

1

2

1

2

No usable endpoints =1

Gen3 support =1

enable=1

disable =0

111 = No usable endpoints.

R_pu (Ω) Bits [3:1]

NC

8450

4530

6980

4530

3240

3400

4750

Note: 0402 1% resistors are required.

R_pu R_pd C(nF)

8.45K 2K NC

8.45K 2K

NC 4.75K

NC 4.75K

PS_1

2K_0402_1%

PS_3

4.75K_0402_1%

1

0

0Reserved for internal use only. Must be 0 at reset.

1

0

0

0

000

001

010

011

100

101

110

111

NC

NC

NC

CV31
.01U_0402_16V7-K

@

CV33
.01U_0402_16V7-K

@

Title

Title

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2

2014/10/22

2014/10/22

2014/10/22

LC Future Center Secret Data

LC Future Center Secret Data

LC Future Center Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2014/10/22

2014/10/22

2014/10/22

Title

ATI_STRATO_PCIE

ATI_STRATO_PCIE

ATI_STRATO_PCIE

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

D

D

D

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Wednesday, April 29, 2015

Allsparks 5B

Allsparks 5B

Allsparks 5B

16 51

16 51

16 51

0.3

0.3

0.3