Kurzweil K150 - PROGRAMMERS MODEL REV A, 150, K150, K150FS Hardware Manual
KURZWEIL 150 FOURIER SYNTHESIZER
HARDWARE PROGRAMMER’S MODEL AND ADDRESS MAP
This document describes the Kurzweil 150 Fourier Synthesizer from the hardware programmer’s point of view. It contains
addresses for all of the hardware registers and brief descriptions of each. At this level the programmer is responsible for all
of the details involved in sound generation, MIDI data decoding (if used), time keeping, front panel display refreshing, and
button scanning.
The reader should be familiar with the documents titled "Model K150 User’s Manual", "150FS Version 1.6 Software", and
"Appendix 1 - K150FS System Exclusive Formats" as an example of one successful K150FS operating system
implementation. However this document was prepared for those interested in creating their own operating system perhaps
emphasizing different aspects of additive synthesis than the Kurzweil implementation, which was aimed primarily at realistic
recreations of acoustic instruments and a comprehensive MIDI implementation. For example, frequency envelopes for
partials might be implemented with the time saved by omitting the dynamic partial allocation feature of the Kurzweil
implementation.
SUMMARY OF HARDWARE RESOURCES
The K150FS consists of three boards: the CPU board, the "engine board", and the "sound board". The latter two make up the
sound generator while the CPU board contains all of the memory and other peripheral devices. The overall system resources
are as follows:
1. 68000 CPU running at 10MHz.
2. Program EPROM up to 128K bytes (4 x 27256 200nS), no wait states.
3. Scratch RAM (non volatile) 16K, no wait states
4. Sound EPROM up to 128K bytes (4 x 27256 200nS) or 256K bytes (4 x 27512), 2,5 wait states
5. Sound RAM (non volatile) 64K, 2,5 wait states
6. Parameter RAM (non volatile) 2K (old style) or 8K (new style), 2,5 waits
7. MC6850 serial I/O chip for MIDI In and Out
8. MC6840 programmable timer chip
9. 16 character 14 segment LED display with decimal points
10. 24 button panel
11. Contact sense for sustain pedal
12. Modulator and demodulator for audio cassette storage
13. General purpose parallel interface (not normally assembled on CPU board)
14. Miscellaneous output port for diagnostics and power-fail shutdown
15. Frequency units converter, functions as a large lookup table
16. Sound generator with 240 sine/noise waves and automatic linear interpolation of amplitude envelopes.
68000 CPU
The 68000 is clocked at 10MHz which is substantially faster than personal computers using the 68000 such as the Atari ST
and Apple Macintosh. Furthermore, for accesses to the primary program EPROM and scratch RAM, there are no wait states.
Programs normally run in Supervisor Mode and there is no special hardware for memory write protection or illegal address
detection. In fact, attempting to read or write a nonexistent address may cause the 68000 to hang due to lack of a DTACK.
The 68000 RESET instruction will
The 68000 address map is as follows:
ADDRESS RANGE ALIASES FUNCTION
$000000 - 00FFFF
$010000 - 01FFFF
$020000 - 020003 -023FFF
$024000 - 02000F -027FFF
$028000 - 02BFFF
$02C000 - 02C7FF -02FFFF
K150FS Programmer’s Model 1 Rev. A 26-APR-88
reset the sound generator and peripherals.
Program EPROM #1, 64K (sockets U55, U57)
Program EPROM #2, 64K (sockets U54, U56)
MC6850 MIDI UART (see below for actual addresses)
MC6840 Timer (see below for actual addresses)
Scratch RAM, 16K
(old style) Parameter RAM, 2K
ADDRESS RANGE ALIASES FUNCTION
$02C000 - 02DFFF -02FFFF
$030000 - 0307FF
$030800 -033FFF
$034000 - 03400A
$03400B
$03400C
$03400D
$03400E -037FFF
$038000 - 380003
$038004 - 03800F -03BFFF
$03C000 -03C7FF
$03C800 - 03C8FF -03FFFF
$040000 - 05FFFF
$060000 - 07FFFF
$080000 - 09FFFF
$0A0000 - 0BFFFF
$0C0000 - 0C7FFF -0DFFFF
$0E0000 - 0E7FFF -0FFFFF
$100000 -FFFFFF
Interrupts use the autovector method of linking to the service subroutine. Only 3 of the possible 7 interrupts are used as
follows:
LEVEL AUTOVECTOR ADDRESS FUNCTION
7 00007C Power fail
5 000074 6850 MIDI Interface
2 000068 6840 Timer
(new style) Parameter RAM, 8K
Sound Generator Partial Control Words
Sound generator control & status
-reservedMiscellaneous Status Register
-reservedCassette output D-to-A Register
Miscellaneous Control Register
Front panel
Reserved for test fixtures
Frequency units converter
General purpose parallel I/O
Sound ROM, 32K-128K, socket U14
Sound ROM, 32K-128K, socket U15
Sound ROM, 32K-128K, socket U16
Sound ROM, 32K-128K, socket U25
Sound RAM, 32K, socket U26
Sound RAM, 32K, socket U27
16 alias copies of all of above
The Power Fail interrupt only happens when the power-supply detects that voltage is dropping such as when the unit is turned
off or the power company fails. There MUST
described below in the Miscellaneous I/O section. If this is not done, the non-volatile RAM contents will be lost and the
backup battery drain will become high enough to deplete the battery in a couple of months. The SRAM SAFE signal is
required to flip a flip-flop into the standby power mode. It is recommended that during program development the backup
battery be removed to prevent unnecessary drain.
be a power-fail service routine and it MUST pulse the SRAM SAFE signal as
MEMORY
The K150FS has several classes of memory present. Program EPROM and scratch RAM run at full 0 wait-state speed and
are present as pairs of memory chips. Sound EPROM, sound RAM, and parameter RAM require wait states but are present
as individual chips for greater flexibility. The table below identifies each kind of memory chip, its function, and its U
number on the CPU board.
ADDRESS RANGE U-LOCATION FUNCTION SIZE CHIP TYPE SPEED
$000000-00FFFF
$010000-01FFFF
$028000-02BFFF
old $02C000-02C7FF U42 Parameter RAM 2K 6116 150nS
new $02C000-02DFFF U42 Parameter RAM 8K 6264 150nS
$040000-04FFFF
$060000-06FFFF
$080000-08FFFF
$0A0000-0AFFFF
$0C0000-0C7FFF
$0E0000-0E7FFF
U55-H U57-L Program EPROM 64K 27256 200nS
U54-H U56-L Program EPROM 64K 27256 200nS
U40-H U41-L Scratch RAM 16K 6264 150nS
U14 Sound EPROM 32K,64K 27256,27512 200nS
U15 Sound EPROM 32K,64K 27256,27512 200nS
U16 Sound EPROM 32K,64K 27256,27512 200nS
U25 Sound EPROM 32K,64K 27256,27512 200nS
U26 Sound RAM 32K 62256 150nS
U27 Sound RAM 32K 62256 150nS
K150FS Programmer’s Model 2 Rev. A 26-APR-88
The primary program EPROM is 16 bits wide and consists of one or two pairs of 27256 EPROMS. U55 and U57 chips must
be present since they are addressed beginning at $000000 and contain the startup and interrupt vectors. U54 and U56 are
optional and may be used if the program becomes larger than 64K bytes. Of course sound data may also be present in either
pair of EPROMs if desired with the advantage of zero wait state data access.
When using an EPROM programmer to prepare software for the K150FS, it is useful to know that the address and data bit
assignments are the same as the industry standard given in databooks. AO is the least significant address bit and A14 is the
most significant. Likewise, DO is the least significant data bit and D7 is the most significant. Data is stored in the EPROM
in positive true polarity.
The primary scratch RAM is also 16 bits wide and consists of a pair of 6264 static RAMs for a total of 16K. This RAM is
non volatile. It is intended for rapid access uses such as the 68000 stack, expanded parameter lists, and the like but could
also be used for RAM-resident sounds with the advantage of zero wait state access.
The parameter RAM, sound RAM, and sound ROM are each 8 bits wide but still appear to the programmer as if they are 16
bits wide. The 8-to-16 bit conversion hardware adds 5 wait states for a 16-bit access in order to do two 8-bit accesses.
However, if the 68000 instruction is a byte mode instruction, only 2 wait states are added. It is possible to put program code
in these memories but operation would be substantially slowed due to the extra wait states. The Sound EPROM sockets will
accept either 27256 EPROMs for 32K bytes each or 27512 EPROMs for 64K bytes each. They can also accept 1 megabit
mask ROMs (128K bytes each) but not 1 megabit EPROMs (the latter have 32 pins instead of 28).
MC6840 TIMER
The MC6840 contains 3 independent counter timers. Timer #1 is completely general purpose and has nothing connected to
its clock input or timer output. Timer #2 can be used by software to count sample periods (51.2uS each) of the sound
generator. Its clock input is connected to a square wave with a 51.2uS period. Timer #3 must be programmed to output a
500KHz square wave which is used as the baud rate input of the MC6850 MIDI UART described below. Nothing is
connected to timer #3’s clock input but the system clock (Enable frequency) is 1.0MHz. The gate inputs to all three timers
are wired to permanent ones.
The 6840 register addresses are as follows:
$024001 (write) Control Register #1 and #3
$024003 (read) Status Register
$024003 (write) Control Register #2
$024005 (read) Timer #1 counter
$024005 (write) Write MSB Buffer Register
$024007 (read) Read LSB Buffer Register
$024007 (write) Timer #1 latches
$024009 (read) Timer #2 counter
$024009 (write) Write MSB Buffer Register
$02400B (read) Read LSB Buffer Register
$02400B (write) Timer #2 latches
$02400D (read) Timer #3 counter
$02400D (write) Write MSB Buffer Register
$02400F (read) Read LSB Buffer Register
$02400F (write) Timer #3 latches
Programming details for the 6840 can be found attached to the end of this document.
MC6850 MIDI UART
A Motorola 6850 Serial Interface Adapter is used for MIDI I/O. Only the serial input and serial output are used; the modem
control outputs are not used and the modem control inputs are hardwired such that full operation of the transmitter and
receiver are permitted. The baud rate is taken from timer 3 of the 6840 described above. For the standard 31.25 KBaud
MIDI rate, 16X clock is selected in the 6850 and timer 3 is set for 2uS = 500KHz.
K150FS Programmer’s Model 3 Rev. A 26-APR-88
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