Keithley 181 Service manual
Service Manual
Model 181
Digital Nanovoltmeter
01981, Keithley Instruments, Inc.
October 1981, Cleveland, Ohio, U.S.A.
Document Number 30816
Model 181 Service Manual Addendum
INTRODUCTION
This addendum to the Model 181 Service Manual is being provided in order to supply you with
the latest information in the least possible time. Please incorporate these changes into the manual
before servicing the Model 181.
Model 262 Low Thermal Voltage Divider
This addendum concerns availability of the Keithley Model 262 Low Thermal Voltage Divider,
which is recommended for verifying accuracy and calibrating the Model 181 mV
Model 262 is a precision low thermal divider with divider ratios of 101:1, lO?l, lO”:l, and lO?l. A
low thermal male-to-male output cable is included with the Model 262. Note that Model 181 verification and calibration procedures that use the Model 262 are included in the Model 262 Instruction Manual.
Section 2, page 2-2:
Include the Model 262 Low Thermal Voltage Divider in the list of available accessories.
ranges.
The
Table 3-1, page 3-1:
Replace Item B in the table with the Model 262
Table 5-1, page 5-l:
Replace Items B and F with the Model 262
I
TABLE OF CONTENTS
SECTION
1
l-l
l-2
1-3
1-4
2
2-l
2-2
2-3
2-4
2-5
2-6
2-7
2-6
2-9
z-10
2-11
3
3-l
3-2
3-3
3-4
3-5
3-6
3-7
3-6
3-9
3-10
3.11
TITLE
Generallnformation ....................................
Introduction ............................................
Warranty Information ....................................
ManualAddenda
Safety Symbols and Terms. ...............................
Accessories ............................................
General ................................................
Model 1463 Low-Thermal Connection Kit
Model 1484 Refill Kit .....................................
Model 1485 Female Connector .............................
Model1486MaleConnector ...............................
Model 1488Shorting Plug .................................
Model 1503 Low-Thermal Solder and Flux
Model1506lnputCable ...................................
Model1507lnputCable ...................................
Model 1615Maintenance Kit ...............................
Model1019 Universal Rack Mounting Kit
Performance Verification ...............................
General ...........................................
Recommended Test Equipment ............................
Environmental Conditions .................................
Performance Verification Procedure ........................
Initial Conditions .........................................
DC Voltage Accuracy Check 12V to lO@S/)
DC Voltage Accuracy Check (2mV to 2OOmV)
HiResolutionCheck ......................................
Damping Function Check ....................
Filter Function Check ........................
NoiseCheck ...............................
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PAGE
.......
.........
....
4
4-l
4-2
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4.16
4-17
4-16
4-19
4-20
4-21
4-22
4-23
4-24
4-25
4-26
4-27
4-28
4-29
4-30
4-31
4-32
Theory of Operation ........ ..............
General .... ............................
Power Supply ..............................
IEEE Standard Interface ......................
Digital Section .............................
Microcomputer Memory .....................
AID Converter Control ......................
AID Operation .............................
Single Slope Phase .........................
Serial/Parallel Conversion, Isolator Control
Clock Circuit .. ... .....................
Display ....................................
D/A Converter .............................
Nanovolt Preamp ...........................
Low Noise Design ..........................
Linearity and Gain ..........................
Feedback Elements .........................
Offs&Null .................................
NMRR Filter and Suffer ......................
Drift Correction .................
Input Protection .. ......................
,nputMuxPumpout .........................
FET Multiplexing ...........................
InputMux
AID Converter .............................
Timing ....................................
MuxFETs
Transconductance Amplifier lGAMPl
integrator ..................................
Reference Supply ...........................
.................................
.................................
.. ....
..........
.....
.,.,4-l
~~~ 4-l
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TABLE OF CONTENTS
(CONTINUEDI
SECTION
5
5-l
5-2
5~3
5-4
5-5
5-6
5-7
5-6
5-9
5-10
5-11
5-12
5-13
5-14
5.15
5-16
5-17
5-18
5.19
5-20
5-21
5-22
5-23
5-24
5-25
5~26
5-27
5-26
5-29
5-30
5-31
5-32
5-33
TITLE
Maintenance .........................................................................................
General ...........................................................................................
RecommendedTestEquipment..........................................................................5- 1
VoltageDivider........................................................................................6 -1
EnvironmentalConditons
CalibrationProcedure ................................................................................
Installation of the Calibration Cover
AIDCalibration(ZVRangel ..........................................................................
lOMegAdjustment.....................................................................................5~ 3
20VRangeAdjustment.................................................................................5 -3
200VRangeAdjustment................................................................................5~ 3
lOOOVRangeAdjustmant...............................................................................5- 3
DIACalibration
.....................................................................................
NanovolrPreampCalibration
Troubleshooting.......................................................................................5- 4
Special Handling of Static Sensitive Devices
Line Power
AIDConverterandDisplay..............................................................................5 -7
DisplayBoard
Nanovolt Preamp Noise Troubleshooting
Preamp NoiseTroubleshooting Checks
ChecksofPreampZero.................................................................................5- 9
BufferCheck.........................................................................................5-1 2
InputCurrentCheck
BootstrapCheck..
LowNoiseSupplyCheck...............................................................................5~1 2
CurrentBiasCheck..
InputFETReplacemenr
NanovoltPreampTroubleshooting.......................................................................5-1 3
DC Volts Attenuator Troubleshooting
lEEEBusCircuitTroubleshooting........................................................................5-1 3
DIACircuitTroubleshooting............................................................................5-1 3
SwitchlnputSectionTroubleshooting....................................................................5-1 3
DigitalTroubleshooting
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.............................................................. .5-4
................................................................. .5-9
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PAGE
5-l
...5- 1
..5 -2
..5~ 2
.5-2
...5 -2
..5~ 3
..5~ 3
5-4
...5 -9
.5-9
...5-1 2
..5~12
..5~12
,.,.5-l 2
,513
..5~15
6
6-1
6-2
6-3
6-4
6-5
Replaceable Parts. .......
General ..................
Ordering Information ......
Factory Service ...........
Component Layouts .......
Schematics ...............
AppendixA............,,..,..,,.,....................,...............................................A-l
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.6-l
..6-1
,.6-l
,.6-l
..6-1
..6-1
ii
LIST OF ILLUSTRATIONS
FIGURE
1-l
1-2
2-l
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
3-l
3-2A
3-28
4-l
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-11
4-10
4-12
4.13
TITLE
Front Panel
Rear Panel
Model 1483
Model 1485
Model 1486 2-l
Model 1488
Model 1503 2~1
Model 1506
Model 1597
Model 1815
Model 1019
DCVPerformanceCheck.........................................,............~~.~~,~~..~..~~,~..,~
2mVand20mVPerformanceCheck ..~..~...............~......
200 Millivolt Performance Check ~. ~.
Latch Enable ............................ ~4~2
AID Control Logic .......................
Charge Balance Timing ...................
Single Slope Timing. .....................
Charge Balance-Single Slope Phase
Simplified Nanovolr Preamp Schematic
NVPA Showing Filter Et Drift Correction.
Preamp AID Timing.
V Range A/D Timing
Transconductance Amplifier. ..............
Simplified A/D Diagram .................. 4-10
Integrator ............................... 4~11
Reference Supply ........................
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......
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PAGE
. . ..l-2
..~.1.2
~2~1
2~1
2~1
2~1
2~1
2-2
~2~2
~3.1
3~2
~4-2
.4~3
~, ,4-3
~4~4
4~5
~4.7
4~8
4-9
,4-9
4-11
5-l
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-17
5-18
5-19
5-20
5-21
5-22
6-l
6-2
6-3
6-4
6-4
6-5
6-6
6-7
6-8
6-8
ShieldedEnclosure..................................................~....~~~
ConnectorAssembly......................................................................~......~.~.~
MaletoMaleConnector
DividerConnection...............................................................................~..~~~~~~.5~ 2
PreampCalibration....................................................~......~.~....~....~~~~~~.~~~~~~~.~ 5.3
DCCalibrator,Kelvin-VarleyDividerandW.. ............... .............
Model1815CalibrationCover..................................................~
480kHzClockl~sec/cm2V/cm..............................~
2.4kHzClock.2~eclcm2Vicm
lnputDisablelOmseclcm2V/cm...................................................................~
lnputDisable50mseclcm2V/cm
ATlOlOutputl0msec/cm2Vlcm..............................................................~
StrobePulsesl0mseclcm2Vlcm..................................................~.......~~~
AT103OutputlOmseclcm2Vlcm...........................................................~..~..~..~~
AT1040utput50msec/cm2Vlcm....................................................................~......5~1 0
V-FOutputl0msec/cm2Vlcm..
lntegratorOutput10mseclcm.5Vlcm.......................................................~........~~..~..5~l 0
AID Output Buffer Output lOOmsec/cm5V/cm
NoisyQ41310pVlcm50ms/cm
Quiet041310~VV/cmWms/cm ......................
NoisyU4O1lOpV/cmWms/cm..
0uietlJ40110~V/cm50ms/cm ...................................................................
Nanwolt Preamp PC-526, Component Location Diagram No. 30377D. Rev. C
Analog Board PC-529, Component Location Diagram No. 30503D. Rev. J
Display Board PC-530, Component Location Diagram No. 30532D, Rev. E
Digital Board PC-531, Component Location Diagram No. 30576D. Rev. J (sheet 1 of 21
Digital Board PC-531, Component Location Diagram No. 30676D. Rev. J (sheet 2 of 21
NanovoltPreampPC-526,SchematicDiagramNo.30586D,Rev.A..
Analog Board PC-529, Schematic Diagram No. 30685D. Rev. C
DisplayBoardPC-530.SchematicDiagramNo.30584D.Rev.C.. ..................
Digital Board PC-531, Schematic Diagram No. 30583D. Rev. F (sheet 1 of 21..
Digital Board PC-531, Schematic Diagram NO. 30583D. Rev F (sheet 2 of 21
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..... .......... ....... ..................
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........................... .. .. .......
.............................. ,~, 59
.. ... .. ......
.... ................
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... .. ........... .....
................ .. ..... ....
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.......... .. ..
............... ..... ........
.......
............ ~.~,~~~~~ ......... ~5~4
............. ,.,,.~,,~ 5.5
....................... 512
.......... .. .....
.....................
.........
..............
~~,~~
................. ~~~5~10
............... ,.,,5-11
~~,.~
.........
......
.,,,
... ,.~ ,, 5~9
........ ~~~.5~9
....
.... ....
.....
~~,.~ ~,
~~~5~2
..~..~~~5- 2
.. ,5-9
~,
~~~5~10
,5-10
,5-11
5-12
6~15
6~16
...
~6~17
~6.18
~6~19
~6~21
6~23
,6~25
6-27
~6~29
5.2
5-9
5~9
iii
I
TABLE
LIST OF TABLES
TITLE
PAGE
Recommended Test Equipment for Performance Verification
3~1
DC Voltage Performance Check (2V to 1OOOVl..
3-2
DC Voltage Performance Check (2mV to 200mVl
3-3
Microcomputer Memory Map ..............................
4~1
Gain Resistors
4~2
Gain Resistors for Volts
4~3
MuxFETs ..................................................
4-4
Recommended Test Equipment ...............................
5~1
Voltage Divider Parts List ................................
5~2
Power Supply Checks .................................
5~3
AIDConverter .....
5-4
Display..
5~5
Preamp Troubleshooting ....................
5-6
DCV Attenuator Troubleshooting
5~7
Replaceable Parts List PC-531 Schematic30593D
Replaceable Parts List PC-529 Schematic30585D
Replaceable Parts List PC-526 Schematic 30586D .........
Replaceable Mechanical Parts ...................
Cross Reference of Manufacturers.
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~, .. .................
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~, ...............
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... .........
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...
...
..
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3-1
.3~1
.3~2
. ...4-2
.4~6
.4~6
. ...4-9
.,.,5-l
. ...5-1
.5-6
.5-7
.5-a
.5~13
.5~13
.6~1
.6~6
.6-10
.6-12
,613
I
MODEL 181
Section 1. General Information
l-l. INTRODUCTION,
The Keithley Model 181 is a 5% and 6% digit DC voltmeter
with resolution to lOnV, The Model 181 is a unique DC
voltmeter in the respect that it combines microprocessor
technology for full programmability with a new concept in
nanovolt front ends, It provides highly accurate, stable and
low noise readings from 1OnV to 1CCQVDC on 7 voltage
ranges. The 2V through the 1CCOV ranges utilize the 5.way
binding posts. The 2mV through the 2CQmV ranges utilize the
special low thermal input connector.
The service manual contains the necessary information for
calibrating and maintaining the Model 181. This information is
provided in various sections throughout the manual. These
sections are listed as Performance Verification, Theory of
Operation and Maintenance/Calibration. Along with this
section, General Information, this manual also includes the
Accessories, a Parts List, and the Schematic Diagrams,
GENERAL INFORMATION
CMRR: 16OdS on mV ranqes. 140dS an V ranges; at DC and line fre
quency 60 or 60Hrl. ,lkR unbalance)
IEEE-488 BUS IMPLEMENTATION:
Multiline Commands: LXX. LLO. SDC. GET.
Unlline Commands: IFC, REN, EOI, SRD. ATN.
PROGRAMMASLE PARAMETERS:
Front Panel Controls: Range. Filter. Zero, Dampin% Hi Resolution.
Internal Parsmeters: SRCI Resoonse. Triswsr Modes. oats
Tetminators.
ADDRESS MODES: Talk-Only and Addressable.
TRIGGER MODES:
one Shot: Updates OUtpUt buffer once at first valid c”““ersi”” after
tdocler on TALK and/or GET.
GENERAL
NOISE: Less than 30nV pip on lowest range with Filter on.
INPVT CAPACITANCE: 5OOOpF on mV ranges.
SETTLING TIME: 0.5s to within 25 digits 01 final reading with Filter on,
Damping off
FILTER: 3~pole diSital: RC = 0.5, 1 or 2 seconds depending 0” range.
CONVERSION SPEED: 4 readings/second.
DISPLAY: Seven 13mm (0.6 in.1 LEO digitswith appropriatedecimal point
and polarity.
OVERLOAD INDICATION: Display indicates polarity and OFLO.
ANALOG OUTPUT:
--
Accuracy: f 10.15% of displayed reading + lm”i~
The Constent: 400ms.
Level: t 2V full scale on all ranges: x1 or x,000 gain
ISOLATION: Input LO 10 Outpur LO or power line ground’ ,400” peak. 5
x lOW.Hz. greater than ,090 paralleled by ,soJ”F
WARMUP: 1 hour IO rated SCCUE.CY when propedy zeroed,
ENWRONMENTAL LIMITS: OperatinS: WC 10 35°C. 0% la 80%
re,atiw hwnidirf .storags: 2vc to 65°C~
POWER: 105~125V or 210-250” lintelm SWlWh selected,. 50~60HZ.
30V.A maxim”m.
INPUT CONNECTORS: Special low thermal to, 20OmV and lower ,ilnges
Binding posts f”,2V to tooov rangss.
DIMENSIONS. WEIGHT: 127mm high x 216mm wde I 359mm deep
15” x BK” x 14W’,. Net weight 3.85kg ,8K lb*.,,
ACCESSORY SVPPLIED: Model ,606 Low Thermal Input Cable
ACCESSORIES AVAILABLE:
Model 1019 Rack Mounting Kit
Model ,483 LOW Thermal Connectlo” Kl,
Model 1484 Refill Kit for 1483 Kit
Model 1485 Female LOW Thermal Input Conneclor
Model ,486 Male LOW Thermal Input Connector
MO& 1488 LOW Thermal Shorting Plug
Model 1503 LOW Thermal Solder and Flux
Model ,506 LOW Thermal Input Cable 14 1tL alps,
Model ,507 LOW Thermal Input Cable 14 11.. Lugs1
Model ,815 Maintenance Kit
I
I
GENERAL INFORMATION
NOTES
1~ NMRA spocilicalions applies for input signals less than 3. ZEROING
12OmV peak~to~peak on the 2mV and 20mV range, ,.2V
poak~to peak on the 200mV range and less than 2X fuli
scale peak~lo-peak on all other ranges. This is necessary in
ordci 10 prevent AID sauration
2 ACCURACY SPECIFICATION
The accuracy specifications arc defined exclusive of noise
The term “when properly roroed” means rereroing during
warmup ifIrs 4 hoursi and after ambient changes in
temperalure of greater than 1’C
MODEL 181
l-2
F,G”RE l-l Front Panel
FIGURE 1-2. Rear Panel
MODEL 181
Section 2. Accessories
2-l. GENERAL
This section describes rhr? va,ious xcesso,~~~s and options
available lor us” with the Model 181.
2.2. Model 1483 Low-Thermal Connection Kit. 1 he Model
1483 Kit Conlains a crimp tool, shielded cable, an assortment
01 copper lugs, copper wire, cadm,um solde, and nylriri brrlts
and nuts, i, is a com,,le,e kit lo, nrnk,ng v”,y low thcrmnl
measuring arcuifs, ihe kit enables th,! use, of ,118 Mode1 181
10 maintain ho i~iqh therma stability 01 the ,~anov,~ll,,m~l,?~ II!
t11s own appllcatiorl,
Figure 2-l. Model 1487
Figure 2-2. Model 1485
Figure 2-5. Model 1503
Figure 2-6. Model 1506
Figure 2-3. Model 1486
2.5. Model 1488 Shorting Plug. ~T~hr! Model 1488 is ~,sef~il for
checking proper operation and Ior cnlihratinq the Model 181~
Its electrical and thermal ~0,1stri~l10,1 mrlimms “,,“,s caused
by thr!,mn, EMFs, The Mode, 1488 is ““,y useful fm checkirii?
the Model 181’s offset and drtfl~
Figure 2~7. Model 1507
4
ACCESSORIES
‘\
.-.
,.
‘:. 3.
MODEL 181
7
;:‘r
Figure 2.8. Model 1815
Figure 2-9. Model 1019
2-2
MODEL 181
PERFORMANCE VERIFICATION
Section 3. Performance Verification
3-6. DC Voltage Accuracy Check i2V to 1wOV Range1
3-4. Performance Verification Procedure
Use the following procedure 10 verify fhe basic accuraw of the
Model 181 ior DC voltage. /I the instrumwIl IS out of
speciflcallon ar any point. perform a complete caIib,atiori iis
CAUTION
The performance verification and all service inform
mation is intended for quaIlfled personnel using
accurate and reliable test eqwment.
WARNING
Some procedures require the use of high voltage.
Take care to prevent contact with live circuits
which could cause electrical shock resulting in
injury or death.
3.5. Initial Conditions
Before beginning thu ver,f,ca,ion procedure. the ,i,slrument
must meer the followng conditiorls:
l, the instrument has beer, subjected 1” extremes
ol temperature, allow sufficient fime for interrlal
kmperatures 10 reach wwronmental conditions
1 ‘. : :
(I
Figure 3-l. DCV Performance Check
DC VOLTAGE PERFORMANCE CHECK
I
I
3-7. DC Voltage Accuracy Check l2mV to 200mVl
TABLE 3-2
12v to 1OOOVl
CAUTION
.,‘181
1.89985 to 1.90015
,6.9978 to 19.0021
,E!xs,s 10 190.021
999.84 to999.16
I
PERFORMANCE VERIFICATION
MODEL 181
A. Dbtnin a low thermal cable and divider box as described in
Section 5.
B. connect the low thermal cable between the 181 and the
divider box.
c. Connect the DC calibrator as shown ill Figure 3~2A. For the
ZmV md 20mV rangm Allow n few nlinUk?S for fhc!rrnal
FMF’S to settle OUL~ Use Figure 3~38 for the 200mV range.
Do Set the DC calibrator for OOWOOO output
E. Sclnct the appropriate range as given in Table 3-3 Select
the range manually by pressing the appropriate Front Panel
button 01~ select the range automat~caily by issuing the apt
propriate command over the bus.
F, Zero the 181 by pressir,g the ZERO button on the Front
Panel or by issuing the appropriate command over the bus.
G Apply lhe riiquired voltage as specified in Table 3~3. Verity
that the displayed reading IS wllllin speclficalions~ Note the
X!X,lM]~
Hi Repeat steps D through G on ,he remaining mV ranges,
I, Reverse the polarity of the source and set i, t” 0000000 a,,~
p”l~
Rerero the 181 by pressing the ZERO button twice.
K. Apply the input as in step G. Verify rhr displayed rcadfng
iwIth opposite polarityi is the same as in step G +3 digits
no
,Y n
Made, 181
Figure 3.2A 2mV and 20mV Performance Check
TABLE 3-3
DC VOLTAGE PERFORMANCE CHECK
3.8. HI RESOLUTION Check
LJpon power [up, ftlc 181 WIII ba in the 5% dlgiI mode ol l~eso~
lllfion iROl~ To cheek fho HI RES funcl~on prncood as follows,
A~ Short thevolts IL0 2nd HI togrthcr~ Press the ZERO butlor~,
on the Front Panel. ~lhis will obtain a stored bascline~
I3 Apply the signal and the displayed reading will cqual thn
dilfr.rence between the stored baseline and the ,npu,
SIgnal.
3-9. DAMPING Function Check
Upor power up, the DAMPING fur,i:t,r,n IS r,,f iDO,, To check
10 see Ihat thi! DAMPING function IS operal~n!] properly, use
me l”llnwlilg procrd”,~e:
A. Select 2v ranq3
8. From a zero reading ;rprily a Fuil Scale signal and obserw
the serrling time,
3-2
I I I I
Figure 3-28. 203 Millivolt Petiormance Check
3-10. FILTER Function Check
Upon Power up the Filter functfon is dfsabled IPlI To chock to
see Li?at the FILTER IS operatfrq properly ust? Ihe following
procedure
A. Select 2V range.
/
H. Press the DAMPING burtor, and ti,w from a 7810 roedln~~
apply R Full Scale signnl Dbscrve fhc settling time,
C With DAMPING on press Ihc FILTER button Frorr a irro
rradli,rg apply a Full Scalii signsl~ Obswvc tl,e sctllmg l,mr.
Do The settling Lyme will be lorrger with thr FILTER enablcti
1 IliS dlffercnce ic”Cals ,ili,l the FILTER is operating
properly. Ths proccdur~ will wily work whcr DAMPING is
“11~
3.1,. NOISE Check
Noise is detined Ion lowest range, as peak-wpeak excursion
over a period of two minutes, tested after warmup while the
inpul is shorted with the Model 1488
I
MODEL 181
Procedure for checking notse:
A. Short the mv ,npu, w,,h a Model ,488 Low Thermiil Short
B. Select the 2mV range,
C. Turn on HI RES so that 6’% digits arc displayed.
PERFORMANCE VERIFICATION
MODEL 181
Section 4. Theory of Operation
4-l. GENERAL
This section contains ln~depth discussions of the maj”r circuit
blocks, which are listed below:
A. Power Supply (included on MotherboardI PC~531. page
B IEEE Standard lnrerface iinr:ludcd on MotherboardI
PC ~531, page 6~27
C DigItal Section (included on Mofhcrboradi PC~531. page
D Dispiay [Display Board1 PC~530, page 6,25.
E D/A Converter iMotherboard PC~531. page
F Nanovolt Preamp lNanovol~ Preamp Board1 PC~526. page
G A/D Corrvcrter (Analog Board) PC~529, page 6~23,
There are several figures and tables [provided wilt1 each major
circuit block that will aid in their oxplanation~
6~27,
THEORY OF OPERATION
4-z. Power supply
While studying the theory of operation for the Power Supply.
it will be helpful 1” refer t” the Schematic Diagram 30583D.
Sheet 1 of 2.
4-3.
The AC power is brought int” the 161 by a recessed line
plug JlOll. Fuse FlOl and line plug J,O,l are located on the
rear panels Switch SlOl is the main power swtch and ii is
located on the Front Panel. Switch S102 is the 115V 1” 230V
configuration switch and is located internally.
4~4
The regulated portion of the 181 power supply is sect
tioned into six different supplies. There are three supplies
(+15V, -15V, +5V) ior the analog section of the 181. The
other three supplies (+ 1%‘. -15V. -+ 5VI are for the digital section of the 181.
The key to the Analog/Digital isolation is the split bobbin
transformer TlOl. The digital supply winding, along with tbe
primary windings, are at the bottom haIf of th~ bobbin, and
the analog supply windings am located al the lw of the
bobbin.
4~5. The six supplies “perate from four separate windings 01
transformer TlOl. The four windings are fed info four full
wave bridae rectifiers: Two recfifiers for the analog section
CR105 ani CR106 and two rectifiers for the digital sect~“n
CR104 and CR107. Capacitors C128, C123. and Cl27 bypass
regulators U12B l5VI, U129 (+ 15Vl and U130 I-15Vl respectively. These are the analog supplies.
Capacitors Cl34 and Cl35 filter the input voltage to U136 and
U137 respectively. Capacitors Cl32 and Cl33 bypass
regulators U136 and Ul37 respectively. Capacitor Cl30 filters
the “utput of CRlC4 Regulator U135 receives its input from
the regulated “utput of Ul36. Q103 and Q105 are configured
as a high current gain voltage regulator. 0104 completes the
unify gain loop by compensating the VeE drop of Q103. CR101
provides short circuit limiting t” the circuit.
4-6. IEEE Standard Interface
While studying the theory of operation oi the IEEE Standard
Interface, it will be helpful 1” refer to the Schematic Diagram
30583,
sheet 1 of 2.
I
THEORY OF OPERATION
X5B30, Sheet 2 of 2 and 305&D, The digital cont~9 civails
of the 181 AID are located on Schematic 30583D. Sheet 2 of 2
while the circuits that they control are located on Schematic
30585D.
The conversion from analog data 10 digital data begins with
the integration cycle. Refer to Figures 4~3 and 4~4. An integration cycle begins with the appropriate signals to the input
amplifier and preamplifier enabled by one 01 more of the Sl
thru S12 lines going to a logic “1”. The charge balance line will
go to a logic “1” after the microprocessor waits for the input
to settle. The “D” Input of U122A also goes to a logic “1” and
is gated 10 U123B through U127B. This clears the 16 bit
counter U123B. The Q output of U122A will enable the input
signal to the integrator on the next rising edge of the 2.5kHr
clock. The microprocessor waits 16.66 milliseconds (the in&
gralion period lor 60Hr. 20~00 miillseconds for 60HrI then the
charge balance start line goes 10 logic “0”. At the next rising
edge of the clock, the Q output goes to a logic “1” again. This
WIII disable thn Input to the integrator and ends the exact 16,66
millisecond integration period.
Charge Balance Flip-Flop
MODEL 181
4-2
TABLE 4-l
MICROCOMPUTER MEMORY MAP
FIGURE 4.2. AID Control Logic
While the integration pcrlod is taking place, pulses from the
V~F arc inputted into the l&bit counter U123B. When the
co”“tcr overflows after 16 cowts, clock pulses are genoiared
which the VIA counts in an internal counter. These clock
pulses become the most significant bits of the result.
24-Bit Result
8 Bits These bits are generated by clock puises
during the Charge Balance phase.
4 Bits This is llhe remainder left on Ihn l&bit
cou”lcr durinij ,he CB phase.
8 Bits These counts are accumulated in the
16 bii counter during the single slope phase.
4 Bits This is Ihe remainder left on the 16~bir
counter during the sin(~lc slope phase,
MODEL 181
Strobt- /
u
j --mllJlJr
E”df”z ~ /y Remainder Strobe P”‘ses
Figure 4-3. Charge Balance Timing
THEORY OF OPERATION
The single slope phase begins uwth the Single Slope Start l~“e
setting the “D” input of U122B 10 “l”, 0” the next risirlg edge
of the 3.84MHr clock it is “OW inputted fo the 74LS393 where
if is counted, similar to the charge balance phases The single
slope phase ends when the comparator goes to “0” and gates
off the 3.84MHr clock from the confer. The remainder left on
the counfer is again read as in the charge balance phase. This
result is added to the charge balance cwnfs fo generate the
24~bit result.
Single Slope, !
start/stop
Single slops ,
Begi”
,,-lrnS-
r
I
FIGURE 4-4. Single Slope Timing
I
THEORY OF OPERATION
Input Disable
TO countet
0
MODEL 181
FIGURE 4-5 Charge Balance Single Slope Phase
4-14 Display
The display lr,formation is outputted on PA0 through PA7 on
the VIA II/O1 bus. The information is updated at a 1.2kHr rate
which means each digit is on for 833 microseconds. Each update begins by presenting new segment information on the
VIA II/O1 bus (PA0 PA71 and outputting a clock pulse oil
CAZ. The clock pulse goes to U203, which is a shift register on
the display board. U203 shifts a digit enable bit 10 the next
digit to be enabled. Ever” eiqht times the displav is updated. a
digitenable bit isgeneratedat P85andgoesto theenabledata
input of the shift register,
V201 C. V2028 and V202C drive the rows of the switch matrix.
~The switches are arranged in a 4 by 4 matrix, eleven of which
are used. The columns of the switch matrix go to Bits O-3 of
the switch ports
The switch port IS located on the motherboard fn Schematic
30583D. Sheet 2 01 2, Sectlo” F5. The segment dwers are
0201 0208~ 111 additlor to driwng the various segments, they
also artivak Ihe appropriale LCD’s,
4-15. DIA Converter
The heart of the D/A section is U117, shown on Schematic
30583D. Sheet 1 of 2~ It is a standard 12~bit D/A converter.
Data for the D/A IS multiplexed with the display data and is
latched info U116. This data is converted into an output current. Ul18 IS configured as a current-to~voltage converter.
Capacitor Cl10 compensates for output capacitance of Ull7.
The output voltage from U118 swings from OV to -1OV. since
ouiput current flows through RF which is internai to Ulll
lAD75411. All bits off yields OV output at Ull8; all bits ON
yields ~IOV output at Ul18.
VR102 is configured as a rcfcrence for Ihe D/A circuil. RIO/,
R108, RI09 arrd U119B scale the reference to ! 1OV. R107
provides an adjustment range on the + 1OV reference which
calibrates positive Full Scale An offset for U119A is provided
by Rlll, R112, R106 and VR102. This offset plus R113 and
R114 provide the scaling which translates the OV to 1OV
swing loutput of U1181 to Ihe desired 2 to +~ 2V swing. R106
calibrates negative full scale by altering the offset voltage on
UllSA,
Capacitor Cl37 filters the output and prevents it from appear
ing like a staircase waveform. VRlO3, VRIO4 and RI30 arc
configured as protection in case the analog output terminals
should be momentarily shorted together or tied to groater lhan
+3ov.
4-16. Nanovolt Presmp
During the theory of operation of the Nanovolt preamp, it will
be helpful to refer to the Schematic Diagram 30856D
4.17. Low Noise Design
One of the major reasons for utilizing a differential input stage
is the Supply Noise Reiec~ion Without proper matching,
power supply noise would have to be or a submicrovolt level
which would be impossible at low frequencies, Both bias cur
rent nom and voltage noise arc the major components of
Supply Noise. In order to minimize voltage noise, a pair of low
noise bipolar supplies are generated on the Nanovolt Preamp
board using U405 and IIS associated componen& VR403 and
VR404 serve as references (6.2 volts1 and R421, R422 and R413
scale the outpur voltages / ~+VRI 10 the desired f lOvolt Ievcl~
By providing the attenuation above 0.3Hr. C412 and C413 pre
vent ampllficafion of U405’s input voltage news U404A
bootstraps these supplies to improve amplifier linearity. The
noise conirlbution from reference zeners VR403 and VA404 IS
4-4
I I
+vr ’
0
N”li
, +I0
/;5
I
I
I
I
I
I
I
I
-va
I
I
I
I
--
~10
b ‘s
---
----
_----
--------
)
-
-----
THEORY OF OPERATION
MODEL 181
rnugl~yiblo, The bootstrap supply is decoupled from the input
via C414. C415, R425and R426. Rejection from the + 15V sups
plies is critic;iil as well. Therefore. current regulators CR406
and CR407 are a necessity iRp> 1M ohm) since Rs of VR403
and VR404 is approximately 100 ohms,
The key to maintaimng low current noise in the drain circuit of
Cl413 IS the selection of a low noise, high gain device for Q414
and maintaining low emitter and base impedances over the
bandwidth, R431, R432 and R433 provide bias for Q414 and
are referer~:ed 10 _t VR for low noise contribution
Noise contribution from the second stage depends upon drain
loads of Q413, gain of the lirst stage and input noise of the second
srage~ Q412 is a precisely matched low noise amplifier Wan
sister piiir which act as the second stage for the 181 preamp,
III addilior 10 low now, Ihls fransislor pa~r IQ4121 is required
because of 1,s hlgtl CMRR performance.
4.18. Linearity and Gain
,r a diifarential DC amplifier. nonlinearities irI the input stage
provide Ihe Iirnifal,on 10 gain linearity under the closed loop
condluon. In fact, no amount of loop gain car cailcol these
nonIinearities. The input FETS are square law devices which
means the output current varies as the square of the VGS. In
order fo r:anr:o, this nonlinearity. a second FET is used as a
load 10 the Hurst FET idifierer,lIaI pair). The degree of linearity
depends upon the match,ng between the two devlces~
The lolaI amplifier loop gain must be kept high so that closed
Ioop gain is independent of open loop gain. This eliminates
problems with gain drifts due to time/temperature var~atlons
inside Ihe loop. To maintain stable closed loop gains of 1000
i2mV rangel. 100 IZOmV range1 and 10 (200mV range) apt
propriate film or wirewound resistors are chosen as feedback
elements. Refer to Table 4~2~
TABLE 4-2
GAIN RESlSTORS
Range
2mv R40S. R414. R435 1000
ZOnl” R410, R415, R435 10” R410
zoomv R411, R416. R434
Thermal drifts in the input amplifier are relatively unimporfant
since they are autozeroed our. Slowly varying drill come
ponents isuch as solder joints, reed relay contacts) are of little
significance. ‘Therefore, no special lowthermal term~naIs are
necessary irl the feedback ,oop
However, for the nanovolt ranges (2mV. ZOmVl, it IS
necessary Lo use wirewound resistors wherever low voltage
signals are present, This is why R435 is a wirewound element,
whereas R434, R409-R416 are film resistors. Film resistors
display much higher voltage noise whereas wirewounds are
avaiInb,e whose noise approaches theoretical limifs. R435 is
s&x&d as 200 ohms since the Johnson noise of this value is
negligible compared to amplifier noise.
Gain Resistors Gain Adjustment
R40S
10 R411
4.20. Offset Null
4.21. NMRR Filter and Buffer
Additional NMRR is provided 111 the preamp using a threepole
cascaded filter. As can be seen from Figure 4~7. the three
poles are provided by three RC networks~
Wher, FFT Q4,S turns o,. sii drw 0405. 0407 and Q4OS~ The
fliters arc mow in tile nrw11 arrd Ihe input signal is now liltered
and amplliicd, The filter settling I~me is equal 10 200
mi,Iiseconds. After lhe 200 millisecond ~rlferval the signa
integration 1s done by the A/D~ FET 0420 (now lums 011, and
FETs Q419. Q405, Q407 arid 0408 lurn off, Since 110 liller IS !n
while the amplifier looks at “zero,” settling time depends on
amplifier speed and is 4 milliseconds. The zero is lhen Inn
tegrated by the A/D.
The reasorl the filter must shut off is so fhc A/D can record
amplifier xxo rlghl after if records sign;lI By keeping the tlrll~
delay bctween signal anti iclo as small as pilss~t~lo, effective
,,o,se ar,d dr,f, iire reduced tc lI,e desired lkwel. Co~lcurrerltly,
filtering of ~nrxmal mode signals IS accomplished only whet1
needed; wl,an looking at the signn,~
T11e first pole is formed by “416, C407 and Q4oS. The on
resistance of Q409 rnair~lains i:,osed loop gain aI all ire
qurncies greater than 10 which maintains ampI,firr stability~
The second pole is formed by C406. R406 and Q407. It is butt
fered from tile third pole by U401 5, The third pale is formed by
R401, C403 arid Q405~ AI, 11,rw ,x>Ies ,havr Ihr same 1,mc con
slant 01 10 miI,lseconds~ U401A builcrs Ihr: oulput 01 thn third
p0le.
Buffers U4OlA and U4OlB are boo&trapped in a similar
fashion to the input amplifier. VR401 and VR402 provide the
+6.2V reference, and emitter followers WI1 and Q402 supply
Ihe currenl 10 ,,4Ol, R40,C and R407D b,as Ihi! r~iemnces.
The effect oi This boofstrap is fo provide higher CMRR 10
“401, Ihnrefore imprrivirng linearity.
The baotstia,, CllClllt aoiis a pole I” 11k ir”qlicrrcy rcsp”“sa 0,
U4016. The dominant pole formed by R407A. R407R. C401
arid C402 m~intnins stability rif the bootsrrap c~rcoif. Q403 and
Q404 illIi ,ciw capai:ilarK:~
boolslraji c~rcuil to preve~lf latch up rcsult,ng lrom driviing
inputs to U4OlB out 01 lhoir common mode range durincj
overload
FtTs used as d,odc clamps 10 Ihii
4-6
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