SERVICE MANUAL
CD RECEIVER
KD-SH99R
Detachable
ATT
ANGLE
CD
FM
AM
CH
AUX SEL
KD-SH99R
EQ
R D
VOLUME
Contents
Safety precaution
Preventing static electricity
Disassembly method
Adjustment method
Flow unit reading TOC
of CD/CD-R/CD-RW
Maintenance of laser pickup
Replacement of laser pickup
Description of major ICs
RM-RK100
Area Suffix
E ------- Continental Europe
EX ----- Central Europe
1- 2
1- 3
1- 4
1-15
1-18
1-20
1-20
1-21~45
COPYRIGHT 2001 VICTOR COMPANY OF JAPAN, LTD.
No.49645
Jun. 2001
KD-SH99R
Safety precaution
!
!
Burrs formed during molding may be left over on some parts of the chassis. Therefore,
pay attention to such burrs in the case of preforming repair of this system.
Please use enough caution not to see the beam directly or touch it in case of an
adjustment or operation check.
1-2
KD-SH99R
Preventing static electricity
1.Grounding to prevent damage by static electricity
Electrostatic discharge (ESD), which occurs when static electricity stored in the body, fabric, etc. is discharged,
can destroy the laser diode in the traverse unit (optical pickup). Take care to prevent this when performing repairs.
2.About the earth processing for the destruction prevention by static electricity
Static electricity in the work area can destroy the optical pickup (laser diode) in devices such as CD players.
Be careful to use proper grounding in the area where repairs are being performed.
2-1 Ground the workbench
Ground the workbench by laying conductive material (such as a conductive sheet) or an iron plate over
it before placing the traverse unit (optical pickup) on it.
2-2 Ground yourself
Use an anti-static wrist strap to release any static electricity built up in your body.
(caption)
Anti-static wrist strap
Conductive material
(conductive sheet) or iron plate
3. Handling the optical pickup
1. In order to maintain quality during transport and before installation, both sides of the laser diode on the
replacement optical pickup are shorted. After replacement, return the shorted parts to their original condition.
(Refer to the text.)
2. Do not use a tester to check the condition of the laser diode in the optical pickup. The tester's internal power
source can easily destroy the laser diode.
4.Handling the traverse unit (optical pickup)
1. Do not subject the traverse unit (optical pickup) to strong shocks, as it is a sensitive, complex unit.
2. Cut off the shorted part of the flexible cable using nippers, etc. after replacing the optical pickup. For specific
details, refer to the replacement procedure in the text. Remove the anti-static pin when replacing the traverse
unit. Be careful not to take too long a time when attaching it to the connector.
3. Handle the flexible cable carefully as it may break when subjected to strong force.
4. It is not possible to adjust the semi-fixed resistor that adjusts the laser power. Do not turn it
CD mechanism ass’y
Damper bracket
Attention when traverse unit is decomposed
*Please refer to "Disassembly method" in the text for pick-up and how to
detach the substrate.
1.Solder is put up before the card wire is removed from connector on
the CD substrate as shown in Figure.
(When the wire is removed without putting up solder, the CD pick-up
assembly might destroy.)
2.Please remove solder after connecting the card wire with
when you install picking up in the substrate.
Front bracket
Feed motor ass’y
FD screw
CD mechanism
control board
Soldering
FD gear
Pickup unit
1-3
KD-SH99R
Disassembly method
Removing the front panel assembly
(See Fig.1)
1.
Press the release button in the lower right part of the
front panel assembly to unlock.
2.
Remove the front panel assembly in the direction of
the arrow.
Removing the top chassis
(See Fig.2 to 6)
Turn on power.
1.
Press the eject button in the upper left part of the
front panel assembly to move the assembly as
shown in Fig.2 and turn off power.
Front panel assembly
Front panel assembly
Eject button
Release button
Fig.1
Top chassis
2.
Remove the two screws A on the upper side of the
body.
Top chassis
A
Front panel assembly
Fig.2
A
Fig.3
1-4
3.
Remove the three screws B on both sides of the
body.
4.
Remove the screw C and the three screws D on the
left side of the body.
5.
Remove the two screws E and the screw F on the
back of the body.
6.
Move the top chassis upward and remove it with the
CD mechanism assembly. The connector on the CD
mechanism assembly is disconnected from
connector CN601 on the main board.
KD-SH99R
Top chassis
BB
Fig.4
Top chassis
C
Heat sink
E
BD
Fig.5
F
Fig.6
1-5
KD-SH99R
Removing the CD mechanism assembly
(See Fig.7)
Prior to performing the following procedure, remove
the top chassis.
1.
Remove the three screws G inside the top chassis
and remove the CD mechanisma ssembly.
Removing the motor assembly
(See Fig.8 to 10)
Prior to performing the following procedure, remove
the top chassis.
1.
Disconnect the wire from connector CN703 on the
main board.
2.
Remove the motor bracket and the spring attached
to the arm braket assembly (R).
Top chassis
G
Spring
G
G
CD mechanisma ssembly
Fig.7
Motor braket
3.
Remove the two screws H attaching the motor
bracket.
4.
Remove the washer attaching the clutch assembly
and pull out the clutch assembly from the shaft.
5.
Remove the two screws I and the motor assembly
from the motor bracket.
Motor braket
Clutch assembly
Motor assembly
Motor assembly
Arm braket assembly (R)
Fig.8
Main board
CN703
CN601
H
Motor braket
H
1-6
Washer
Fig.10
R
Fig.9
Removing the main board
(See Fig.11 to 15)
Prior to performing the following procedures, remove
the top chassis and the motor bracket.
1.
Disconnect the flexible wire from connector CN701
and CN702 on the main board respectively.
2.
Move the front bracket backward until it stops.
3.
Remove the four screws J attaching the arm
brackets (L) and (R). Move the right and arm lefter
brackets from the rod gear.
4.
Remove the rod gear.
5.
Remove the screw K attaching the rear panel to the
bottom cover on the back of the body.
J
Arm
brackets (L)
J
CN701
L
CN702
Main board
Fig.11
KD-SH99R
L
Arm
brackets (R)
J
Rod gear
Arm brackets (R)
Arm brackets (L)
Main board
Rod gear
Fig.12
Rear panel
K
Fig.13
Bottom cover
1-7
KD-SH99R
6.
Remove the two screws L and move the main board
backwards to release the two joints a. (The main
board will be removed with the rear panel and the
rear heat sink)
7.
Remove the screw M and N attaching the rear heat
sink.
8.
Remove the three screws O and the screw P
attaching the rear panel. Remove the main board.
Joint a
Joint a
Main board
Fig.14
Removing the lifter switch board
(See Fig.16)
Prior to performing the following procedures, remove
the top chassis, the motor bracket and the main
board.
O
Rear panel
Lifter switch board
P
N
M
Rear heat sink
Fig.15
Bottom cover
1.
Remove the two screws Q attaching the lifter switch
board.
1-8
Q
Fig.16
KD-SH99R
Removing the lifter board
(See Fig.17 to 23)
Prior to performing the following procedure, remove
the top chassis assembly and thefront panel
assembly.
1.
Disconnect the flexible wire from connector CN702
on the main board.
2.
Remove the four screws R attaching the front
bracket on both sides of the body.
3.
Push the pin of the joint c on the front of the front
bracket to release the lock lever.
Main board
CN702
Front bracket
Fig.17
Front bracket
Front bracket
R
Fig.18
Joint c
Front bracket
Lock lever
R
Fig.19Fig.20
1-9
KD-SH99R
4.
Remove the screw S attaching the lifter board cover
in the rear of the front bracket.
5.
Release the two joints d while pushing the front side.
Move the lifter board cover inthe direction of the
arrow and release the eight joints e.
Joint d
Joints e
Lifter board cover
Joints e
Joint d
6.
Remove the two screws T attaching the lifter board
on the front of the body.
S
Joints e
Lifter board
Joint e
Front bracket
Fig.21
Lifter board cover
Fig.22
1-10
Fig.23
T
KD-SH99R
<Front panel assembly>
Prior to performing the following procedure, remove
the front panel assembly.
Removing the front board
(See Fig.24 and 25)
1.
Remove the four screws U attaching the rear panel
to the front panel assembly.
2.
Release the eleven joints f of the front panel and the
rear panel.
3.
Disconnect the wire from connector CN503 on the
front board.
4.
If necessary, unsolder connector CN502 on the front
board.
Removing the volume board
(See Fig.25 and 26)
Prior to performing the following procedure, remove
the rear panel.
U
Line in board
U
Joint f 11
Front board
V
Rear panel
Fig.24
Soldering
(CN502)
CN503
Fig.25
Soldering
W
V
U
U
Volume board
W
1.
Remove the two screws W attaching the volume
board.
2.
Disconnect the volume knob, ring lens and volume
ring from the volume board.
3.
If necessary, unsolder the volume board.
Removing the line in board
(See Fig.25 and 27)
Prior to performing the following procedure, remove
the rear panel.
1.
Disconnect the wire from connector CN503 on the
front board.
2.
Pull out the line in board from the front panel
assembly.
Volume board
Volume lens, Volume ring
Rng knob
Fig.26
Line in board
Fig.25
1-11
KD-SH99R
<CD mechanism section>
Removing the CD mechanism control
board (See Fig.1 and 2)
1.
Unsolder the part a and b on the CD mechanism
control board.
2.
Remove the stator fixing the CD mechanism control
board and the damper bracket (To remove the stator
smoothly, pick up the center part).
3.
Remove the screw A attaching the CD mechanism
control board.
4.
Remove the CD mechanism control board in the
direction of the arrow while releasing it from the two
damper bracket slots d and the front bracket slot e.
5.
Disconnect the flexible wire from connector on the
pickup unit.
ATTENTION:
Turn the FD gear in the direction of the
arrow to move the entire pickup unit to
the appropriate position where the
flexible wire of the CD mechanism unit
can be disconnected easily.
(Refer to Fig.2)
CD mechanism assembly
D
h
Front bracket
Pickup unit
Damper bracket
D
A
Fig.1
e
b
Flexible wire
a
h
c
D
d
CD mechanism
control board
Shift the lock
Removing the loading motor
(See Fig.3 to 5)
Prior to performing the following procedure, remove
the CD mechanism control board.
1.
Remove the two springs f attaching the CD
mechanism assembly and the front bracket.
2.
Remove the two screws B and the front bracket
while pulling the flame outward.
3.
Remove the belt and the screw C from the loading
motor.
Loading motor
C
FD gear
f
B
Loading motor
Pull outward
Fig.2
CD mechanism control board
f
B
Front bracket
Fig.3
Front bracket
Pull outward
1-12
Fig.5
Belt
Flame
Fig.4
KD-SH99R
Removing the CD mechanism assembly
(See Fig.1, 6 to 9)
Prior to performing the following procedure, remove
the CD mechanism control board and the front
bracket (loading motor).
1.
Remove the three screws D and the damper
bracket.
2.
Raise the both sides fix arms and move the fix plates
in the direction of the arrow to place the four shafts g
as shown in Fig.8 and 9.
3.
Remove the CD mechanism assembly and the two
springs h attaching the flame.
4.
Remove the two screws E and both sides rear
damper brackets from the dampers. Detach the CD
mechanism assembly from the left side to the right
side.
ATTENTION:
The CD mechanism assembly can be
removed if only the rear damper
bracket on the left side is removed.
CD mechanism
h
Front bracket
CD mechanism
D
Flame
assembly
D
assembly
h
D
Damper bracket
D
A
Fig.1
e
b
Damper bracket
D
Fig.6
a
h
c
D
d
CD mechanism
control board
h
Fix plate (L)
g
Fix arm (R)
D
Fig.7
Rear damper bracket
g
Fig.8
Rear damper bracket
E
Fix plate(R)
E
Fix arm (L)
Damper
Damper
g
g
Fig.9
1-13
KD-SH99R
Removing the feed motor assembly
(See Fig.10)
Prior to performing the following procedure, remove
the CD mechanism control board, the front bracket
(loading motor) and the CD mechanism assembly.
1.
Remove the two screws F and the feed motor
assembly.
Removing the pickup unit
(See Fig.10 and 11)
Prior to performing the following procedure, remove
the CD mechanism control board, the front bracket
(loading motor), the CD mechanism assembly and
the feed motor assembly.
1.
Detach the FD gear part of the pickup unit upward.
Then remove the pickup unit while pulling out the
part i of the FD screw.
Feed motor assembly
F
FD gear
Nut push spring plate
FD screw
Pickup unit
Fig.10
Part i
Part j
Pickup unit
G
Pickup mount nut
Pickup unit
ATTENTION:
2.
Remove the screw G attaching the nut push spring
plate and the pickup mount nut from the pickup unit.
Pull out the FD screw.
When reattaching the pickup unit,
reattach the part j of the pickup unit,
then the part i of the FD screw.
Removing the spindle motor
(See Fig.12 and 13)
Prior to performing the following procedure, remove
the CD mechanism control board, the front bracket
(loading motor), the CD mechanism assembly and
the feed motor assembly.
1.
Turn up the CD mechanism assembly and remove
the two springs k on both sides of the clamper arms.
Open the clamper arm upward.
2.
Turn the turn table, and remove the two screws H
and the spindle motor.
k
FD screw
Spindle motor
Fig.11
k
Fig.12
H
1-14
H
Fig.13
Adjustment method
KD-SH99R
Test instruments required for adjustment
1. Digital oscilloscope (100MHz)
2. AM Standard signal generator
3. FM Standard signal generator
4. Stereo modulator
5. Electric voltmeter
6. Digital tester
7. Tracking offset meter
8. Test Disc JVC :CTS-1000
9. Extension cable for check
EXTGS004-26P 1
Standard measuring conditions
Power supply voltage DC14.4V(11 V to 16V allowance)
Load impedance 4 (4 to 8 allowance)
Line-Out Level/Impedance 4.0V/20k load(fuull scall)
How to connect the extension cable for adjusting
Standard volume position
Balance and Bass &Treble volume : lndication"0"
Loudness : OFF
BBE : OFF
Frequency Band
FM 87.5MHz ~107.9MHz
FM 87.5MHz 108.0 MHz
AM 530kHz ~ 1710 kHz(with channel interval set to 10kHz)
AM 531 kHz 1602 kHz(with channel interval set to 9 kHz)
Dummy load
Exclusive dummy load should be used for AM,and FM. For
FM dummy load,there is a loss of 6dB between SSG output
and antenna input.The loss of 6dB need not be considered
since direct reading of figures are applied in this working
standard.
(with channel interval set to 200kHz)
(with channnel interval set to 50kHz)
EXTLX003-20PC
EXTLX003-7PC
EXTLX003-20P
EXTGS004-26P
EXTLX003-7P
EXTLX003-2P
1-15
KD-SH99R
< Service mode >
The menu in the service mode can be switched with UP/DOWN.
The menu selected by the SEL button input is executed.
The ordinary mode
"UP" + "DOWN" + VR counterclockwise rotation.
DEL EEPROM EEPROM data all clear (changer is connected).
CH CH ERR CD changer error career call (changer is connected).
DELL CH ERR CD changer EEPROM clear (EEPROM career)
RUNNING CD CD running mode (Do not use in service).
RUNNING SH Running mode of front panel (Do not use in service).
DEL DATA CD ERROR MECHA ERR error career deletion.
CD ADJ R Self adjustment value call (It is a display switch with VR).
MEKACON WR Sub-microcomputer writing (Do not use in service).
TEMP DATA Temperature data call.
VERSION Microcomputer version confirmation.
The display changes in the up/down key.
The main microcomputer : SH99 J203
The Sub-microcomputer : SH99S 122
CD ERROR CD relation error career reading
< Error display >
Item Content
DISC_ERROR_0
DISC_ERROR_1
DISC_ERROR_2
DISC_ERROR_3
DISC_ERROR_4
DISC_ERROR_5
EJECT_ERR
Others
FOCUS NG
Self adjustment NG
CLV NG
TOC reading NG
or
MP3 FILE CHECK NG
BLANK DISC
1-16
MECHA ERR Panel relation error career reading
<ERROR CODE of Panel mechanism>
Memory to EEPROM of 6 digits, 1st and 2nd digit are indicate the operation mode when occur the error,
3rd to 6th digit are indicate details of error.
LCD indication time is use lower 2digits of details of error.
This series is indicate ERR XX (XX is error code).
<ex.> When details of error is 0A0001 , it is indicate ERR 01, details of error is 0E0031 , it is ERR 31.
Switch is from this side sequentially PSW1, PSW2,.....PSW6.
Details of error Error code
1. Error of door open (fault of PSW1)
(1) Time out by PSW1 not changed
(2) PSW1 change during waiting 300ms after open position detected
2. Error of door close (fault of PSW6)
(1) Time out by PSW6 not changed
(2) PSW6 change during waiting 300ms after close position detected
3. Error of shift to DETACH position (fault of PSW5)
(1) Time out by PSW5 not changed to open side
(2) Shift to open side, pass the DETACH position then detect ANGLE1
(3) Time out by PSW5 not changed to close side
(4) Shift to close side, pass the DETACH position then detect close position
4. Error of angle adjustment
4-1 Shift to ANGLE1 (fault of PSW4)
(1) Time out by PSW4 not changed to shift for open side
(2) Shift to open side, pass the ANGLE1 then detect ANGLE2
(3) Time out by PSW4 not changed to shift for close side
(4) Shift to close side, pass the ANGLE1 then detect DETACH position
4-2 Shift to ANGLE2 (fault PSW3)
(1) Time out by PSW3 not change to shift for open side
(2) Shift to open side, pass the ANGLE2 then detect ANGLE3
(3) Time out by PSW3 not changed to shift for close side
(4) Shift to close side, pass the ANGLE2 then detect ANGLE1
4-3 Shift to ANGLE3 (fault PSW2)
(1) Time out by PSW2 not changed to shift for open side
(2) Shift to open side, pass the ANGLE3 then detect OPEN position
(3) Time out by PSW2 not changed for shift for close side
(4) Shift to close side, pass the ANGLE3 then detect ANGLE2
5. PSW fault condition at initialize
When all PSW is checked immediately after RESET, and the state of SWITCH which
cannot be originally is detected, it is displayed as ERR 00.
0A0001
0A0002
0B0006
0B0007
0C0011
0C0012
0C0013
0C0014
0D0021
0D0022
0D0023
0D0024
0E0031
0E0032
0E0033
0E0034
0F0041
0F0042
0F0043
0F0044
000000
KD-SH99R
1-17
KD-SH99R
Flow until reading TOC of CD/CD-R/CD-RW
FEED RETURN
OFFSET SELF ADJUSTMENT
LASER ON
Pre SP KICK
LENS UP
FOCUS ON
THE SPINDLE START
TRAKING BALANCE
RF GAIN
FOCUS GAIN
TRACKING
TOC READING
Becomes DRVMUTE=H and the output of the IC604 driver becomes possible.
Picking up is moved to surroundings on the inside until becoming REST SW=L.
Afterward, moves in the direction of outer again and stops in the place in which
became REST SW=H.
FOCUS OFFSET, TRACKING OFFSET, and RF OFFSET are done, and
OFFSET of RF AMP in IC603 is corrected.
400ms turns the spindle motor before the focus search starts.
Lens UP of the pick is done. At this time, S character curve becomes about
2.0Vp-p by CTS-1000.
The down of the lens and FOCUS ONing are made.
Changes into CD-RW MODE, and serches for FOCUS in case of no FOCUS ON
even if FOCUS search(UP DOWN) is done three times.
The spindle motor is rotated up to the number of necessary rotations.
In the state of tracking OFF, do the self adjustment of wavy OFFSET of TE2 to 0.
It takes time to adjust the one with a large gap of the traking balance of picking up.
At this time, the racking error becomes about 2.8Vp-p by CTS-1000.
In the state of traking OFF, do the self adjustment of the RF level of RF(TP601)
to 1.0-1.2Vp-p. After adjusts,traking ON is done.
Do th eself adjustment of the gain intersection of the focus servo to 1.2kHz
(300ms).
Do the self adjustment of the gain intersection of the focus servo to 1.2kHz.
(300ms).
Time expands in DISC that the number of total tracks with CD-TEXT is a lot of.
1-18
1Tr. HEAD
TP603
TE2
TP605
FEED
TP634
SP0
TP636
It is a head of 1Tr., and the reproduction begins.
Shape of waves when based on Vref(TP602)
FE
2.0Vp-p
2.8Vp-p
FE : Focus error signal
TE : T Tracking error signla
FEED : FEED deive signal
SPO : Spindle drive signal
Adjustment part
KD-SH99R
IC941
C143
C144
TE2
TE
FE
C142
C944
D942
FOD
R630
C632 C633
C635
C631
C634
C636
C630
C629
R629
R636
C626
C628
R942
Q941
C637
R637
C678
C841
R876
C860
R134
C308
R941
R944
C622
R620 R621
C620 C621
C623
C627
C625
C624
C638
X602
R678
C677
C614
C615
IC603
R634
C680
C616
CN601
R677
C945
R853
R661
R695
R696
C639
C304
IC607
C307
R687
R688
R689
R855
R627
C641
X603
C302
R647
C643
R643
R857
R856
C642
C301
R690
C640
R697
R694
C305
R691
R698
C303
R667
R699
R665
R666
R668
R669
C669
R663
C687
R693
R676
TRD
C913
C686
R840
R839
IC606
R624
R838
R672
R673
R674
R675
R877
SPO
IC604
C676
C651
R662
C679
R633
X602
R619
R639
R651
R654
R650
R631
R644
R652
C351
C350
Q683
IC605
R655
IC803
C916
R211
C653
R649
IC805
R642
C450
R653
IC806
R659
C852
C851
R658
R111
R660
R641
C952
L622
R656R657
C161
C451
C654
IC804
C352
C321
FEED
C961
D402
D412
D416
D408
D401
C948
C947
C943
C941
C946
C949
C927
C141
IC941
C944
C143
C144
D942
L961
CN301
CN901
C926
CN302
D961
R977
C968
R978
C329
C921C922
D332
R231
R232
C928
D410
D414
R337
R976
C408
D967
Q232
R131
D962
C924
Q132
Q131
Q231
R132
C409
C272
D231
B1
IC401
R233
C404
C172
R243
R237
C323
C407
C410
R238
C244
D131
C405
B2
C273
R234
R244
IC171
R277
C173
C401
C243
C403
C241 C242
C220
R220
C402
C406
C309
R137
R143
C306
R120
R138
R133
C917
C120
C310
IC301
R144
C912
R134
C142
C302
C308
R942
C304
C305
R877
Q941
C307
R941
C301
C303
C945
R624
R944
C913
C622
R620R621
C643
C620C621
CN601
IC604
C623
R643
C626
C627
R627
R647
C687
C686
R857
R687
R688
R856
R840
C625
R689
R695
R855
R663
R691
R696
C641
R690
R661
C629
IC603
C630
R693
C624
R694
C642
R630
C628
R629
R697
R698
C676
C631
C632 C633
R699
R665
R666
R672
C637
C635
R839
R673
R669
R674
R838
C669
R675
IC606
R667
R668
C640
C634
R676
C636
X603
C638
R636
C639
R637
CN701
R679
R686
IC602
R680
R685
R681
R684
R682R683
IC601
D723
D724
D725
D726
D727
D728
D729
C721
D730
C722
C725
R933
R930
R923
R932
R924
R931
D914
D912
D722
C723
D721
CN702
C724
D796
CN771
IC961
C964
R963
C967
R962
Q755
R961
C330
R343
R436
R336
D701
C331
R344
C969
R325
R328
R331
C328
C327
R327
Q983
C971
R437
R340
C962
R329
Q35
R964
C965
C986
IC323
C977
D986
X51
C982
IC322
C332
R341
C334
C333
C978
R332
R342
R330
C325
C910
C175
R854
C452
IC911
C915
L852
R851
L851
R833
R911
R834
C203
C817
C818
D964
C450
C451
C103
C57
C163
R162
C25
D161
R164
D111
R163
D162
R161
PP2
R631
R644
C916
R617
R954
C321
C352
C351
R625
C951
C650
R645
IC951
R615
R618
C952
C350
R616
R111
R817
R813
C657
C811
R811
C164
C804
R823
C655
C656
C809
R211
R827
C653
C821
R821
R822
C803
R824
IC801
C161
C162
L622
C651
C812
R639
R812
R649
C822
C820
R814
R656R657
R658
R659
R660
R642
Q683
IC703
R641
C808
C814
C654
R784
C824
R662
R783
IC605
R633
C816
IC771
C772
C826
X602
R776
R655
IC802
IC804
R835
C819
C679
R619
R651
C710
R653
R775
R778
C852
R729
C771
R777
R654
C851
R725
R746
R779
R780
R650
R652
R723
R831
IC803
IC806
IC805
R832
R830
R766
D702
C714
BZ791
IC701
R759
R768
R702
X801
C713
C791
C708
X601
X701
R757
R758
R603R606
R798
R623
R648
R646
R628
R797
R626
D795
Main board
(Forward side)
J1
C117
L1
CN705
C998
C2
C4
Q34
D11
C34
C9
Q91
R83
R93
C81
Q81
C91
IC51
C5
C55
C53
C7
CN703
C32
TU1
R614
PP1
B3
IC608
R773
R781
R765
R782
R774
R772
R763
R764
R762
R770
R736
R761
R709
R722
R721
R724
R720
R719
R718
R717
R715R716
R714
TH951
R713
X702
BZ791
IC961
C931
C991 C992 C993
C997
C990
D1
D2
J1
R837
R692
C671
R671
R844
R843
B14
RF
B10
R664
R670
C645
R635
C617
C618
R852
B15
C644
R638
R632
X603
C612
R640
C646
C647
Vref
Q636
C996
CN771
B4
C773
C754
C774
C1
C3
R754
C755
B17
B5
C2
Q13
C11
CN705
D754
C10
C4
C84
R11
R4
C94
R5
Q11
C9
R14
R12
B18
R81
R13
X51
C82
R82
C45
C81
C6
C92
C44
C91
R92
C46
R35
R34
Q52
R56
R91
R55
C42C43
C41
R3
C5
R1
R51
C40
L51
Q1
C7
C53
PP2
Q51
R2
C47
Q32
C8
R33
Q33
B6
C56
C32
R32
R36
Q22
CN703
TU1
R23
PP1
R26
Q23
R726
C48
R727
C22
C21
C23
R24
R739
C719
R734
R735
C712
R745
R753
R728
R731
R732
R733
R707
R708
R710
R711
R701
R751
X702
C707
C702
C701
IC702
C964
C972
C973
R971
R975
C971
C967
Q966
C966
C969
R968
C965
R969
R10
R986
Q965
R15
R970
Q979
R987
Q12
C977
D978
C978
Q977
C51
C52
R53
R913
D980
R52
R54
R219
C54
R218
C25
C57
R118
R119
Q24
R21
R22
R28
R816
R167
C809
C24
R25
R825
R767
C164
R826
C804
C803
R27
R815
C808
C820
B8
C49
C807
C711
C806
C805
C815
C825
C826
D965
B9
L701
D963
R866
C710
R951
R738
R965
R743
R740
R868
R730
R864
C864
R796 R852
R999
R863
R865
R867
C714
R794
R793
Q701
R795
R792
R755
R769
R747 R748
R737
R742
R741
C706
C713
X701
C708
C705
C703 C704
C715
R705
R706
R927
R703
D711
R925
R135
C995
CN301
R136
R338
CN302
R961
R339
C337
R178
Q423
C987
C962
R335
Q323
Q321
C329
R276
R274
C323
R984
C982
R333
Q322
R176
C273
Q986
R334
C994
C325
C336
R275
R435
R985
C174
C175
C910
C452
C918
C911
C915
R175
C203
C212
R352
C210
C450
C451
C103
C916
C352
B7
Q642
C112
R177
R912
C321
C351
R351
C952
C350
Q161
R165
R622
C652
C161
C162
R166
C653
Q641
R634
X602
C816
C853
C680
R678
C660
L606
R677
B606
C678
C677
R870
C866
R869
R871
R872
R874
C841
C876
R876
R853
C878
C614
C615
C616
C860
C863
R859
X801
R861
R862
C862
BZ791
C605
R860
C861
B16
C606
R604
C792
C601
R791
C604
R602
R605
C791
X601
R601
C602
C726
Q791
R926
CN704
R922
Main board
(Reverse side)
D404
C961
CN901
C925
C923
L961
R235
D406
R236
D405
D961
B11
R172
C901
R272
R273
C272
C173
R173
R174
D911
C914
C912
D913
C913
C110
C671
IC607
R670
C617
C618
C609
C603
C942
D407
B12
D415
C409
C408
D403
R242
R241
R245
R402
C410
R404
C172
R401
C943
R403
R145
C242
C407
R141
C941
C401
C405
R146
R142
R405
C241
C403
C406
R246
D409
D411
C305
C402
C306
C310
R305
R301
C309
C141
IC941
C142
C308
D413
R943
C302
C303
C944
Q942
C307
C945
R304
R302
D941
B13
C301
R303
R836
R842
R841
R837
R844
R843
B14
B10
R692
R671
R664
C646
B15
C647
C644
C645
R638
R635
R632
Q636
X603
C612
R640
C619
R607
R608R609
L601
C611
C613
R928
R929
R613
C610
R612
R611
CN602
R610
RF shape of waves
1.0 1.2Vp-p
1-19
KD-SH99R
Maintenance of laser pickup
(1) Cleaning the pick up lens
Before you replace the pick up, please try to
clean the lens with a alcohol soaked cotton
swab.
(2) Life of the laser diode
When the life of the laser diode has expired,
the following symptoms will appear.
(1) The level of RF output (EFM output:ampli
tude of eye pattern) will be low.
Is RF output
0.8
YES
O.K
(3) Semi-fixed resistor on the APC PC board
The semi-fixed resistor on the APC printed
circuit board which is attached to the pickup
is used to adjust the laser power.Since this
adjustment should be performed to match the
characteristics of the whole optical block,
do not touch the semi-fixed resistor.
If the laser power is lower than the specified
value,the laser diode is almost worn out, and
the laser pickup should be replaced.
If the semi-fixed resistor is adjusted while
the pickup is functioning normally,the laser
pickup may be damaged due to excessive current.
NO
Replace it.
Replacement of laser pickup
Turn off the power switch and,disconnect the
power cord from the ac outlet.
Replace the pickup with a normal one.(Refer
to "Pickup Removal" on the previous page)
Plug the power cord in,and turn the power on.
At this time,check that the laser emits for
about 3seconds and the objective lens moves
up and down.
Note: Do not observe the laser beam directly.
1-20
Play a disc.
Check the eye-pattern at measures
between TP601 and TP602.
Finish.
Description of major ICs
UPD784215AGC146(IC701):MAIN CPU
1.Pin layout
75 51
76
50
KD-SH99R
2.Block diagram
INTP2/NMI
INTP0,INTP1
INTP3-INTP6
TI5/TO5
TI6/TO6
TI7/TO7
TI8/TO8
RTP0-RTP7
AV R
ANI0-ANI7
AV R
TI00
TI01
TO0
TI1
TO1
TI2
TO2
ANO0
ANO1
EF1
AV
EF0
AV
DD
AV
PCL
BUZ
100
125
PROGRAMMABEL
INTERRUPT
CONTROLLER
TIMER/COUNTER
TIMER/COUNTER1
TIMER/COUNTER2
TIMER/COUNTER5
TIMER/COUNTER6
TIMER/COUNTER7
TIMER/COUNTER8
WATCH TIMER
OUTPUT PORT
D/A
CONVERTER
SS
A/D
CONVERTER
SS
CLOCK OUTPUT
CONTROL
BUZZER OUTPUT
(16 BITS)
(8 BITS)
(8 BITS)
(8 BITS)
(8 BITS)
(8 BITS)
(8 BITS)
WATCHDOG
TIMER
REAL-TIME
26
78K/IV
CPU CORE
RAM
ROM
UART/IOE1
BAUD-RATE
GENERATOR
UART/IOE2
BAUD-RATE
GENERATOR
CLOCKED
SERIAL
INTERFACE
BUS I/F
PORT 0
PORT 1
PORT 2
PORT 3
PORT 4
PORT 5
PORT 6
PORT 7
PORT 8
PORT 9
PORT 10
PORT 12
PORT 13
SYSTEM
CONTROL
RxD1/SI1
TxD1/SO1
ASCK1/SCK1
RxD2/SI2
TxD2/SO2
ASCK2/SCK2
SI0
SO0
SCK0
AD0-AD7
A0-A7
A8-A15
A16-A19
RD
WR
WAIT
ASTB
P00-P06
P10-P17
P20-P27
P30-P37
P40-P47
P50-P57
P60-P67
P70-P72
P80-P87
P90-P95
P100-P103
P120-P127
P130,P131
RESET
X1
X2
XT1
XT2
V
DD
SS
V
TEST
1-21
KD-SH99R
Pin No. Symbol I/O Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PREQ
AMUTE
DIMMER-OUT
ANT PEM
VDD
X2
X1
VSS
XT2
XT1
RESET
BUS-INT
PS2
RDS-SCK
RDS-DA
REMOCON
AVDD
AVREF0
SD-ST
MRC DATA
KEY0
KEY1
TEMP
LEVEL
SQ
S.METER
AVSS
INLOCK
NC
AVREF
BUS-SI
BUS-SO
BUS-SCK
(STAGE)
LCD-DA
LCD-CL
LCD-CE
BUZZER
EPDAI
EPDAD
EPCLK
BUS-I/O
PM0
PM1
O
Mechanism power supply ON/OFFdemand output("L":On demand)
O
Audio output MUTE control signal output ("L" :MUTE ON)
O
Non connected
O
Non connected
O
Non connected
O
Non connected
O
Unused output port
O
Antenna remote output
-
5V connection
Sub-clock 32.738MHz
I
Sub-clock 32.738MHz
-
GND connection
Sub-clock 12.5MHz
I
Sub-clock 12.5MHz
Reset detection terminal
I
Non connected
O
J-BUS signal interrupt input
I
POWER SAVE2 BACK UP synchronization. It is H input and stop mode.
I
Unused input port
I
RDS clock input
I
RDS data input
I
Remote control signal input
-
5V connction
-
5V connection
I
Station detector, stereo signal input.
It is H and broadcasting station havingBroadcasting station,L:stereo
I
MRC DATA input
I
Key input 0
I
Key input1
I
Temperature data input for contrast correction
I
Level meter input
I
S.QUALITY level input
I
S.METER level input
-
GND connection
O
The LOCK detection output. At LOCK:H
O
Unused output port
-
5V connection
I
J-BUS data input
O
J-BUS data output
I/O
J-BUS clock I/O
I
H:L:Initialization port
O
Data output to LCD driver
O
Clock output to LCD driver
O
Chipenable output to LCD driver
O
Buzzer output
I
Communication data input of 12C
O
Communication data input of 12C
O
Communication data input of 12C
O
The J-BUS I/O switch output. When outputting :H,When inputting :L
O
Panel close side motor control signal output
O
Panel opening side motor control signal output
UPD784215AGC146(1/2)
1-22
Pin No. Symbol I/O Function
51
52
53
54
DETACH
Non connected
O
Non connected
O
Non connected
O
The detach signal input. It is L of 200ms or more and operation mode.
I
It is H and POWER SAVE.
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
VCR CONT
PNL SW1
PNL SW2
PNL SW3
PNL SW4
PNL SW5
PNL SW6
AFCK
SEEK/STOP
S MUTE
FM/AM
PLL-CE
PLL-DO
PLL-CLK
PLL-DI
TEL-MUTE
AMP KILL
VSS
DIMMER-IN
PS1
Signal output for VCR control
O
Panel position detection switch one signal input.
I
Panel position detection switch two signal input.
I
Panel position detection switch three signal input.
I
Panel position detection switch four signal input.
I
Panel position detection switch five signal input.
I
Panel position detection switch six signal input
I
The Af check output. When you check AF:L.
O
The auto seek stop switch output. At SEEK:H, STOP:L.
O
Software mute output for CF switch noise.
O
FM and the AM switch output. At FM:H,At AM:L
O
CE output for IC control for PLL.
O
Data output for IC control for PLL.
O
Clock output for IC control for PLL.
O
Data input for IC control for PLL.
I
Telephone ,ute detection input.
I
POWER-AMP, ON/OFF switch output. H:OFF
O
GND connection
Dimmer detection input. L:Dimmer ON
I
At POWER SAVE of POWER SAVE1.ACC and synchronization:L.
I
When operating :H.
75
76
77
78
79
80
81
82
83
84
85
86
87
88
POWER
CD-ON
MUTE
W-LPF1
W-LPF2
W-MUTE
VDD
VOL-DA
VOL-CLK
CF-SEL
PMKICK
EMPH
VOL-1
The POWER ON/OFF switch output. At the time of the POWER ON:H.
O
The CD power supply control signal output. At CD:H.
O
The mute output. At the time of the MUTE ON:L.
O
Sub woofer cutoff frequency control output 1
O
Sub woofer cutoff frequency control output 2
O
The mute output for the sub woofer. At the time of the MUTE ON:H.
O
5V connection.
O
Data output for IC control for electronic volume.
O
Clock output for IC control electronic volume.
O
Signal output for FM belt region filter switch.
O
Signal output for panel motor kick
O
The CD emphasis output. When turning.At On:H.
O
Non connected
O
Pulse which rotation volume pulse signal inputs, and becomes
I
judgment of change actually.
89
90
91
92
93
94
95
96
97
98
99
100
VOL-2
(J/R)
BUCK
CCE
LSI RST
TEST
(DISC SEL)
SW1
rotation volume pulse signal input
I
H:J version and L:R version
I
Non connected
O
Non connected
O
CDLSI reset signal output
O
GND connection
Non connected
O
Non connected
O
Non connected
O
Non connected
O
Non connected
O
Panel SW1
I
KD-SH99R
UPD784215AGC146(2/2)
1-23
KD-SH99R
UPD63711AGC(IC603):RF Servo amp
1.Pin layout
144 109
1
108
36
37 72
73
2.Pin function
Pin No. Symbol I/O Function
1
2
3
4
VSSO
ZRASO
ZCASO
ZCAS1
-
It is GND of the logic circuit.
O
It is RFOK signal output terminal.
I
Reset signal input terminal. (Active row)
I
Command/parameter identification signal input terminal
A0=L:STB active=Address register set. A0=H:STB active= Parameter set.
5
VSSO
I
The data strove signal input terminal. It is signal to de the latch in LSI as
for the cereal data.
6
ZOE
I
The clock signal input terminal to input and output the cereal data. Input
data from terminal SI is taken by standing up about this signal, and the
cereal data from the terminal SO is output with go down.
7
8
9
ZUWE
ZLWE
VSSO
O
The cereal data and the status signal are output.
I
Cereal data input terminal.
I
The crystal oscillation control terminal. Please input the reset signal
before stopping the crystal oscillation. Moreover, the crystal oscillation is
steady and input the reset signal, please when moves from the state of
the crystal oscillation stop to the ordinary mode.
XTALEN=L:ordinary mode XTALEN=H:Crystal oscillation stop.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
VDD0
VSS0
RA8
IO0
IO1
IO2
IO3
IO4
IO5
VSSO
-
Positive power supply supply terminal to logic circuit.
-
Positive power supply supply terminal to D/A converter.
O
R-ch audio signal output terminal.
-
It is D/A converter GND.
-
The outside credit capacitor connection terminal for SCF regulator.
-
It is D/A converter GND.
O
L-ch audio signal output terminal.
-
Positive power supply supply terminal to D/A converter.
O
Output terminal of right channel voice data. PWM output.
O
Left channel voice data audio output terminal. PWM output.
-
Positive power supply supply terminal to crystal oscillation circuit.
O
Crystal departure pendulum connection terminal (Output)
I
Crystal departure pendulum connection terminal (Input)
-
It is GND of the crystal oscillation circuit.
-
Positive power supply supply terminal to logic circuit.
O
The output terminal of priemphasis information in sub code Q.
When the emphasis is added, high level is output. Polarity can be
switched by the command.
F6H LSB EP=0:Normal output EP=1:Reversing output.
28
IO6
O
Flag output terminal which shows that data under output is composed by
data which cannot be corrected.(active high)
29
IO7
I
The cereal data input terminal to building DAC into. When DSP etc. are
not connected with latter part, it should be short with the terminal DOUT.
30
31
IO8
IO9
O
It is an output terminal of the cereal voice data.
I
Cereal clock input terminal to building DAC into.
The output voice data changes from DOUT by standing up about this
clock. The system connected with latter part must take data by standing
up about this signal.
32
IO10
O
The output voice data changes from DOUT by standing up about this
clock.The system connected with latter part must take data by standing
up about this signal.
UPD63711AGC(1/3)
1-24
Pin No. Symbol I/O Function
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
IO11
IO12
IO13
VSSO
VDD1
IO14
IO15
DREQ
DRESP
IOP7
IOP6
IOP5
IOP4
IOP3
IOP2
IOP1
IOP0
HDBDIR
DVDD
PACK
TSO
TSI
TSCK_B
TSTB_B
DGND
TEST0
TEST1
ATEST
AGND
FD
TD
SD
MD
DACO
FBAL
TBAL
TEVCA
AVDD
EFM
ASY
C3T
RFI
AGCO
AGCI
RFO
I
LRCK signal input terminal to building DAC into.
O
Signal which distinguishes left channel/right channel of voice data output
from DOUT.
O
Terminal (88.2kHz)(WDCK)of the output of the frequency signal twice
defect detection output terminal(HOLD) LRCK HOLD/WDCK can be
switched with the microcomputer.
O
Terminal of output of data of Digital audio interface.
-
It is GND of the logic circuit.
O
Buffer ring output terminal of oscillation.
I
The state of this terminal is output to Bit5 of the status output.
-
Positive power supply supply terminal to logic circuit.
O
It is EFM-synchronous detection signal.becomes high-level when the
O
output of the synchronous pattern detection signal and the frame
counter is corresponding by the EFM recovery part, and becomes a row
level at the disagreement.
O
Mirror output terminal. (MIRR).It is a frame synchronous signal of PLL
system. The one that a basic frequency (44.1kHz)of the reading signal
obtained in PLL system was divided makes almost equally to the
synchronization(7.35kHz) of one frame. (WFCK)MIRR/WFCK can be
switched with the microcomputer.
O
the terminal for the monitor of the bit clock. When PLL is locked, the
go down edge of the EFM signal and this signal locks.
-
it is GND of the logic circuit.
O
The output terminal which shows the C1 error correction result. Even
go down of RFCK is fixed.
O
It is an output terminal which shows the C2 error correction result. Even
of RFCK is fixed.
-
Positive power supply supply terminal to logic circuit.
O
It is PACK synchronous signal shows the head of packing.
O
It is a cereal output terminal of the CD-TEXT data.
I
It is a serial input terminal of the CD-TEXT control parameter.
I
Cereal clock input terminal of CD-TEXT.
I
Terminal of input of parameter strove signal of CD-TEXT.
-
It is GND of the logic circuit.
I
It is a test terminal. Please connect with GND usually.
O
It is a test terminal. Please make to the opening usually.
-
It is GND of an analog circuit.
O
Focus drive output terminal.
O
Tracking drive output terminal.
O
Thread drive output terminal.
O
Spindle drive output terminal.
O
It is DAC output terminal for the adjustment. A set value of CRAM7FH is
output.
O
It is DAC output terminal for the adjustment. A set value of CRAM7CH is
output (built-in RF FE amplifier offeset).
O
It is DAC output terminal for the adjustment. A set value of CRAM7DH is
output.
O
It is DAC output terminal for the adjustment. A set value of CRAM7EH is
output (built-in RF TE amplifier offset).
-
It is a positive power supply supply terminal to an analog circuit.
O
EFM signal output terminal.
I
It is a standard voltage input terminal of the EFM comparator.
-
Capacitor connection terminal for 3T detection.
I
RF signal input terminal for EFM data generation.
O
RF signal output terminal after gain is adjusted.
I
Input terminal of RF-AGC amplifier.
O
Output terminal of RF saming amplifier.
KD-SH99R
UPD63711AGC(2/3)
1-25
KD-SH99R
Pin No. Symbol I/O Function
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
EQ2
EQ1
RF
AGND
A
C
B
D
F
E
AVDD
REFOUT
FE
FEO
TE
TEO
TE2
TEC
AGND
PD
LD
PN
AVDD
-
Equalizer part connection terminal of RF amplifier.
I
Reversing input terminal of RF saming amplifier.
-
It is GND of an analog circuit.
I
Photo detector A input terminal.
I
Photo detector B input terminal.
I
Photo detector C input terminal.
I
Photo detector D input terminal.
I
Photo detector F input terminal.
I
Photo detector E input terminal.
-
Positive power supply supply terminal to analog circuit.
O
reference potential output terminal.
I
Focus make an error amplifier reversing input terminal.
O
Focus Allah amplifier output terminal.
I
Tracking make an error amplifier reversing input terminal.
O
Tracking error amplifier output terminal.
O
Terminal to which tracking error after amplifies is output.
I
The tracking comparator input terminal. The tracking error signal which
cuts the DC element is input. The tracking 0 crossing is detected by
using this signal in LSI.
-
it is GND of an analog circuit.
I
It is a terminal of the input of the detection signal of PD for the LD output
monitor.
O
LD control current output terminal.
I
It is a control polarity set value of the APC circuit.
-
Positive power supply supply terminal to analog circuit.
UPD63711AGC(2/2)
TC74VHC157FT-X(IC803):DAC SW
1.Pin lauout 2.Pin function
SELECT
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
ASG
B
Y
A
B
YYB
A
B
Y
A
8
16
15
14
13
12
11
10
Vcc
ST
4A
4B
4Y
3A
3B
3Y
9
ST
H
L
L
L
L
X:Don't Care
INPUTS
X
L
L
H
H
ABSELECT
X
L
H
X
X
X
X
X
L
H
OUTPUT
L
L
H
L
H
1-26
UPD70F3033AC015(IC606):SUB CPU
1.Pin layout
100 76
1
75
KD-SH99R
25
26 50
51
2.Pin function
Pin No. Symbol I/O Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
TSI
TSCK
JBSO
JBSI
JBCK
EVDD
EVSS
TSTB
XRESET
MIRR
AO
SO
SI
SCK
WSEN
DSPRST
SWAIT
VPP
SA4
SA5
SA6
STB
DRVMUTE
LOAD1
LOAD2
SA0
SA1
SA2
SA3
RESET
XT1
XT2
VSS
VDD
CLKOUT
WR
---
---
RD
---
JBCONT
PON
AD0
AD1
AD2
AD3
O
CD TEXT control parameter cereal output.
O
CD TEXT control cereal clock output.
O
JBUS cereal data output.
I
JBUS cereal data input.
I/O
Cereal clock I/O.
-
5V(power supply for port for I/O).
-
GND(GND for port for I/O).
O
CD TEXT parameter strobe signal output.
O
LSI reset output.
I
MIRR signal input(H:Speculer).
O
Command:/parameter:H switch signal output.
I
DSP cereal data input.
O
DSP cereal data input.
O
DSP cereal data clock output.
O
Internal CD/DC operation of MP3 operation & beginning.
O
DSP RESET:L.
I
WAIT signal input from DECODER.
-
FLASH writing power supply.
O
DECODER address passing output.
O
DECODER address passing output.
O
DECODER address passing output.
(Non connected)
O
DSP cereal data latch output.
O
Servo deriver MUTE control signal output(L:MUTE:ON)
O
Loading drive.
O
Loading drive.
O
DECODER address passing output.
O
DECODER address passing output.
O
DECODER address passing output.
O
DECODER address passing output.
I
Microcomputer reset terminal(L:Reset)
I
Sub-clock
-
Sub-clock
-
-
The main clock crystal oscillation machine.
I
The main clock crystal oscillation machine(20MHz).
-
5V
-
GND
O
Internal system clock output(Non connecte)
O
DECODER data writing.
O
(Non connected)
O
(Non connected)
O
DECODER data reading.
O
Address bus enable.
O
JBUS I/O switch.
I
Mechanism power supply ON:L.
I/O
DECODER I/O data bus
I/O
DECODER I/O data bus
I/O
DECODER I/O data bus
I/O
DECODER I/O data bus
UPD70F3033AC015(1/2)
1-27
KD-SH99R
Pin No. Symbol I/O Function
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
AD4
AD5
AD6
AD7
BVDD
BVSS
---
---
---
---
---
---
---
--MD
MC
ML
MP3SEL
PREQ
AMUTE
AVDD
AVSS
AVREF
PDET
SW2
SW3
SW4
REST
RFOK
REQ
EXP
ADIN0
ADIN1
ADIN2
ADIN3
---
CONT+B
SW1
PACK
INT0
INT1
JBINT
TESTMODE
12CD
---
12CC
RXDO
SID
SIC
TSO
I/O
DECODER I/O data bus.
I/O
DECODER I/O data bus.
I/O
DECODER I/O data bus.
I/O
DECODER I/O data bus.
-
5V
-
GND
O
(Non connected)
O
(Non connected)
O
(Non connected)
O
(Non connected)
O
(Non connected)
O
(Non connected)
O
(Non connected)
O
(Non connected)
O
DAC mode control data.
O
DAV mode control clock.
O
DAC mode control latch.
O
MP3/CD-DA switch SW L:Cd H:MP3
O
Mechanism power supply ON/OFF demand output(L:ON demand)
O
Audio output MUTE control signal output(L:MUTE ON)
-
5V(Power supply for AD converter)
-
GND(GND for AD converter)
-
5V(Standard voltage for AD converter)
I
BACKUP power supply detection(L:BACKUP power supply ON)
I
SW2 mechanism switch.
I
SW3 mechanism switch.
I
SW4 mechanism switch.
I
Surroundings position detection switch(L:Surroundings)
I
RFOK signal input.
I/O
Data demand.
I
H:Export L:For country 8cm CD.
I
Test key input 0 (A/D input)
I
Test key input (A/D input of one)
I
Test key input (A/D input of two)
I
Test key input (A/D input of three)
O
(Non connected)
I
LSI5V ON power supply control signal and JBUS control signal input.
I
SW1 mechanism switch.
I
PACK synchronous signal of CD-TEXT.
I
DECODER interrupt request.
I
DECODER interrupt request.
I
J-BUS interrupt signal input.
I
L: test mode shift.
I/O
12C data line.
O
(Non connected)
I/O
12C clock line.
I
FLASH writing cereal data input.
O
MP3 cereal data output and FLASH writing cereal data output.
O
MP3 cereal clock output and FLASH writing cereal clock output.
I
CD-TEXT data serial input.
UPD70F3033AC015(2/2)
1-28
MAS3507D-QG-G10 (IC806) :MP3 decoder
1.Pin layout
SID
SII
SIC
PI3
PI2
PI1
PI0
CLKO
PUP
WSEN
WRDY
AVDD
CLKI
AVSS
PI4
33 32 31 30 29 28 27 26 25 24 23
34
35
36
37
38
39
40
41
42
43
44
1
234567891011
XVSS
XVDD
PI8
SOC
SOI
SOD
22
21
20
19
18
17
16
15
14
13
12
KD-SH99R
PI12
PI13
PI14
PI15
PI16
PI17
PI18
PI19
RCS
PR
VSENS
DCSO
2.Block diagram
MPEG Bit Stream
Digital Audio Output
TE
POR
I2CC
Volume
Tone
Control
VSS
VDD
I2CD
(TOP VIEW)
EOD
DCEN
Sync
MPEG
Decoder
RTR
RTW
DCSG
Ancillary
Data
C
Decoder
to
Status
Config.Reg.
PIO
Status Start-up Config.
1-29
KD-SH99R
3.Pin function
Pin no. Symbol I/O Function
MAS3507D-QG-G10(1/2)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
TE
POR
I2CC
I2CD
VDD
VSS
DCEN
EOD
RTR
RTW
DCSG
DCSO
VSENS
PR
PCS
PI19
PI18
PI17
PI16
PI15
PI14
PI13
PI12
SOD
SOI
SOC
PI18
XVDD
XVSS
SID
SII
SIC
PI4
PI3
PI2
I
I
I/O
I/O
Supply
Supply
I
OUT
OUT
OUT
Supply
O
I
IN
IN
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
O
O
O
IN/OUT
Supply
Supply
I
I
I
IN/OUT
IN/OUT
IN/OUT
Test Enable
Reset, Active Low
2
I C Clock Line
2
I C Data Line
Positive Supply for Digital Parts
Ground Supply for Digital Parts
Enable DC/DC Converter or Voltage Supervision
PIO End of DMA, Active Low
PIO Ready to Read, Active Low
PIO Ready to Write, Active Low
DC Converter Transistor Ground
DC Converter Transistor Open Drain
DC Converter Voltage Sense
PIO DMA Request Read/Write
PIO Chip Select, Active Low
PIO Data(19)
i)Demand Pin in SDI mode
ii)data bit(7),MSB in PIO DMA input mode
PIO Data(18)
i)MPEG header bit11-MPEG ID(SDI mode)
ii)data bit(6) in PIO DMA input mode
PIO Data (17)
i)MPEG header bit 12-MPEG ID(SDI mode)
ii)data bit(5) in PIO DMA input mode
PIO Data(16)
i)SIC,alternative input for SIC(SDI mode)
ii)data bit(4) in PIO DMA input mode
PIO Data(15)
i)SII, alternative input for SII(SDI mode)
ii)data bit(3) in PIO DMA input mode
PIO Data(14)
i)SID, alternative input for SID (SDI mode)
ii)data bit(2) in PIO DMA input mode
PIO data(13)
i)MPEG header bit 13-Layer ID (SDI mode)
ii)data bit(1) in PIO DMA input mode
PIO Data (12)
i)MPEG header bit 14-Layer ID (SDI mode)
ii)data bit(0) in PIO DMA input mode
Serial Output Data
Serial Output Frame Identification
Serial Output Clock
Start-up : Clock output scaler on/off
1)
Operation : MPEG CRC error
Positive Supply of Output Buffers
Ground of Output Buffers
Serial Input Data
Serial Input Frame Identification
Serial Input Clock
Start-up : Select SDI/PIODMA input mode
1)
Operation : MPEG-Frame Sync
Start-up : Enable Layer 3 / Disable Layer 3 decoding
1)
Operation : MPE Gheader bit 20(Sampling Frequency)
Start-up : Enable Layer 2 / Disable Layer 2 decoding
1)
Operation : MPEG header bit 21(Sampling Frequency)
1-30
3.Pin function
Pin no. Symbol I/O Function
36
PI1
IN/OUT
Start-up : SDO Select 32 bit mode / 16 bit I S mode
1)
Operation : MPEG header bit 30(Emphasis)
37
P0
IN/OUT
Start-up : Select Multimedia mode / Broadcast mode
1)
Operation MPEG header bit 31 (Emphasis)
38
39
40
41
CLKO
PUP
WSEN
ERDY
O
O
I
O
Clock Output (normal 24.576 MHz)
Power Up, i.e.Status of Voltage Supervision
WS Enable : Enable DSP
WSEN=0 : Valid clock input at CLKI
WSEN=1 : Clock synthesizer PLL locked
42
43
44
AVDD
CLKI
AVSS
1)
Start-up configuration see Table 2.7.3. in (1)
Supply
I
Supply
Supply for Analog Circuits
Clock Input
Ground Supply for Analog Circuits
KD-SH99R
MAS3507D-QG-G10(2/2)
2
BU4066BCFV-X (IC322) : Quad analog switch
1. Pin layout & Block diagram
VDD C1 C4 I/O4 I/O3O/I4 O/I3
14 13 12 11 810 9
1234 756
I/O1 O/I1 O/I2 I/O2 VssC2 C3
1-31
KD-SH99R
LC895199K-ND2(IC601):CD-ROM decoder
1.Pin layout
144 109
1
108
36
37 72
73
2.Pin function
Pin No. Symbol Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSSO
ZRASO
ZCASO
ZCAS1
VSSO
ZOE
ZUWE
ZLWE
VSSO
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
VDD0
VSS0
RA8
IO0
IO1
IO2
IO3
IO4
IO5
VSSO
IO6
IO7
IO8
IO9
IO10
IO11
IO12
IO13
VSSO
VDD1
IO14
IO15
DREQ
DRESP
IOP7
IOP6
IOP5
IOP4
IOP3
IOP2
IOP1
IOP0
HDBDIR
RAS signal output terminal to buffer DRAM
CAS signal output 0 terminal to buffer DRAM(0 is used usually)
CAS signal output terminal 1 to buffer DRAM
Buffer DRAM output enable
Buffer DRAM upper write enable
Buffer DRAM lower write enable
Address signal output terminal to data buffer DRAM
5.0V
Address signal output terminal to data buffer DRAM
Data I/O terminal to data buffer DRAM. With built-in pull-up resistor
Data I/O terminal to data buffer DRAM. With built-in pull-up resistor
3.3V
Data I/O terminal to data buffer DRAM.With buolt-in pull-up resistor
General-purpose I/O port
LC895199K-ND2(1/3)
1-32
Pin No. Symbol Function
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
TEST0
XTALCK
XTAL
VDD0
VSS0
MCK
TEST1
DSDATA
DLRCK
DBCK
C2PO
SDATA
BCK
LRCK
EXCK
WFCK
SBSO
SCOR
PLL1
PLL2
PLL3
VSS0
VDD1
ZRESET
MCK3
CSCTRL
ZRO
ZWR
ZCS
SUA0
SUA1
SUA2
SUA3
SUA4
SUA5
SUA6
D0
D1
D2
VDD0
VSS0
D3
D4
D5
D6
D7
ZINTO
ZINT1
ZSMAIT
ZRSTCPU
CSEL
ZHRST
ATPINSEL
ZDASP
ZCS3FX
ZCS1FX
DA2
VSS1
VDD1
The terminal TEST.Please connect with VSS
X'tal oscillation circuit input terminal
X'tal oscillation circuit output terminal
5.0V
1/1,2/2,STOP output terminal of XTALCK
The terminal TEST. Please connet with VSS
DAC output terminal
Terminal for CD-DSP I/F
SUB-CODE I/O terminal
Relation connection of PLL terminal
(It is analog VSS in version LC895199 with built-in PLL)
3.3V (It is analog VDD in version LC895199 with buikt-in PLL)
LSI reset terminal
1/1, 1 /5, 2/5, 1/512, and STOP output terminal of XTALCK
Active Lo and Hi selection terminal on MC(microcontroller) side CS
Reading data of MC(microcontroller) signal input terminal
Writing data of MC(microcontroller) signal input terminal
Register chip selection signal input terminal from MC(microcontroller)
MC(microcontroller) register selection signal terminal
MC(microcontroller) data signal terminal.With buit-in puul-up resistor.
5.0V
MC(microcontroller) data signal terminal. With buit-in pull-up resistor.
Interrupt request signal output terminal to MC(microcontroller)
WAIT signal to MC(microcontroller)
Reset signal to CPU
ATAPI control signal
ATAPi data bus
Terminal ATAPI arrangement select terminal. Connects with VDD0
ATAPI data bus
3.3V
KD-SH99R
LC895199K-ND2(2/3)
1-33
KD-SH99R
Pin No. Symbol Function
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
DAO
ZPDIAG
DA1
ZIOCS16
HITRQ
ZDMACK
VSS1
IORDY
ZDIOR
ZDIOR
DMARQ
VSS1
DD15
DDO
DD14
DD1
VDDO
VSS1
DD13
DD2
DD12
DD3
VSS1
DD11
DD4
DD10
VSS1
VDD0
DD5
DD9
DD6
VSS1
DD8
DD7
VDD1
ATAPI data bus
ATAPI data bus
ATAPi data bus
ATAPi control signal
ATAPI control signal
5.0V
ATAPI control signal
ATAPI control signal
5.0V
ATAPI control signal
3.3V
LC895199K-ND2(3/3)
1-34
HA13164 (IC961) : Regulator
1.Pin layout
KD-SH99R
2.Block diagram
123456789101112131415
ANT OUT
EXT OUT
ANT CTRL
CTRL
CD OUT
AUDIO OUT
C3
0.1u
C4
0.1u
C5
0.1u
C6
10u
2
1
11
12
10
MEMORY
7
VCC ACC
8
Surge Protector
BIAS TSD
15
3
C1
100u
C2
0.1u
13
ILM AJGND
+B
ACC
BATT.DET OUT
9
COMPOUT
6
VDD OUT
4
SW5VOUT
5
ILMOUT
14
R1
C7
0.1u
0.1u
C8
3.Pin function
Pin No. Symbol Function
1
2
EXT
ANT
Output voltage is VCC-1 V when M or H level applied to CTRL pin.
Output voltage is VCC-1 V when M or H level to CTRL pin and H level
to ANT-CTRL.
3
4
5
6
7
8
9
10
11
12
13
14
15
ACC
VDD
SW5V
ACC5V
ANT CTRL
MEMORY
BATT DET
9V
CTRL
CD8V
AJ
ILMI
GND
Connected to ACC.
Regular 5.7V.
Output voltage is 5V when M or H level applies to CTRL pin.
Output for ACC detector.
L:ANT output OFF , H:ANT output ON
Connected to VCC.
Low battery detect.
Output voltage is 9V when M or H level applied to CTRL pin.
L:BIAS OFF, M:BIAS ON, H:CD ON
Output voltage is 8V when H level applied to CTRL pin.
Adjustment pin for ILM output voltage.
Output voltage is 10V when M or H level applies to CTRL pin.
Connected to GND.
UNIT R:
C:F
note1) TAB (header of IC)
connected to GND
1-35
KD-SH99R
LC75878W (IC501) : LCD driver
1. Pin layout
100 ~ 76
2. Block diagram
OSC
VLCD
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VDD
VSS
1
~
25
26 ~ 50
P1
GENERAL
PORT
CLOCK
GENERATOR
CONTRAST
ADJUSTER
P4
75
~
51
COM1
COMMON
DRIVER
COM8
S75/COM9
S74/COM10
S73
SEGMENT DRIVER & LATCH
CONTROL
REGISTER
SHIFT REGISTER
CCB
INTERFACE
S1
3. Pin function
No. Symbol
1~73
74
75
76~83
84~87
88
89
90
91
92
93
94
95
96
97
98
99
100
1-36
SEG1~SEG73
SEG74
SEG75
COM8~COM1
P1~P4
VDD
VLCD
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VSS
OSC
LCD RESET
CE
CL
DI
DI
INH
I/O
O
Segment driver output pin.
O
Segment driver output pin.
O
Segment driver output pin.
O
Common driver output pin.
O
General-purpose output pin.
-
Logic block power supply pin.
-
LCD driver power supply pin.
O
LCD driver bias 4/4 voltage (H-level) power pin.
I
LCD driver bias 3/4 voltage (intermediate level) power pin.
I
LCD driver bias 2/4 voltage (intermediate level) power pin.
I
LCD driver bias 1/4 voltage (intermediate level) power pin.
I
LCD driver bias 0/4 voltage (L-level) power pin.
-
Power supply pin to connect to ground.
I/O
Oscillator pin.
I
Display off, general-purpose output port L fixed input pin.
I
Chip enable
I
Synchronization clock
I
Transfer data
Function
CL
CE
M61508FP-X (IC911) : E. volume
1. Pin layout & Block diagram
VCC
(Anarog)
2. Pin function
Pin No.
1
2
3
DEFP IN1
DEFN IN1
4
5
6
7
8
9
DEFN OUT1
SEL OUT1
10
11
12
13
14
15
TONE OUT1
FADER IN1
REAR OUT1
FRONT OUT1
NonFader OUT1
16
17
18
19
VDDOUT1
VDDOUT2
20
21
22
NonFader OUT2
23
24
25
26
FRONT OUT2
REAR OUT2
FADER IN2
TONE OUT2
27
28
29
SEL OUT2
DEFN OUT1
30
31
32
33
34
35
DEFN IN1
DEFP IN1
36
REF
Symbol Function
REF
Grand for IC signal
Differential motion amp. Positive terminal
Differential motion amp. Negative terminal
INA1
INB1
INC1
IND1
Input terminal of input selector switch channel 1
Input terminal of input selector switch channel 1
Input terminal of input selector switch channel 1
Input terminal of input selector switch channel 1
Differential output terminal (-)
Input selector output terminal
VOL IN1
Volume 1 input terminal
Tone output terminal
Volume 2 input terminal
Fader volume control (Rear) output terminal
Fader volume control (Front) output terminal
Non fader volume output terminal
GND
DATA
GND terminal
Control data input terminal
Test terminal
Test terminal
CLOCK
VDD
Clock input terminal for serial data transport
Power supply terminal for digital
Non fader volume control output terminal
Fader volume (Front) output terminal
Fader volume (Rear) output terminal
Volume 2 input terminal
Tone output terminal
VOL IN2
Volume 1 input terminal
Input selector output terminal
Differential output terminal (-)
IND2
INC2
INB2
INA2
Input terminal of input selector switch channel 2
Input terminal of input selector switch channel 2
Input terminal of input selector switch channel 2
Input terminal of input selector switch channel 2
Differential motion amp negative input terminal
Differential motion amp positive input terminal
VCC
Power supply terminal
50K
27282930313233343536
LOUDNESS
+
3BAND TONE CONTROL
(BASS/MID/TREBLE)
ZERO CROSS
DETECTOR
ZERO CROSS
DETECTOR
LOUDNESS
+
3BAND TONE CONTROL
(BASS/MID/TREBLE)
A
B
B
A
2526
Zero detect
Select SW
121110987654321
24 23 22 21 20 19
VDO
(Digital)
Soft select
12dB
I/F
12dB
TIMER
DETECTOR
GND
13 14 15 16 17
KD-SH99R
18
1-37
KD-SH99R
M63008FP-X (IC604) : 5ch Actuator driver
1.Pin layout
CH3IN
OUT3
IN3-
VBS2
Vm2
IN3+
N.C
VM3-
VM3+
GND
VM4+
VM4-
VM5+
VM5-
OUT5
IN5-
IN5+
IN4+
IN4-
OUT4
2.Block diagram
IN1+
IN1-
OUT1
VM1(+)
VM1(-)
VM2(+)
VM2(-)
OUT2
IN2-I
IN2+
VREFO
VREF
REGB
REG+
IN1-
Vm1
IN1+
VBS1
REG+
REGB
Vm1
5
VBS2
CH1
CH2
VBS1
VREF
X5
X5
E1
E2
VBS1
VBS1
VBS1
VBS1
3
6
7
9
8
12
13
14
15
16
21
20
2
VREG
1
OUT1
VM1-
VM1+
GND
1.25V
19 17
VM2+
R
R
Vrefm1
VM2-
BIAS
IN2-
OUT2
VBS1
Low,Open
MUTE ON
1~4
CH
IN2+
4
Vm1
VBS1
MUTE1
MUTE2
VBS2
18
VREF
SS,GND
39
Vm2
HI :Sleep
5CH
10 113233
VREFO
Vrefm2
VREFO
SLEEP
TSD
Vm2
38
VBS2
R
R
E3
VBS2
CH3
X8
VBS2
CH4
X8
E4
VBS2
CH5
X8
VBS2
E5
40
37
41
42
34
35
31
30
23
24
22
29
28
26
25
27
IN3IN3+
OUT3
CH3 IN
VM3(+)
VM3(-)
VM4(+)
VM4(-)
IN4IN4+
OUT4
VM5(+)
vm5(-)
IN5IN5+
OUT5
MUTE1 MUTE2
SS,GND
GND (4PIN)
1-38
PCM1716E-X (IC802) : D/A converter
KD-SH99R
1. Pin layout
2. Block diagram
BCK
LBCK
DATA
ML/llS
MC/DM1
MD/DM0
CS/WO
MODE
MUTE
RST
3. Pin function
Pin
Symbol Function
No.
1
LRCK
2
DATA
3
BCK
4
CLKO
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
XTI
XTO
DGND
VDD
VDD2R
AGND2R
EXTR
NC
VOUTR
AGND1
Vcc1
VOUTL
NC
EXTL
AGND2L
Vcc2L
ZERO
RST
CS/IWO
MODE
MUTE
MD/DM0
MC/DM1
ML/IIS
28 15
114
Serial
Input
I/F
Mode
Control
I/F
Mult-level
8X Oversampling
Digital Filter
with
Function Controller
SCK
BPZ-Cont
Crystal OSC
XTI XTO CLKO Vcc1 VccAGND1 DGND
Delta-Sigma
Modulator
Power Supply
Vcc2L
DAC
DAC
AGND2L
Vcc2R
AGND2R
Open drain
Low-pass
Filter
Low-pass
Filter
I/O
I
LRCK clock input
I
Serial audio data input
I
Bit clock input for serial audio data
O
Buffered output of system clock
I
Oscillator input / External clock input
O
Oscillator output
-
Digital ground
-
Digital power +5V
-
Analog power +5V
-
Analog ground
O
Rch common pin of analog output amp
-
Non connection
O
Rch analog voltage output of audio signal
-
Analog ground
-
Analog power +5V
O
Lch analog voltage output of audio signal
-
Non connection
O
Lch common pin of analog output amp
-
Analog ground
-
Analog power +5V
O
Zero data flag
I
Reset
I
Chip select / Input format selection
I
Mode control select
I
Mute control
I
Mode control, Data / De-emphasis selection 1
I
Mode control, BCK / De-emphasis selection 2
I
Mode control, WDCK / Input format selection
VoutL
EXTL
VoutR
EXTR
ZERO
1-39
KD-SH99R
SAA6579T-X(IC51):RDS
1.Pin layout
QUAL
RDDA
Vref
MUX
ODA
V
V
SSA
CIN
SCOUT
2.Block diagram
1
2
3
4
5
6
7
8
RDCL
16
T57
15
OSCO
14
OSCI
13
V
0DD
12
V
SSD
11
TEST
10
MODE
9
121413
3.Pin function
4
8
7
CLOCKED
COMPARATOR
5
3
REFERENCE
VOLT AGE
Pin No.
1
2
3
4
ANTIALIASING
FILTER
6 11
Symbol
VP1
QUAL
RDDA
Vref
MUX
57 kHz
BANDPASS
(8th ORDER)
COSTAS LOOP
VARIABLE AND
FIXED DIVIDER
CLOCK
REGERATION
AND SYNC
RECONSTRUCTION
FILTER
TEST LOGIC AND OUTPUT
SELECTOR SWITCH
OSCILATOR
AND
DIVIDER
BIPHASE
SYMBOL
DECODER
910
Description
Quality indication output
RDS data output
Reference voltage output (0.5VDDA)
Multiolex signal input
QUALITY BIT
GENERATOR
DIFFERENTIAL
DECODER
1
2
15
15
1-40
5
6
7
8
9
10
11
12
13
14
15
16
VDDA
VSSA
CIN
SCOUT
MODE
TEST
VSSD
VDDD
OSCI
OSCO
T57
RDCL
+5V supply voltage for analog part
Ground for analog part (0V)
Subcarrier input to comparator
Subcarrier output of reconstruction filter
Oscllator mode / test control input
Test enable input
Ground for digital part (0V)
+5V supply voltage for digital part
Oscillator input
Oscillator output
57 kHz clock signal output
RDS clock output
+
+
-
-
+
+
-
-
-
+
+
BA3220FV-X (IC301,IC401) : Line out amp
1.Pin layout
LGND
13
8
OUTL OUTR RGND
14
3220
17
2.Block diagram
CL-
14
KD-SH99R
CR-
1112
10
9
CR+
8
REFL
1
2
Vcc
3
INL
4
NFLCL+
REFR
FILTER
56
FIL
NFR
7
INR
1-41
KD-SH99R
IS41C16256-35T(IC602):RAM
1.Pin layout
2.Block diagram
OE
WE
LCAS
UCAS
RAS
44
21
122
CAS
CLOCK
GENERATOR
RAS
CLOCK
GENERATOR
REFRESH
COUNTER
WE
CAS WE
RAS
CONTROL
LOGICS
DATA I/O BUS
COLUMN DECODERS
SENSE AMPLIFIERS
OE
CONTROL
LOGIC
OE
I/O0-I/O15
A0-A8
ADRESS
BUFFERS
MEMORY ARRAY
ROW DECODER
DATA I/O BUFFERS
262.144 x 16
1-42
IC-PST9333U-X (IC702) : Reset IC
1. Pin layout 2. Block diagram
KD-SH99R
1
NC
GND
3. Pin function
2
GND
Pin No.
1
2
3
4
NC
4
Vcc
3
VOUT
Symbol
NC
GND
VOUT
Vcc
Vcc
Function
Non connect
GND terminal
Reset signal output terminal
Power supply terminal
NC
4
1
3
2
VOUT
GND
1-43
KD-SH99R
NJM4565V-X (IC171,IC951,IC323) : Ope amp
1. Pin layout & Block diagram 2. Pin function
Pin
Function
No.
1
2
3
4
A
B
8
7
6
8
1
2
3
4
5
6
7
8
A output
A-input
A+input
VB+input
B-input
B output
V+
NJM4580V-X (IC801) : CD LPF
1. Pin layout & Block diagram 2. Pin function
1
2
3
4
A
B
8
7
6
8
Pin
No.
1
2
3
4
5
6
7
8
Function
A output
A -input
A +input
VB +input
B -input
B output
V+
RPM6938-SV4 (IC561) : Remote sensor
1.Block diagram
AMP
I/V
conversion
PD
magnetic shield
1-44
BPF
fo
trimming
circuit
AGC
Detector
Vcc
Comp
Vcc
22k
Rout
GND
S-81332HG-KC-X (IC804) : Regulator
KD-SH99R
1. Pin layout
1 Vout
2 GND
3 Vin
1 2 3
LB1830M-X(IC608):Regulator
1.Pin layout
IN2 IN1 Vm Vm1 Vcont
10 9 8 7 6
2. Block diagram
VIN 3
VREF
1 VOUT
2
GND
2.Block diagram
OUT1 Vs OUT2
VCC
12345
Vcc OUT2 GND OUT1 Vs
Logic
Predriver
IN1 IN2 Vm
TC74VHC126FT-X(IC605):Buffer
1.Pin layout 2.Function
1
1G
1A
1Y
2G
2A
2Y
2
3
4
5
6
14
13
12
11
10
9
Vcc
4G
4A
4Y
3G
3A
INPUTS OUTPUT
G
L
H
H
Vcont
A
X
L
H
X:Don't Care
Z: High impedance
Vref
GND
Vref
Y
Z
L
H
GND
7
3Y
8
1-45
KD-SH99R
VICTOR COMPANY OF JAPAN, LIMITED
MOBILE ELECTRONICS DIVISION
PERSONAL & MOBILE NETWORK BUSINESS UNIT. 10-1,1Chome,Ohwatari-machi,Maebashi-city,Japan
(No.49645)
200106
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