JVC KD-SH9700, KD-SH9750 Service Manual

SERVICE MANUAL

CD RECEIVER

4983120035

KD-SH9750,KD-SH9700

ATT

ANGLE

EQ

CD

DAB

DISC

FM

PRESET

PRESET

R D

Detachable

AM

CH

AUX SEL

RM-RK100

SRC

DISC

VOLUME

D

DISP

ATT

SEL

3456 M21

BBE

MODE

KD-SH9750

Area Suffix

J -------------------------- U.S.A.
C --------------------- CANADA

KD-SH9750C KD-SH9700J

KD-SH9700

Area Suffix

J -------------------------- U.S.A.

ARSENAL rogo
Line output level
WARRANTY

KD-SH9750J

4 V 4 V 2 V

2 YEAR 1 YEAR 1 YEAR

TABLE OF CONTENTS

1 Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

2 Disassembly method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

3 Adjustment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28

4 Description of major ICs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-34

COPYRIGHT © 2003 VICTOR COMPANY OF JAPAN, LIMITED

No.49831

2003/5

SPECIFICATION

AUDIO
AMPLIFIER
SECTION

TUNER
SECTION

CD
PLAYER
SECTION

GENERAL Power Requirement Operating Voltage DC 14.4 V (11 V to 16 V allowance)

Design and specifications are subject to change without notice.
If a kit is necessary for your car consult your telephone directory for the nearest car audio speciality shop.

1-2 (No.49831)

Maximum Power Output Front 50 W per channel

Rear 50 W per channel

Continuous Power Output (RMS) Front 19 W per channel into 4 Ω, 40 Hz to

20,000 Hz at no more than 0.8% total
harmonic distortion.

Rear 19 W per channel into 4 Ω, 40 Hz to

20,000 Hz at no more than 0.8% total
harmonic distortion. 0.8% total

harmonic distortion.
Load Impedance 4 Ω (4 Ω to 8 Ω allowance)
Equalizer Control Range Frequencies 60 Hz, 150 Hz, 400 Hz, 1 kHz, 2.4 kHz,

6 kHz, 12 kHz

Level ±10 dB
Frequency Response 40 Hz to 20,000 Hz
Signal-to-Noise Ratio 70 dB
Line-In Level/Impedance (KD-SH9750 only)
Line-Out Level/Impedance KD-SH9750 4.0 V/20 kΩ load (full scale)

Output Impedance 1 kΩ
Frequency Range FM 87.5 MHz to 107.9 MHz (with channel

[FM Tuner] Usable Sensitivity 11.3 dBf (1.0 µV/75 Ω)

[AM Tuner] Sensitivity 20 µV

Type Compact disc player
Signal Detection System Non-contact optical pickup (semiconductor laser)
Number of channels 2 channels (stereo)
Frequency Response 5 Hz to 20,000 Hz
Dynamic Range 98 dB
Signal-to-Noise Ratio 102 dB
Wow and Flutter Less than measurable limit
MP3 (MPEG Audio Layer 3) Max. Bit rate 320 Kbps

(R)

WMA (Windows Media

Grounding System Negative ground
Allowable Operating Temperature 0°C to +40°C (32°F to 104°F)
Dimensions (W x H x D) Installation Size 182 mm x 52 mm x 161 mm

Audio) Max. Bit rate 192 Kbps

LINE IN 1.5 V/20 kΩ load

KD-SH9700 2.0 V/20 kΩ load (full scale)

interval set to 200 kHz) 87.5 MHz to

108.0 MHz (with channel interval set to
50 kHz)

AM 530 kHz to 1 710 kHz (with channel

interval set to 10 kHz) 531 kHz to 1 602
kHz (with channel interval set to 9 kHz)

50 dB Quieting Sensitivity 16.3 dBf (1.8 µV/75 Ω)

Alternate Channel Selectivity (400 kHz)

Frequency Response 40 Hz to 15,000 Hz

Stereo Separation 35 dB

Capture Ratio 1.5 dB

Selectivity 35 dB

Panel Size 188 mmx 58 mm x 17 mm

Mass 1.8 kg (4.0 lbs) (excluding accessories)

65 dB

(7-3/16" x 2-1/16" x 6-3/8")

(7-7/16" x 2-5/16" x 11/16")

1.1 Safety Precautions

SECTION 1

Precautions

!

!

Burrs formed during molding may be left over on some parts of the chassis. Therefore,
pay attention to such burrs in the case of preforming repair of this system.

Please use enough caution not to see the beam directly or touch it in case of an
adjustment or operation check.

(No.49831)1-3

1.2 Preventing static electricity

Electrostatic discharge (ESD), which occurs when static electricity stored in the body, fabric, etc. is discharged, can destroy the laser
diode in the traverse unit (optical pickup). Take care to prevent this when performing repairs.

1.2.1 Grounding to prevent damage by static electricity

Static electricity in the work area can destroy the optical pickup (laser dio de) in devices such as CD players.
Be careful to use proper grounding in the area where repairs are being performed.

(1) Ground the workbench

Ground the workbench by laying conductive material (such as a conductive sh eet) or an iron plate over it before placing the
traverse unit (optical pickup) on it.

(2) Ground yourself

Use an anti-static wrist strap to release any static electricity built up in your body.

(caption)
Anti-static wrist strap

1M

Conductive material
(conductive sheet) or iron plate

(3) Handling the optical pickup

• In order to maintain quality during transport and before instal lation, both sides of the laser di ode on the replacement optica l
pickup are shorted. After replacement, return the shorted parts to their original condition.
(Refer to the text.)

• Do not use a tester to check the condition of the laser diode in the optical pickup. The tester's internal power source can easily
destroy the laser diode.

1.3 Handling the traverse unit (optical pickup)

(1) Do not subject the tra v erse unit (optical pickup) to strong shocks, as it is a sensitive, complex unit.
(2) Cut off the shorted part of the flexible cable using nippers, etc. after replacing the optical pickup. For specific details, refer to the

replacement procedure in the text. Remove the anti-static pin when replacing the traverse unit. Be careful not to take too long a

time when attaching it to the connector.
(3) Handle the flexible cable carefully as it may break when subjected to strong force.
(4) It is not possible to adjust the semi-fixed resistor that adjusts the laser power. Do not turn it.

1.4 Attention when traverse unit is decomposed *Please refer to "Disassembly method" in the text for the CD pickup unit.

• Apply solder to the short land before the flexible wire is disconnected from the connector on the CD pickup unit.
(If the flexible wire is disconnected without applying solder, the CDpickup may be destroyed by static electricity.)

• In the assembly, be sure to remove solder from the short land after connecting the flexible wire.

Short-circuit point

(Soldering)

Flexible wire

1-4 (No.49831)

Short-circuit point

Pickup

Pickup

SECTION 2

Disassembly method

2.1 Main body section

2.1.1 Removing the front panel assembly (See Fig.1)

(1) Push th e detach button in the lower right part of the front

panel assembly.

(2) Remove the front panel assembly in the direction of the

arrow.

Front panel assembly

Detach button

Fig.1

(No.49831)1-5

2.1.2 Removing the top chassis (See Figs.2 to 6)

• Turn on power.
(1) Push the eject bu tton in the upper right part of the front

panel assembly to move the front panel assembly as
shown in Fig.2 and turn off power.

(2) Remove the two screws A attaching the top chassis from

the top side of the main body. (See Fig.3.)

(3) Remove the three screws B attaching the top chassis from

the both sides of the main body. (See Figs.4 and 5.)

(4) Remove the screw C and three screws D attaching the heat

sink from the left side of the main body. (See Fig.5.)

(5) Remo ve the two screws E and screw F attaching the top

chassis from the back side of the main body. (See Fig.6 .)

(6) Move the top chassis upward and remove it with the CD

mechanism assembly. The connector CN501 on the CD
mechanism assembly is disconnected from the connector
CN981 on the main board.

Top chassis

Front panel assembly

C

Top chassis

BB

Fig.4

Top chassis

Heat sink

Fig.5

E

Eject button

Fig.2

Top chassis

Fig.6

AA

BD

F

Front panel assembly

1-6 (No.49831)

Fig.3

2.1.3 Removing the mecha control board (See Fig.7)

• Prior to performing the following procedures, remove the top
chassis.
(1) Disconnect the card wire from the connector CN601 on the

mecha control board.

(2) Remove the five screws G attaching the mecha control

board.

(3) Release the joints a and b, remove the mecha control

board

Mecha control board

G

CN601

2.1.4 Removing the CD mechanism assembly (See Fig.8)

• Prior to performing the following procedure, re move the top
chassis.
(1) Remove the three screws H from the inside of the top

chassis and remove the CD mechanism assembly.

a

Top chassis

b

G

Fig.7

H

HH

CD mechanism assembly

Fig.8

(No.49831)1-7

2.1.5 Removing the motor assembly (See Figs.9 to 11)

• Prior to performing the following procedures, remove the top
chassis.
(1) Remove the spring from the motor bracket. (See Fig.9.)
(2) Disconnect the wire from the connector CN982 on the main

board. (See Fig.10.)

(3) Remove the two screws J attaching the motor bracket.

(See Fig.10.)

(4) Remove the washer attaching the clutch assembly and pull

out the clutch assembly from the shaft. (See Fig.11.)

(5) Remove the two screws K attaching the motor assembly to

the motor bracket. (See Fig.11.)

Main board

Spring

Motor braket

Fig.9

CN982

Motor braket

Clutch assembly

J

Fig.10

Motor braket

K

Motor assembly

1-8 (No.49831)

Washer

Fig.11

2.1.6 Removing the main board (See Figs.12 to 16)

A

A

• Prior to performing the following procedures, remove the top
chassis and motor assembly.
(1) Disconn ect the flexible wires from the connectors CN703

and CN991 on the main board respectively. (See Fig.12.)
(2) Move the front bracket backward until it stops.
(3) Remove the four screws L attaching the arm brackets (L)

and (R). Move the arm brackets (L) and (R) from the rod

gear. (See Fig.12.)
(4) Remove the rod ge ar.
(5) Remove the screw M attaching the rear panel to the bottom

cover from the back side of the main body. (See Fig.14.)
(6) Remove the three scre ws N attaching th e main board a nd

move the main board backwards to release the two joints

c. (The main board will be removed with the rear panel and

rear heat sink) (See Figs.12 and 15.)
(7) Remove the scre w P and Q attaching the rear heat sink.

(See Fig.16.)
(8) Remove the three screws R and screw S attaching the rear

panel, then remove the main board. (See Fig.16.)

Rear panel

M

Bottom cover

Fig.14

Joint c

Main board

Joint c

rm

brackets (L)

L

CN703

rm brackets (R)

NN

Main board

Arm
brackets (R)

L

Rod gear

CN991

Fig.12

Arm brackets (L)

M

R

Rear panel

S

Fig.15

P

Q

Rear heat sink

Fig.16

Rod gear

Fig.13

Main board

(No.49831)1-9

2.1.7 Removing the lifter switch board (See Fig.17)

• Prior to performing the following procedure, remove the top
chassis, motor assembly and main board.
(1) Remove th e two screws T attach ing the lifter sw itch boa rd

to the bottom chassis.

2.1.8 Removing the lifter board (See Figs.18 to 24)

• Prior to performing the following procedures, remove the top
chassis and front panel assembly.
(1) Disconne ct the flexible wire from the connector CN991 on

the main board. (See Fig.18.)

(2) Remove the four screws U attaching the front bracket on

the both sides of the main body. (See Figs.19 and 20.)

(3) Push th e pin of the joint d on the front side of the front

bracket to release the detach lever. (See Fig.21.)

(4) Remove the screw V attaching the connector cover in the

rear side of the front bracket. (See Fig.22.)

(5) Release the two joints f w hile pushing them from the front

side, and then move the connector cover in the direction of
the arrow and release the eight joints e. (See Figs.22 and

23.)

(6) Remove the two screws W attaching the lifter board from

the front side of the main body. (See Fig.24.)

Main board

Lifter switch board

Front bracket

Bottom chassis

T

Fig.17

U

Fig.19

CN991

1-10 (No.49831)

Front bracket

U

Fig.20

Front bracket

Fig.18

r

Joint d

f

Front bracket

Joint f

V

Connector cover

Joint e

Joints e

Lifter board

Fig.21

Joint

Front bracket

Fig.22

e

Datch leve

Joint e

Joint

Joint e

Fig.23

Fig.24

Connector cover

W

(No.49831)1-11

2.1.9 Removing the front board (See Figs.25 to 28)

• Prior to performing the following procedures, remove the fro nt
panel assembly.
(1) Remove the six screws X atta ching the rear panel to the

front panel assembly. (See Fig.25.)

(2) Pul l out the volume knob from the front side of the front

panel assembly. (See Fig.26.)

(3) Release the ten joints g of the front panel and the rear pan-

el. (See Fig.27.)

(4) Take out the front boa rd from the front panel assembly.

(See Fig.28.)

XX

Rear panel

XX

Fig.25

Front panel assembly

Volume knob

Joints g

Joints g

Fig.26

Rear panel

Joints g

Joints g

Fig.27

Front board

Fig.28

1-12 (No.49831)

2.2 CD Mechanism section

A

2.2.1 Removing the top cover
(See Figs.1 and 2)

(1) Remove the fo ur screws A on the both side of the body.
(2) Lift the front side of the top cover an d move the top cover

backward to release the two joints a.

Top cover

Joints a

A

Joints a

A

Fig.1

Fig.2

Top cover

(No.49831)1-13

2.2.2 Removing the connector board
(See Figs.3 to 5)

CAUTION:

Before disconnecting the flexible wire from the pickup, solder
the short-circuit point on the pickup. No observance of this
instruction may cause damage of the pickup.
(1) Remove the screw B fixing the connector board.
(2) Solder the short-circuit point on the pickup.
(3) Disconnect the flexible wire from the pickup.
(4) Move th e connector board in the direction of the arrow to

release the two joints b.

(5) Unsolder the wires on the connector board if necessary.

CAUTION:

Unsolder the short-circuit point after reassembling.

B

Connector board

Flexible wire

Wires

Joints b

Short-circuit point

Fig.3

Short-circuit point

(Soldering)

Pickup

Flexible wire

Frame

Pickup

Fig.4

B

Connector board

Fig.5

1-14 (No.49831)

2.2.3 Removing the DET switch

(See Figs.6 and 7)

(1) Exten d the two tabs c of the feed sw. hol der and pull out

the switch.

(2) Unsol der the DET switch wire if necessary.

DET

switch

Connector

board

Pickup

Fig.6

DET switch

Tab c

Tab c

DET switch wire

Feed sw. holder

Fig.7

(No.49831)1-15

2.2.4 Removing the chassis unit

r

(See Figs.8 and 9)

• Prior to performing the following procedure, remove the top

cover and connector board.
(1) Remove the two suspension springs (L) and (R) attaching

the chassis unit to the frame.

CAUTION:

• The shape of the suspension spring (L) and (R) are
different. Handle them with care.

• When reassembling, make sure that the three shafts
on the underside of the chassis unit are inserted to the
dampers certainly.

Suspension spring (R)

Chassis unit

Suspension spring (L)

Frame

Suspension spring (R)

Chassis unit

Shafts

Damper

Damper

Suspension spring (L)

Fig.8

Shaft

Dampe

Frame

Fig.9

1-16 (No.49831)

2.2.5 Removing the clamper assembly
(See Figs.10 and 11)

• Prior to performing the following procedure, re move the top

cover.
(1) Remove the clamper arm spring.
(2) Move the clamper assembly in the direction of the arrow to

release the two joints d.

Clamper arm
spring

Joint d

Joint d

Clamper assembly

Fig.10

Clamper arm spring

Chassis rivet
assembly

Joint d

Clamper assembly

Chassis rivet assembly

Joint d

Fig.11

(No.49831)1-17

2.2.6 Removing the loading / feed motor assembly
(See Figs.12 and 13)

• Prior to performing the following procedure, remove the top

cover, connector board and chassis unit.
(1) Remove the screw C and move the loading / feed motor

assembly in the direction of the arrow to remove it from the
chassis rivet assembly.

(2) Disconnect the wire from the loading / feed motor assembly

if necessary.

CAUTION:

When reassembling, connect the wire from the loadin g /
feed motor assembly to the flame as shown in Fig.12.

Loading / feed motor assembly

Fig.12

Loading / feed motor assembly

C

Fig.13

1-18 (No.49831)

2.2.7 Removing the pickup unit

r

(See Figs.14 to 18)

• Prior to performing the following procedure, re move the top

cover, connector board and chassis unit.
(1) Remove the screw D and pull out the pu. shaft holder from

the pu. shaft.
(2) Remove the screw E attaching th e feed sw. holder.
(3) Move the part e of the pickup unit upward with the pu. shaft

and the feed sw. holder, then release the joint f of the feed

sw. holder in the direction of the arrow. The joint g of the

pickup unit and the feed rack is released, and the feed sw.

holder comes off.
(4) Remove the pu. shaft from the pickup unit.
(5) Remove the scre w F attaching the feed rack to the pickup

unit.

2.2.8 Reattaching the pickup unit
(See Figs.14 to 17)

(1) Reattach the feed rack to the pickup unit using the screw F.
(2) Reattach the feed sw. holder to the feed rack while setting

the joint g to the slot of the feed rack and setting the joint f
of the feed rack to the switch of the feed sw. holder
correctly.

(3) As the feed sw. holder is temporarily attached to the pickup

unit, set to the gear of the joint g and to the bending part of
the chassis (joint h) at a time.

CAUTION:

Make sure that the part i on the underside of the feed
rack is certainly inserted to the slot j of the change lock

lever.
(4) Reattach the feed sw. holder using the screw E.
(5) Reattach the pu. shaft to the pickup unit. Reatta ch the pu .

shaft holder to the pu. shaft using the screw D.

Part e

Joint g

Feed sw. holder

Feed rack

Part i

E

Slot j

F

Fig.15

Pu. shaft

Pickup unit

Joint f

Joint h

Fig.16

Feed rack

Pickup unit

Feed sw. holder

D

Pu. shaft holde

Joint f

Pu. shaft

D

Pu. shaft holder

Feed sw. holder

Pickup unit

Fig.14

Part e

E

Joint g

Pickup unit

Feed rack

Fig.17

Pickup unit

Joint g

Joint f

Feed sw. holder

Fig.18

(No.49831)1-19

2.2.9 Removing the trigger arm

r

(See Figs.19 and 20)

• Prior to performing the following procedure, remove the top
cover, connector board and clamper unit.
(1) Turn the trigger arm in the direction of the arrow to release

the joint k and pull out upward.

CAUTION:

When reassembling, insert the part m and n of the trigger
arm into the part p and q at the slot of the chassis rivet
assembly respectively and join the joint k at a time.

Chassis rivet assembly

Trigger arm

Chassis

rivet

assembly

Joint k

Trigger arm

Fig.19

Part p

Part q

Part m

Part n

2.2.10 Removing the top plate assembly

(See Fig.21)

• Prior to performing the following procedure, remove the top
cover, connector board, chassis unit, and clamper assembly.
(1) Remove the screw H.
(2) Move the top plate assembly in the direction of the arrow to

release the two joints r.

(3) Unsolder the wire marked s if necessary.

H

Fig.20

Top plate assembly

Joints

s

Fig.21

1-20 (No.49831)

2.2.11 Removing the mode sw. / select lock arm
(See Figs.22 and 23)

• Prior to performing the following procedure, re move the top

plate assembly.
(1) Bring up the mode sw. to release from the link plate (joint t)

and turn in the direction of the arrow to release the joint u.
(2) Unsol der the wire of the mode sw. marked s if necessary.
(3) Turn th e select lock arm in the direction of the arrow to

release the two joints v.
(4) The select lock arm spring comes off the select lock arm at

the same time.

Link plate

Joint u

Fig.22

Joint t

Mode sw.

Select lock arm

s

Top plate

Select lock arm

Link plate

Select lock arm

Fig.23

Top plate

Hook w

Select lock
arm spring

Joints v

(No.49831)1-21

2.2.12 Reassembling the mode sw. / select lock arm
(See Figs.24 to 26)

REFERENCE:

Reverse the above removing procedure.
(1) Reattach the select lock arm spring to the top plate and set

the shorter end of the select lock arm spring to the hook w
on the top plate.

(2) Set the other longer end of the select lock arm spring to the

boss x on the underside of the select lock arm, and join the
select lock arm to the slots (joint v). Turn the select lock
arm as shown in the figure.

(3) Reattach the mode sw. while setting the part t to th e first

peak of the link plate gear, and join the joint u.

CAUTION:

When reattaching the mode sw., check if the points y and
z are correctly fitted and if each part operates properly.

Select lock arm spring

Hook w

Joint v

Joint v

Select lock arm

Boss x

Fig.24

Joint t

Point y

Link plate

Point z

Link plate

Fig.25

Mode sw.

Select
lock arm

Joint t

Joint u

Fig.26

1-22 (No.49831)

2.2.13 Removing the select arm R / link plate

(See Figs.27 and 28)

• Prior to performing the following procedure, re move the top

plate assembly.
(1) Bri ng up the select arm R to release from the link plate

(joint a') and turn as shown in the figure to release the two
joints b' and joint c'.

(2) Move the link plate in th e direction of the arrow to release

the joint d'. Remove the link plate spring at the same time.

REFERENCE:

Before removing the link plate, remove the mode sw..

Select arm R

Joint b'

Link plate spring

Joint c'

Joint a'

Link plate

Joint b'

Fig.27

Joint r

2.2.14 Reattaching the Select arm R / link plate

(See Figs.29 and 30)

REFERENCE:

Reverse the above removing procedure.
(1) Reattach th e link plate spring.
(2) Reattach the li nk plate to the link pla te spri ng wh ile joini ng

them at joint d'.

(3) Reattach the joint a' of the select arm R to the first peak of

the link plate while joining the two joints b' with the slots.
Then turn the select arm R as shown in the figure. The top
plate is joined to the joint c'.

CAUTION:

When reattaching the sele ct arm R, check if the points e'
and f' are correctly fitted and if each part operates
properly.

Top plate

Select arm R

Joint b'

Joint d'

Link plate

Fig.28

Link plate spring

Joint c'

Joint d'

Joint b'

Joint a'

Fig.29

Joint a'

Point e'

Link plate

Point f'

Fig.30

(No.49831)1-23

2.2.15 Removing the loading roller assembly
(See Figs.31 to 33)

• Prior to performing the following procedure, remove the

clamper assembly and top plate assembly.
(1) Push inw ard the loading roller assembly on the gear side

and detach it upward from the slot of the joint g' of the lock
arm rivet assembly.

(2) Detach the loading roller assembly from the slot of the joint

h' of the lock arm rivet assembly.
The roller guide comes off the gear section of the loading

roller assembly.
Remove the roller guide and the HL washer from the shaft

of the loading roller assembly.
(3) Remove the screw J attaching the lock arm rivet assembly.
(4) Push th e shaft at the join t i' of the lock arm rivet assembly

inward to release the lock arm rivet assembly from the slot

of the L side plate.
(5) Extend the lock arm rivet assembl y outward and release

the joint j' from the boss of the chassis rivet assembly. The

roller guide springs on both sides come off at the same

time.

CAUTION:

When reassembling, reattach the left and right roller
guide springs to the lock arm rivet assembly before
reattaching the lock arm rivet assembly to the chassis
rivet assembly. Make sure to fit the part k' of the roller
guide spring inside of the roller guide. (Refer to Fig.34.)

Roller guide
spring

Part k'

Chassis rivet assembly

Loading roller assembly

Loading roller assembly

Roller guide
spring

Fig.32

Boss

Roller guide

Joint h'

Roller guide spring

Loading roller assembly

HL washer

Loading roller assembly

Joint g'

Lock arm rivet assembly

Fig.31

Roller guide

Roller guide spring

Roller guide spring

J

Lock arm rivet assembly

Lock arm rivet assembly

L side plate

Roller guide spring

Joint i'

Joint j'

Fig.33

Roller guide

HL washer

Roller shaft assembly

Loading roller

Roller guide spring

Fig.34

1-24 (No.49831)

2.2.16 Removing the loading gear 5, 6 and 7
(See Figs.35 and 36)

• Prior to performing the following procedure, re move the top

cover, chassis unit, pickup unit and top plate assembly.
(1) Remove the screw K attaching the loading gear bracket.

The loading gear 6 and 7 come off the loading gear
bracket.

(2) Pull out the loading gear 5.

K

Loading gear 5

Loading gear bracket

K

Loading gear 6

Loading gear 5

Loading gear 3

Fig.35

Loading gear bracket

Loading gear 6

Loading gear 7

Fig.36

(No.49831)1-25

2.2.17 Removing the gears
(See Figs.37 to 40)

• Prior to performing the following procedure, remove the top

cover, chassis unit, top plate assembly and pickup unit.

• Pull out the loading gear 3. (See Fig.35.)

(1) Pull out the feed gear.
(2) Move the loading plate assembly in the direction of the

arrow to release the L side plate from the two slots m' of the
chassis rivet assembly. (See Fig.37.)

(3) Detach the loading plate assembly upward from the

chassis rivet assembly while releasing the joint n'. Remove
the slide hook and loading plate spring from the loading
plate assembly.

(4) Pul l out the loading gear 2 and remove the change lock

lever.

(5) Remo ve the E ring a nd washer atta ching th e change gear

2.

(6) The change gear 2, change gear spring and adjusting

washer come off.
(7) Remo v e the loading gear 1.
(8) Move the change plate rivet assembly in the direction of the

arrow to release from the three shafts of the chassis rivet

assembly upward. (See Fig.38.)
(9) Detach the loading gear plate rivet assembly from the shaft

of the chassis rivet assembly upward while releasing the

joint p'. (See Figs.38 and 40.)

(10) Pull out the loading gear 4.

Change plate
rivet assembly

Shafts

E ring

Loading plate assembly

Loading plate spring

Joint p'

Loading gear 4

Loading gear plate
rivet assembly

Shaft

Loading gear 2

Loading gear 1

Chassis rivet assembly

Change gear 2

Fig.38

Joint n'

Slide hook

Feed gear

Fig.37

Slot m'

L side plate

Loading plate assembly

Joint n'

Slot m'

Chassis rivet assembly

Chassis rivet assembly

E ring

Washer

Change gear 2

Change gear

spring

Adjusting

washer

Change plate

rivet assembly

L side plate

Slot m'

Slot m'

Fig.39

Loading gear 1

Loading gear 2

Change lock lever

Loading gear 4

1-26 (No.49831)

Chassis rivet assembly

Loading gear plate rivet

assembly

Fig.40

2.2.18 Removing the turn table / spindle motor
(See Figs.41 and 42)

• Prior to performing the following procedure, re move the top

cover, connector board, chassis unit and clamper assembly.
(1) Remove the two screws L attaching the spindle motor

assembly through the slot of the turn table on top of the
body.

(2) Unsol der the wire on the connector board if necessary.

Turn table

L

Fig.41

L

Turn table

Spindle motor

Fig.42

(No.49831)1-27

SECTION 3

Adjustment

3.1 Adjustment method  Test instruments required for adjustment

(1) Digital oscilloscope (100MHz)
(2) AM Standard signal generator
(3) FM Stand ard signal generator
(4) Stereo modulator
(5) Electric voltmeter
(6) Digital tester
(7) Tracking offset meter
(8) Test Disc JVC :CTS-1000
(9) Extension ca ble for check

EXTSH002-22P × 1

 Standard volume position

Balance and Bass &Treble volume : lndication"0"
Loudness : OFF

 How to connect the extension cable for adjusting

Caution:

Be sure to attach the heat sink and rear bracket onto the power amplifier IC and regulator IC respectively, before supply the power.
If voltage is applied without attaching these parts, the power amplifier IC and regulator IC will be destroyed by heat.

 Standard measuring conditions

Power supply voltage DC14.4V (11 to 16V)
Load impedance 20KΩ (2 Speakers connection)
Output Level Line out 2.0V (Vol. MAX)

 Frequency Band

FM1 87.5MHz to 107.9MHz

(with channel interval set to 200kHz)

87.5MHz to 108.0MHz
(with channel interval set to 50kHz)

AM 530MHz to 1710MHz

(with channel interval set to 10kHz)
531MHz to 1602MHz

(with channel interval set to 9kHz)

 Dummy load

Exclusive dummy load should be used for AM,and FM. For FM
dummy load,there is a loss of 6dB between SSG output and
antenna input.The loss of 6dB need not be considered since
direct reading of figures are applied in this working standard.

The cardboard is cut in a suitable size.
uses for the insulation stand of mechanism.

Extension cable

EXTSH002-22P

1-28 (No.49831)

3.2 Service mode

r

When entering the service mode, "DATA CLEAR" is displayed without fail.

: Initial display

SEL

POWER

SOURCE

A

DATA_CLEAR

DISC+/-:CATEGORY

: SEEK UP

: SEEK DOWN

: DISC UP

: DISC DOWN

EPROM_CLEAR

NAME_CLEAR
CD_ERROR_CLEAR
CH_ERROR_CLEAR
SH_MECHA_ERROR_CLEAR

EPROM_CLEAR

NAME_CLEAR

CD_ERROR_CLEAR
CH_ERROR_CLEAR
SH_MECHA_ERROR_CLEAR

EPROM_CLEAR
NAME_CLEAR

CD_ERROR_CLEAR

CH_ERROR_CLEAR
SH_MECHA_ERROR_CLEAR

EPROM_CLEAR
NAME_CLEAR
CD_ERROR_CLEAR

CH_ERROR_CLEAR

SH_MECHA_ERROR_CLEAR

EPROM_CLEAR
NAME_CLEAR
CD_ERROR_CLEAR
CH_ERROR_CLEAR

SH_MECHA_ERROR_CLEAR

PICTURE_CLEAR

DSP_ERROR_CLEAR

PICTURE_CLEAR

DSP_ERROR_CLEAR

___NOW
___ERROR_CLEAR

SEL

*Letter turn on and off
(Turn on: 0.5sec, Turn off: 0.5sec)

___NOW
___NAME_CLEAR

SEL

*Letter turn on and off
(Turn on: 0.5sec, Turn off: 0.5sec)

___NOW
___CD_ERROR_CLEAR

SEL

*Letter turn on and off
(Turn on: 0.5sec, Turn off: 0.5sec)

___NOW
___CH_ERROR_CLEAR

SEL

*Letter turn on and off
(Turn on: 0.5sec, Turn off: 0.5sec)

___NOW
___SH_MECHA_ERROR_CLEAR

SEL

*Letter turn on and off
(Turn on: 0.5sec, Turn off: 0.5sec)

___NOW
___PICTURE_CLEAR

SEL

*Letter turn on and off
(Turn on: 0.5sec, Turn off: 0.5sec)

___NOW
___DSP_ERROR_CLEAR

SEL

*Letter turn on and off
(Turn on: 0.5sec, Turn off: 0.5sec)

EPROM all clear & Flash ROM all clear
(Following all contents are cleared.)

Execute by "SEL" key
Normal
display

EPROM (DISC/LINE NAME) clear

Execute by "SEL" key

Normal
display

EPROM (CD ERROR) clear

Execute by "SEL" key

Normal
display

EPROM (CH ERROR) clear

Execute by "SEL" key

Normal
display

EPROM (SH DOOR MECHA ERROR) clear

Execute by "SEL" key

Normal
display

Flash ROM (all PICTURE) clear

Execute by "SEL" key

Normal
display

Flash ROM (all DSP retry count number) clea

Execute by "SEL" key

Normal
display

RUNNING_MODE

DISC+/-:FUNCTION

B

C

RUNNING_CD
RUNNING_SH_MECHA

RUNNING_CD

RUNNING_SH_MECHA

RUNNING_CD
COUNT :
ERROR :

SEL

RUNNING_SH_MECHA
COUNT :
ERROR :

SEL

CD running mode (SH mecha open)

Running number

CD error during running mode

by error code chart

Door mecha running mode (No retry action)

Running number

Door error during running mode

by error code chart

(No.49831)1-29

B

C

CD_DATA_READ

DISC+/-:FUNCTION

ERROR_READ

DISC+/-:FUNCTION

ADJ_NOW

ADJ_INT
OTHERS

ADJ_NOW

ADJ_INT

OTHERS

ADJ_NOW
ADJ_INT

OTHERS

CD_ERROR_READ

CH_ERROR_READ
SH_MECHA_ERROR_READ

CD_ERROR_READ

CH_ERROR_READ

SH_MECHA_ERROR_READ

ADJ_NOW
FEB__ ____TEB__
FGA__ ____TGA__

SEL

FEO__ ____RFG__
TEO__

ADJ_INT
FEB__ ____TEB__
FGA__ ____TGA__

SEL

FEO__ ____RFG__
TEO__

OTHERS
IOP__TEMP____I T
IOP__INT__

SEL

TEMP__MAX__
P_TOTAL_ H

TOTAL_ERROR :
E1_ _____2_
E2_ _____3_

SEL

E3_ _____4_
1__ 5_

TOTAL_ERROR :
E1_ _____2_
E2_ _____3_

SEL

E3_ _____4_
1__ 5_

CD data display
Hex. code display
Total running time display
(Four figures (to 9999), hour only, omit)

CD error display
Total error number
Display by error code chart

CH error display
Total error number
Display by error code chart

VERSION

MAIN_V
CD_V
CH_V

A

CD_ERROR_READ
CH_ERROR_READ

SH_MECHA_ERROR_READ

CD_ERROR_READ
CH_ERROR_READ
SH_MECHA_ERROR_READ

E1_
E2_

SEL

E3_
1__

INIT_RETRY____TOTAL_
INIT_RETRY_NG_TOTAL_

SEL

SH door mecha error display
Display by error code chart

DSP initial setting data error
Retry total number of initial setting
Error number: NG after retry two times
(First transmit NG Retry first transmit NG
Second transmit NG : 1 count)

1-30 (No.49831)

3.3 Troubleshooting

Feed section

Is the voltage output at
IC621 pin "40" 5V or 0V?

NO YES NO

Is the wiring for IC621
pin "40"?

Is 3.3V present at IC681
pin "6"?

YES

Is 4V present at both
sides of the feed motor?

YES

Check the feed motor.

Focus section

When the lens is
moving:

4V

Does the S-search
waveform appear at
IC681 pins "13" and "14"?

Spindle section

Is the disk rotated?

YES

Does the RF signal
appear at IC601 pin "19"?

YES

Is the RF waveform at
IC601 pin "19" distorted?

YES

Proceed to the Tracking
section

NO

Is 6V or 2V present at
IC681 "16" and "17"?

Check IC681.

NO

Check the circuits in
the vicinity of IC681
pins "13","14"and"1".

YES

Check the pickup and
its connections

NO

Is 4V present at IC681
pins "15" and "16"?

Check the spindle motor
and its wiring

NO

Check the circuits in the
vicinity of IC601 pin "19"

NO

or the pickup

NO

NO

YES

YES

Check the vicinity of
IC621.

YES

Check the feed motor
connection wiring.

NO

Is 4V present at IC621
pins "41" ?

Check the vicinity of
IC681.

YES

YES

Check CD 8V
and 5V.

NO

Check the circuits in
the vicinity of IC621
or IC621

Tracking section

When the disc is rotated
at first:

Is the tracking error signal
output at IC601 "11"?

Check IC621.

Approx. 1.2V

YES

YES YES

Check the circuit in the
vicinity of IC601 pins
"2" to "7".

Check the pickup and
its connections

(No.49831)1-31

3.4 Flow of functional operation unit TOC read

When the pickup correctly moves
to the inner area of the disc

$82

Microprocessor
commands

FMO
TC94A14FA "40"

FEED MOTOR
+TERMINAL
IC681 "17"

REST SW

When correctly focused

FEO
TA2157 "15"

$83

$81

Focus Servo Loop ONo

v

3.3V
Hi-Z
0V

6V
4V
2V

OFF

ON

Pickup feed to the inner area

2.2V

RF signal eye-pattern
remains closed

RF signal eye-pattern
opens

Power ON

Set Function CD

Disc inserted

YES

Laser emitted

Focus search

Disc rotates

n

Tracking loop closed

TOC read out

YES

When the laser diode correctly

emits

Microprocessor
commands

SEL
TC94A14FA "38"

LD
CN601 "10"

"No disc"
display

When the disc correctly rotates

Microprocessor
commands

DMO
TC94A14FA "41"

Spindle
motor(-)
IC681 "16"

$84 $86 $ A200

Acceleration Servo CLV

Rough
Servo

0.5 Sec 0.5 Sec

$84

3.3V
0V

4V

0V

3.3V

2.2V
0V

6V

3.2
2V

1-32 (No.49831)

Jump to the first track

Play

Tracking Servo Loop ON

RF signal

Rough Servo Modev

CLV Servo Mode
(Program Area)

CLV Servo Mode
(Lead-In Area;
Digital :0)

3.5 Maintenance of laser pickup

(1) Cleaning the pick up lens

Before you replace the pick up, please try to clean the lens
with a alcohol soaked cotton swab.

(2) Life of the laser diode

When the life of the laser diode has expired, the following
symptoms will appear.

• The level of RF output (EFM output: amplitude of eye
pattern) will be low.

3.6 Replacement of laser pickup

Turn off the power switch and,disconnect the
power cord from the ac outlet.

Replace the pickup with a normal one.(Refer
to "Pickup Removal" on the previous page)

Is RF output

1.0 0.4Vp-p?

NO

Replace it.

YES

O.K

(3) Semi-fixed resistor on the APC PC board

The semi-fixed resistor on the APC printed circuit board
which is attached to the pickup is used to adjust the laser
power.Since this adjustment should be performed to match
the characteristics of the whole optical block, do not touch
the semi-fixed resistor.
If the laser power is lower than the specified value, the
laser diode is almost worn out, and the laser pickup should
be replaced. If the semi-fixed resistor is adjusted while the
pickup is functioning normally, the laser pickup may be
damaged due to excessive current.

Plug the power cord in,and turn the power on.
At this time,check that the laser emits for
about 3seconds and the objective lens moves
up and down.
Note: Do not observe the laser beam directly.

Play a disc.

Check the eye-pattern at RF test point.

Finish.

(No.49831)1-33

SECTION 4

S

T

T

Description of major ICs

4.1 AK7740VT (IC101) : Audio DSP with AD/DA converter

• Pin layout

• Block diagram

AINL3

AINR2

AINL2

AINR1

AINL1

VREFH

AVD D

AVSS
DVSS
DVDD

XTI

XTO

AINR3AINL4AINR4AINL+AINL-

4847464544434241403938

1
2
3
4
5
6
7
8
9
10
11
12

1314151617181920212223

JX

CLKO

SMODE

AINR+AINR-AVSS

48 pin LQFP
(TOP VIEW)

SDIN

LRCLK

BITCLK

SDINA

SDOUTA

VCOMAVDDAOUTAOU

37

36
35
34
33
32
31
30
29
28
27
26
25

24

DVSS

DRDY

SDOUT

DVDD

Note) JX , SDIN and SDINA are Pull-down pins

SMODEXTOXTICLKOUTBITCLKLRCLK

AOUTL2
AOUTR2
BVSS
DVSS
DVDD
INT_RE
S_RESE
RQ
SCLK
SI
SO
RDY

SDOUTA

SDINA

SDIN

RQ

SO

SCLK

RDY

DRDY

JX

SMODEXTOXTICLKOUTBITCLKLRCLK

OUTAE

SW3

RQ

SI

SI

SO

SCLK

RDY

DRDY

JX

DSP

ISEL[2:0]

SDOUTD1

SDOUTD1

SDINA

SDIN

SDOUT

72kbit DLRAM

*SW1,SW2,SW3,ISEL[2:0],

OUTAE control register

SW0

CONTROLLER

SD ATA

SW2

SW2

SW1

ADC

AINL-

AINL+

AINR-

AINR+

SDATA AOUTL

SD ATA

INT_RESET

VREFF

DAC1

DAC2

AOUTR

AOUTL

AOUTR

INT_RESET

S_RESETS_RESET

AINL-

AINL+
AINL1
AINL2
AINL3
AINL4

AINR-

AINR+
AINR1
AINR2
AINR3
AINR4

VREFF
VCOM

AOUTL1

AOUTR1

AOUTL2

AOUTR2

SDOUT

1-34 (No.49831)

Note)

C

A
B

When C is "L" (0) then A connects with Q

Q

• Pin function
Pin No. Symbol I/O Function

1 AINL3 I ADC single-ended analog Lch input pin No.3
2 AINR2 I ADC single-ended analog Rch input pin No.2
3 AINL2 I ADC single-ended analog Lch input pin No.2
4 AINR1 I ADC single-ended analog Rch input pin No.1
5 AINL1 I ADC single-ended analog Lch input pin No.1
6 VREFH I Analog Reference voltage input pin.

Normally, connect to AVDD (pin 7), and connect 0.1mF and 10mF capacitors between this pin and

AVSS.
7 AVDD - Power supply pin for analog section 3.3V (typ)
8 AVSS - Analog ground 0V
9 DVSS - Ground pin for digital section 0V

10 DVDD - Power supply pin for digital section 3.3V (typ)
11 XTI I Master clock input pin

Connect a crystal oscillator between this pin and the XTO pin or input the external CMOS clock signal

XTI pin.

12 XTO O Crystal oscillator output pin

When a crystal oscillator is used, it should be connected between XTI and XTO.

When the external clock is used, keep this pin open

13 CLKO O Clock output pin Outputs the XTI clock. Allows the output to be set to "L" by control register setting.
14 JX I External condition jump pin (Pull down)
15 SMODE I Slave/master mode selector pin

Set LRCLK and BITCLK to input or output mode.

SMODE-"L": Slave mode (These are set to input mode.)

SMODE-"H": Master mode (These are set to output mode.)

16 LRCLK I/O LR channel select Clock pin

SMODE-"L": Slave mode : Inputs the fs clock.

SMODE-"H": Master mode : Outputs the fs clock.

17 BITCLK I/O Serial bit clock pin

SMODE-"L": Slave mode : Inputs 64 fs or 48 fs clocks.

SMODE-"H": Master mode : Outputs 64 fs clocks.

18 SDIN I DSP Serial data input pin (Pull down)

Compatible with MSB/LSB justified 24 20 and 16 bits.

19 SDINA I DSP Serial data input pin (Pull down)

Leave opens or connect to DVSS at using the internal ADC.

Compatible with MSB justified 24 bits.

(No.49831)1-35

4.2 BA3220FV-X (IC171,IC271) : Line out amp

+

­+

-

-

+

+

-

-

-

+

+

• Pin layout

• Block diagram

14

8

3220

17

CL-

14

LGND

13

OUTL OUTR RGND

1112

10

CR-

9

CR+

8

REFL

REFR

FILTER

1

2

Vcc

3

INL

4

NFLCL+

56

FIL

NFR

7

INR

1-36 (No.49831)

4.3 BA5830FP-X (IC681) : Power driver

• Pin Layout & Block diagram

22232425262728 15161718192021

BIAS

Pre Vcc

­+

­+

+

­+

-

­+

• Pin function
Pin No. Symbol Function

1 OPIN2(-) CH2 Pre OP amplifier invert input
2 OPOUT 2 CH2 Pre OP amplifier output
3 OPIN1(-) CH1 Pre OP amplifier invert input
4 OPOUT 1 CH1 Pre OP amplifier output
5 REG-B Connect to external Tr Base
6 REG(+) Regulator terminal of output feedback
7 PreGND Pre Block and Regulator GND
8 MUTE Mute terminal

9 PowGND Power Block GND
10 PowVcc1 CH1, 2 Power Block Vcc
11 VO1(-) Driver CH1 negative output
12 VO1(+) Driver CH1 positive output
13 VO2(-) Driver CH2 negative output
14 VO2(+) Driver CH2 positive output

10k

L

-

H

+

1.65V

20k

10k

2.4V

20k

­+

+

-

10k

PreGND

7654321 141312111098

CH4 CH3

10k 10k 10k 10k

-

20k

10k

10k

LD/SLED

CONTROL

H

L

10k

­+

+

-

10k

MUTE

CONTROL

Pow
GND

Pow

GND

Pow

Vcc2

Pow

Vcc1

+

Level shifter

Level shifter

+

-

+

10k 10k 10k 10k

T.S.D

10k

-

+

10k

CH1

10k

-

+

Level shifter

Level shifter

+

10k

-

10k

-

10k

CH2

T.S.D : thermal shutdown
Unit of resistance : [ ]

Pin No. Symbol Function

15 VO3(+) Driver CH3 positive output
16 VO3(-) Driver CH3 negative output
17 VO4(+) Driver CH4 positive output
18 VO4(-) Driver CH4 negative output
19 PowVcc2 CH3, 4 Power Block VCC
20 PowGND Power Block GND
21 CNT Control terminal
22 LDIN Loading input
23 OPOUTSL SLED Pre OP amplifier output
24 OPINSL(-) SLED Pre OP amplifier invert input
25 OPOUT3 CH3 Pre OP amplifier output
26 OPIN3(-) CH3 Pre OP amplifier invert input
27 BIAS BIAS input
28 PreVcc Pre-Block VCC

-

+

10k

-

+

10k

NOTE:

When PIN2,4,22,25 is high ("H"), the positive output pin of the driver is high ("H") and the negative output pin is low ("L").
When PIN23 is high ("H"), the positive output pin of CH4 is low ("L") and negative output pin is high ("H").

(No.49831)1-37

4.4 BA6956AN (IC981) : Reversible motor driver

• Pin layout & Block diagram

1 2 3 4 5 6 7 8 9

TSD

CONTROL LOGIC

REF

OUT2

RNF

VM

OUT1

Vcc

FIN

• Pin function • Truth table
Pin No. Symbol Function

1 VREF Output high voltage level control terminal
2 OUT2 Output terminal for motor
3 RNF GND of driver division
4 OUT1 Output terminal for motor

FIN RIN OUT1 OUT2 MODE

H L H L Forward rotation mode
L H L H Reverse rotation mode
H H L L Break Mode

L L OPEN OPEN Stand-by mode
5 VM Power supply for driver division
6 Vcc Power supply for signal division
7 FIN Input terminal for control logic
8GNDGND
9 RIN Input terminal for control logic

4.5 BD4833FVE-W (IC702) : Regulator

• Pin layout • Block diagram

VOUT

1

54V

DD

GND

RIN

VDD

2

SUB

3

N.C.

• Pin functions
Pin No Symbol Function

1 VOUT Reset output
2 SUB Sub slate (connect to GND)
3 N.C. Non connect
4GNDGND
5 VDD Power supply voltage

1-38 (No.49831)

GND

VOUT

Vref

GND

4.6 BR24C01AFV-W-X (IC502) : EEPROM

A

•Pin layout

Vcc WP SCL SDA

A0 A1 A2 GND

• Block diagram

A0

1

7bit

A1

2

A2

3

GND

• Pin function
Pin name I/O Description

Vcc - Power supply

GND - Ground (0v)

A0,A1,A2 IN Slave address set

SCL IN Serial clock input

SDA IN / OUT Slave and word address,serial data input, serial data output *1

WP IN Write protect input

*1 An open drain output requires a pull-up resister.

4

ADDRESS
DECODER

CONTROL LOGIC

HIGH VOLTAGE GEN.

1kbit EEPROM ARRAY

SLAVE/WORD

7bit

ADDRESS REGISTER

START

STOP

Vcc LEVEL DETECT

ACK

8bit

DATA
REGISTER

Vcc

8

7

WP

6

SCL

5

SD

(No.49831)1-39

4.7 BR24C16F-W-X (IC703) : EEPROM

A

• Pin layout

VCC WP SCL SDA

A0 A1 A2 GND

• Block diagram

A0 1

A1 2

A2 3

GND 4

11bit

Address

decoder

Control circuit

High voltage osc circuit

16kbit EEPROM allay

11bit

START

Slave Ward

Address resister

Power supply
voltage det.

STOP

• Pin function
Symbol I/O Function

Vcc - Power supply.

GND - GND

A0,A1,A2 I No use connect to GND.

SCL I Serial clock input.

SDA I/O Serial data I/O of slave and ward address.

WP I Write protect terminal.

*1 An open drain output requires a pull-up resister.

ACK

8bit

Data

resister

8 Vcc

7 WP

6 SCL

5 SD

1-40 (No.49831)

4.8 BU4066BCFV-X (IC152,IC252,IC352) : Quad analog switch

• Pin layout & Block diagram

VDD C1 C4 I/O4 I/O3O/I4 O/I3

14 13 12 11 810 9

1234 756

I/O1 O/I1 O/I2 I/O2 VssC2 C3

(No.49831)1-41

4.9 HA13166 (IC911) : System regulator for car-audio

• Pin layout

• Block diagram

EXTOUT

D1

D2

ANTOUT

D3

D4

ANT CTRL

CTRL

CDOUT

AUDIOOUT

+

VCC

8 3

-

1

C3

0.1u

2

C4

0.1u

7

Vth

11

VthH

12

C5

0.1u

10

+

C6
10u

+

­+

+

-

+

VthM

­+

-

VREF

+

-

GND

­+

Surge Protector

BIAS

VREF

VREF

15

ACC

+

-

Vth

TSD

+

VREF

-

+

-

TAB

+

-

VREF

GND ILM AJ

C1
100u

+

C2

0.1u

6

5

4

9

14

13

+B

ACC

COMPOUT

SW5VOUT

VDDOUT

C7

0.1u

DSPOUT

C9

0.1u

ILMOUT

C8

0.1u

UNIT R:Ω
C:F

note 1) TAB(header of IC)
connected to GND

1-42 (No.49831)

4.10 HD74HCT126T-X (IC503,IC941) : Buffer

•Pin layout •Pin function
Input Output

1C

1A

1Y

2C

2A

2Y

GND

• Block diagram

1

2

3

4

5

6

7

14

13

12

11

10

Vcc

4C

4A

4Y

3C

9

3A

8

3Y

CA Y

LX Z
HL L
HH H

H : High level
L : Low level
X : Irrelevant
Z : Off (Hhigh-impedance)state of a 3-stage output

1A

1C

2A

2C

3A

3C

4A

1Y

2Y

3Y

4Y

4C

(No.49831)1-43

4.11 LH28F160BJHET93 (IC803) : 16M flash memory

A

• Pin layout

• Block diagram

A15 1

14 2

A

13 3

A
A

12 4

11 5

A

A

10 6

9 7

A
A

8 8

19 9

A

NC 10

WE# 11

RP# 12

V

CCW 13

WP# 14

RY/BY# 15

A

18 16

A

17 17

7 18

A
A

6 19

A

5 20

A

4 21

A

3 22

A

2 23

A1 24

Output

buffer

48-LEAD TSOP

STANDARD PINOUT

12mm x 20mm

TOP VIEW

DQ0 to DQ15

Input

buffer

48
47
46
44
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

16

A
BYTE#
GND
DQ

15/A-1

DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
GND
CE#
A0

-1-A19

Input

buffer

Address

latch

Address

counter

Y

decoder

X

decoder

Output

Multiplexer

Boot block 0

Boot block 1

Parameter block 0

Parameter block 1

Parameter block 2

ID code

register

Status

register

comparator

Y gate

Main block 0

Parameter block 3

Parameter block 4

Parameter block 5

Data

32k word
(64k byte)
Main block

x 31

Main block 1

register

Command

interface

Data

machine

Main block 29

Main block 30

user

Write

state

I/O logic

Write/Erase

voltage

selecter

VCC
BYTE#

CE#
WE#
OE#
RP#
WP#

RY/BY#
VCCW

VCC
GND

1-44 (No.49831)

• Pin function
Pin No. Symbol I/O Function

1 to 8 A

9A

15

to A

19

I Address input for memory address

8

I Address input for memory address
10 NC - Non connection
11 WE# I Write enable
12 RP# I Reset
13 VCCW - Power supply for write/erase
14 WP# I Write protect
15 RY/BY# O Ready/Busy

16,17 A

18 to 25 A

18,A17

to A

7

I Address input for memory address

I Address input for memory address

0

26 CE# I Chip enable
27 GND - Ground
28 OE# I Output enable
29 DQ
30 DQ
31 DQ
32 DQ
33 DQ
34 DQ
35 DQ
36 DQ

0
8
1
9
2

10

3

11

I/O Data input/output
I/O Data input/output
I/O Data input/output
I/O Data input/output
I/O Data input/output
I/O Data input/output
I/O Data input/output

I/O Data input/output
37 VCC - Power supply
38 DQ
39 DQ
40 DQ
41 DQ
42 DQ
43 DQ
44 DQ
45 DQ
45 A

4

12

5

13

6

14

7

15

-1

I/O Data input/output

I/O Data input/output

I/O Data input/output

I/O Data input/output

I/O Data input/output

I/O Data input/output

I/O Data input/output

I/O Data input/output

I Address input for memory address
46 GND - Ground
47 BYTE# I Byte enable
48 A

16

I Address input for memory address

(No.49831)1-45

4.12 MN102H60KCJ1 (IC801) : LCD display sub CPU

• Pin layout

100 76

1

75

25

26 50

51

• Pin function
Pin No. Symbol I/O Function

1 RES O LCD reset output
2 RE O Read enable ou tput for extension memory
3 WE O Write enable output for extension memory
4 VCCWCNT O Writing voltage control for external ROM
5 RY/BY I Read/Busy input for extension memory
6 CS0 O Chip select1 output for exte nsion memory
7 NC - Connect to ground
8 SWLED4 O SW_LED flashing output 4 for [PRESET1-6] key LED

9 SWLED5 O SW_LED flashing output 5 for [SEEKUP]+[SEEKDOWN] key LED
10 SWLED6 O SW_LED flashing output 6 for [DISCUP]+[DISCDOWN] key LED
11 NC - Connect to ground
12 WORD I Bus width setting for extension memory (H: 8-bit width)

13 to 16 A0 to A3 O Extension memory output 0 to 3

17 VDD - Power supply
18 NC O Not use (Base clock output)
19 VSS - Ground
20 XI I Connect to ground
21 XO O Not connect
22 VDD - Power supply
23 OSCI I Crystal connecting termi nal (25MHz)
24 OSCO O Crystal connecting terminal (25MHz)
25 MODE I Mode setting input, pull up (H: memory extension mode)

26 to 33 A4 to A11 O Extension memory output 4 to 11

34 AVDD - Analog power supply

35 to 42 A12 to A1 9 O Extension memory output 12 to 19

43 AGND - Analog reference power supply, connect to ground
44 A20 O Extension memory output 20
45 THERMAL I Thermal fuse input
46 ANA I Audio level input for spectrum analyzer
47 WDOUT O Watch dog timer over flow output (H: over flow)
48 PON O Power on output
49 RD O LCD read strobe output
50 LCDCLK O LCD driver clock output (300kHz)
51 WR O LCD write strobe output

52,53 NC - Not connect

54 AVDD - Analog reference power supply, connect to AVDD
55 RS O LCD regist select output

1-46 (No.49831)

Pin No. Symbol I/O Function

56 CS O LCD chip select output
57 NC - Connect to ground
58 VOL1 I Rotary encoder input 1
59 VOL2 I Rotary encoder input 2
60 SWLED3 - Not connect
61 AGND - Analog ground

62 to 65 KEY0 to KEY3 I Key 0 to 3 input AD terminal

66 VDD - Power supply
67 SWLED0 O SW_LED flashing output 0 for [VOL] key LED
68 SWLED1 O SW_LED flashing output 1 for [SEL] key LED
69 SWLED2 O SW_LED flashing output 2 for [DISP] key LED
70 DISPCLK I Serial communication clock input
71 DISPDATA I Displaying data input (Serial)
72 KEYDATA O Key code data output (Serial)
73 SIFDA I/O On board serial writing data input/output pull up
74 SIFCK I On board serial writing clock input, pull up
75 NMI I NMI (H fix)
76 DISPCE I Chip enable input for serial communication
77 - Ground
78 PSAVE2 I POWER SAVE2 (Memory power supply off) detecting input
79 NC - Not use
80 KEY_IN I Key interrupt input
81 ADSEP I Address data separate /common mode setting terminal H: separate mode
82 RESET I Reset input (L: reset)
83 VDD - Power supply terminal

84 to 91 D0 to D7 I Extension memory input 0 to 7

92 GND - Ground

93 to 100 P10 to P17 I LCD data bus input/output 0 to 7

(No.49831)1-47

4.13 IC-PST3424U-X (IC802) : Reset

T

• Pin layout

VOUT

VDD

• Block diagram

1

2

VDD

43VSS

NC

2

Vref

3

VSS

• Pin function
No. Pin Name Function

1 Vout Reset Signal Output PIN
2 VDD VDD PIN / Voltage Detect PIN
3 NC Non connect
4 VSS VSS PIN

+

-

1 VOU

1-48 (No.49831)

4.14 NJM2360AM-X (IC931) : DC-DC convertor

•Pin layout

1. Cs

1
2
3
4

• Block diagram

8
7
6
5

2. Es

3. C

4. GND

5. INV

6. Vcc

7. S

8. C

T

IN

I

D

Switch
collector

Switch
emitter

Timing
capacitor

4.15 NJM4565V-X (IC131,IC231,IC331,IC351,IC431,IC572) : Dual operational amplifier

• Pin layout & Block diagram

1

1

Q

1

QS

Q

2

R

2

Ipk

C OSC

T

3

COMP

V

REF

4GND

1.25V

+

-

8

A

2

+

-

7

B

3

+

-

4

6

5

Driver

8

collector

Ipk sense

7

+

6

V

Comparator

5

reversal input

1

AOUTPUT

2

A-INPUT

3

A+INPUT

4

V

5

B+INPUT

6

B-INPUT

7

B OUTPUT

8

V

(No.49831)1-49

4.16 NJU7241F25-X (IC651) : Regulator

T

• Pin layout

GND 1

5 STB

VIN 2

VOUT 3

• Block diagram

4 NC

VIN 2

STB 5

Vref

GND 1

4.17 NJU7241F33-X (IC504,IC804) : Voltage regulator

• Pin layout

PIN FUNCTION

1

2

5

1. GND

IN

2. V

3. VOUT

4. +NC

5. STB

Short protect

3 VOU

1 GND

3

4

4.18 RPM6938-SV4 (IC805) : Remote control receiver

• Block diagram

I/V
conversion

PD

magnetic shield

AMP

BPF

for
trimming circuit

AGC

Vcc

Comp

Detector

22k
ohm

3

1

2

VDD

OUT

GND

1-50 (No.49831)

4.19 PCM1716E-X (IC571) : D/A converter

O

•Pin layout

28 15

114

• Block diagram

BCK

LBCK

DATA

ML/llS
MC/DM1
MD/DM0

CS/WO

MODE

MUTE

RST

Serial

Input

I/F

Mode

Control

I/F

8X Oversampling

Digital Filter

with

Function Controller

SCK

BPZ-Cont

Crystal OSC

XTI XTO CLKO Vcc1 VccAGND1 DGND

• Pin function
Pin No. Symbol I/O Function

1 LRCK I LRCK clock input
2 DATA I Serial audio data input
3 BCK I Bit clock input for serial audio data
4 CLKO O Buffered output of system clock
5 XTI I Oscillator input / External clock input
6 XTO O Oscillator output
7 DGND - Digital ground
8 VDD - Digital power +5V

9 VDD2R - Analog power +5V
10 AGND2R - Analog ground
11 EXTR O Rch common pin of analog output

amp
12 NC - Non connection
13 VOUTR O Rch analog voltage output of audio

signal
14 AGND1 - Analog ground
15 Vcc1 - Analog power +5V

Mult-level

Delta-Sigma

Modulator

Vcc2L

DAC

DAC

Power Supply

AGND2L

Vcc2R

AGND2R

Open drain

Low-pass

Filter

Low-pass

Filter

VoutL

EXTL

VoutR

EXTR

ZER

Pin No. Symbol I/O Function

16 VOUTL O Lch analog voltage output of audio

signal
17 NC - Non connection
18 EXTL O Lch common pin of analog output

amp
19 AGND2L - Analog ground
20 Vcc2L - Analog power +5V
21 ZERO O Zero data flag
22 RST I Reset
23 CS/IWO I Chip select / Input format selection
24 MODE I Mode control select
25 MUTE I Mut e co nt rol
26 MD/DM0 I Mode control, Data /

De-emphasis selection 1
27 MC/DM1 I Mode control, BCK /

De-emphasis selection 2
28 ML/IIS I Mode control, WDCK /

Input format selection

(No.49831)1-51

4.20 TA2157FN-X (IC601) : RF amp

• Pin layout

24 ~ 13

1 ~ 12

• Block diagram

13

14

15

16

17

18

19

20

21

10pF

40k30k

20k 20k

20k

20k

15k

50 A

12k

12k

BOTTOM

PEAK

20k

20k

20k

PEAK

1.3V

40k

240k

15pF

240k

15pF

40k

50k

2k

20k

50k

14k

K

1

15k

x0.5
x2

x0.5
x2

1k

2k

1.75k

10pF

12

11

10

9

8

7

6

5

4

PIN
VCTRLPIN

1-52 (No.49831)

180k

40pF

22

23

24

SEL

(APC SW)

180k

40pF

3k

3k

TEB

(TE BAL)

60k

60k

RFGC

(AGC Gian)

VCC APC ON -50% +12dB

HiZ APC ON 0% +6dB

GND

APC OFF

(LDO=H)

50% 0dB

94k

94k
22k

22k

3

2

1

TEB

(TE BAL)

Normal mode

(0dB)

Normal mode

(0dB)

CD-RW mode

(+12dB)

• Pin function
Pin No. Symbol I/O Function

1 VCC - 3.3V power supply pin
2 FNI I Main-beam amp input pin
3 FPI I Main-beam amp input pin
4 TPI I Sub-beam amp input pin
5 TNI I Sub-beam amp input pin
6 MDI I Moni tor photo diode amp input pin
7 LDO O Laser diode amp output pin
8 SEL I APC circuit ON/OFF control signal, laser di ode (LDO) control signal input

or bottom/peak detection frequency change pin.

SEL
GND
Hiz
VCC

9 TEB I Tracking error balance adjustment signal input pin

Adjusts TE signal balance by eliminating carrier component from PWM signal (3-state output,

PWM carrier = 88.2kHz) output from TC94A14F/FA
TEBC pin using RC-LPF and inputting DC.

TEBC input voltage:GND~VCC
10 TEN I Tracking error signal generat ion amp negative-phase input pin
11 TEO O Tracking error signal generation amp output pin.

Combining TEO signal RFRP signal with TC94A14F/FA configures tracking search system.
12 RFDC O R F signal peak detection output pin
13 GVSW I AGC/FE/TE amp gain change pin

APC
circuit

LDO
OFF Connected VCC through 1k resistor
ON

Control signal output

ON Control signal output

GVSW Mode
GND
Hiz

CD-RW
Normal

VCC

14 VRO O Reference voltage (VRO) output pin

*VRO=1/2VCC When VCC=3.3V
15 FEO O Focus error signal generation amp output pin
16 FEN I Focus error signal generation amp negative-phase input pin
17 RFRP O Signal amp output pin for track count

Combining RFRP signal and TEO signal with TC94A14F/FA configures tracking search system.

18
19
20

21 AGCIN I RF signal amplitude adjustment amp input pin
22 RFO O RF signal generation amp output pin
23 RFI I RF signal generation amp input pin
24 GND - GND pin

REIS
RFGO
RFGC

I

O

RF signal amplitude adjustment amp output pin

I

RF amplitude adjustment control signal input pin

Adjusts RF signal amplitude by eliminating carrier component from PWM signal (3-state output,
PWM carrier=88.2kHz)output fromTC94A14F/14FA *RFGC pin using RC-LPF and inputting DC.

*RFGC input voltage:GND~VCC

(No.49831)1-53

4.21 TC94A14FA (IC621) : DSP & DAC

• Pin layout & Block daiagram

48 47 46 45 44 43 42 41 40 39

38 37 36 35 34 33

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

LPF

generator

Micro-

controller

interface

Clock

1-bit

DAC

Correction

Audio out

circuit

circuit

Address

circuit

16 k

RAM

Digital
output

PWM

Servo

control

ROM

RAM

CLV servo

Synchronous

guarantee

EFM

decoder

Sub code

decoder

Digital equalizer

automatic

adjustment circuit

A/D

Data

slicer

VCO

PLL

TMAX

D/A

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

64

• Pin function
Pin No Symbol I/O Descroption

1 BCK O Bit clock output pin.32fs,48fs,or 64fs selectable by command.
2 LRCK O L/R channel clock output pin."L" for L channel and "H " for R channel.

Output polarity can be inverted by command.
3 AOUT O Audio data output pin. MSB-first or LSB-first selectable by command.
4 DOUT O Digital data output pin.Outputs up to double-speed playback.
5 IPF O Correction flag output pin.

When set to "H", AOUT output cannot be corrected by C2 correction processing.
6V
7V

DD3
SS3

- Digital 3.3V power supply voltage pin.

- Digital GND pin.
8 SBOK O Subcode Q data CRCC result output pin. "H" level when result is OK.
9 CLCK O Subcode P-W data read I/O pin. I/O polarity selectable by command.

10 DATA O Subcode P-W data output pin.
11 SFSY O Playback frame sync signal output pin.
12 SBSY O Subcode block sync signal output pin. "H" level at S1 when subcode sync is detected.
13 HSO
14 UHSO
15 PV

DD3

I/O General-purpose input / output pins.Input port at reset.

- PLL-only 3.3V power supply voltage pin.

16 PDO O EFM and PLCK phase difference signal output pin.

17

161514131211101 2 3 4 5 6 7 8 9

1-54 (No.49831)

Pin No Symbol I/O Descroption

17 TMAX O TMAX detection result output pin.

TMAX Detection Result
Longer than fixed period

Within fixed period
Shorter than fixed period

TMAX Output

"PV

DD3"

"HiZ"

SS3"

"AV

18 LPFN I Inverted input pin for PLL LPF amp.
19 LPFO O Output pin for PLL LPF amp.
20 PVREF - PLL-only VREF pi n.
21 VCOF O VCO filter pin.
22 AV

SS3

- Analog GND pin.
23 SLCO O DAC output pin for data slice level generation.
24 RF I I RF signal input pin. Zin selectable by command.
25 AV

DD3

- Analog 3.3V power supply voltage pin.
26 RFCT I RFRP signal center level input pin.
27 RFZI I RFRP signal zero-cross input pin.
28 RFRP I RF ripple signal input pin.
29 FEI I Focus error signal input pin.
30 SBAD I Sub-beam adder signal input pin.
31 TEI I Tracking error input pin. Inputs when tracking servo is on.
32 TEZI I Tracking error signal zero-cross input pin.
33 FOO O Focus equalizer output pin.
34 TRO O Tracking equalizer output pin.
35 VREF - Analog reference power supp ly voltage pin.
36 RFGC O RF amplitude adjustment control signal output pin.
37 TEBC O Tracking balance control signal output pin.
38 SEL O APC circuit ON/OFF signal output pin. At laser on, high impedance with UHS="L",

H output with UHS="H".

39 AV

DD3

- Analog 3.3V power supply voltage pin.
40 FMO O Feed equalizer output pin.
41 DMO O Disc equalizer output pin.
42 V
43 V

SS3
DD3

- Digital GND pin.

- Digital 3.3V power supply voltage pin.
44 TESIN I Test input pin. Normally, fixed to "L".
45 XV

SS3

- System clock oscillator GND pin.
46 XI I System clock oscillator input pin.
47 XO O System clock oscillator output pin.
48 XV
49 DV

DD3

R - DA converter GND pin.

SS3

- System clock oscillator 3.3V power supply voltage pin.

50 RO O R-channel data forward output pin.
51 DV

DD3

- DA converter 3.3V power supply pin.
52 DVR - Reference voltage pin.
53 LO O L-channel data forward output pin.
54 DV

L - DA converter GND pin.

SS3

55 Z DET O 1 bit DA converter zero detection flag output pin.
56 V

SS5

- Microcontroller interface GND pin.
57 BUS0
58 BUS1

I/O Microcontroller interface data I/O pins.59 BUS2
60 BUS3
61 BUCK I Microcontroller interface clock input pin.
62 /CCE I Microcontroller interface chip enable signal input pin.At "L", BUS0 to BUS3 are active.
63 /RST I Reset signal input pin. At reset, "L".
64 V

DD5

- Microcontroller interface 5V power supply pin.

(No.49831)1-55

4.22 TC94A20F-008 (IC652) : Audio digital processor with DAC and SRAM

• Pin layout & Block diagram

Po1/A4

Po0/A3

TXo

TESTP

VSSR

Po2/A5

32

VRARRoVDAR

31

30

29

28

27

26

33

VDALLoVRAL

25

24

23

VSSL

VSS

STANDBY

VDD

22

21

20

19

18

/LRCKiB/A2

17

BCKiB/A1

16

Po3/A6

VDDT

Po4/A7

Po5/A8

Po6/A9

Po7

VSS

IRQ/REQ/A10R

VDDM(SRAM)

Fi0/ /OE

register

C-Pointer

register

Y-Pointer

register

X-Pointer

Bus

DAC

Switch

register

34

35

36

General

Output Port

37

38

39

40

41

Flag

42

43

DIT

2sets

Address Calc.

ERAM

CROM

2k word

*7

4k word

YRAM

4k word

Y0 - Y1 - Y2

X0 - X1 - X2

DAC

AX AY

MX MY MZ

MAC ALU

SDi1/A0

15

LRCKiA

14

BCKiA

13

A3

SDi0

Audio. I/F

12

LRCKo

11

BCKo

10

9

SDo

87

VDDT

round & limit

A2

round & limit

A0 A1

MiACK/A11R

6

/MiCK/SCL

Fi1/ /CAS

VSSM(SRAM)

Pi0/io0

Pi1/io1

VSS

Timer

44

4546

Interrupt

Control

I-Bus

SRAM I/F

47

48

49

Pi2/io2

General

Input Port

50

Pi3/io3

XRAM

4k word

SRAM I/F

51

52

VDD

Pi4/CLCK/io4

53

Pi5/DATA/io5

X-Bus

1Mbit

54

SRAM

Y-Bus

I/F

SubQ

55

56

VSSP

Fi2/SBSY/io7

PRAM

256word

57

PDo

Control

Program

4k*3

PROM

VC0

58

VCoi

=12kword

59

VDDP

40bit

Timing

Generator

60

Decoder

Instruction

61

62

Xi

VDDX

Microcom. I/F

63

Xo

64

VSSX

543

MiDiO/SDA

/MiLP/ /RAS

/MiCS/ /WE

2

MiMD

1

/RESET

TSTiN/SFSY/io6

CKi/CKo/Po6/SBOK

1-56 (No.49831)

• Pin function
Pin No. Symbol I/O Function

1 /RESET I Hard reset input (H:Operation L: Reset)
2 MiMD I Mode select input for MCU interface (H:IIC L:Serial)
3 /MiCS I Chip select input for MCU interface

/WE O Write-enable for external DRAM

4 /MiLP I Latch pulse input for MCU interface

/RAS O Low address strobe for external DRAM
5 MiDio I/O Data input and output for MCU interface (IIC:SDA)
6 /MiCK I Clock input for MCU interface (IIC:SCL)
7 MiACK O Acknowledge output for MCU interface

A11R O Address output-11 for external DRAM
8 VDDT - Power supply for digital circuit (3.3V)
9 SDo O Data output

10 BCKo O Bit clock output
11 LRCKo O LR clock output
12 SDi0 I Data input-0
13 BCKiA I Bit clock input-A
14 LRCKiA I LR clock input-A
15 SDi1 I Data input-1 (Address output-5 for external SRAM)

A0 O Address output-1 for external DRAM

16 BCKiB I Bit clock input-B

A1 O External DRAM address output-1

17 LRCKiB I LR clock input-B (Enable signal output for external SRAM)

A2 O Address-2 for external DRAM
18 VDD - Power supply for digital circuit (2.5V)
19 STANBY I Control input for stand-by mode (H:STB,L:Normal)
20 VSS - Ground for digital circuit
21 VSSL - Ground for DAC Lch
22 VRAL - Reference voltage for DAC Lch
23 LO O DAC Lch output
24 VDAL - Power supply for DAC Lch (2.5V)
25 VDAR - Power supply for DAC Rch (2.5V)
26 RO O DAC Rch output
27 VRAR - Reference voltage for DAC Rch
28 VSSR - Ground for DAC Rch
29 TESTP I Test terminal (H:Test mode L:Normal)
30 TXO O SPDIF output
31 Po0 O General output port-0

A3 O Address-3 for external DRAM
32 Po1 O General output port-1

A4 O Address-4 for external DRAM
33 Po2 O General output port-2

A5 O Address-5 for external DRAM
34 Po3 O General output port-3

A6 O Address-6 for external DRAM
35 VDDT - Power supply for digital circuit (3.3V)
36 Po4 O General output port-4

A7 O Address-7 for external DRAM
37 Po5 O General output port-5 (Address output-7 for external SRAM)

A8 O Address-8 for external DRAM
38 Po6 O General output port-6 (Address output-6 for external SRAM)

A9 O Address-9 for external DRAM
39 Po7 O General output port-7
40 VSS - Ground for digital circuit
41 IRQ/REQ I/O Interruption input (BS I/F:REQ output)

A11R O Address-11 for external DRAM
42 VDDM - Power supply for built-in 1Mbit SRAM (2.5V)
43 Fi0 I Flag input-0

/OE O Enable output for external up DRAM

44 Fi1 I Flag input-1

/CAS O Column address strobe for external DRAM

45 VSSM - Ground for built-in 1Mbit SRAM

(No.49831)1-57

4.23 TDA7404D-X (IC151,251) : Car radio signal processor

• Pin layout

• Block diagram

1

14

28

15

MIX

Gain/Auto Zero

Input Multiplexer

Mono/Beep

Mixing Stage

Beep

Loudness

Volume

Soft Mute

Digital Control I C-Bus

Treble

2

Bass

Mono Fader
Mono Fader

Mono Fader
Mono Fader

Mono Fader
Mono Fader

Zero Cross

Supply

1-58 (No.49831)

4.24 TDA7560-8U (IC301) : Car radio amplifier

•Pin layout

1 25

IN1

IN2

IN4

TAB

P-GND2

ST-BY

OUT2-

Vcc

OUT2+

OUT1-

P-GND1

SVR

OUT1+

S-GND

IN3

OUT3+

C-GND

OUT3-

P-GND3

• Block diagram

Vcc1 Vcc2

ST-BY

Vcc

MUTE

OUT4+

OUT4-

P-GND4

HSD

100nF470uF

IN1

IN2

IN3

IN4

MUTE

0.1µF

0.1µF

0.1µF

0.1µF

AC-GND

0.47uF 47uF

SVR TAB S-GND

HSD

HSD/V

OUT1+

OUT1-

PW-GND

OUT2+

OUT2-

PW-GND

OUT3+

OUT3-

PW-GND

OUT4+

OUT4-

PW-GND

OFF

DET

(No.49831)1-59

4.25 TMP91CW12AF4NB1 (IC501) : CPU

• Pin layout

75 51

76 50

100 26

125

• Block diagram
Pin No Symbol I/O Function

1 VREFL - Connect to ground
2 AVSS - Connect to ground
3 AVCC - Connect to 3.3V
4 CDON O CD power supply (3.3V) control
5 CDREQ O CD mechanism power supply re quest
6 CDMUTE O ICD mute
7 MP3RESET O CD MP3 reset
8 MP3STB O CD MP3 standby (H: Standby)

9 to 11 NC - Not connect

12 SW2 I CD mechanism SW2
13 REST I CD mechanism rest SW

14 to 17 NC - Not connect

18 LCDCE/SO O Chip enable to LCD driver (Not connect)
19 LCDDA/SI O Data to LCD driver (Not connect)
20 LCDCK O Clock to LCD driver (Not connect)
21 BUSS0 I JVC BUS data
22 BUSSI O JVC BUS data
23 BUSSCK I/O JVC BUS clock
24 AM0 Pull up to 3.3V
25 DVCC - Connect to 3.3V
26 X2 Crystal oscillator (24.576MHz)
27 DVSS - Connect to ground
28 X1 Crystal oscillator (24.576MHz)
29 AM1 Pull up to 3.3V
30 RESET I Reset

31,32 NC - Not connect

33 EMU0 - Not connect
34 EMU1 - Not connect
35 B.DET I Back up power supply detection (H: STOP mode)
36 SW1 I CD mechanism SW1
37 P.DET I Main power off detection (H: HALT mode)

38 to 42 NC - Not connect

43 ALE - Not connect
44 BUS3 I/O CD DSP data3
45 BUS2 I/O CD DSP data2
46 BUS1 I/O CD DSP data1
47 BUS0 I/O CD DSP data0

1-60 (No.49831)

Pin No Symbol I/O Function

48 BUCK O Clock to CD DSP data
49 CCE O CD DSP chip enable
50 DSPRESET O CD DSP reset
51 NC Not connect
52 DISCSEL I 8cm DISC mode (L)
53 DACSEL I DAC mode (H)
54 WMASEL I WMA mode (H)
55 TESTMODE I LCD/AD key/Remocon invalidity selection (L)
56 RWSEL O CD-RW switching (RW:L)
57 LD/FE O LOADING/FEED switching (H:LD, L:FE)
58 LOAD O Loading (L:Loading, H:Eject)
59 /BUSIO O JVC BUS input/output control (Inverting output)
60 BUSIO O JVC BUS input/output control
61 NC - Not connect
62 DVSS - Connect to ground
63 NMI I Connect to P.DET
64 DVCC - Connect to 3.3V
65 DACML O DAC mode control latch
66 DACMC O DAC mode control BCk
67 DACMD O DAC mode control data
68 DACCS O DAC chip select

69 to 77 NC - Not connect

78 BOOT
79 NC - Not connect
80 8VDET I CD mechanism power supply detection (L: 8V exist)
81 MP3REQ I CD MP3 request

82,83 NC - Not connect

84 MP3DI I CD MP3 data
85 MP3CK O Clock for CD MP3 data
86 BUSINT I Interrupt for JVC BUS transmission start

87,88 NC - Not connect

89 DVCC - Connect to 3.3V
90 NC - Not connect
91 DVSS - Connect to ground
92 KEY0 I Key input0 (8-bits A/D input)
93 KEY1 I Key input1 (8-bits A/D input)
94 TEMP I detecting sign al for high temperature
95 IOP I IOP measuring signal of pick

96 to 99 NC - Not connect

100 VREFH - Connect to 3.3V

(No.49831)1-61

4.26 TMP91CW12AF4RA3 (IC501) : CPU

• Pin layout

75 51

76 50

100 26

125

• Block diagram
Pin No Symbol I/O Function

1 VREFL - Connect to ground
2 AVSS - Connect to ground
3 AVCC - Connect to 3.3V
4 CDON O CD power supply (3.3V) control
5 CDREQ O CD mechanism power supply re quest
6 CDMUTE O ICD mute
7 MP3RESET O CD MP3 reset
8 MP3STB O CD MP3 standby (H: Standby)

9 to 11 NC - Not connect

12 SW2 I CD mechanism SW2
13 REST I CD mechanism rest SW

14 to 17 NC - Not connect

18 LCDCE/SO O Chip enable to LCD driver (Not connect)
19 LCDDA/SI O Data to LCD driver (Not connect)
20 LCDCK O Clock to LCD driver (Not connect)
21 BUSS0 I JVC BUS data
22 BUSSI O JVC BUS data
23 BUSSCK I/O JVC BUS clock
24 AM0 Pull up to 3.3V
25 DVCC - Connect to 3.3V
26 X2 Crystal oscillator (24.576MHz)
27 DVSS - Connect to ground
28 X1 Crystal oscillator (24.576MHz)
29 AM1 Pull up to 3.3V
30 RESET I Reset

31,32 NC - Not connect

33 EMU0 - Not connect
34 EMU1 - Not connect
35 B.DET I Back up power supply detection (H: STOP mode)
36 SW1 I CD mechanism SW1
37 P.DET I Main power off detection (H: HALT mode)

38 tp 42 NC - Not connect

43 ALE - Not connect
44 BUS3 I/O CD DSP data3
45 BUS2 I/O CD DSP data2
46 BUS1 I/O CD DSP data1
47 BUS0 I/O CD DSP data0

1-62 (No.49831)

Pin No Symbol I/O Function

48 BUCK O Clock to CD DSP data
49 CCE O CD DSP chip enable
50 DSPRESET O CD DSP reset
51 NC Not connect
52 DISCSEL I 8cm DISC mode (L)
53 DACSEL I DAC mode (H)
54 WMASEL I WMA mode (H)
55 TESTMODE I LCD/AD key/Remocon invalidity selection (L)
56 RWSEL O CD-RW switching (RW:L)
57 LD/FE O LOADING/FEED switching (H:LD, L:FE)
58 LOAD O Loading (L:Loading, H:Eject)
59 /BUSIO O JVC BUS input/output control (Inverting output)
60 BUSIO O JVC BUS input/output control
61 NC - Not connect
62 DVSS - Connect to ground
63 NMI I Connect to P.DET
64 DVCC - Connect to 3.3V
65 DACML O DAC mode control latch
66 DACMC O DAC mode control BCk
67 DACMD O DAC mode control data
68 DACCS O DAC chip select

69 to 77 NC - Not connect

78 BOOT
79 NC - Not connect
80 8VDET I CD mechanism power supply detection (L: 8V exist)
81 MP3REQ I CD MP3 request

82,83 NC - Not connect

84 MP3DI I CD MP3 data
85 MP3CK O Clock for CD MP3 data
86 BUSINT I Interrupt for JVC BUS transmission start

87,88 NC - Not connect

89 DVCC - Connect to 3.3V
90 NC - Not connect
91 DVSS - Connect to ground
92 KEY0 I Key input0 (8-bits A/D input)
93 KEY1 I Key input1 (8-bits A/D input)
94 TEMP I detecting signal for high temperture
95 IOP I IOP measuring signal of pick

96 t0 99 NC - Not connect

100 VREFH - Connect to 3.3V

(No.49831)1-63

4.27 UPD784217AGC217 (IC701) : CPU

• Pin layout

75 51

76 50

100 26

125

• Block diagram
Pin No Symbol I/O Function

1 S.SELECT O E-VOL selection output, H: REAR L: FRONT
2 DSP.SELECT O DSP or Source direct selection output, H: Source direct L: DSP
3 LIN E IN ON O OTH ER
4 AMP KILL O Internal amplifier ON/OFF selection, H: OFF L: ON

5 to 7 NOT USE - Not connect

8 ANT CONT O Antenna remote control

9 VDD - Power supply
10 X2 ­11 X1 I
12 VSS - Ground
13 XT2 ­14 XT1 ­15 RESET I System reset
16 REMOCON I Remocon input
17 BUS-INT I J-BUS INT
18 PS2 I Power save2, H means STOP mode
19 CD-REQ I CD REQ INPUT
20 RDS-SCK - Not use
21 STEERING REMOCON I Steering remocon input
22 KEY DATA I KEY DATA
23 AVDD - A/D converter power supply
24 AVREF0 - A/D reference voltage
25 VOL1 I Volume encoder pulse input 1
26 VOL2 I Volume encoder pulse input 2

27 to 29 NOT USE - Connect to ground

30 MRC I MRC input
31 SQ I Not use, pull down
32 SM I S.METER input
33 AVSS - Ground
34 NOT USE - Not connect
35 STAGE3 I Feature selection, H: SH9750 L: SH9700
36 AVREF ­37 BUS-SI I J-BUS data input
38 BUS-SO O J-BUS data output
39 BUS-SCK I/O J-BUS clock input/output
40 BUS-I/O O J-BUS I/O selection output: H input: L
41 DISP DA O DISPLAY DATA output
42 DISP SCK O DISPLAY SCK
43 DISP CE O DISPLAY CE
44 BUZZER O Buzzer output
45 E2PROM-DI I I2C data input
46 E2PROM-DO O I2C data output
47 E2PROM-CLK O I2C clock output

1-64 (No.49831)

Pin No Symbol I/O Function

48 NOT USE - Not connect
49 DETACH I Detach detect input; H means detaching
50 RDY I DSP data writing ready input
51 INPUT OVER I lLINE,AUX input over detecting port, L: Input over
52 S.RESET O DSP system reset output
53 INIT.RESET O DSP initialize reset output
54 RQ O DSP request in put, RQ=L: Interface to micom
55 DSP SCK O DSP CLOCK OUTPUT
56 DSP DA O DSP data output
57 DSP SI I DSP data input
58 BBE O BBE ON/OFF selecting output, H: BBE1,2,3,FIX L: OFF
59 NOT USE - Not connect
60 RDS DA - Not use
61 SD/ST I Station detector or stereo indicator input;

H means a station is there, L means the program is stereo.
62 AFCK - Not use
63 SEEK/STOP O Auto seek and stop selecting output; H means seeking, L means receiving.
64 CF SEL O Wide & Narrow
65 FM/AM O FM,AM band selecting output; H=FM, L=AM
66 PLL-CE O CE output for PLL IC
67 PLL-DO O Data output for PLL IC
68 PLL-CLK O Clock output for PLL IC
69 PLL-DI I Data input from PLL IC
70 TEL-MUTING I Telephone muting detection input; Active level can be selected H or L in PSM
71 DIM-OUT O Dimmer detector output
72 VSS - Ground
73 DIM-IN I Dimmer detector input L=dimmer on
74 PS1 I Power save1 L=ACC off
75 POWER O Power ON/OFF control output H=power on
76 NOT USE O Not connect
77 MUTING O Muting output L=muting on
78 CD MUTING I CD mute input L=mute on
79 CD RESET O CD reset control out H=reset on
80 NOT USE - Not connect
81 VDD - Power supply
82 VOL-MUTE - Not use
83 VOL-DA O Data output for e-vol IC
84 VOL-CLK O Clock output for e-vol IC
85 NOT USE O Not connect
86 SUB MUTING O Muting control output for subwoofer
87 LPF1 O LPF control1
88 LPF2 O LPF control2
89 STAGE2 I Feature selection H: R or Do L: J or U
90 STAGE1 I Feature selection H: R or U L: J or Do
91 PM0 O Panel motor close control output
92 PM1 O Panel motor open control output
93 PMKICK O Panel motor kick control output
94 TEST For rewriting flash memory
95 PNL-SW1 I Panel posi tion sw1
96 PNL-SW2 I Panel posi tion sw2
97 PNL-SW3 I Panel posi tion sw3
98 PNL-SW4 I Panel posi tion sw4
99 PNL-SW5 I Panel posi tion sw5

100 PNL-SW6 I Panel position sw6

(No.49831)1-65

VICTOR COMPANY OF JAPAN, LIMITED

AV & MULTIMEDIA COMPANY MOBILE ENTERTAINMENT CATEGORY 10-1,1chome,Ohwatari-machi,Maebashi-city,371-8543,Japan

(No.49831)

Printed in Japan

WPC