SERVICE MANUAL
CD RECEIVER
KD-LX333R
KD-LX333R
Contents
Safety precaution
Preventing static electricity
Disassembly method
Adjustment method
STDM
1-2
1-3
1-4
1-13
SOURCE
ATT
7
9
8
KD-LX333R
10
12
11
Flow of finctional operation intil opelation
until TOC read
Maintenance of laser pickup
Replacement of laser pickup
Description of Major ICs
OFF
Area Suffix
E
EX
Continental Europe
Central Europe
1-14
1-16
1-16
1-17~33
COPYRIGHT 2002 VICTOR COMPANY OF JAPAN, LTD.
No.49715
Jun. 2002
Description of major ICs
/
TC9490FA (IC521) : DSP & DAC
1.Pin layout & Block daiagram
KD-LX333R
DV
SS3
RO
DV
DD3
DVR
LO
DV
SS3
ZDET
SS5
V
BUS0
BUS1
BUS2
BUS3
BUCK
/CCE
/RST
VXDD3XOXI
SS3
XV
TEIN
DD3VSS3
V
DMO
FMO
DD3
AV
SEL
TEBC
RFGC
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
49
50
51
52
LPF
Clock
generator
1-bit
DAC
PWM
Servo control
A/D
53
54
55
56
Address
circuit
ROM
RAM
Digital equalizer
automatic
adjustment circuit
57
58
59
60
61
62
Micro-
controller
interface
circuit
Correction
Audio output
circuit
16k
RAM
Digital output
CLV servo
Sync signal
protection
EFM
Sub code
detector
63
VCO
PLL
TMAX
REF
V
D/A
Data
slicer
TRO
FOO
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
TEZI
TEI
SBAD
FEI
RFRP
RFZI
RFCT
DD3
AV
RFI
SLCO
SS3
AV
VCOF
REF
RV
LPFO
LPFN
64
DD5
V
17
TMAX
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
BCK
LRCK
AOUT
DOUT
IPF
DD3
V
V
SBOK
CLCK
DATA
SFSY
SBSY
/HSO
UHSO
DD3
PV
PDO
SS3
1-17
KD-LX333R
2.Pin function (1/2)
Pin No.
1
2
3
4
Symbol
BCK
LRCK
AOUT
DOUT
5
6
7
8
9
10
11
12
13
14
VDD3
VSS3
SBOK
CLCK
DATA
SFSY
SBSY
/HSO
/UHSO
IPF
I/O
O
O
O
O
O
-
-
O
I/O
O
O
O
O
O
TC9490FA(2/3)
Function
Bit clock outputpin 32fs, 48fs, or 64fs selectable by command.
L/R channel clock output pin."L" for L channe and "H" for R channel.
Output polarity can be inverted by command.
Audio data output pin. MSB-first or LSB-first selectable by command.
Digital data output pin. Outputs up to double-speed playback.
Correction flag output pin.When set to "H",AOUT output cannot be corrected
by C2 correction processing.
Digital 3.3V power supply voltage pin.
Digital GND pin.
Subcode Q data CRCC result output pin."H" level when result is OK.
Subcode P-W data read clockI/O pin. I/O polarity selectable by command.
Subcode P-W data output pin.
Playback frame sync signal output pin.
Subcode block sync signal output pin. "H" level at S1 when subcode sync is
detected.
Playback speed mode flag output pins.
/HSO
H
H
L
--
H
L
L
--
Playback speed/UHSO
Normal
Double
4 times
---
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
PVDD3
PDO
TMAX
LPFN
LPFO
PVREF
VCOF
SS3
AV
SLCO
RFI
AV
RFCT
RFZI
RFRP
FEI
SBAD
TEI
TEZI
FOO
TRO
REF
V
-
PLL-only 3.3V power supply voltage pin.
O
EFM and PLCK phase difference signal output pin.
O
TMAX detection result output pin.
TMAX OutputTMAX Detection result
Longer than fixed period
Within fixed period
Shorter than fixed period
I
Inverted input pin for PLL LPF amp.
O
Output oin for PLL LPF amp.
-
PLL-only V
VCO filter pin.
O
Analog GND pin.
DAC output pin for data slice level generation.
O
RF signal input pin.Zin selectable by command.
I
Analog 3.3V power supply voltage pin.
RFRP signal center level input pin.
I
RFRP signal zero-cross input pin.
I
RF ripple signal input pin.
I
Focus error signal input pin.
I
Sub-beam adder signal input pin.
I
Tracking error input pin. Inputs when tracking servo is on.
I
Tracking error signal zero-cross input pin.
I
Focus equalizer output pin.
O
Tracking equalizer output pin.
O
Analog reference power supply voltage pin.
-
REF pin.
"PVDD3"
"HIZ"
"AV
SS3"
1-18
KD-LX333R
2.Pin function (2/2)
Pin No.
36
37
38
39
40
41
42
43
44
45
Symbol
RFGC
TEBC
SEL
AV
FMO
DMO
V
V
TESIN
XV
46
47
48
49
XV
DV
50
51
52
DV
DVR
53
54
55
56
57
58
59
60
61
62
63
64
DV
ZDET
V
BUS0
BUS1
BUS2
BUS3
BUCK
/CCE
/RST
V
DD3
SS3
DD3
XI
XO
DD3
RO
DD3
LO
SS5
DD5
SS3
SS3
SS3
I/O
O
O
O
O
O
-
-
I
-
I
O
-
O
-
O
O
-
I/O
I
I
I
-
TC9490FA(3/3)
Function
RF amplitude adjustment control signal output pin.
Tracking balance control signal output pin.
APC circuit ON/OFF signal output pin. At laser on,high impedance with
UHS="L" ,H output with UHS="H".
Analog 3.3V power supply voltage pin.
Feed equalizer output pin.
Disc equalizer output pin.
Digital GND pin.
Digital 3.3V power supply voltage pin.
Test input pin. Normally,fixed to "L".
System clock oscillator GND pin.
System clock oscilatoe input pin.
System clock oscillator output pin.
System clock oscillator 3.3V power supply voltage pin.
DA converter GND pin.
R-channel data forward output pin.
DA converter 3.3V power supply pin.
Reference voltage pin.
L-channel data forward output pin.
DA converter GND pin.
1 bit DA converter zero data detection flag output pin.
Microcontroller interface GND pin.
Microcontroller interface data I/O pins.
Microcontroller interface clock input pin.
Microcontroller interface chip enable signal input pin.At "L".
Bus0 to BUS3 are active.
Reset signal input pin. At reset,"L".
Microcontroller interface 5V power supply pin.
NJM4565MD (IC151,IC171,IC323) : Operational amp
+
A OUTPUT
-
A INPUT
+
A INPUT
V
1
2
3
-
4
8
V
B OUTPUT
7
B INPUT
-
6
5
+
B INPUT
1-19
KD-LX333R
TA2147F-X (IC501) : RF amp.
1.Terminal layout
2.Block diagram
VRO
FEO
FEN
RFRP
RFRPIN
RFGO
RFGC
AGCIN
RFO
RFN
13GVSW
14
15
16
17
18
19
20
21
22
23
10pF
40k
30k
20k 20k
20k
20k
BOTTOM
3k
15k
50 A
12k
12k
PEAK
20k
180k
40pF
20k
20k
PEAK
1.3V
240k
180k
40k
40k
240k
15pF
15pF
40pF
60k
60k
50k
2k
20 A
20k
60 A
50k
14k
k
1
80k
80k
20k
20k
15k
x0.5
x2
x0.5
x2
1k
2k
1.75k
10pF
12 RFDC
11
TEO
10
TEN
TEBC
9
8
SEL
7
LDO
MDI
6
5
TNI
4
TPI
3
FPI
2
FNI
1-20
GND
24
3k
1
Vcc
3.Pin function
Pin No.
1
2
3
4
5
6
7
8
Symbol
Vcc
FNI
FPI
TPI
TNI
MDI
LDO
SEL
I/O
Function
-
3.3V Power supply pin
I
Main-beam amp input pin
I
Main-beam amp input pin
I
Sub-beam amp input pin
I
Sub-beam input pin
I
Monitor photo diode amp input pin
O
Laser diode amp output pin
I
APC circuit ON/OFF control signal,laser diode (LDO) control signal input or
bottom/peak detection frequency change pin.
KD-LX333R
9
10
11
12
13
TEBC
TEN
TEO
RFDC
GVSW
APC
circuit
GND OFF
HIZ
Vcc
I
Tracking error balance adjustment signal pin
Adjusts TE signal balance by eliminating carrier component from
PWM signal(3-state output, PWM carrier = 88.2kHz) output from
TC9490F/FA TEBC pin using RC-LPF and inputting DC.
TEBC input voltage:GND~Vcc
I
Tracking error signal generation amp negative-phase input pin
O
Tracking error signal generation amp output pin.
Combining TEO signal and RFRP signal with TC9490F/FA configures
tracking search system.
O
RF signal peak detection output pin
I
AGC/FE/TE amp gain change pin
GND
HIZ
Vcc
Connected to Vcc
through 1k resistor
Control signal output
ON
Control signal output
ON
ModeGVSW
CD-RW
CD-DA
CD-DA
LDOSEL
14
15
16
17
18
19
20
21
22
23
24
VRO
FEO
FEN
RFRP
RFRPIN
RFGO
RFGC
AGCIN
RFO
RFN
GND
Reference voltage (VRO) output pin *VRO = 1/2 Vcc when Vcc = 3.3V
O
Focus error signal generation amp output pin
O
Focus error signal generation amp negative-phase input pin
I
Signal amp output pin for track count
O
Combining RFRP signal TEO signal with TC9490F/FA configures tracking
search system.
Signal generation amp input pin for track count
I
RF signal amplitude adjustment amp output pin
O
RF amplitude adjustment control signal input pin
I
Adjusts RF signal amplitude by eliminating carrier component from PWM
signal (3-state output, PWM carrier = 88.2kHz) output from TC9490F/FA
RFGC pin using RC-LPF and inputting DC.
*RFGC input voltage : GND-Vcc
RF signal amplitude adjustment amp input pin
I
RF signal generation amp output pin
O
RF signal generation amp input pin
I
GND pin
-
1-21
KD-LX333R
F
TA8273H (IC941) : Power amp
1.Block diagram
INRF
0.22 F
AC CONT1
INRR
0.22 F
+
Vcc 1/2 Vcc 3/4
2200 F 0.022
6 20
+
11
-
+
+
-
9
7
OUT RF+
OUT RF-
1
Protective
circuit
+
-
+
12
+
-
GND
8
OUTRR+
5
OUTRR-
3
GND
2
ST BY
REF
47 F
INLF
AC CONT2
PRE GND
INLR
+5V
ST ON
+
0.22 F
+
0.22 F
4
Stand by
Switch
Mute
10
+
Ripple
Filter
Mute
22
circuit
3.3 F
+
15
-
+
-
17
19
10K
+
OUTLF+
OUTLF-
Low Level
Mute ON
25
18
21
23
GND
OUTLR+
OUT LR-
13
14
Protective
circuit
-
+
+
-
1-22
ON TIME
22 F
Muting &
16
+
ON Time Control
Circuit
GND
24
2.Terminal layout
KD-LX333R
3.Pin function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
SymbolPin No. Function
AC CONT 1
GND
OUTRRSTBY
OUTRR+
VCC1/2
OUTRFGND
OUTRF+
REF
INRF
INRR
PREGND
INLR
INLF
ONTIME
OUTLF+
GND
OUTLFVCC3/4
OUTLR+
MUTE
OUTLRGND
AC CONT 2
Header of IC
Power GND
Outpur(-) for Rear Rch
Stand by input
Output (+) for Rear Rch
Power input
Output (-) for Front Rch
Power GND
Output (+) for Front Rch
Ripple filter
Front Rch input
Rear Rch input
Signal GND
Rear Lch input
Front Lch input
Power on time control
Output (+) for Front Lch
Power GND
Output (-) for Front Lch
Power input
Output (+) for Rear Lch
Muting control input
Output (-) for Rear Lch
Power GND
Header of IC
TA8273H
1-23
KD-LX333R
UPD784217AGC168 (IC701) : Main micon
1.Pin layout
100 ~ 76
1
75
~
25
26 ~ 50
2.Pin functions(1/3)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Symbol
SW2
SW3
SW4
RST-SW
LMO
LM1
DIM-OUT
ILLUM1
VDD
X2
X1
VSS
XT2
XT1
RESET
SW1
BUS-INT
PS2
CRUISE
RDS-SCK
RDS DA
REMOCON
AVDD
AVREFO
TEM1
KEY0
KEY1
KEY2
LEVEL
MRC
SQ
SM
AVSS
W-VOL
DOT-CNT
AVREF
BUS-SI
BUS-SO
BUS-SCK
STAGE2
LCD-DA
LCD-SCK
~
51
I/O
Function
I
CD mechanical switch 2 detection signal input
I
CD mechanical switch 3 detection signal input
I
CD mechanical switch 4 detection signal input
I
Rest switch detection signal input
O
Motor signal control signal output at loading
O
Motor signal control signal output at leject
O
DIMMER pulse control output
O
POWER ON:H,FLAT PANEL:L
-
5V
-
-
-
GND
-
I
Reset detection teaminal
I
CD mechanical switch 1 detection signal input
I
J-BUS int
I
POWER SAVE2. Operating together with BACKUP.H input:STOP
I
Pulse signal for CRUISE input(only in 330R)
I
RDS clock input
I
RDS data input
I
Remocon input(111R:READY)
-
5V
-
5V
I
Temperature detection input
I
Key input 0
I
Key input 1
I
Key input 2
I
Level meter input
I
MRC output voltage detection
I
S.QUALITY level input
I
S.METER level input
-
GND
O
Subwoofer volume control analog output
O
Dot matrix contrast adjustment analog output
-
5V
I
J-BUS data input
O
J-BUS data output
I/O
J-BUS clock input and output
I
H:LX333R L:LX111R
O
Data output to LCD driver
O
Clock output to LCD driver
1-24
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