VIDEO TECHNICAL GUIDE
COPYRIGHT © 2000 VICTOR COMPANY OF JAPAN, LTD.
No. 86056
September 2000
2000 Basic DVC Models
DIGITAL VIDEO CAMERA
INDEX
INDEX-1
SECTION 1 OUTLINE OF THE PROCUCTS
1.1 COMPARSION TABLE OF DV MODELS SPECIFICATION BY PRODUCTS YEAR.............1-1
1.1.1 Comparison table of DV models specification by products year.....................................1-1
1.1.2 Specification of the DVC models....................................................................................1-3
SECTION 2 EXPLANATION OF ELECTRICAL CIRCUIT
2.1 CIRCUIT OUTLINE..............................................................................................................2-1
2.1.1 Basic block diagram.......................................................................................................2-1
2.2 CCD (ICX220AK/ICX221BK)................................................................................................2-2
2.2.2 CCD Image Sensor........................................................................................................2-3
2.2.3 Numbers of pixel for main models..................................................................................2-6
2.3 EXPLANATION OF CAMERA CIRCUIT...............................................................................2-7
2.3.1 Present AW / AE control system....................................................................................2-7
2.3.2 AF (Auto Focus) control.................................................................................................2-13
2.3.3 EIS (Electric Image Stabilizer) control............................................................................2-14
2.4 CAMERA SYSREM IC'S FUNCTION...................................................................................2-15
2.4.1 Camera DSP (IC4301: JCY0120) function.....................................................................2-15
2.5 EXPLANATION OF DECK CIRCUIT ....................................................................................2-22
2.5.1 Deck system overall structure........................................................................................2-22
2.5.2 PB equalizer and ATF....................................................................................................2-23
2.5.3 PLL operation................................................................................................................2-24
2.5.4 Basic principle of Viterbi detection .................................................................................2-25
2.5.5 Audio recording mode....................................................................................................2-26
2.5.6 Audio signal processing.................................................................................................2-27
2.5.7 Clock system for audio data...........................................................................................2-28
2.5.8 Deck DSP IC function....................................................................................................2-29
2.5.9 Audio AMP IC function...................................................................................................2-35
2.6 SYSCON CPU.....................................................................................................................2-38
2.6.1 Contents of SYSCON CPU processing..........................................................................2-38
2.6.3 System composition.......................................................................................................2-39
2.6.4 SYSCON CPU block diagram........................................................................................2-40
2.6.5 SYSCON CPU (IC1001: MN1021617HL) pin functions..................................................2-41
2.7 DECK CPU...........................................................................................................................2-44
2.7.1 Contents of DECK CPU processing...............................................................................2-44
2.7.2 DECK system composition.............................................................................................2-44
2.7.3 Tracking Error information..............................................................................................2-45
2.7.4 1394 interface control....................................................................................................2-46
2.7.5 JLIP Video Capture........................................................................................................2-46
2.7.6 DECK CPU block diagram.............................................................................................2-47
2.7.7 Deck CPU (IC1401: MN103004KRH) pin functions........................................................2-48
INDEX-2
SECTION 3 HEAD CLOG WARNING
3.1 HEAD CLOG WARNING OF DVC........................................................................................3-1
3.1.1 Structure of Sync Blocks and Error correction................................................................3-1
3.1.2 Error Rate of DVC..........................................................................................................3-3
3.1.3 Previous method of head clog detection ........................................................................3-4
3.1.4 New method of head clog detection...............................................................................3-5
SECTION 4 DOCTOR SYSTEM
4.1 WHAT IS DOCTOR PROGRAM?.........................................................................................4-1
4.1.1 Matching of Doctor Program with Microcomputer Program............................................4-1
4.1.2 Use of Doctor Program for Camcorder...........................................................................4-2
4.1.3 Revision of Service Support System Software for Doctor Program................................4-2
4.1.4 Procedure to Rewrite Doctor Program...........................................................................4-3
4.2 DOCTOR PROGRAM SYSTEM IN THE PRESENT CIRCUMSTANCES.............................4-5
4.2.1 ON/OFF address and Program address.........................................................................4-5
4.2.2 Writing function of EEPROM data..................................................................................4-7
4.2.3 Upgrade of the service support system..........................................................................4-7
SECTION 1
OUTLINE OF THE PROCUCTS
1-1
1.1 COMPARSION TABLE OF DV MODELS SPECIFICATION BY PRODUCTS YEAR
1.1.1 Comparison table of DV models specification by products year (1/2)
Model
Function
Battery BN-V11 Ni-Cd
(6V, 1100 mAh)
BN-V12 Ni-Cd
(6V, 1200 mAh)
BN-V20 Ni-MH
(6V, 2000 mAh)
Continuous shooting tim e:
when VF is used:
BN-V12: 1hr.10min.
BN-V20: 1hr.50min.
when LCD is used:
BN-V12: 1hr.
BN-V20: 1hr.40min.
BN-V207 Lithium-ion
(7.2V, 700 mAh)
BN-V214 Lithium-ion
(7.2V, 1400 mAh)
Continuous shooting tim e:
when VF is used:
BN-V207: 1hr.
BN-V214: 2hrs.20min.
BN-V856: 8hrs.30min.
when LCD is used:
BN-V207: 50min.
BN-V214: 1hr.55min.
BN-V856: 7hrs.
BN-V408 Lithium-ion
(7.2V, 800 mAh)
BN-V416 Lithium-ion
(7.2V, 1600 mAh)
BN-V428 Lithium-ion
(7.2V, 2800 mAh)
Continuous shooting tim e:
when VF is used:
BN-V408: 1hr.15min.
BN-V416: 2hrs.30min.
BN-V428: 4hrs.20min.
BN-V856: 8hrs.40min.
when LCD is used:
Charging the battery Charging time: AA-V15 us ed
70 min. (BN-V11)
70 min. (BN-V12)
110 min. (BN-V20)
Charging time: AA-V20 us ed
90 min. (BN-V207)
180 min. (BN-V214)
Charging time: AA-V40 us ed
90 min. (BN-V408)
120 min. (BN-V416)
200 min. (BN-V428)
Viewfinder Color LCD 0.55" 113k pixels
B/W CRT
Color LCD 0.55" 113k pixels
B/W LCD 0.24" 76k pi xels
Color LCD 0.44" 113k pixels
B/W LCD 0.24" 76k pi xels
LCD monitor Non
2.5" 480 × 234 = 112k pixels
3" 480 × 234 = 112k pixels
Horizontal resolution: 240 lines
Amorphous silicon transistor
2.5" 480 × 234 = 112k pixels
3" 480 × 234 = 112k pixels
3.5" 480 × 234 = 112k pixels
Horizontal resolution: 240 lines
Amorphous silicon transistor
←
Image device 1/4"
Total 766 × 596 = 460k pixels
(*799 × 711 = 540k pixels)
Effective aria 611 × 480 = 290k pixels
(*601 × 576 = 350k pixels)
1/4"
Total 998 × 677 = 680k pixels
(*998 × 797 = 800k pixels)
Effective aria 711 × 485 = 340k pixels
(*702 × 575 = 400k pixels)
←
Horizontal resolution 360 Lines 400 Lines
←
Electric image
stabilizer
Yes
←←
Sensitivity 10 lux (*12 lux)
50 IRE Level, Slow Shutter off
16 lux (*18 lux)
50 IRE Level, Slow Shutter off
18 lux
50 IRE Level, Slow Shutter off
Lens specification F1.6 f = 3.9 to 62.4 mm
←
F1.8 f = 3.6 to 36.0 mm
Tele macro Yes
←←
Zoom ratio
Optical zoom: 16
×
Digital zoom: 4×/10× or 8×/20
×
Max. zoom: 160× or 320
×
←
Optical zoom: 10
×
Digital zoom: 4×/10×,25× or 45
×
Max. zoom: 100× ,250× or 450
×
Snapshot 5 mode
With frame
Full
Pin-up
Pin-up 4-division
Pin-up 9-division
←←
Playback snapshot Yes
←←
Playback digital zoom
Yes 10
×
RM-V712U
Yes 4
×
RM-V711U
Yes 10× or 25
×
RM-V716U
2000 Fusion DV Model1998 Fusion DV Model 1999 Fusion DV Model
Table 1-1-1 Comparison table of DV models specification by products year (1/2)
1-2
••••
Comparison table of DV models specification by products year (2/2)
Model
Function
Slow motion Yes
RM-V712U
Yes (Frame Advance)
RM-V711U (optional: GR-DVF11U)
Yes (Frame Advance)
RM-V716U
Video auto li
g
ht Yes Yes ( /No
)
Yes
Audio 2ch
(
48kHz,16-bit) /4ch(32kHz,12-bit
)
←←
Snapshot search No
←←
Record end search No
←←
Audio dubbing No (Yes:PAL model,32kHz only,RCU
only)
Yes (32kHz only,RCU only)
←
V.insert editin
g
No
←
Yes (SP onl
y)
Time code Yes
←←
Headphone terminal No
←←
AV output terminal RCA
(Video Audio L/R)
←
Ø3.5 mini
S output terminal Yes
←←
JLIP terminal Yes
←←
PC terminal No Yes (No: GR-DVF11U) Yes
(No: GR-DVF10,DVL100U,DVL305U,
DVL307U)
Digital still image output
terminal
No Yes (No: GR-DVF11U) Yes
(No: GR-DVF10,DVL100U,DVL305U,
DVL307U)
DV terminal No Yes (EG/EK Model Output only) Yes
(Output only: GR-DVL100EG/EK,
DVL108EG/EK,DVL200EG/EK,
DVL300EG/EK,DVL308EG/EK)
JLIP related
software
GV-CB3 JLIP video capture box (optional)
JLIP video capture Ver.2.0
JLIP video producer Ver.1.13
Provided CD-ROM or optional HS-V4KIT
(No: GR-DVF11U)
JLIP video capture Ver.3.0
JLIP video producer Ver.1.16
Provided CD-ROM or optional HS-V14KIT
(No: GR-DVF10,DVL100U,DVL305U,
DVL307U)
JLIP video capture Ver.3.1
JLIP video producer Ver.2.0
Picture Navigator (DSC model only)
JLIP ID number 06
←←
Remote control sensor Yes
←←
Button battery
(only for clock backup)
Yes: CR-2025 type Yes: CR-2032 type (built-in)
←
2000 Fusion DV Model1998 Fusion DV Model 1999 Fusion DV Model
Table 1-1-1 Comparison table of DV models specification by products year (2/2)
1-3
1.1.2 Specification of the DVC models
MODEL
SIGNAL
FORMAT
CCD VF
LDC
MONIDVTERMINAL
DIGITAL
STILL
OUTPUT
DSC MMC
DIGITAL
ZOOM
GR-DVF10 NTSC 1/4" 680K B/W 3.0 INCH IN/OUT - - - 250 X
GR-DVA10 NTSC 1/4" 680K COLOR 3.0 INCH IN/OUT YES - - 100 X
GR-DVA11/K NTSC 1/4" 680K COLOR 3.0 INCH IN/OUT YES DSC
MMC
100 X
GR-DVL100U NTSC 1/4" 680K B/W 2.5 INCH IN/OUT - - - 250 X
GR-DVL300U NTSC 1/4" 680K B/W 2.5 INCH IN/OUT YES - - 250 X
GR-DVL305U NTSC 1/4" 680K COLOR 2.5 INCH IN/OUT - - - 250 X
GR-DVL307U NTSC 1/4" 680K B/W 3.0 INCH IN/OUT - - - 250 X
GR-DVL500U NTSC 1/4" 680K COLOR 3.0 INCH IN/OUT YES - - 250 X
GR-DVL505U NTSC 1/4" 680K B/W 3.0 INCH IN/OUT YES DSC - 250 X
GR-DVL507U NTSC 1/4" 680K B/W 3.5 INCH IN/OUT YES - - 250 X
GR-DVL805U NTSC 1/4" 680K COLOR 3.5 INCH IN/OUT YES DSC - 250 X
GR-DVL300UM NTSC 1/4" 680K B/W 2.5 INCH IN/OUT YES - - 250 X
GR-DVL505UM NTSC 1/4" 680K B/W 3.0 INCH IN/OUT YES DSC - 250 X
GR-DVL805UM NTSC 1/4" 680K COLOR 3.5 INCH IN/OUT YES DSC - 250 X
GR-DVL300KR NTSC 1/4" 680K B/W 2.5 INCH IN/OUT YES - - 250 X
GR-DVL805KR NTSC 1/4" 680K COLOR 3.5 INCH IN/OUT YES DSC - 250 X
GR-DVL100EG PAL 1/4" 800K B/W 2.5 INCH OUT
∗
OPTION
- - 100 X
GR-DVL107EG PAL 1/4" 800K B/W 2.5 INCH IN/OUT YES - - 100 X
GR-DVL108EG PAL 1/4" 800K B/W 2.5 INCH OUT YES DSC
MMC
100 X
GR-DVL109EG PAL 1/4" 800K B/W 2.5 INCH IN/OUT YES DSC
MMC
100 X
GR-DVL200EG PAL 1/4" 800K B/W 3.0 INCH OUT YES DSC - 100 X
GR-DVL300EG PAL 1/4" 800K COLOR 3.5 INCH OUT YES - - 100 X
GR-DVL307EG PAL 1/4" 800K COLOR 3.5 INCH IN/OUT YES - - 100 X
GR-DVL308EG PAL 1/4" 800K COLOR 3.5 INCH OUT YES DSC
MMC
100 X
GR-DVL309EG PAL 1/4" 800K COLOR 3.5 INCH IN/OUT YES DSC
MMC
100 X
GR-DVL100EK PAL 1/4" 800K B/W 2.5 INCH OUT
∗
OPTION
- - 100 X
GR-DVL107EK PAL 1/4" 800K B/W 2.5 INCH IN/OUT
∗
OPTION
- - 100 X
GR-DVL108EK PAL 1/4" 800K B/W 2.5 INCH OUT YES DSC
MMC
100 X
GR-DVL109EK PAL 1/4" 800K B/W 2.5 INCH IN/OUT YES DSC
MMC
100 X
GR-DVL200EK PAL 1/4" 800K B/W 2.5 INCH OUT YES DSC - 100 X
GR-DVL300EK PAL 1/4" 800K COLOR 3.5 INCH OUT YES - - 100 X
GR-DVL308EK PAL 1/4" 800K COLOR 3.5 INCH OUT YES DSC
MMC
100 X
GR-DVL105A PAL 1/4" 800K B/W 2.5 INCH IN/OUT
∗
OPTION
- - 450 X
GR-DVL300A PAL 1/4" 800K B/W 2.5 INCH IN/OUT YES - - 450 X
GR-DVL800A PAL 1/4" 800K COLOR 3.5 INCH IN/OUT YES DSC - 450 X
GR-DVL105A-S PAL 1/4" 800K B/W 2.5 INCH IN/OUT
∗
OPTION
- - 450 X
GR-DVL300A-S PAL 1/4" 800K B/W 2.5 INCH IN/OUT YES - - 450 X
GR-DVL800A-S PAL 1/4" 800K COLOR 3.5 INCH IN/OUT YES DSC - 450 X
GR-DVL100EA PAL 1/4" 800K B/W 2.5 INCH IN/OUT
∗
OPTION
- - 450 X
GR-DVL300EA PAL 1/4" 800K COLOR 3.5 INCH IN/OUT YES - - 450 X
GR-DVL300ED PAL 1/4" 800K B/W 2.5 INCH IN/OUT YES - - 450 X
GR-DVL400ED PAL 1/4" 800K B/W 3.0 INCH IN/OUT YES - - 450 X
GR-DVL500ED PAL 1/4" 800K COLOR 3.0 INCH IN/OUT YES - - 450 X
GR-DVL600ED PAL 1/4" 800K B/W 3.5 INCH IN/OUT YES - - 450 X
GR-DVL707ED PAL 1/4" 800K B/W 3.5 INCH IN/OUT YES DSC - 450 X
GR-DVL800ED PAL 1/4" 800K COLOR 3.5 INCH IN/OUT YES DSC - 450 X
CC9370 NTSC 1/4" 680K B/W 3.0 INCH IN/OUT - - - 250 X
∗
OPTION: HS-V14KITE (CD-ROM and Cables)
Table 1-1-2 Specification of the DVC models
SECTION 2
EXPLANATION OF ELECTRICAL CIRCUIT
2-1
2.1 CIRCUIT OUTLINE
2.1.1 Basic block diagram
CCD
IC4301
CAMERA_DSP
IC4302
FIELD
MEMORY
TMY(8)
TMC(4)
TG
V.DRV
IC5501
FOCUS
DRIVER
&
ZOOM
DRIVER
IC4851
IRIS
DRIVER
&
HALL
AMP
IC4802-IC4805
SYSCON
CPU
IC1001
DYO(4),DCO(4)
BUS(16)
IRIS_O/C
DATA_OUT
IC3001
DECK_DSP
IC3002
16M
DRAM
IC3501
REC AMP
&
PB AMP
IC1401
DECK
CPU
IC3201
DVEQ
IC3301
DVANA
HSE
AUDIO
AMP
IC2201
RD(16)
RA(10)
MIC UNIT
INT_MIC / L
INT_MIC / R
A_OUT / R
A_OUT / L
MAIN
10
FMY(8)
FMC(4)
H1, H2, RG
XAVD, XAHD
IC1003
E2PROM
IC1004
RTC
32kHz
X1002
ANA_IO
S_DT_IN
AD(16)
S_DT_IN
S_DT_OUT
ON
SCREEN
IC1002
DRIVE+,-
FOCUS (4)
ZOOM (4)
IC1601
MDA
M
M
M
CAPSTAN
MOTOR
DRUM
MOTOR
LOADING
MOTOR
VIDEO
HEAD
IRIS PWM
AIDAT
DODAT
AIDAT
DODAT
MDA_IN
ATF_GAIN, M_VCOCTL, PBVCOCTL, FSPLLCTL
DV_C
LCD_R-Y
DATA_OUT
CLK27,CLK18,CLK13
OPTICAL
BLOCK
CCD_OUT
CDS/AGC
A/D
IC4201
CAM_AD(10)
54MHz
X5501
1394PHY
IC3101
TPA+,TPATPB+,TPB-
DATA_OUT
SUB
S_DT_OUT
LOAD_FWD
LOAD_REV
V1,V2,V3,V4
PD(4)
DYI(4),DCI(4)
HSE
PBDATA
ADDT(16)
ADDT(16)
ADDT(16)
ANA_IO
SPK+,SPK-
SP
PB_ENV
PB_ENV
IRIS PWM
RECC_ADJ
RECC_ADJ
H_GAIN,H_OFFSET
H_GAIN,H_OFFSET
MDA_IN
CCD
40
JUNCTION50
D_COIL_U
D_COIL_V
D_COIL_W
C_COIL_U
C_COIL_V
C_COIL_W
1F
1S
2F
2S
PBO
ATFO
IC5001
DATA_OUT
LCD
DRIVER
IC7601
MONI
LCD
R
G
B
SW
IC7604
VF
LCD
R
G
B
MONITOR20
LCD
DRIVER
IC7101
VF
LCD
EEP
ROM
RXD
TXD
SRV_TX
IF_RX
IC8001
DSC_IF
M32_R/D
CPU
IC8002
IC8003
16Mb
FLASH
DSC
01
REAR70
PC
RX
GND
J552
TX
JLIP
RX
TX
GND
EDIT
J553
IC1302
IC1014
IF_RX
IF_TX
TXD
RXD
EDIT_CTL
JLIP_L
M32_DTIN
PC_RX
PC_TX
JLIP_RX
JLIP_TX
32D(16)
32A(25) 32A(19)
JACK60
ATF_GAIN, M_VCOCTL
PBVCOCTL, FSPLLCTL
LCD_B-Y
LCD_Y
M32_DTOUT
TXD
RXD
M32_DTOUT
M32_DTIN
VIDEO
OUT
DV_Y
MY(8),MC(4)
DV_C
DV_Y
V_OUT
Y_OUT
C_OUT
S_OUT
AV
OUT
DV
AV_DET
MY(8),MC(4)
IC7603
A_OUT / R
A_OUT / L
DATA_OUT
VF_R, VF_G, VF_B, VBLK
VC1, BLK1
DRUM_REF
CAP_REF
DRUM_PG
DRUM_FG
CAP_FG
J501
J503
J502
*only for B/W VF model
DATA_OUT
JACK60
PD(4)
M14D2 Series
OSD_DATA
Fig. 2-1-1 Basic block diagram
2-2
2.2 CCD (ICX220AK/ICX221BK)
This IC functions as an interline CCD (Charge
Coupled Device = one of solid-state pickup
devices). Since this CCD conforms to the SD
mode of the DV standard, it has an optimum
number of vertical pixels for the MPEG2 main level
and it realizes a horizontal resolution of 450 TV
lines. As same as general CCD's currently in use,
this CCD is capable of camera shaking correction
and electronic panning and tilting owing to the
extension area of 33 percent extra in both the
vertical and horizontal directions.
Moreover, this CCD provides high quality wide
picture whose aspect ratio is exactly 16:9 without
vertical interpolation.
High sensitivity and low dark current are realized
thanks to adoption of the Super HAD CCD
technology with the color filters of yellow, cyan,
magenta and complementary green mosaic filters.
This CCD has an electronic shutter function that is
able to vary charge storage time by the field period
read system.
Frame period read system is realized by joint use
of the newly developed TG IC.
HØ1
HØ2
ØRG
ØSUB
VØ1
VØ2
VØ3
VDD
Photo
Sensor
VØ4
1
Ye
G
Ye
Mg
Ye
G
Cy
Mg
Cy
G
Cy
Mg
Ye
G
Ye
Mg
Ye
G
Horizontal-Register
Vertical-Register
14131211108 9
7 6 5 4 3 2
GND
VOUT
TEST
∗
Cy
Mg
Cy
G
Cy
Mg
GND
VL
∗
Fig. 2-2-1 CCD block diagram
ELEMENT STRUCTURE Int e rline type CCD image sensor
Optical size 1/4 inch size format
Total pixels NTSC: 998 (H) × 677 (V) approx. 680,000 pixels, PAL: 998×797 approx. 800,000 pixels
Effective pixels NTSC: 962 (H) × 654 (V) approx. 630,000 pixels, PAL: 962×774 approx. 740,000 pixels
4:3 NTSC NT SC: 711 (H) × 485 (V) approx. 340,000 pixels, PAL: 702×575 approx. 400,000 pixels
16:9 18MHZ NTSC: 948 (H) × 485 (V) approx. 460,000 pixels, PAL: 936×575 approx. 540,000 pixels
16:9 5fsc NTSC: 942 (H) × 485 (V) approx. 460,000 pixels, PAL: 922×575 approx. 530,000 pixels
H direction: Front 4 pixels, Rear 32 pixels
V direction: Front 11pixels, Rear 12 pixels
Board material Silicon
OB
Table 2-2-1 CCD functions
Pin No. Label In/Out Descript ion Pin No. Label In/Out Descript ion
1
V
φ
4
In Vertical register transfer clock 8 VOUT Out Video signal output
2
V
φ
3
In Vertical register transfer clock 9 GND - Ground
3
V
φ
2
In Vertical register transfer clock 10
φ
RG
In Reset gate clock
4
V
φ
1
In Vertical register transfer clock 11
Hφ1
In Horizontal register transfer clock
5 GND - Ground 12
H
φ
2
In Horizontal register transfer clock
6 T EST - Open 13
φ
SUB
In Su bstrate clo c k
7 VDD - Power supply 14 VL - Protect transistor bias
Table 2-2-2 CCD pin function
2-3
2.2.2 CCD Image Sensor
Main difference in CCD adopted with DVC and VHS-C.
(Pixel)
7.15µ m
5.55
µ
m
(Pixel)
3.80µ m
4.15
µ
m
33% EIS Area
962(H)
711(H)
485(V)
654(V)
Picture Area
13.5MHz
18MHz
510(H)
492(V)
9.54545MHz
(Pixel)
7.3µ m
4.7
µ
m
500(H)
582(V)
9.45833MHz
(Pixel)
4.85µ m
4.65
µ
m
752(H)
582(V)
14.1875MHz
(Pixel)
3.85µ m
3.50
µ
m
33% EIS Area
962(H)
702(H)
575(V)
774(V)
Picture Area
13.5MHz
18MHz
NTSC: effective 630,000 (Image 340,000) pixels PAL: effective 740,000 (Image 400,000) pixels
NTSC: effective250,000 pixels PAL: effective 290,000 pixels
PAL (760H-type): effective 440,000 pixels
510H-type/760H-type 1/4" CCD for VHS-C
960H-type 1/4" CCD (w/ EIS area) for DVC
(GR-DVX7, GR-DVF31/DVL40, GR-DVL300 etc.)
NTSC PAL NTSC PAL PAL (760H)
9.54545MHz
910fH × 2/3
910fH = 4 × fsc
Horizontal drive
frequency
9.45833MHz
908fH × 2/3
14.1875MHz
908fH
DVC VHS-C
18MHz: 1144fH
Picture area:13.5MHz: 858fH
13.5MHz = 18MHz × 3/4
13.5MHz: DVC format Y signal sampling frequency
f
H
= 15.734264KHz (PAL: 15.625KHz): Horizontal sync frequency
f
SC
= 3.579545MHz (PAL: 4.433618MHz): Color sub-carrier frequency
Fig. 2-2-2 Pixel number and pixel size of various CCD
2-4
1. Feature of CCD for this model
This CCD adopts the drive frequency and the number of pixels conforming to the DVC format. The
horizontal drive frequency is 18MHz based on 13.5MHz that is Y signal sampling frequency of the DVC
format. And the number of pixels secures the horizontal resolution of 400 lines that conforms to the high
resolution DVC format. Moreover, to keep resolution even if EIS is switched on, the CCD having EIS
(Electric Image Stabilizer) area (approx. 33% in area) is adopted.
Adoption of the usual 1/4”-type CCD realizes miniaturization of the lens unit with keep the zoom ratio of 10
times, and it also realizes miniaturization of whole body.
On the other hand, a pixel size gets smaller as the evil effect of miniaturization and large numbers of pixel.
It becomes unfavorable in the point of CCD sensitivity and dynamic range. For such reason, the minimum
object illumination is determined as 18 Lux EIA standard.
2. Improvement of the CCD for DVC
It is elaborated the following idea to make up for the decline of the sensitivity of CCD at all.
1) Optimization of the on-chip microlens
Loss of incident light is minimized by reduction of ineffective area between microlenses on the pixels.
Photo
shielding AI
Light
Ineffective
Effective
Transfer
section
On-chip microlens On-chip microlens
Sensor
Transfer
section
Ineffective
Light
Photo
shielding AI
Transfer
section
Transfer
section
Effective
Fig. 2-2-3 Structural drawing of CCD image sensor
2-5
2) Construction of internal lens
Since the internal lens is constructed between the color filter and gobo, the light condensation
efficiency is improved even for inclined incident light.
Sensor V. Register
On-chip
microlens
Color filter
Poly Si
Gobo
V. Register
Poly Si
Internal len
s
On-chip
microlens
Color filter
Gobo
Sensor
Fig. 2-2-4 Structural drawing of internal lens
2-6
2.2.3 Numbers of pixel for main models
Models Optical size Total pixels
Effective pixels
(EIS)
practical pixels
GR-DV1
GR-DVM1
GR-DVX
1/3” approx. 570,000
908H 616V
approx. 530,000
858H 614V
approx. 350,000
704H 499V
GR-DVL /DVL9000U
GR-DVL7 /DVL9600U
1/3”
Progressive
scan
approx. 380,000
758H 504V
–
approx. 360,000
724H 494V
GR-DVY
GR-DVM5U /DV3U
GR-DVF10U /20U
1/4” approx. 460,000
766H 596V
approx. 420,000
724H 582V
approx. 290,000
611H 480V
GR-DVX7
GR-DVM70U /50U
GR-DVA1 /F1
GR-DVF11 /21 /31U
GR-DVA10 /F10 /A11
GR-DVL100 /200 /300U
1/4” approx. 680,000
998H 677V
approx. 630,000
962H 654V
approx. 340,000
711H 485V
GR-DVL700
GR-DVL9800U
1/3”
Progressive
scan
approx. 680,000
1002H 662V
approx. 630,000
962H 654V
approx. 340,000
720H 480V
DSC XGA: 630,000
962H 654V
GR-DV1E
GR-DVM1E
GR-DVXE
1/3” approx. 670,000
908H 728V
approx. 620,000
858H 726V
approx. 420,000
704H 594V
GR-DVL9000E
GR-DVL9500E /9600E
1/3”
Progressive
scan
approx. 450,000
758H 592V
–
approx. 420,000
724H 582V
GR-DVM5E /DV3E
GR-DVF1E /DVF10E
1/4” approx. 540,000
766H 711V
approx. 500,000
724H 697V
approx. 530,000
601H 576V
GR-DVX4E /DVX7E
GR-DVL20 /30 /40E
GR-DVL100 /200 /300E
GR-DVL9200E
1/4” approx. 800,000
998H 797V
approx. 740,000
962H 774V
approx. 400,000
702H 575V
GR-DVL9700E /9800E 1/3”
Progressive
scan
approx. 800,000
1002H 782V
approx. 740,000
962H 774V
approx. 420,000
720H 576V
DSC XGA: 740,000
962H 774V
GR-SXM46 /SX41E
GR-SXM26 /SX21E
1/4” approx. 470,000
795H 596V
–
approx. 440,000
752H 582V
GR-FX11 /FXM16E
GR-FX102 /FXM106S
1/4” approx. 320,000
537H 597V
–
approx. 290,000
500H 582V
VHS-C
NTSC
GR-AXM220U
GR-SXM920U
1/4” approx. 270,000
537H 505V
–
approx. 250,000
510H 492V
DVC
PAL
DVC
NTSC
VHS-C
PAL
Table 2-2-3 Numbers of pixel for main models
2-7
2.3 EXPLANATION OF CAMERA CIRCUIT
2.3.1 Present AW / AE control system
The signal-processing block of the present camera system is composed as shown below ( Fig. 2-3-1)
CCD A/D
COLOR
SEPARATION
LPF
MATRIX
ENCODER
PROCESS
AGC
GCA
GCA
Y
R
G
B
Y
C
TG
DRIVE
IRIS DRIVE
CAMERA CPU
IR SENSOR
∗
1
∗
2
∗
3
∗
4
∗
5
∗
1 Iris control
∗
2 Shutter speed setting
∗
3 Analog amp gain (AGC gain)
∗
4 WB setting (RED gain, BLUE gain)
∗
5 Parameter for picture compensation (color reproducibility, S/N ratio…)
Fig. 2-3-1 Camera block configuration
2-8
1. AE (Auto Exposure) control
The luminance level of camera output picture is controlled to always be proper exposure regardless of the
brightness and illumination of the object.
1) AE input information
•
Average of luminance level divided a frame picture into 48 blocks passed through the LPF.
•
The area ratio of the sections having luminance components higher than a certain level to the
whole sections.
AE control
Weighting of
sectioned data
Caluculation of
evaluation value
Target > Evaluation?
AGC gain down
↓
Slow shutter OFF
↓
Iris close
Iris open
↓
AGC gain up
↓
Slow shutter ON
RET
Fig. 2-3-2 AE control flow chart
2) Weighting of data on sections
Though the respective data on 48 sections are weighted, the basic settin g is to weight the center part
high.
Low
Low
High
High LowLow
Fig. 2-3-3 Weighting of data on sections
2-9
3) AE control and output luminance signal level
Gain-up mode: AUTO (OFF and AGC modes are the same as the VHS-C camcorder)
100 IRE
Open
0 IRE
5000 lux 300 lux 40-50 lux 10 lux
Close
MAX
MIN
1/30
1/60
1/240
ON
OFF
50 IRE
LUMINANCE
IRIS
APERTURE
AGC
GAIN
SHUTTER
SPEED
AUTO
LIGHT
ILLUMINATIONBRIGHT DARK
(2)
(1)
(3)
(4)
(5)
(6)
Fig. 2-3-4 AE control and output luminance signal level
2-10
(1) When the intensity of illumination is high and iris aperture is stopped down, the iris is opened for
compensating drop of the signal level by changing the shutter speed to high (1/250 sec).
(2) Since raising the AGC gain deteriorates the S/N ratio, the E-E level is slightly lowered in the
exposure compensation by controlling the AGC as compared with the iris control mode.
(3) As the intensity of illumination becomes low and AGC gain rises to maximum, the camera enters
the slow shutter mode (1/30 sec).
(4) When the camera enters the slow shutter mode, the signal level r ises by 6 dB and the AGC gain
drops in inverse proportion to the signal level.
(5) The auto-light is turned on when the illumination turns down a little more after the camera entered
the slow shutter mode and AGC gain rose to the maximum. There is a hysteresis to prevent
hunting as the auto-light is switched on/off.
(6) The intensity of illumination shown in the f igure is just an example and it varies depending on the
object, angle of view, etc.
2-11
2. AW (Auto White balance) control
AW control compensates the Red component gain and Blue component gain shown in the camera block
diagram to keep the white balance in the camera picture under every kind of light source.
Basic input data for AW control are three of the following.
(1) R, G, B levels of sections divided a picture into 48 sections.
(2) Data on existence/absence of infrared rays in the light source. This data is used for judging the
sort of the light so urce.
(3) Illumination judged with the exposure compensation parameters (iris/ AGC gain/ shutter speed).
The white balance is controlled by the following setting referring to the R, G, B data on the section that is
judged as a white (uncolored) part of the picture according to the three kinds of data mentioned above.
Red component gain = Green level / Red level
Blue component gain = Green level / Blue level
Besides the white balance control, balance among color phases is controlled by the parameter control in
the color signal processing from RGB to C signal depending on the light source.
1) Light source judging process
IR FLICKER BRIGHT LIGHT
DC component AC component (Over 4000 Lx)
SOURCE
Yes Yes Yes HAROGEN
Yes Yes No
∗
Yes No Yes OUT DOOR
Yes No No OUT DOOR
No Yes Yes FL LIGHT
No Yes No FL LIGHT
No No Yes FL LIGHT
No No No FL LIGHT
∗
: OUT DOOR or HAROGEN (not FL LIGHT)
Table 2-3-1 Light source judging process
2-12
2) AWB cont rol algorithm
AWB control
Light source judgment
(Gain limiter setting)
Sunlight?
Gain calculation from white block data
(Calculation value = Target gain)
Gain setting (adjustment) for the sunlight
(Adjustment value = Target value)
Optimum time constant setting for gain
control
Is the WB deviating to
blue?
R-gain up / B-gain down
Is the WB deviating to
red?
R-gain down / B-gain up
RET
YES
NO
NO
NO
YES
YES
The upper and lower limits of each gain are set according to
the ratio between R and B components and judgment of the
light source by the infrared sensor.
Setting of the control time constant to avoid unnatural color
variation.
Fig. 2-3-5 AW control flow chart
The light source of the natural light (sunlight), halogen lamp (indoor) or fluorescent lamp is judged
according to data of the infrared sensor and data on the illumination.
Since the gain to be compensated by the white balance control greatly varies depending on the
device used (CCD, IR cut filter, lens, etc.) and parameter for color separation, settings of limiter,
control time constant and color reproducing parameters differ from model to model.
2-13
2.3.2 AF (Auto Focus) control
1. Auto Focus operation during slow shutter mode
Though the basic Auto Focus operation is the sam e as usual, the interval of Auto Focus operation varies
conforming to the timing of the picture data renewal when the camera is in the slow shutter mode. For
example, in case the Gain-up mode is set to Auto, the shutter speed is changed to 1/30(2V) according to
the illumination of the object. Therefore, the Auto Focus operation also works every 2V. The Auto focus
operation works every 4V in Slow-4X mode and every 10V in Slow-10X in the same way.
1/60
Data
Renewal/processing
1/30
VD
Focus
operation
2V
Fig. 2-3-6 AF operation timing in slow shutter mode
2. Improvement of the Low-contrast performance
To improve the AF performance in the low contrast subject (such as the man's face), a route that has low
stage filter (HPF1) is added newly. The low contrast subject contains the frequency element that is not
comparatively high.
BPF HPF2 Rectifier
Peak
Addition
HPF1 Rectifier
Peak
Addition
HPF2 Rectifier
Peak
Addition
AFE
HPE
HPF1
HPF2
BPF
HPF1 Rectifier
Peak
Addition
HPF1 Rectifier
Peak
Addition
HPF2 Rectifier
Peak
Addition
AFE1
HPE1
HPF1
HPF2
HPF2 Rectifier
Peak
Addition
AFE2
HPE2
HPF1: 500KHz
HPF2: 1.7MHz
Previous
New
Fig. 2-3-7 Addition of AFE low stage filter
2-14
2.3.3 EIS (Electric Image Stabilizer) control
The accurate compensation without picture quality deterioration is possible by using CCD with expansion
area and correcting it two times.
CCD
CDS / AGC /
ADC
IWD FMC
VRAM
TG/
V_DRIVER
CPU
13.5 MHz18 MHz
Vector
(1) (2)
(3)
(4)
DSP
Fig. 2-3-8 EIS system block diagram
962
654(*774)
800
240(*288)
720
245(*292)
(1) Cutting out at TG (2) Cutting out at IWD
(3) Cutting out at Field Memory (4) Camera output
2 lines mixing transfer
Fig. 2-3-9 EIS operation
2-15
2.4 CAMERA SYSTEM IC'S FUNCTION
2.4.1 Camera DSP (IC4301: JCY0120) function
1. Camera DSP (IC4301: JCY0120) internal block diagram
CLK45
ADIN [9:0]
YO
CLR
SSG1
EIS/FMC
VRAM Contol
Vector Detect
ID
CLKYCA
CLK13
CLK13X
YOUT
SSG for TG/YCA
SSG2
CLK13
Main SSG
AUTO
CLKYCA
Auto operation
process
CLK18I
CLK13I
CLK27I
CLKGEN
Clock generate
TVSEL0
Y/C
CLKYCA
Y/C signal
process
IWD
CLK14
Frequency
converter
KIZU
White noise
compensation
SELECT
CLK13
ANA I/F
CLK13
Analog input
interface
NTSC/PAL
Color Encoder
CLKENC2
ENC
CLKENC1
CVF
CLK13
Interface for Color
Viewfer
KASHA
CLK13
Shutter sound
occurrence
D/A Converter
CLKENC1
YDAC
CO
D/A Converter
CLKENC2
CDAC
D/A Converter
CLK13
Y2DAC
Y2O
D/A Converter
CLK13
RYDAC
D/A Converter
CLK13
BYDAC
D/A Converter
KDAC
RYO
RYO
KO
BEND
PWM
AFBEND
AYO [3:0]
ACO [3:0]
COUT
Y2OUT
RYOUT
BYOUT
KOUT
CLKYCA
IRSI
HDYCA
VDYCA
FLDYCA
VBDAT
VBSTART
Test signal generator / Wipe / OSD mix
Hadamard NR / Mix / Signal select
CSYNC
HDANA
VDANA
CSYNC1
DYI [3:0]
DCI [3:0]
EOUT1 EOUT5 EOUT9
EOUT2 EOUT6 EOUT10
EOUT3 EOUT7 EOUT11
EOUT4 EOUT8 EOUT12
CLK27
INHA
INVA
ANACNT
FMY [7:0]
FMC [3:0]
TMY [7:0]
TMC [3:0]
IE1 FMRE1 FMWE1
IE2 FMRE2 FMWE2
OMT
MCLK RAD
FMWR WAD
RAE1 WAE1
RAE2 WAE2
DSC I/F
CLK13
DSC interface
FLDDSC
CLKDSC
HDDSC
VDDSC
CLKYCA
DSYO [7:0]
DSCO [7:0]
DSYI [7:0]
DSCI [7:0]
EDAC
12ch EVR DAC
ESSG
CLK13
SSG for Encoder
CBLK
CSYNC
BF
LSW
HRST4T
VRST4T
VBGEN
CLK13
VBID/WSS
Generator
YCIN
LHFO
ADYC
CLKYCA
ADKZ
HDTG
VDTG
SLEN
OSD I/F
CLK13
CLK13X
OSD Interface
DVC I/F
CLK13
DVC Interface
CLK27
DVSL SLDV
SLCV
FMSLSLFMDSSLSLDS
VBLK0
BLK10
BLK20
OSY_V OSY_1
OSR_V OSY_2
OSB_V
DYO [3:0]
DCO [3:0]
INH
INV
OUTH
OUTV
VR VBLK
VG BLK1
VB BLK2
VC1
VC2
HDOSD
VDOSD
CLKOSD
HDANA13
VDANA13
HDFMC
VDFMC
FLDFMC
OUTH13
OUTV13
CLKYCA
CLK13
CLK13X
CLKENC1
CLKENC2
RE DSTB
LWE HWE
CS RWSEL
ALE USEL0
USEL1
BUS [15:0]
CPU I/F
CPU Interface
CONTROL SINGNAL
DBI[15:0]
VDMDA
HDCPU VDCPU
FRP FLDCPU
Fig. 2-4-1 Camera DSP (IC4301: JCY0120) internal block diagram
2-16
2. Camera DSP (IC4301: JCY0120) pin functions (1/6)
Pin No. Label In/Out Description
100 VDMDA Out Vertical reference signal output for MDA
158 PWM Out PWM output
20 CLK45 Out 4.5MHz output
1 VSS - Ground for Digital
251 VDDE - Power supply for Digital (I/O)
255 CSYNCI
191 HDANA
117 VDANA
36 ANACNT
33 AY00
113 AY01
186 AY02
32 AY03
35 AC00
34 AC01
187 AC02
114 AC03
188 INHA
115 INVA
138 ADDVSS - Ground for add Digital
256 VDDE - Power supply for Digital (I/O)
64 VSS - Ground for Digital
69 ADDVDDE - Power supply for add Digital (I/O)
137 DSYO0
208 DSYO1
270 DSYO2
61 DSYO3
136 DSYO4
207 DSYO5
60 DSYO6
59 DSYO7
140 DSCO0
210 DSCO1
272 DSCO2
142 DSCO3
139 DSCO4
209 DSCO5
63 DSCO6
62 DSCO7
211 CLKDSC Out Clock for DSC
141 HDDSC Out Horizontal reference pulse output for DSC
212 VDDSC
143 FLDDSC
70 ADDVSS - Ground for add Digital
271 VDDE - Power supply for Digital (I/O)
146 DSYI0
215 DSYI1
145 DSYI2
Not used-
Not used-
Out Vertical reference pulse output for DSC
In Digital luminance signal input for DSC
Table 2-4-1 Camera DSP (IC4301: JCY0120) pin functions (1/6)
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