JDI TX54D82MM0BAA Specification

To : Shenzhen JLD Electronics Co., Ltd

TECHNICAL DATA

Date : June 05, 2013

Product Name

(NOTES)

1. This document may, wholly or partially, be subject to change without notice.

2. All rights are reserved ; No one is permitted to reproduce, duplicate or distribute in any form,

the whole or part of this document without Japan Display's prior written consent.

3. No one is permitted to explain nor disclose the contents of this document to third parties without

Japan Display's prior written consent.

4. Japan Display will not be held responsible for any damage to the user that may result from accidents

or any other reasons during operation of the user's unit according to this document, any previous

reports or oral discussions.

5. Circuitry and other examples described herein are meant merely to indicate the characteristics and

performance of Japan Display's products.

Japan Display assumes no responsibility for any intellectual property claims or other problems that

may result from applications based on the examples described herein.

6. No license is granted by implication or otherwise under any patents or other rights of any third

party or Japan Display Inc.

7. LIFE SUPPORT APPLICATIONS

use in LIFE SUPPORT SYSTEMS.

: The product covered by this document is not authorized for

TX54D82MM0BAA

CONTENTS

No. Item Sheet No. Page

— CONTENTS DPBC10000499-1 1-1/1
— RECORD OF REVISION DPBC10000499-1 2-1/1
— DESCRIPTION DPBC10000499-1 3-1/1

1 ABSOLUTE MAXIMUM RATINGS DPBC10000499-1 4-1/2 - 4-2/2
2

INITIAL OPTICAL CHARACTERISTICS DPBC10000499-1 5-1/3 - 5-3/3
3 ELECTRICAL CHARACTERISTICS DPBC10000499-1 6-1/1
4 BLOCK DIAGRAM DPBC10000499-1 7-1/1
5 INTERFACE PIN ASSIGNMENT DPBC10000499-1 8-1/5 - 8-5/5
6 INTERFACE TIMING DPBC10000499-1 9-1/5 - 9-5/5
7
8
9

10

DIMENSIONAL OUTLINE DPBC10000499-1 10-1/3 - 10-3/3

DESIGNATION OF LOT MARK

COSMETIC SPECIFICATIONS

PRECAUTION

DPBC10000499-1 11-1/1
DPBC10000499-1 12-1/3 - 12-3/3
DPBC10000499-1 13-1/3 - 13-3/3

Japan Display Inc. Date Jun. 05, 2013 DPBC10000499-1

Sh.

No.

Page

1-1/1

RECORD OF REVISION

The upper section : Before revision

Date Summary

The lower section : After revision

Sheet No. Page

Japan Display Inc. Date Jun. 05, 2013 DPBC10000499-1 Page

Sh.

No.

2-1/1

DESCRIPTION

Note : The LED for the backlight unit is integrated within this module.

Product Name : TX54D82MM0BAA

GENERAL SPECIFICATIONS

Effective Display Area : (H)422.4 × (V)337.92 (mm)

Number of Pixels : (H)2,560 × (V)2,048 (pixels)

Sensor

Area

: Top/Right of Landscape

Number of pixels (H)440 × (V)16

Aspect ratio : 5:4

Pixel Pitch : (H)0.165 × (V)0.165 (mm)

Pixel Arrangement : 3 subpixel per 1 pixel , Vertical Stripe

Display Mode : Transmissive Mode

Normally Black Mode

Frame frequency : 50 Hz

Top Polarizer Type : Anti-glare (Surface hardness: 2H)

Supported Grayscale : 10-bits per each subpixel

LCM Mode : IPS-NEO

(pixels)

Input Signal : 4-channel LVDS (LVDS = Low Voltage Differential Signaling)

Back Light : Edge Light Type with white LED

External Dimensions : (H)459.8 × (V)375.3 × (t)(43.0)

Weight : 4200g max (3950g typ.)

RoHS :Compliance

Japan Display Inc. Date Jun. 05, 2013 DPBC10000499-1 Page

Sh.

No.

3-1/1

1. ABSOLUTE MAXIMUM RATINGS

1.1 ENVIRONMENT ABSOLUTE MAXIMUM RATINGS

Item Unit Note

Panel surface Temperature 0 60

Operating Storage

Min. Max. Min. Max.

-20 60 °C 1)
Humidity 2) 2) %RH 1)
Vibration - 2.45 (0.25G) - 9.8 (1.0G)

Shock - 14.7 (1.5G) - 294 (30G)

Corrosive Gas Not Acceptable Not Acceptable -

TCON Surface Temperature - 85

LED Driver parts Temperature - 85

- 85 °C 6)

- 85 °C 7)

Notes

1) Temperature and Humidity should be applied to the panel surface of the TFT module and
not to the system installed with the module.

2) Ta ≤ 40°C : Relative humidity should be less than 85%RH max. Dew is prohibited.
Ta > 40°C : Relative humidity should be lower than the moisture of the 85%RH at 40°C .

3) Frequency of vibration is between 15Hz and 100Hz, except resonance point and z-direction
( panel face top and bottom ).

4) Pulse width of the shock wave pattern is 10ms approximately.

5) LCD module should be mounted with chassis by screwed all 8 positions, which 4 positions are
top and bottom side, other 4 positions are on right and left side.

6) FPGA-IC

7）MOSFET : MOSFET are placed at below on LED driver board.

m/s
m/s

2

2

3)

4)

MOSFET

MOSFET

I/F

LED driver

Japan Display Inc. Date Jun. 05, 2013 DPBC10000499-1 Page

Sh.

No.

4-1/2

1.2 ELECTRICAL ABSOLUTE MAXIMUM RATINGS

(1) TFT-LCD Module

Item Symbol Min. Max. Unit Note

V
V

V

V

V

DD

ID

ICM

ESD0

ESD1

Power Supply Voltage

Input Differential voltage swing

Input common mode voltage

Electrostatic Durability

Notes 1) It is applied to LVDS specifications.

Typ 1.25V

V

ICM

2) Discharge Coefficient: 200pF-250Ω, Environmental: 25°C-70%RH

3) It is applied to I/F connector pins.

4) It is applied to the surface of a metallic bezel and a LCD panel.

(2) Back Light Inverter

Item Symbol Min. Max. Unit Note

Input Voltage

V

IN

ON/OFF Control Input Voltage ON/OFF 0 6.0 V

PWM signal Voltage Vpwm 0 6.0 V

V

SS

-0.3 13.2 V
100 900 mV 1)
500 1800 mV 1)

±100 V 2),3)

±8 kV 2),4)

Positive Channel
Negative Channel

V

ID

Ground

Vss = 0 V

-0.3 30.0 V

= 0 V

Date PageJapan Display, Ltd. Jun. 05, 2013 DPBC10000499-1

Sh.

No.

4-2/2

2. INITIAL OPTICAL CHARACTERISTICS

0

m

3

The following initial optical characteristics are measured under stable conditions.
It takes about 30 minutes to reach stable conditions.
The measuring point is the center of display area unless otherwise noted.
The optical characteristics should be measured in a dark room or equivalent environment.
All initial optical characteristics items should be applied when panels have been shipped.

Measuring equipment : CS-2000 , CA-210, or EZ-contrast
Ambient Temperature =25°C, V

2.1 SPECIFICATION

=12.0V, VIN=24V , fV=50Hz

DD

Item Condition Unit Notes

Contrast ratio θ = 0° — 1), 2)

Contrast ratio CR88° φ = 0 , 90 , 180 , 27

Brightness Bwh θ = 0°

Brightness uniformity

Color x — 1)

chromaticity y

White

Buni 1023 75 — — %

Buni 511 70 — — %

θ = 0° Gray scale = 102

θ = 0° Gray scale = 511

θ = 0°

Variation of color point θ = ±80

by viewing angle (Gray scale = 1023)

Response time ton+toff — 25 — ms 3)

Rise ton

Fall toff

φ = 0, 90, 180, 270

Min. Typ. Max.

900 1200 —

50 — —

850 1200 —

0.264 0.324

0.279 0.339

0.294

0.309

— — 0.04

2

cd/

Δu'v' 5)

1)

6)

4)

Japan Display Inc. Date Jun. 05, 2013 DPBC10000499-1 Page

Sh.

No.

5-1/3

Notes

K

m

b

(

φ

φ

1) Definition of Viewing Angle ( gray scale = 1023 )

=90°

(12 o'clock)

φ=180°

(9 o'clock)

2) Definition of Contrast Ratio (CR)

CR=

X'

LCD Module

(Luminance at displaying WHITE)

(Luminance at displaying BLACK)

Y

θ=0

Z

Z'

θ

eye

Y'

=270°

(6 o'clock)

φ

φ=0°

X (3 o'clock)

3) Definition of Response Time

Displaying Data Signal BLAC

%
100

90

Optical Response
(Luminance)

10

0

Panel surface temperature = 45°C

4) Definition of Brightness Uniformity
Display pattern is white (511/1023 level). The brightness uniformity is defined by the following equation.
Brightness at each point is measured and then Buni can be calculated using the maximum and minimu

rightness values.

Buni=

where, Bmax = Maximum brightness measured.
Bmin = Minimum brightness measured.

Bmin

Bmax

)

×100

WHITE BLACK

ton

toff

Japan Display Inc. Date

Jun. 05, 2013 DPBC10000499-1 Page

Sh.

No.

5-2/3

90%

(1)

(2)

(3)

50%

10%

: measuring point

5) Variation of color position on CIE is defined as difference between colors for TFT-LCD module.

u'=

4x

-2x + 12y +3 -2x + 12y +3

(4)

(7)

10%

v'=

9y

(5)

(8)

50%

(6)

(9)

90%

6) PWM dimming signal Voltage should be 3.0V.

Japan Display Inc. Date Jun. 05, 2013 DPBC10000499-1 Page

Sh.

No.

5-3/3

3. ELECTRICAL CHARACTERISTICS

R

K

t

3.1 TFT-LCD MODULE

Item Symbol Min. Typ. Max. Unit Note

Power Supply Voltage

Power Supply Current

Ripple Voltage of Power Supply

1) DC current at f

Notes

=50.0Hz, f

V

CL

V

I

V

=74MHz, VDD=12.0V and display pattern is a full White (1023).

DD

DD

DD

Ta=25°C, V

SS

=0V

11.4 12.0 12.6 V

- 1.3 1.5 A 1),2)

- - 0.15 V

DC Ampere Meter

TFT Module

V

DD

V

SS

2) A protection fuse is built into this module. Current capacity of the power supply for V

greater than 6A, so that the fuse can 'blow' if there is a problem with the power supply.

3.2 BACK LIGHT

Item Symbol

Min Typ Max

Value

Unit

Input Voltage Vin 21.6 24 26.4 V
Input Current Iin - 1.9 2.5 A
Input Power Pin - 54 W
ON/OFF Control ON 2.5 3.3 5.0 V
Input Voltage OFF 0 - 0.5 V
PWM dimming signal High
Input Voltage

ON/OFF

PWM

Low

2.5 3.3 5.0
0-0.9

PWM Duty -5­PWM Frequency PWMf 150 -

46

100

1000

Vdc

%

Hz 1)

Ta=25℃

Note

should be

DD

1) In oder to avoid interference image on screen such as beat noise,
please pay attention and keep PWM drive frequency away from the multiple
number of panel drive frequency.

Japan Display, Ltd. Jun. 05, 2013 DPBC10000499-1Date Page

Sh.

No.

6-1/1

4. BLOCK DIAGRAM

(1) TFT Module

LVDS
Timing
Picture
Control

DC power supply

Gate Driver

G2064

LVDS

Receiver

G1

G2

DC/DC

TFT-LCD

D1 D2 D7680

Drain Driver

Timing

Converter

G1

G2

Gate Driver

G2064

Tcon

(2) Back light unit

DC power supply

ON/OFF Control

Brightness Control

LED (Series)

Right side

LED (Series)

LED (Series)

Left side

LED driver

LED (Series)

Date PageJapan Display, Ltd. Jun. 05, 2013 DPBC10000499-1

Sh.

No.

7-1/1

5. INTERFACE PIN ASSIGNMENT

5.1 TFT-LCD MODULE

LEFT I/F connector (CN1) (CH1, 2) RIGHT I/F connector (CN2) (CH3, 4)

1
2
3

Power

Supply

4
5
6
7
8

9
10 ARX0n 10 CRX0n
11 ARX0p 11 CRX0p
12 ARX1n 12 CRX1n
13 ARX1p 13 CRX1p
14
15 ARX2n 15 CRX2n
16 ARX2p 16 CRX2p

CH1 CH3

17 ACLKn 17 CCLKn
18 ACLKp 18 CCLKp
19
20 ARX3n 20 CRX3n
21 ARX3p 21 CRX3p
22 ARX4n 22 CRX4n
23 ARX4p 23 CRX4p
24
25 BRX0n 25 DRX0n
26 BRX0p 26 DRX0p
27 BRX1n 27 DRX1n
28 BRX1p 28 DRX1p
29
30 BRX2n 30 DRX2n
31 BRX2p 31 DRX2p
32 BCLKn 32 DCLKn

CH2 CH4

33 BCLKp 33 DCLKp
34
35 BRX3n 35 DRX3n
36 BRX3p 36 DRX3p
37 BRX4n 37 DRX4n
38 BRX4p 38 DRX4p
39
40 TEST 40 TEST
41 TEST 41 TEST

Notes 1)

2)

All V
All V

pins should be grounded.

SS

pins should be connected to +12.0 V (typ.).

DD

3) TEST Pins are only for Japan Display use. (Must be kept open and do not connect any input.)

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

INPUT CONNECTOR : HIROSE
Plug FX15S-41S-0.5SH (PCB connector side)

FX15S-41P-C (cable side)

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

Power

Supply

1
2
3
4
5
6
7
8
9

14

19

24

29

34

39

Date PageJapan Display, Ltd. Jun. 05, 2013 DPBC10000499-1

Sh.

No.

8-1/5

5.2 BACK-LIGHT UNIT

CN3 : JST S14B-PH-SM4-TB (Inverter PCB Connector side)
(Matching connector : JST PHR-14 (Cable side))

Pin No. Symbol

1
2
3
4
5
6
7
8
9

10

V

IN

V

IN

V

IN

V

IN

V

IN

V

SS

V

SS

V

SS

V

SS

V

SS

Power Supply (typ. 24.0V)

GND (0V)

Description Note

11 NC Not Connecting
12 ON/OFF High : Lamp ON, Low : Lamp OFF
13 NC Not Connecting
14 PWM PWM Dimming signal

Notes

1) All VIN pins should be connected to +24.0V (Typ.).

2) All VSS pins should be grounded. The metal bezel is internally connected to GND.

3) High level : 2.5 ~ 5.0V, Low level : 0 ~ 0.5V

4) High level : 2.5 ~ 5.0V, Low level : 0 ~ 0.9V

1)

2)

3)

4)

Date PageJapan Display, Ltd. Jun. 05, 2013 DPBC10000499-1

Sh.

No.

8-2/5

5.3 BLOCK DIAGRAM OF INTERFACE

TFT-LCD Module SideGraphic Side

horizontal pixel

(1 - 1279)

A0-A9

B0-B9

C0-C9

DTMG

horizontal pixel

(2 - 1280)

A0-A9

B0-B9

C0-C9

DTMG

DCLK

Host
Graphics
Controller

1TxIN

ODD

2TxIN

EVEN

CH1

CH2

1Tx 0p
1Tx 0n

1Tx 1p

1Tx 1n

1Tx 2p
1Tx 2n

1Tx 4p
1Tx 4n

2Tx 0p
2Tx 0n

2Tx 1p
2Tx 1n

2Tx 2p
2Tx 2n

2Tx 4p
2Tx 4n

1TCLKp

1TCLKn

2TCLKp
2TCLKn

ARx 0p
ARx 0n

ARx 1p

ARx 1n

ARx 2p
ARx 2n

ARx 4p
ARx 4n

BRx 0p
BRx 0n

BRx 1p
BRx 1n

BRx 2p
BRx 2n

BRx 4p
BRx 4n

ACLKp

ACLKn

(BCLKp)
(BCLKn)

CH1

100Ω

100Ω

100Ω

100Ω

CH2

100Ω

100Ω

100Ω

100Ω

100Ω

horizontal pixel

ARxOUT

ODD

BRxOUT

EVEN

PLLPLL

(1 - 1279)

A0-A9

B0-B9

C0-C9

DTMG

horizontal pixel

(2 - 1280)

A0-A9

B0-B9

C0-C9

DTMG

DCLK

Converter

horizontal pixel

(1281 - 2559)

horizontal pixel

(1282 - 2560)

DCLK

Host
Graphics
Controller

3TxIN

ODD

4TxIN

EVEN

LVDS Transmitter 1

CH3

CH4

PLL

LVDS Transmitter 2

CCLKp/n

DCLKp/n

LVDS Receiver 1

CH3

CH4

LVDS Receiver 2

A 0 ~ A 9 : A SUB Pixel data
B 0 ~ B 9 : B SUB Pixel data
C 0 ~ C 9 : C SUB Pixel data
DTMG : Display timing signal
DCLK : Dot Clock (DCLK of CH2, 4 are not used.)

Notes 1) The host system must have the transmitter in-situ to drive the module.

2) LVDS cable impedance should be 100 ohms per twisted-pair line when used differentially.

CRxOUT

ODD

DRxOUT

EVEN

horizontal pixel

(1281 - 2559)

horizontal pixel

(1282 - 2560)

DCLKPLL

Converter

Date PageJapan Display, Ltd. Jun. 05, 2013 DPBC10000499-1

Sh.

No.

8-3/5

5.4 CORRESPONDENCE BETWEEN INPUT DATA AND DISPLAY IMAGE

Display data of adjacent pixel is latched during one cycle of DCLK.

(1,1)

pixel : A 0 ~ A 9 : A SUB Pixel data

B 0 ~ B 9 : B SUB Pixel data

ABC

1,1 3,1 5,1 … 1279,1 2,1 4,1 6,1 … 1280,1 1281,1 1283,1 1285,1 … 2559,1 1282,1 1284,1 1286,1 … 2560,1

1,2 3,2 5,2 … 1279,2 2,2 4,2 6,2 … 1280,2 1281,2 1283,2 1285,2 … 2559,2 1282,2 1284,2 1286,2 … 2560,2

1,3 3,3 5,3 … 1279,3 2,3 4,3 6,3 … 1280,3 1281,3 1283,3 1285,3 … 2559,3 1282,3 1284,3 1286,3 … 2560,3

1,4 3,4 5,4 … 1279,4 2,4 4,4 6,4 … 1280,4 1281,4 1283,4 1285,4 … 2559,4 1282,4 1284,4 1286,4 … 2560,4

:::::::::: ::::: :::::

:::::::::: ::::: :::::

:::::::::: ::::: :::::

:::::::::: ::::: :::::

:::::::::: ::::: :::::

:::::::::: ::::: :::::

:::::::::: ::::: :::::

:::::::::: ::::: :::::

1,2064 3,2064 5,2064 … 1279,2064 2,2064 4,2064 6,2064 … 1280,2064 1281,2064 1283,2064 1285,2064 … 2559,2064 1282,2064 1284,2064 1286,2064 … 2560,2064

C 0 ~ C 9 : C SUB Pixel data

CH1 (LEFT_ODD) CH2 (LEFT_EVEN) CH3 (RIGHT_ODD) CH4 (RIGHT_EVEN)

Date

Sh.

No.

PageJapan Display, Ltd. Jun. 05, 2013 DPBC10000499-1

8-4/5

5.5 RELATIONSHIP BETWEEN DISPLAY COLORS AND INPUT SIGNALS

Input A SUB Pixel Data B SUB Pixel Data C SUB Pixel Data

A9A8A7···A3A2A1A0B9B8B7···B3B2B1B0C9C8C7···C3C2C1C0

Color

Black 000000000000000000000000

A (1023) 111111110000000000000000

B (1023)

Basic C (1023) 000000000000000011111111

B(1023) C(1023)

Color

A(1023) C(1023)

A(1023) B(1023)

White 111111111111111111111111

Black 000000000000000000000000

A (1) 000000010000000000000000

A (2) 000000100000000000000000

A : ::::::::::::::::::::::::

A (1022) 111111100000000000000000

A (1023) 111111110000000000000000

Black 000000000000000000000000

B (1) 000000000000000100000000

B (2) 000000000000001000000000

B : ::::::::::::::::::::::::

B (1022)

B (1023)

Black 000000000000000000000000

C (1) 000000000000000000000001

C (2) 000000000000000000000010

C : ::::::::::::::::::::::::

C (1022) 000000000000000011111110

C (1023) 000000000000000011111111

MSBLSBMSBLSBMSBLSB

000000001111111100000000

000000001111111111111111

111111110000000011111111

111111111111111100000000

: ::::::::::::::::::::::::

: ::::::::::::::::::::::::

000000001111111000000000

000000001111111100000000

: ::::::::::::::::::::::::

Notes 1) Definition of gray scale :

Color (n) : Number in parenthesis indicates gray scale level. Larger n corresponds to a brighter level.

2) Data : 1 : High, 0 : Low

Date PageJapan Display, Ltd. Jun. 05, 2013 DPBC10000499-1

Sh.

No.

8-5/5

6. INTERFACE TIMING

K

6.1 LVDS RECEIVER TIMING CHARACTERISTICS

(Regulation with the Input Terminal of the Module)

t

RP0

t

RP1

t

RP2

t

RP3

t

RP4

t

RP5

t

RP6

+

t

sk

+

t

+

t

+

t

+

t

+

t

Vdiff=0V

sk

sk

sk

sk

sk

sk

1/t

t

RP0

t

RP1

t

RP2

t

RP3

t

RP4

t

RP5

t

RP6

Rx3

Rx2 Rx1 Rx0

CL

1/7

6/7

5/7

4/7

3/7

2/7

t

CLK

Vdiff=0V Vdiff=0V

(X=0,1,2,3,4)

Max.

71 74 76

t

CLK

-

t

sk

0

-

t

sk

t

CLK

-

t

sk

t

CLK

-

t

sk

t

CLK

-

t

sk

t

CLK

-

t

sk

t

CLK

-

t

sk

1/7

6/7

5/7

4/7

3/7

2/7

t

CLK

0

t

CLK

t

CLK

t

CLK

t

CLK

t

CLK

1/7

6/7

5/7

4/7

3/7

2/7

0

t

t
t
t
t
t

CLK

+

CLK

CLK

CLK

CLK

CLK

t

RinX Rx6

Rx5 Rx4

ACLKp

(CCLKp)

RinX=(RinXp)-(RinXn)

Item Symbol Min. Typ.

DCLK MHz

t

sk

Parameter
Data Skew Margin - -400 0 +400
Input Data Position0
Input Data Position1

RinX

(X=0,1,2,

3,4)

Input Data Position2
Input Data Position3
Input Data Position4
Input Data Position5
Input Data Position6

Unit Remarks

ps

ns

CH1(2)_CLKp

t

CKP

CH3(4)_CLKp

Item Symbol Min. Typ.

CLKp

Input CLK Position

t

CKP

Date PageJapan Display, Ltd. Jun. 05, 2013 DPBC10000499-1

Vdiff=0V

Vdiff=0V

Max.

-1 0 +1 DCLK

Sh.

No.

Unit Remarks

9-1/5

6.2 LVDS MAPPING

Input

ODD

1 pixel

Rxm(6) Rxm(5) Rxm(4) Rxm(3) Rxm(2) Rxm(1) Rxm(0)

A(C)Rx0p/n

A(C)Rx1p/n B7 B6 B5

A(C)Rx2p/n

A(C)Rx3p/n B3 B2 A3 A2

A(C)Rx4p/n B1 B0 A1 A0C1 C0

B4

A9 A8 A7 A6 A5 A4

C5 C4 B9 B8

-

--

C3 C2

DTMG

-

C9 C8 C7 C6

EVEN

B(D)Rx0p/n

B(D)Rx1p/n B7 B6 B5

B4

A9 A8 A7 A6 A5 A4

C5 C4 B9 B8

-

-

--

C3 C2

C9 C8 C7 C6

B(D)Rx2p/n

DTMG

B(D)Rx3p/n B3 B2 A3 A2

B(D)Rx4p/n B1 B0 A1 A0C1 C0

A(C)RCLKp/n

B(D)RCLKp/n

A0 ~ A9 : Pixel A Data (9;MSB, 0;LSB)
B0 ~ B9 : Pixel B Data (9;MSB, 0;LSB)
C0 ~ C9 : Pixel C Data (9;MSB, 0;LSB)
DTMG : Display timing signal
RCLK : Dot Clock

Date PageJapan Display, Ltd. Jun. 05, 2013 DPBC10000499-1

Sh.

No.

9-2/5

6.3 TIMING CHART

tV

DTMG

DTMG

DCLK

tVD

tVB

1st 1st

tH

tHD

tCYC

tCH tCL

DCLK

2.0V

0.8V

Video input (CH1) (n,1) ~ (n,1279) (n+1,1) ~ (n+1,1279)

Video input (CH2) (n,2) ~ (n,1280) (n+1,2) ~ (n+1,1280)

Video input (CH3) (n,1281) ~ (n,2559) (n+1,1281) ~ (n+1,2559)

Video input (CH4) (n,1282) ~ (n,2560) (n+1,1282) ~ (n+1,2560)

(n=1,2,3, ~ 2064)

Date PageJapan Display, Ltd. Jun. 05, 2013 DPBC10000499-1

Sh.

No.

9-3/5

6.4 INTERFACE TIMING SPECIFICATIONS

Item Symbol Min. Typ. Max. Unit Note

Frame

DCLK

Frequency
Frequency 1/tCYC 71 74 76 MHz 1)

Duty tCH/tCYC 45 50 55 %

f

V

49 50 51 Hz

Period (Hor) tH 698 712 1023 tCK

DTMG

Width Active (Hor) tHD 640 640 640 tCK

Period (Ver) tV 2072 2076 2303 tH

Width Active (Ver) tVD 2064 2064 2064 tH

DTMG Jitter

ΔtVB

-1 0 1 tH

Note

1) Since DCLK and inverter driving frequency are optimized, please be noted that DCLK should
be set within this spec. Otherwise, optical side effect may happen.

Date

Sh.

No.

PageJapan Display, Ltd. Jun. 05, 2013 DPBC10000499-1

9-4/5

6.5 TIMING BETWEEN INTERFACE SIGNALS AND POWER SUPPLY

12V

10V

Power Supply
VDD

1V

0V

TPR

TDR

10V

1V

TINTDF

Interface Signal

LVDS:

CH1~CH4

Back-light
Vin

Back-light
PWM Signal

Back-light
ON/OFF

0V

(Hi-z) 2)

0V

0V

21.6V

1ms min.

1ms min.

TBR

Valid

ON

Black

1ms min.

1F2F3F

Black Black

TBF

1ms min.

0V

Notes

1) Timing of the power supply voltage and input signals should be set using the following specifications.

0.5ms ≤ TPR ≤ 10ms
10ms ≤ TDR ≤ 50ms

-10ms ≤ TDF ≤ 50ms
TIN ≥ 1s

*Before the end of the Interface Signal, black image is shown for the

last 3 frames. Refer to above Interface Signal Timing.
TBR ≥ 500ms
TBF ≥ 100ms

2) LVDS signals must be Low or High-impedance (Hi-z) state when VDD is off.

Date PageJapan Display, Ltd. Jun. 05, 2013 DPBC10000499-1

Sh.

No.

9-5/5

7. DIMENSIONAL OUTLINE
(1)FRONT VIEW

Note 1)Dimension in parentheses are reference value.

2)Tolerance not specified is ±0.5mm

3)Maximum forfue for the screw in mounting module : 0.49n/m.

Japan Display Inc. Date Page 10-1/3

Jun. 05, 2013 DPBC10000499-1

Sh.
No.

(2)REAR VIEW

Scale:NTS
Unit:mm

Japan Display Inc. Date Page 10-2/3

Jun. 05, 2013 DPBC10000499-1

Sh.
No.

Japan Display Inc. Date Page 10-3/3

Jun. 05, 2013 DPBC10000499-1

Sh.
No.

8. DESIGNATION OF LOT MAR

K

8.1 LOT MARK

5 digits for production number

(00001 ~ 99999)

Optional mark 4)

Production location mark 5)

Week 3)

Month 2)

Year 1)

Notes

1) Year Mark 2) Month Mark Month Mark 3) Week (Day) Mark
2013 3 1 01 7 07 1 ~ 7 1
2014 4 2 02 8 08 8 ~ 14 2
2015 5 3 03 9 09 15 ~ 21 3
2016 6 4 04 10 10 22 ~ 28 4
2017 7 5 05 11 11 29 ~ 31 5

6 061212

4) for Japan Display internal use only. 5) Production management sign

T Made in Taiwan

8.2 Revision (REV.) control

Revision version is denoted by letter A through Z, except I and O, for Japan Display manufacturing
convenience.

Rev. Note

A —

8.3 Location of lot mark

The Lot mark is printed on a label which is attached to the rear bezel, as shown in 7. External Dimensional.
The style of character can be changed without prior notice.

TX54D82MM0BAA

Lot mark

REV.

3093T 00001

REV

MADE IN TAIWAN

∗ TX54D82MM0BAA 12093T 00001 ∗

0 1 00 0 G 1 T 100001

Japan Display, Ltd. Date Jun. 05, 2013 DPBC10000499-1 Page

Sh.

No.

11-1/1

9. COSMETIC SPECIFICATIONS

9.1 CONDITIONS FOR COSMETIC INSPECTION

(1) Viewing zone

Inspection view

a) The figure shows the correspondence

between eyes (of inspector) and
TFT-LCD module.

q < 45°
q < 5°

b) Inspection should be executed only from

front side and only A-zone.
Cosmetic of B-zone and C-zone are ignore.
(refer to 9.2 DEFINITION OF ZONE)

(2) Environmental

a) Temperature : 25°C
b) Ambient light : sufficient darker condition when operating inspection.

c) Back-light : when non-operating inspection, back-light should be off.

: when non-operating inspection

: when operating inspection

about
300mm

TFT-LCD module

: about 1000 lx and non-directive when non-operating inspection.

θ

θ

0

Light

9.2 DEFINITION OF ZONE

A-zone

B-zone

C-zone

•A-zone : Display area (pixel area).

•B-zone : Area between A-zone and C-zone.

•C-zone : Metal bezel area.
(Include I/F connector)

Sh.

No.

DPBC10000499-1 PageJapan Display, Ltd. Date Jun. 05, 2013

12-1/3

9.3 COSMETIC SPECIFICATIONS

When displaying conditions are not stable (ex. at turn on or off), the following
specifications are not applied.

Max. acceptable number

A-zone

01), 2)

12

12

0

0

0

15 pcs —

not allowed.

Operating

inspection

No.

Dot Sparkle 560 ≦

1

Defect mode

Item

1-dot

2-dot

3-dot pcs

4-dots
Density 2 pcs/φ20mm 6)

Black 2-dots 2

mode 3-dots 0 Units 3), 5)

Total (Without slightly bright dot)

2

Line defect 5% ND filter — —

3 Uneven brightness

Stain inclusion

4

Line shape

W: width (mm)

L: length (mm)

Stain inclusion

5

Dot shape

D: ave. dia. (mm)

Scratch on polarizer

6

Line shape

W: width (mm)

W < 0.1 pcs 7)

0.4 < D ≦ 0.6 4

W ≦ 0.02 L: Ignore Ignore
W ≦ 0.04

W ≦ 0.08

L: length (mm)

Scratch on polarizer

7

Dot shape

D: ave. dia. (mm)

W > 0.08 — 0

204≦S＜560

Total

1-dot 13 pcs 3), 4)

4-dots 0

Density 2 pcs/φ20mm 6)

Total 15 pcs

L < 1.0 4

L ≧ 1.0 0

D ≦ 0.22 Ignore

D ≦ 0.4 5 pcs 7)

D > 0.6 0

L ≦ 40 10

L > 40 0 pcs 8)

L ≦ 20 10

L > 20 0

D ≦ 0.2 Ignore
D ≦ 0.6 10 pcs 8)

D > 0.6 0

Unit Note

pcs

pcs

1), 2)

Japan Display, Ltd. Date Jun. 05, 2013 DPBC10000499-1 Page

Sh.

No.

12-2/3

Max. acceptable number

A-zone

Serious one is

non-

operating

inspection

No. Item Unit Note

Bubbles, peeling

8

in polarizer

D: ave. dia. (mm)

9

Wrinkles on polarizer

D ≦ 0.3 Ignore
D ≦ 0.5 10 pcs 8)
D ≦ 1.0 5

D > 1.0

not allowed.

Notes 1) Sparkle mode: Brightness of dot is defined in ABC grayscale level.

2)

Bright dot (A,B,C) : Brightness of dot ≧560 grayscale level.
Tiny Bright dot (A,B,C): Brightness of dot ≧204 grayscale level.

3)

Black mode: brightness of dot is less than 70% at white. (visible to eye)

4)

1 dot: defect dot is isolated, not attached to other defect dot.

5)

N dots: N defect dots are consecutive. (N means the number of defects dots)

6)

Density: number of defect dots inside 20mm φ.

7)

Those stains which can be wiped out easily are acceptable.

8)

Polarizer area inside of B-zone is not applied.

0

——

Japan Display, Ltd. Date Jun. 05, 2013 DPBC10000499-1 Page

Sh.

No.

12-3/3

10. PRECAUTION

Please pay close attention to the following precautions whilst using, handling and mounting the TFT module.

10.1 Precaution for handling and mounting

(1) Applying excessive force to any part of the module may result in partial deformation of the frame or
mould, which could result in permanent damage to the display.
(2) The module should be held gently and firmly using both hands. In order to avoid internal damage
never hold the module by just one hand. Also never drop or hit the module.
(3) The module should be installed using the mounting holes of the module.
(4) Uneven force such as twisted stress should not be applied directly to the module once it is mounted
within the cover case. The cover case must have sufficient strength such that any external forces are not
transmitted directly to the module.
(5) It is recommended that you maintain a gap between the display module and the rear chassis so as to avoid
any mechanical stress being passed to the module.

Cover case

(6) The edge of the cover case should be positioned with more than a 1mm overlap from the edge of
the module's upper frame.
(7) A transparent protective plate should be added to the front of the display in order to protect both the
polarizer and TFT cell. The transparent protective plate should have sufficient strength such that the
plate can not be deformed, due to external forces, and touch the module. Polarizer surface hardness is 2H.
(8) Materials containing acetic acid and chlorine should not be used for the cover case nor for other parts
which are positioned in close proximity to the module. This is because the Acetic acid will attack
the polarizer, whilst the chlorine will attack the electric circuits by way of electro-chemical reaction.
(9) The front polarizer on the TFT cell should be handled carefully, due to its softness, and must not be
touched, pushed or rubbed with glass, tweezers or anything harder than an HB pencil lead.
The surface of the polarizer should not be touched nor rubbed with bare hands, greasy or dusty clothes.
(10) If the surface of the polarizer becomes dirty it should be gently wiped using an absorbent cotton
(Traysee CC clean cloth), chamois or other soft material, slightly dampened with petroleum benzene.
IPA (isopropyl alcohol) is recommended to clean away the traces of adhesive which is used to attach
the front/rear polarizers to the TFT cell. Other cleaning chemicals such as acetone, toluene and alcohol
should not be used to clean adhesives because they cause chemical damage to the polarizer.
(11) Saliva or water drops should be immediately wiped off. Otherwise, the affected portion of the polarizer
may become deformed and its color may fade.
(12) The module should not be opened or modified, under any circumstances, as this may cause it to
malfunction.

B-zone

Fig.1 Cross sectional view of a monitor set

Effective display area

Edge of
cover case

TFT module

Polarizer

above precaution (5)

Japan Display, Ltd. Date Jun. 05, 2013 DPBC10000499-1 Page

Sh.

No.

13-1/3

(13) The metallic bezel of the module should not be handled with bare hand or dirty gloves. Otherwise,
the color of the metallic frame may become dirty during its storage. It is recommended to use clean
soft gloves and clean finger stalls whilst the module is handled during incoming inspection and
production assembly processes.
(14) Please pay attention to the packing and handling not to apply strong Z axis vibration. Because during
our vibration test, of course we didn't have any functional failure, but we observed very tiny bright dots
(within spec though) at Z axis direction.

10.2 Precaution to operation

(1) Spike noise could result in the mis-operation of this module. The level of spike noise should be as follows:

-200mV

≤

over- and under- shoot of VDD ≦ +200mV
VDD including over- and under- shoot should not exceed the absolute maximum ratings.
(2) Optical response times, luminance and chromaticity depend on the temperature of the TFT module.
(3) Sudden temperature changes may cause dew on and/or in the module. Dew can cause damage to the
polarizer and/or electrical contacting areas of the module. Dew causes fading of the image quality.
(4) Using screen saver is recommended that it avoids any potential of sticking image.
(5) This module has high frequency circuits. Sufficient suppression to electromagnetic interference should
be done by the system manufacturers. Grounding and shielding methods may be effective to minimize
such interference.
(6) Noise may be heard when the back-light is operated. If necessary, sufficient suppression should be
done by the system manufacturers.
(7) The module should not be connected or disconnected whilst the main system is operating.
(8) Connecting or disconnecting the I/F cables, whilst the power and data signals are present, could result in
permanent damage to the module. The I/F connectors should only be connected and disconnected after the
power supply and data signal have been turned off.
(9) The ambient temperature near the operated module should be satisfied with the absolute maximum ratings.

Unless it meets the specifications, sufficient cooling system should be adopted to system.

10.3 Electrostatic discharge control

(1) This module consists of a TFT cell and electronic circuits with CMOS-ICs, which are very susceptible to
electrostatic discharge. Persons who are handling the module should be grounded through adequate
methods such as a wrist band. I/F connector pins should not be touched directly with bare hands.
(2) The polarizer protective film should be removed slowly so as to avoid an excessive build-up of
electrostatic charge.

10.4 Precaution to strong light exposure

(1) The module should not be exposed to strong light. Otherwise, characteristics of the polarizer and
color filter, may be degraded.

10.5 Precaution to storage

When modules are stored, for long period's of time, the following precautions should be taken:
(1) Modules should be stored in a dark place. It is prohibited to apply direct sunlight or fluorescent light
during storage. Modules should be stored between 0 to 35°C at normal humidity (60%RH or less).
(2) The surface of the polarizer should not come into direct contact with other objects.
It is recommended that modules should be stored in the original Japan Display shipping box.

Japan Display, Ltd. Date Jun. 05, 2013 DPBC10000499-1 Page

Sh.

No.

13-2/3

10.6 Precaution to handling protection film

(1) The protective film for polarizers should be pealed off slowly and carefully by people who are
electrically grounded with adequate methods such as wrist bands. Also ionized air should be blown
over the module during the peeling process.
Dust on the polarizer should be blown off gently using an ionized nitrogen gun.
(2) The protective film should be peeled off carefully to avoid it rubbing on the polarizer. If the film rubs
together with the polarizer it is possible that a small amount of adhesive may remain on the polarizer.
(3) The module with protective film should be stored under the conditions explained in 9.5 (1). However ,
in case's where the storage time is excessive, some adhesive may remain on the polarizer even after
the protective film has been removed. In the case where a module is stored at higher temperatures
and/or higher humidity, adhesive may remain on the polarizer. Any remaining adhesive may cause
non-uniformity of the displayed image.

10.7 Safety

(1) Since both the TFT cell is made of glass, handling of any broken module's should be carried out with
the utmost care so as to avoid any injury. Hands which have come into direct contact with
liquid crystal material should be washed immediately and thoroughly.
(2) The module should not be taken apart during operation so that back-light drives by high voltage.

10.8 Use restrictions and limitations

(1) In no event shall Japan Display, Ltd. be liable for any incidental, indirect or consequential damages in
connection with the installation or use of this product, even if informed of the possibility there of
in advance. These limitations apply to all causes action in aggregate, including without limitation breach
of contract, breach of warranty, negligence, strict liability, misrepresentation and other torts.
(2) This product is not authorized for military applications or other applications which pose a significant
risk of personal injury.

Japan Display, Ltd. Date Jun. 05, 2013 DPBC10000499-1 Page

Sh.

No.

13-3/3