JDI TX76D02VM0BAA Specification

TECHNICAL DATA

仕様書パターン2 CAS表紙

Date : Mar. 26, 2013

Product Name

(NOTES)

1. This document may, wholly or partially, be subject to change without notice.

2. All rights are reserved ; No one is permitted to reproduce, duplicate or distribute in any form,

the whole or part of this document without Japan Display's prior written consent.

3. No one is permitted to explain nor disclose the contents of this document to third parties without

Japan Display's prior written consent.

4. Japan Display will not be held responsible for any damage to the user that may result from accidents

or any other reasons during operation of the user's unit according to this document, any previous

reports or oral discussions.

5. Circuitry and other examples described herein are meant merely to indicate the characteristics and

performance of Japan Display's products.

Japan Display assumes no responsibility for any intellectual property claims or other problems that

may result from applications based on the examples described herein.

6. No license is granted by implication or otherwise under any patents or other rights of any third

party or Japan Display Inc.

7. LIFE SUPPORT APPLICATIONS

use in LIFE SUPPORT SYSTEMS.

: The product covered by this document is not authorized for

TX76D02VM0BAA

CONTENTS

No. Item Sheet No. Page

CONTENTS DPBC10000482 - 1 1-1/1

－

RECORD OF REVISIONS DPBC10000482 - 1 2-1/1

－

DESCRIPTION DPBC10000482 - 1 3-1/1

－

ABSOLUTE MAXIMUM RATINGS DPBC10000482 - 1
INITIAL OPTICAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS DPBC10000482 - 1
BLOCK DIAGRAM DPBC10000482 - 1 7-1/1
INTERFACE PIN ASSIGNMENT DPBC10000482 - 1 8-1/5 - 8-5/5
INTERFACE TIMING DPBC10000482 - 1
DIMENSIONAL OUTLINE DPBC10000482 - 1

DPBC10000482 - 1

4-1/2 - 4-2/2
5-1/3 - 5-3/3

6-1/1

9-1/5 - 9-5/5

10-1/2 - 10-2/2

Japan Display Inc.

Date Mar. 26, 2013

Sh.

No.

DPBC10000482 - 1

Page 1-1/1

RECORD OF REVISIONS

Date Sheet No. Summary

Japan Display Inc.

Date Page

Sh.

No.

DPBC10000482 - 1

2-1/1Mar. 26, 2013

Note : The LED for the backlight unit is integrated within this module.

Product Name : TX76D02VM0BAA

Effective Display Area : (H)641.28 × (V)404.808 (mm)

Number of Pixels : (H)2,560 × (V)1,616 (pixels)

Aspect ratio : 16 : 10.1

Pixel Pitch : (H)0.2505 × (V)0.2505 (mm)

Color Pixel Arrangement : R+G+B Vertical Stripe

Display Mode : Transmissive Mode

Normally Black Mode

Frame frequency : 60 Hz

Top Polarizer Type : Anti-glare (Surface hardness: 2H)

Number of Colors :1,073,741,824 colors ( 10bit )

LCM Mode : IPS-Pro (New Process)

Input Signal : 4-channel LVDS (LVDS = Low Voltage Differential Signaling)

Back Light : Edge Light Type with white LED

External Dimensions : (H)687.3 × (V)454.4 × (t)37.5 (mm)

Weight : 7100g typ

RoHS : Compliance

Japan Display Inc.

Date Mar. 26, 2013 Page

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No.

DPBC10000482 - 1

3-1/1

1. ABSOLUTE MAXIMUM RATINGS

1.1 ENVIRONMENT ABSOLUTE MAXIMUM RATINGS

Item Unit Note

Panel surface Temperature 0 50

Operating Storage

Min. Max. Min. Max.

-20 60 °C 1)
Humidity 2) 2) %RH 1)
Vibration - 2.45 (0.25G) - 9.8 (1.0G)

Shock - 14.7 (1.5G) - 294 (30G)

m/s
m/s

2

2

Corrosive Gas Not Acceptable Not Acceptable -
Illumination at LCD Surface - 50,000 - 50,000 lx
TCON Surface Temperature - 85

LED Driver Parts Temperature

-85

Rear frame Temperature -

65 - 65

-85°C 6)

-

85

°C
°C

Notes

1) Temperature and Humidity should be applied to the panel surface of the TFT module and
not to the system installed with the module.

2) Ta ≤ 40°C : Relative humidity should be less than 85%RH max. Dew is prohibited.
Ta > 40°C : Relative humidity should be lower than the moisture of the 85%RH at 40°C .

Relative humidity ( %RH )

100

80

Opera

60

ting

40

range

20

Storage range

3), 5)

4), 5)

7）
8）

20 40 60 80-20-40 0

Environment Temperature ( °C )

3) Frequency of vibration is between 15Hz and 100Hz, except resonance point and z-direction
( panel face top and bottom ).

4) Pulse width of the shock wave pattern is 10ms approximately.

5) The LCD module should be mounted and fixed to a monitor chassis by all 16 screws whose holes

are located two each at top, bottom, right and left side, and remaining 8 pcs at rear side of the module.

6) FPGA-IC

7）MOSFET

8) See below picture.

LED position

LED position

Japan Display Inc.

Date Mar. 26, 2013 Page

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No.

DPBC10000482 - 1

4-1/2

1.2 ELECTRICAL ABSOLUTE MAXIMUM RATINGS

(1) TFT-LCD Module

Vss = 0 V

Item Symbol Min. Max. Unit Note

Power Supply Voltage V

Input Differential voltage swing V

Input common mode voltage V

Electrostatic Durability

V
V

DD

ID

ICM

ESD0

ESD1

- 13.2 V
100 900 mV 1)
500 1800 mV 1)

±100 V 2),3)

±8 kV 2),4)

Notes 1) It is applied to LVDS specifications.

Positive Channel

Typ 1.25V

VICM VID

Negative Channel
Ground

2) Discharge Coefficient: 200pF-250Ω, Environmental: 25°C-70%RH

3) It is applied to I/F connector pins.

4) It is applied to the surface of a metallic bezel and a LCD panel.

(2) LED driver
Vss = 0 V

Item Symbol Min. Max. Unit Note

Input Voltage Vin - 30.0 V

ON/OFF Control Input Voltage ON/OFF 0 6.0 V

PWM dimming signal Voltage PWM 6.0

0V

Japan Display Inc.

Date Mar. 26, 2013 Page

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No.

DPBC10000482 - 1

4-2/2

2. INITIAL OPTICAL CHARACTERISTICS

The following optical characteristics are measured under stable conditions. It takes about 30 minutes
to reach stable conditions. The measuring point is the center of display area unless otherwise noted.
The optical characteristics should be measured in a dark room or equivalent environment.
All initial optical characteristic items should be applied when panels have been shipped.

Measuring equipment : CS-1000A or CA-210, EZ-contrast
Ambient Temperature =25±3°C, VDD=12.0V, fV=60Hz, Vin=24V

2.1 SPECIFICATION

Items Condition

Contrast ratio (900) (1100) - -

Contrast ratio at ±85° (50) - - ° 1)

Brightness (550) (650) -

Brightness
uniformity

Color

chromaticity

Variation of color point

by viewing angle (Gray scale = 1023)

Gray scale = 1023
Gray scale = 511 θ = 0

Red

Green

Blue

White

x (0.615) (0.645) (0.675)
y (0.297) (0.327)
x (0.278) (0.308) (0.338)
y (0.590) (0.620) (0.650)
x (0.116) (0.146) (0.176)
y (0.033) (0.063) (0.093)
x (0.269) (0.299) (0.329)
y (0.285) (0.315) (0.345)

Tr

Response time

Tf θ = 0

Total

γ - (2.2) -

θ = 0

φ = 0, 90, 180, 270

θ = 0

θ = 0

θ = ±80

φ = 0, 90, 180, 270

θ = 0

Min. Typ. Max. Unit Notes

1), 2)

(70) - ­(65) - -

cd/m

%

2

6)

4)

1)

(0.357)

ΔCIE

- - (0.04)

Δu'v'

5)

- (10) (20) 3)

- (10) (20)

ms

- (20) (40)

-

Japan Display Inc.

Date Mar. 26, 2013 Page

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No.

DPBC10000482 - 1

5-1/3

Notes

(

φ

r

1) Definition of Viewing Angle ( gray scale = 1023 )

=90°

(12 o'clock)

φ=180

(9 o'clock)

2) Definition of Contrast Ratio (CR)

CR=

X'

TFT Module

(Luminance whilst displaying WHITE)

(Luminance whilst displaying BLACK)

Y

θ=0

Z

Z'

θ

eye

Y'

φ=270

(6 o'clock)

φ

φ=0°

X (3 o'clock)

3) Definition of Response Time

Displaying Data Signal BLACK

%
100

90
Optical Response
(Luminance)

10

0

Panel surface temperature = 45°C

4) Definition of Brightness Uniformity
Display pattern is white (511/1023 level). The brightness uniformity is defined by the following equation.
Brightness at each point is measured and then Buni can be calculated using the maximum and minimum
brightness values.

Buni=

where, Bmax = Maximum brightness measured.
Bmin = Minimum brightness measured.

Bmin

Bmax

)

×100

WHITE BLACK

T

Tf

Japan Display Inc.

Date Mar. 26, 2013

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No.

DPBC10000482 - 1

Page 5-2/3

9/10V

(1)

(2)

(3)

(4)

(7)

1/10V

: measuring point

5) Variation of color position on CIE is defined as difference between colors for TFT-LCD module.

u'=

6) PWM dimming signal should be 100％.

4x

-2x + 12y +3 -2x + 12y +3

1/10H

v'=

9y

(5)

(8)

(6)

(9)

9/10H

Japan Display Inc.

Date Mar. 26, 2013 Page

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No.

DPBC10000482 - 1

5-3/3

3. ELECTRICAL CHARACTERISTICS

y

3.1 TFT-LCD MODULE

Ta=25°C, Vss=0V

Item Symbol Min. Typ. Max. Unit Note
Power Supply Voltage V
Power Supply Current I

Ripple Voltage of Power Supply V

Notes 1) DC current at fv=60.0Hz, fCLK=67.5MHz, VDD=12.0V and display pattern is a full White (1023).

DD

DD

DDR

11.4 12.0 12.6 V

- 1.4 1.8 A 1),2)

- - 0.15 V

DC Ampere Meter

TFT Module

DD

V

VSS

2) A protection fuse is built into this module. Current capacity of the power supply for VDD should be
greater than 6A, so that the fuse can 'blow' if there is a problem with the power supply.

3.2 BACK LIGHT

Ta=25°C

Item Symbol

Min Typ Max

Value

Unit

Note

Input Voltage Vin 21.6 24 26.4 V
Input Current Iin - 3.8 4.2 A
Input Power Pin W
ON/OFF Control ON 2.5 5.0 V
Input Voltage OFF 0 - 0.5 V
PWM dimming signal
Input Voltage

PWM　Duty
　PWM　Frequenc

ON/OFF

PWN

-

PWMｆ

High

LOW

- 91.2 111

3.3

2.5 3.3 5.0 Vdc
0-

10

(140)

-

(150)

0.9 Vdc

100

(160)

％

Hz

1）

1) specifications should be applied at 140Hz～160Hz.

Japan Display Inc.

Date Mar. 26, 2013 Page

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No.

DPBC10000482 - 1

6-1/1

4. BLOCK DIAGRAM

(1) TFT Module

LVDS
Timing
Picture
Control

LVDS

Receiver

Timing

Converter

Tcon

DC power supply

(2) Back light unit

G1
G2

Gate Driver

G1616

DC/DC

Drain Driver

D1 D2 D2560

G1
G2

TFT-LCD

Gate Driver

G1616

LED (Series)

Right side

DC power supply

ON/OFF Control

Brightness Control

Japan Display Inc.

LED (Series)

LED (Series)

LED (Series)

Left side

LED (Series)

LED driver

LED (Series)

Date Mar. 26, 2013 Page

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5. INTERFACE PIN ASSIGNMENT

5.1 TFT-LCD MODULE

LEFT I/F connector (CN1) (CH1, 2) RIGHT I/F connector (CN2) (CH3, 4)

1VDD 1VDD
2VDD 2VDD
3VDD 3VDD

Power

Supply

CH1 CH3

CH2 CH4

Notes 1) All VSS pins should be grounded.

2) All VDD pins should be connected to +12.0 V (typ.).

3) TEST Pins are only for Hitachi use.

4VDD 4VDD
5VDD 5VDD
6VSS 6VSS
7VSS 7VSS
8VSS 8VSS

9VSS 9VSS
10 ARX0n 10 CRX0n
11 ARX0p 11 CRX0p
12 ARX1n 12 CRX1n
13 ARX1p 13 CRX1p
14 VSS 14 VSS
15 ARX2n 15 CRX2n
16 ARX2p 16 CRX2p
17 ACLKn 17 CCLKn
18 ACLKp 18 CCLKp
19 VSS 19 VSS
20 ARX3n 20 CRX3n
21 ARX3p 21 CRX3p
22 ARX4n 22 CRX4n
23 ARX4p 23 CRX4p
24 VSS 24 VSS
25 BRX0n 25 DRX0n
26 BRX0p 26 DRX0p
27 BRX1n 27 DRX1n
28 BRX1p 28 DRX1p
29 VSS 29 VSS
30 BRX2n 30 DRX2n
31 BRX2p 31 DRX2p
32 BCLKn 32 DCLKn
33 BCLKp 33 DCLKp
34 VSS 34 VSS
35 BRX3n 35 DRX3n
36 BRX3p 36 DRX3p
37 BRX4n 37 DRX4n
38 BRX4p 38 DRX4p
39 VSS 39 VSS
40 TEST 40 TEST
41 TEST 41 TEST

INPUT CONNECTOR : HIROSE
Plug FX15S-41S-0.5SH (PCB connector side)

FX15S-41P-C (cable side)

Power

Supply

Japan Display Inc.

Date Mar. 26, 2013 Page

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DPBC10000482 - 1

8-1/5

5.2 BACK-LIGHT UNIT

CN3 : JST S14B-PH-SM4-TB (Inverter PCB Connector side)
(Matching connector : JST PHR-14 (Cable side))

Pin No. Symbol

1VIN
2VIN
3 VIN Power Supply (typ. 24.0V)
4VIN
5VIN
6VSS
7VSS
8 VSS GND (0V)
9VSS

10 VSS
11 NC Not　Connecting
12 ON/OFF High : Lamp ON, Low : Lamp OFF
13 NC Not　Connecting
14 PWM PWM　dimming　signal

Notes

1) All VIN pins should be connected to +24.0V (Typ.).

2) All VSS pins should be grounded. The metal bezel is internally connected to GND.

3) High level : 2.5 ~ 5.0V, Low level : 0 ~ 0.5V

4) High level : 2.5 ~ 5.0V, Low level : 0 ~ 0.9V

Description Note

1)

2)

3)

4)

Japan Display Inc.

Date Mar. 26, 2013 Page

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No.

DPBC10000482 - 1

8-2/5

5.3 BLOCK DIAGRAM OF INTERFACE

TFT-LCD Module SideGraphic Side

horizontal pixel

(1 - 1279)

R0-R9

G0-G9

B0-B9

DTMG

horizontal pixel

(2 - 1280)

R0-R9

G0-G9

B0-B9

DTMG

DCLK

Host
Graphics
Controller

1TxIN

ODD

2TxIN

EVEN

CH1

CH2

1Tx 0p
1Tx 0n

1Tx 1p

1Tx 1n

1Tx 2p
1Tx 2n

1Tx 4p
1Tx 4n

2Tx 0p
2Tx 0n

2Tx 1p
2Tx 1n

2Tx 2p
2Tx 2n

2Tx 4p
2Tx 4n

1TCLKp

1TCLKn

2TCLKp
2TCLKn

ARx 0p
ARx 0n

ARx 1p

ARx 1n

ARx 2p
ARx 2n

ARx 4p
ARx 4n

BRx 0p
BRx 0n

BRx 1p
BRx 1n

BRx 2p
BRx 2n

BRx 4p
BRx 4n

ACLKp

ACLKn

(BCLKp)
(BCLKn)

CH1

100Ω

100Ω

100Ω

100Ω

CH2

100Ω

100Ω

100Ω

100Ω

100Ω

horizontal pixel

ARxOUT

ODD

BRxOUT

EVEN

PLLPLL

(1 - 1279)

R0-R9

G0-G9

B0-B9

DTMG

horizontal pixel

(2 - 1280)

R0-R9

G0-G9

B0-B9

DTMG

DCLK

Converter

horizontal pixel

(1281 - 2549)

horizontal pixel

(1282 - 2560)

DCLK

Host
Graphics
Controller

3TxIN

ODD

4TxIN

EVEN

LVDS Transmitter 1

CH3

CH4

PLL

LVDS Transmitter 2

CCLKp/n

DCLKp/n

LVDS Receiver 1

CH3

CH4

LVDS Receiver 2

R0 ~ R9 : Pixel R Data
G0 ~ G9 : Pixel G Data
B0 ~ B9 : Pixel B Data
DTMG : Display timing signal
DCLK : Dot Clock (DCLK of CH2, 4 are not used.)

Notes 1) The host system must have the transmitter in-situ to drive the module.

2) LVDS cable impedance should be 100 ohms per twisted-pair line when used differentially.

CRxOUT

ODD

DRxOUT

EVEN

horizontal pixel

(1281 - 2549)

horizontal pixel

(1282 - 2560)

DCLKPLL

Converter

Japan Display Inc.

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DPBC10000482 - 1

8-3/5

5.4 CORRESPONDENCE BETWEEN INPUT DATA AND DISPLAY IMAGE

Display data of adjacent pixel is latched during one cycle of DCLK.

(1,1)

pixel : R0 ~ R9 : R data

G0 ~ G9 : G data

RGB

1,1 3,1 5,1 … 1279,1 2,1 4,1 6,1 … 1280,1 1281,1 1283,1 1285,1 … 2549,1 1282,1 1284,1 1286,1 … 2560,1

1,2 3,2 5,2 … 1279,2 2,2 4,2 6,2 … 1280,2 1281,2 1283,2 1285,2 … 2549,2 1282,2 1284,2 1286,2 … 2560,2

1,3 3,3 5,3 … 1279,3 2,3 4,3 6,3 … 1280,3 1281,3 1283,3 1285,3 … 2549,3 1282,3 1284,3 1286,3 … 2560,3

1,4 3,4 5,4 … 1279,4 2,4 4,4 6,4 … 1280,4 1281,4 1283,4 1285,4 … 2549,4 1282,4 1284,4 1286,4 … 2560,4

:::::::::: ::::: :::::

:::::::::: ::::: :::::

:::::::::: ::::: :::::

:::::::::: ::::: :::::

:::::::::: ::::: :::::

:::::::::: ::::: :::::

:::::::::: ::::: :::::

:::::::::: ::::: :::::

1,1616 3,1616 5,1616 … 1279,1616 2,1616 4,1616 6,1616 … 1280,1616 1281,1616 1283,1616 1285,1616 … 2549,1616 1282,1616 1284,1616 1286,1616 … 2560,1616

B0 ~ B9 : B data

CH1 (LEFT_ODD) CH2 (LEFT_EVEN) CH3 (RIGHT_ODD) CH4 (RIGHT_EVEN)

Japan Display Inc.

Date Mar. 26, 2013

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Page 8-4/5

5.5 RELATIONSHIP BETWEEN DISPLAY COLORS AND INPUT SIGNALS

Input Red Data Green Data Blue Data

R9 R8 R7 ··· R3 R2 R1 R0 G9 G 8 G7 ··· G3 G2 G1 G0 B9 B8 B7 ··· B3 B2 B1 B0

Color

Black 000000000000000000000000

Red (1023) 111111110000000000000000

Green (1023)

Basic Blue (1023) 000000000000000011111111

Color Cyan 000000001111111111111111

Magenta 111111110000000011111111

Yellow 111111111111111100000000

White 111111111111111111111111

Black 000000000000000000000000

Red (1) 000000010000000000000000

Red (2) 000000100000000000000000

Red : ::::::::::::::::::::::::

Red (1022) 111111100000000000000000

Red (1023) 111111110000000000000000

Black 000000000000000000000000

Green (1)000000000000000100000000

Green (2)000000000000001000000000

Green : ::::::::::::::::::::::::

Green (1022)

Green (1023)

Black 000000000000000000000000

Blue (1) 000000000000000000000001

Blue (2) 000000000000000000000010

Blue : ::::::::::::::::::::::::

Blue (1022) 000000000000000011111110

Blue (1023) 000000000000000011111111

MSBLSBMSBLSBMSBLSB

000000001111111100000000

: ::::::::::::::::::::::::

: ::::::::::::::::::::::::

000000001111111000000000

000000001111111100000000

: ::::::::::::::::::::::::

Notes 1) Definition of gray scale :

Color (n) : Number in parenthesis indicates gray scale level. Larger n corresponds to a brighter level.

2) Data : 1 : High, 0 : Low

Japan Display Inc.

Date Mar. 26, 2013 Page

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DPBC10000482 - 1

8-5/5

6. INTERFACE TIMING

K

tsk

+tsk

k

+tsk

tsk

+tsk

tsk

+tsk

tsk

+tsk

tsk

+tsk

tsk

+tsk

6.1 LVDS RECEIVER TIMING CHARACTERISTICS

(Regulation with the Input Terminal of the Module)

t

RP0

t

RP1

t

RP2

t

RP3

t

RP4

t

RP5

t

RP6

RinX Rx6

ACLKp

(CCLKp)

Item Symbol Min. Typ. Max.

DCLK

t

sk

Parameter
Data Skew Margin - -450 0 +450
Input Data Position0
Input Data Position1

RinX

(X=0,1,2,

3,4)

Input Data Position2
Input Data Position3
Input Data Position4
Input Data Position5
Input Data Position6

Rx5 Rx4

Rx3

Rx2 Rx1 Rx0

RinX=(RinXp)-(RinXn)

1/t

CL

1

t
t
t
t
t
t
t

RP0

RP1

RP2

RP3

RP4

RP5

RP6

7

6
7

5
7

4
7

3
7

2
7

Vdiff=0V

t

CLK

Vdiff=0V Vdiff=0V

(X=0,1,2,3,4)

Unit Remarks

66.5 67.5 68.5

t

CLK

t

CLK

t

CLK

t

CLK

t

CLK

t

CLK

-

-ts

0

-

-

-

-

-

1

t

7

CLK

1

t

7

0

6

t

7

CLK

5

t

7

CLK

4

t

7

CLK

3

t

7

CLK

2

t

7

CLK

6

t

7

5

t

7

4

t

7

3

t

7

2

t

7

CLK

0

CLK

CLK

CLK

CLK

CLK

MHz

ps

ns

CH1(2)_CLKp

t

CKP

CH3(4)_CLKp

Item Symbol Min. Typ. Max.

CLKp

Japan Display Inc.

Input CLK Position

Date Mar. 26, 2013 Page

t

CKP

Sh.

No.

Vdiff=0V

Vdiff=0V

-1 0 +1 DCLK

DPBC10000482 - 1

Unit Remarks

9-1/5

6.2 LVDS MAPPING

Input

ODD

1 pixel

Rxm(6) Rxm(5) Rxm(4) Rxm(3) Rxm(2) Rxm(1) Rxm(0)

A(C)Rx0p/n

A(C)Rx1p/n G7 G6 G5

A(C)Rx2p/n

DTMG

A(C)Rx3p/n G3 G2 R3 R2

A(C)Rx4p/n G1 G0 R1 R0B1 B0

R9 R8 R7 R6 R5 R4

G4

B5 B4 G9 G8

(Vsync) (Hsync)

-

B3 B2

B9 B8 B7 B6

-

EVEN

B(D)Rx0p/n

B(D)Rx1p/n G7 G6 G5

R9 R8 R7 R6 R5 R4

G4

B5 B4 G9 G8

(Vsync) (Hsync)

B(D)Rx2p/n

B(D)Rx3p/n G3 G2 R3 R2

B(D)Rx4p/n G1 G0 R1 R0B1 B0

DTMG

-

-

B9 B8 B7 B6

B3 B2

A(C)RCLKp/n

B(D)RCLKp/n

R0 ~ R9 : Pixel R Data (9;MSB, 0;LSB)
G0 ~ G9 : Pixel G Data (9;MSB, 0;LSB)
B0 ~ B9 : Pixel B Data (9;MSB, 0;LSB)
DTMG : Display timing signal
RCLK : Dot Clock

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DPBC10000482 - 1

9-2/5

6.3 TIMING CHART

tV

DTMG

DTMG

DCLK

tVD

tVB

1st 1st

tH

tHD

tCYC

tCH tCL

DCLK

2.0V

0.8V

(n,1) ~ (n,1279) (n+1,1) ~ (n+1,1279)

(n,2) ~ (n,1280) (n+1,2) ~ (n+1,1280)

(n,1025) ~ (n,2559) (n+1,1025) ~ (n+1,2559)

(n,1026) ~ (n,2560) (n+1,1026) ~ (n+1,2560)

(n=1,2,3, ~ 1615)

Japan Display Inc.

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9-3/5

6.4 INTERFACE TIMING SPECIFICATIONS

Item Symbol Min. Typ. Max. Unit Note

DCLK

DTMG

Note

1) Since DCLK and inverter driving frequency are optimized, please be noted that DCLK should
be set within this spec. Otherwise, optical side effect may happen.

Frequency 1/tCYC 66.5 67.5 68.5 MHz 1)

Duty tCH/tCYC 45 50 55 %

Period (Hor) tH 664 690 840 tCK

Width Active (Hor) tHD 640 640 640 tCK

Period (Ver) tV 1620 1630 1730 tH

Width Active (Ver) tVD 1616 1616 1616 tH

DTMG Jitter

ΔtVB

-1 0 1 tH

Japan Display Inc.

Date Mar. 26, 2013

Sh.

No.

DPBC10000482 - 1

Page 9-4/5

6.5 TIMING BETWEEN INTERFACE SIGNALS AND POWER SUPPLY

12V

10V

Power Supply
VDD

1V

0V

TPR

TDR

10V

1V

TINTDF

Interface Signal

LVDS:

CH1~CH4

Back-light
Vin

Back-light
PWM Signal

0V

(Hi-z) 2)

0V

0V

TBR

(21.6V)

(1ms min)

(1ms min)

(20ms min)

Valid

ON

(1ms min)

Black

Black Black

TBF

(20.6V)

(10ms min)

(1ms min)

1F2F3F

Back-light
ON/OFF

0V

Notes

1) Timing of the power supply voltage and input signals should be set using the following specifications.

0.5ms ≤ TPR ≤ 10ms
10ms ≤ TDR ≤ 50ms

-10ms ≤ TDF ≤ 50ms
TIN ≥ 1s

*Before the end of the Interface Signal, black image is shown for the

last 3 frames. Refer to above Interface Signal Timing.
TBR ≥ 500ms
TBF ≥ 100ms

2) LVDS signals must be Low or High-impedance (Hi-z) state when VDD is off.

Japan Display Inc.

Date Mar. 26, 2013 Page

Sh.

No.

DPBC10000482 - 1

9-5/5

7. DIMENSIONAL OUTLINE

(1) Front View

Note 1）The dimension in a parenthesis is reference value.

2）Unspecified tolerance to be±1.0mm.

3) Maxmum torque for M4 screw : 1.2N･m.

Japan Display Inc.

Date

Mar. 26, 2013

Sh.

No.

DPBC10000482 - 1

Unit ：mm
Scale：NTS

Page 10-1/2

(2) Rear Vie

w

Note 1）The dimension in a parenthesis is reference value.

2）Unspecified tolerance to be±1.0mm.

3) Maxmum torque for M4 screw : 1.2N･m.

Unit ：mm
Scale：NTS

Japan Display Inc.

Date

Mar. 26, 2013

Sh.

No.

DPBC10000482 - 1

Page 10-2/2