IS63LV1024 |
ISSI® |
128K x 8 HIGH-SPEED CMOS STATIC RAM
3.3V REVOLUTIONARY PINOUT
SEPTEMBER 2000
FEATURES
•High-speed access times: 8, 10, 12 and 15 ns
•High-performance, low-power CMOS process
•Multiple center power and ground pins for greater noise immunity
•Easy memory expansion with CE and OE options
•CE power-down
•Fully static operation: no clock or refresh required
•TTL compatible inputs and outputs
•Single 3.3V power supply
•Packages available:
–32-pin 300-mil SOJ
–32-pin 400-mil SOJ
–32-pin TSOP (Type II)
DESCRIPTION
The ISSI IS63LV1024 is a very high-speed, low power, 131,072-word by 8-bit CMOS static RAM in revolutionary pinout. The IS63LV1024 is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices.
When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down to 250 µW (typical) with CMOS input levels.
The IS63LV1024 operates from a single 3.3V power supply and all inputs are TTL-compatible.
FUNCTIONAL BLOCK DIAGRAM
A0-A16 |
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128K X 8 |
DECODER |
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MEMORY ARRAY |
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VCC
GND
I/O
I/O0-I/O7 DATA COLUMN I/O
CIRCUIT
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CE |
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CONTROL |
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OE |
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CIRCUIT |
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WE |
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ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774 |
1 |
Rev. H
10/02/00
IS63LV1024 |
ISSI® |
PIN CONFIGURATION
32-Pin SOJ
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32 |
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A16 |
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A0 |
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1 |
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A1 |
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31 |
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A15 |
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2 |
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A2 |
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30 |
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A14 |
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3 |
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A3 |
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29 |
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A13 |
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4 |
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28 |
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CE |
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5 |
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OE |
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I/O0 |
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27 |
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I/O7 |
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6 |
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I/O1 |
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26 |
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I/O6 |
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7 |
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Vcc |
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8 |
25 |
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GND |
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GND |
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24 |
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Vcc |
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9 |
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I/O2 |
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23 |
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I/O5 |
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10 |
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I/O3 |
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I/O4 |
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11 |
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21 |
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A12 |
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WE |
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12 |
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A4 |
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20 |
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A11 |
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13 |
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A5 |
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19 |
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A10 |
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14 |
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A6 |
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18 |
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A9 |
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A7 |
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16 |
17 |
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A8 |
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PIN DESCRIPTIONS
A0-A16 |
Address Inputs |
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CE |
Chip Enable Input |
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OE |
Output Enable Input |
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WE |
Write Enable Input |
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I/O0-I/O7 |
Bidirectional Ports |
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Vcc |
Power |
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GND |
Ground |
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PIN CONFIGURATION
32-Pin TSOP (Type II) (T)
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32 |
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A16 |
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A0 |
1 |
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A1 |
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2 |
31 |
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A15 |
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A2 |
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3 |
30 |
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A14 |
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A3 |
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4 |
29 |
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A13 |
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CE |
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5 |
28 |
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OE |
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I/O0 |
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6 |
27 |
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I/o7 |
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I/O1 |
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7 |
26 |
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I/O6 |
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Vcc |
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8 |
25 |
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GND |
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GND |
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9 |
24 |
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Vcc |
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I/O2 |
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10 |
23 |
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I/O5 |
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I/O3 |
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I/O4 |
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11 |
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21 |
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A12 |
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WE |
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12 |
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A4 |
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20 |
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A11 |
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A5 |
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19 |
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A10 |
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A6 |
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18 |
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A9 |
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A7 |
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A8 |
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TRUTH TABLE
Mode |
WE |
CE |
OE |
I/O Operation |
Vcc Current |
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Not Selected |
X |
H |
X |
High-Z |
ISB1, ISB2 |
(Power-down) |
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Output Disabled H |
L |
H |
High-Z |
ICC1, ICC2 |
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Read |
H |
L |
L |
DOUT |
ICC1, ICC2 |
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Write |
L |
L |
X |
DIN |
ICC1, ICC2 |
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ABSOLUTE MAXIMUM RATINGS(1)
Symbol |
Parameter |
Value |
Unit |
VTERM |
Terminal Voltage with Respect to GND |
–0.5 to Vcc + 0.5 |
V |
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TBIAS |
Temperature Under Bias |
–55 to +125 |
°C |
TSTG |
Storage Temperature |
–65 to +150 |
°C |
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PT |
Power Dissipation |
1.0 |
W |
Notes:
1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2 Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. H
10/02/00
IS63LV1024 |
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ISSI® |
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OPERATING RANGE |
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Range |
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Ambient Temperature |
VCC |
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Commercial |
0°C to +70°C |
3.3V ± 0.3V |
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Industrial |
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–40°C to +85°C |
3.3V ± 0.15V |
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DC ELECTRICAL CHARACTERISTICS (Over Operating Range) |
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Symbol |
Parameter |
Test Conditions |
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Min. |
Max. |
Unit |
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VOH |
Output HIGH Voltage |
VCC = Min., IOH = –4.0 mA |
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2.4 |
— |
V |
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VOL |
Output LOW Voltage |
VCC = Min., IOL = 8.0 mA |
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0.4 |
V |
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VIH |
Input HIGH Voltage |
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2.2 |
VCC + 0.3 |
V |
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VIL |
Input LOW Voltage(1) |
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–0.3 |
0.8 |
V |
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ILI |
Input Leakage |
GND ≤ VIN ≤ VCC |
Com. |
–1 |
1 |
µA |
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Ind. |
–5 |
5 |
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ILO |
Output Leakage |
GND ≤ VOUT ≤ VCC, Outputs Disabled |
Com. |
–1 |
1 |
µA |
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Ind. |
–5 |
5 |
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Notes:
1. VIL = –3.0V for pulse width less than 10 ns.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
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-8 ns |
-10 ns |
-12 ns |
-15 ns |
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Symbol |
Parameter |
TestConditions |
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Min. |
Max. |
Min. |
Max. |
Min. |
Max. |
Min. |
Max. |
Unit |
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ICC1 |
Vcc Operating |
VCC = Max., CE = VIL |
Com. |
— |
160 |
— |
150 |
— |
130 |
— |
120 |
mA |
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Supply Current |
IOUT = 0 mA, f = Max. |
Ind. |
— |
170 |
— |
160 |
— |
140 |
— |
130 |
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ISB |
TTL Standby |
VCC = Max., |
Com. |
— |
55 |
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45 |
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40 |
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35 |
mA |
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Current |
VIN = VIH or VIL |
Ind. |
— |
55 |
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45 |
— |
40 |
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35 |
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(TTL Inputs) |
CE ≥ VIH, f = Max |
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ISB1 |
TTL Standby |
VCC = Max., |
Com. |
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25 |
— |
25 |
— |
25 |
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25 |
mA |
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Current |
VIN = VIH or VIL |
Ind. |
— |
30 |
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30 |
— |
30 |
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30 |
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(TTL Inputs) |
CE ≥ VIH, f = 0 |
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ISB2 |
CMOS Standby |
VCC = Max., |
Com. |
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5 |
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5 |
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5 |
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5 |
mA |
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Current |
CE ≤ VCC – 0.2V, |
Ind. |
— |
10 |
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10 |
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10 |
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10 |
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(CMOS Inputs) |
VIN ≥ VCC – 0.2V, or |
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VIN ≤ 0.2V, f = 0 |
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Notes:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
CAPACITANCE(1,2)
Symbol |
Parameter |
Conditions |
Max. |
Unit |
CIN |
Input Capacitance |
VIN = 0V |
6 |
pF |
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CI/O |
Input/Output Capacitance |
VOUT = 0V |
8 |
pF |
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Notes:
1.Tested initially and after any design or process changes that may affect these parameters.
2.Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V.
Integrated Silicon Solution, Inc. — 1-800-379-4774 |
3 |
Rev. H
10/02/00