Intel Corporation N83C196KB, N87C196KB16, S80C196KB, S80C196KB16 Datasheet
*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
July 1994COPYRIGHT©INTEL CORPORATION, 1995 Order Number: 270909-006
8XC196KB/8XC196KB16
COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER
Y
8 Kbytes of On-Chip ROM/OTP
Available
Y
232 Byte Register File
Y
Register-to-Register Architecture
Y
28 Interrupt Sources/16 Vectors
Y
1.75 ms 16 x 16 Multiply (16 MHz)
Y
3.0 ms 32/16 Divide (16 MHz)
Y
Powerdown and Idle Modes
Y
Five 8-Bit I/O Ports
Y
16-Bit Watchdog Timer
Y
12 MHz and 16 MHz Available
Y
Dedicated 15-Bit Baud Rate Generator
Y
Dynamically Configurable 8-Bit or
16-Bit Buswidth
Y
Full Duplex Serial Port
Y
High Speed I/O Subsystem
Y
16-Bit Timer
Y
16-Bit Up/Down Counter with Capture
Y
Pulse-Width-Modulated Output
Y
Four 16-Bit Software Timers
Y
10-Bit A/D Converter with Sample/Hold
Y
HOLD/HLDA Bus Protocol
Y
Extended Temperature Available
The 8XC196KB is a 16-bit microcontroller available in three different memory varieties: ROMless (80C196KB),
8K ROM (83C196KB) and 8K OTP (One Time ProgrammableÐ87C196KB). The 8XC196KB is a high performance member of the MCS
É
96 microcontroller family. The 8XC196KB has the same peripheral set as the
8096BH and has a true superset of the 8096BH instructions. Intel’s CHMOS process provides a high performance processor along with low power consumption. To further reduce power requirements, the processor can
be placed into Idle or Powerdown Mode.
Bit, byte, word and some 32-bit operations are available on the 80C196KB. With a 16 MHz oscillator a 16-bit
addition takes 0.50 ms, and the instruction times average 0.37 ms to 1.1 ms in typical applications.
Four high-speed capture inputs are provided to record times when events occur. Six high-speed outputs are
available for pulse or waveform generation. The high-speed output can also generate four software timers or
start an A/D conversion. Events can be based on the timer or up/down counter. Also provided on-chip are an
A/D converter, serial port, watchdog timer and a pulse-width-modulated output signal.
The 8XC196KB has a maximum guaranteed frequency of 12 MHz. The 8XC196KB16 has a maximum guaranteed frequency of 16 MHz. All references to the 80C196KB also refer to the 80C196KB16; 83C196KB, Rxxx;
87C196KB and 87C196KB16 unless otherwise noted. The ROM device does not have a speed indicator at the
end of the device name. Instead it has a ROM code number.
With the commercial (standard) temperature option, operational characteristics are guaranteed over the temperature range of 0
§
Ctoa70§C. With the extended temperature range option, operational characteristics are
guaranteed over the temperature range of
b
40§Ctoa85§C.
Package Designators: N
e
68-pin PLCC, Se80-pin QFP (commercial only). Prefix Designators: TeExtend-
ed Temperature.
*Other brands and names are the property of their respective owners.
8XC196KB/8XC196KB16
270909– 1
Figure 1. 8XC196KB Block Diagram
2
8XC196KB/8XC196KB16
PROCESS INFORMATION
This device is manufactured on P629.0 and 629.1, a
CHMOS III-E process. Additional process and reliability information is available in Intel’s
Components
Quality and Reliability Handbook,
Order Number
210997.
270909– 2
EXAMPLE: N87C196KB16 is 68-Lead PLCC
OTPROM, 16 MHz.
For complete package dimensional data, refer to the
Intel Packaging Handbook (Order Number 240800).
NOTE:
1. EPROMs are available as One Time Programmable
(OTPROM) only.
Figure 2. The 8XC196KB Nomenclature
Table 1. Thermal Characteristics
Package
i
ja
i
jc
Type
PLCC 35§C/W 13§C/W
QFP 70§C/W 4§C/W
All thermal impedance data is approximate for static air
conditions at 1W of power dissipation. Values will change
depending on operation conditions and application. See
the Intel
Packaging Handbook
(order number 240800) for a
description of Intel’s thermal impedance test methodology.
Table 2. 8XC196KB Memory Map
Description Address
External Memory or I/O 0FFFFH
04000H
Internal ROM/EPROM or External 3FFFH
Memory (Determined by EA
)
2080H
Reserved. Must contain FFH. 207FH
(Note 5)
2040H
Upper Interrupt Vectors 203FH
2030H
ROM/EPROM Security Key 202FH
2020H
Reserved. Must contain FFH. 201FH
(Note 5)
201AH
Reserved. Must Contain 20H 2019H
(Note 5)
CCB 2018H
Reserved. Must contain FFH. 2017H
(Note 5)
2014H
Lower Interrupt Vectors 2013H
2000H
Port 3 and Port 4 1FFFH
1FFEH
External Memory 1FFDH
0100H
232 Bytes Register RAM (Note 1) 00FFH
0018H
CPU SFR’s (Notes 1, 3) 0017H
0000H
NOTES:
1. Code executed in locations 0000H to 00FFH will be
forced external.
2. Reserved memory locations must contain 0FFH unless
noted.
3. Reserved SFR bit locations must contain 0.
4. Refer to 8XC196KB quick reference for SFR descriptions.
5. WARNING: Reserved memory locations must not be
written or read. The contents and/or function of these locations may change with future revisions of the device.
Therefore, a program that relies on one or more of these
locations may not function properly.
3
8XC196KB/8XC196KB16
270909– 3
Figure 3. 68-Pin Package (PLCC Top View)
NOTE:
The above pin out diagram applies to the OTP (87C196KB) device. The OTP device uses all of the programming pins shown
above. The ROM (83C196KB) device only uses programming pins: AINC
, PALE, PMODE.n, and PROG. The ROMless
(80C196KB) doesn’t use any of the programming pins.
4
8XC196KB/8XC196KB16
270909– 4
NOTE:
N.C. means No Connect (do not connect these pins).
Figure 4. 80-Pin QFP Package
NOTE:
The above pin out diagram applies to the OTP (87C196KB) device. The OTP device uses all of the programming pins shown
above. The ROM (83C196KB) device only uses programming pins: AINC
, PALE, PMODE.n, and PROG. The ROMless
(80C196KB) doesn’t use any of the programming pins.
5
8XC196KB/8XC196KB16
PIN DESCRIPTIONS
Symbol Name and Function
V
CC
Main supply voltage (5V).
V
SS
Digital circuit ground (0V). There are multiple VSSpins, all of them must be connected.
V
REF
Reference voltage for the A/D converter (5V). V
REF
is also the supply voltage to the analog
portion of the A/D converter and the logic used to read Port 0. Must be connected for A/D
and Port 0 to function.
ANGND Reference ground for the A/D converter. Must be held at nominally the same potential as
V
SS
. Connect VSSand ANGND at chip to avoid noise problems.
V
PP
Programming voltage. Also timing pin for the return from power down circuit.
XTAL1 Input of the oscillator inverter and of the internal clock generator.
XTAL2 Output of the oscillator inverter.
CLKOUT Output of the internal clock generator. The frequency of CLKOUT is (/2 the oscillator
frequency. It has a 50% duty cycle.
RESET Reset input to and open-drain output from the chip. Input low for at least 4 state times to reset
the chip. The subsequent low-to-high transition re-synchronizes CLKOUT and commences a
10-state-time RESET sequence.
BUSWIDTH Input for buswidth selection. If CCR bit 1 is a one, this pin selects the bus width for the bus
cycle in progress. If BUSWIDTH is a 1, a 16-bit bus cycle occurs. If BUSWIDTH isa0an8-bit
cycle occurs. If CCR bit 1 is a 0, the bus is always an 8-bit bus.
NMI A positive transition causes a vector through 203EH.
INST Output high during an external memory read indicates the read is an instruction fetch and
output low indicates a data fetch. INST is valid throughout the bus cycle. INST is activated
only during external memory accesses.
EA Input for memory select (External Access). EA equal to a TTL-high causes memory accesses
to locations 2000H through 3FFFH to be directed to on-chip ROM/OTPROM. EA equal to a
TTL-low causes accesses to these locations to be directed to off-chip memory.
ALE/ADV Address Latch Enable or Address Valid output, as selected by CCR. Both pin options provide
a latch to demultiplex the address from the address/data bus. When the pin is ADV
, it goes
inactive high at the end of the bus cycle. ALE/ADV
is activated only during external memory
accesses.
RD Read signal output to external memory. RD is activated only during external memory reads.
WR/WRL Write and Write Low output to external memory, as selected by the CCR. WR will go low for
every external write, while WRL
will go low only for external writes where an even byte is
being written. WR
/WRL is activated only during external memory writes.
BHE/WRH Bus High Enable or Write High output to external memory, as selected by the CCR. BHE will
go low for external writes to the high byte of the data bus. WRH
will go low for external writes
where an odd byte is being addressed. BHE
/WRH is activated only during external memory
writes.
READY Ready input to lengthen external memory cycles. If the pin is low prior to the falling edge of
CLKOUT, the memory controller goes into a wait mode until the next positive transition in
CLKOUT occurs with READY high. When the external memory is not being used, READY has
no effect. Internal control of the number of wait states inserted into a bus cycle (held not
ready) is available in the CCR.
HSI Inputs to High Speed Input Unit. Four HSI pins are available: HSI.0, HSI.1, HSI.2 and HSI.3.
Two of them (HSI.2 and HSI.3) are shared with the HSO Unit.
HSO Outputs from High Speed Output Unit. Six HSO pins are available: HSO.0, HSO.1, HSO.2,
HSO.3, HSO.4 and HSO.5. Two of them (HSO.4 and HSO.5) are shared with the HSI Unit.
6
8XC196KB/8XC196KB16
PIN DESCRIPTIONS (Continued)
Symbol Name and Function
Port 0 8-bit high impedance input-only port. Three pins can be used as digital inputs and/or as
analog inputs to the on-chip A/D converter.
Port 1 8-bit quasi-bidirectional I/O port. These pins are shared with HOLD, HLDA and BREQ
.
Port 2 8-bit multi-functional port. All of its pins are shared with other functions in the 87C196KB.
Pins P2.6 and P2.7 are quasi-bidirectional.
Ports 3 and 4 8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the
multiplexed address/data bus, which has strong internal pullups.
HOLD Bus Hold input requesting control of the bus. Enabled by setting WSR.7.
HLDA Bus Hold acknowledge output indicating release of the bus. Enabled by setting WSR.7.
BREQ Bus Request output activated when the bus controller has a pending external memory
cycle. Enabled by setting WSR.7.
TxD The TxD pin is used for serial port transmission in Modes 1, 2 and 3. In Mode 0 the pin is
used as the serial clock output.
RxD Serial Port Receive pin used for serial port reception. In Mode 0 the pin functions as input or
output data.
EXTINT A rising edge on the EXTINT pin will generate an external interrupt.
T2CLK The T2CLK pin is the Timer2 clock input or the serial port baud rate generator input.
T2RST A rising edge on the T2RST pin will reset Timer2.
PWM The pulse width modulator output.
T2UP-DN The T2UPDN pin controls the direction of Timer2 as an up or down counter.
T2CAPTURE A rising edge on P2.7 will capture the value of Timer2 in the T2CAPTURE register.
PMODE Programming Mode Select. Determines the EPROM programming algorithm that is
performed. PMODE is sampled after a chip reset and should be static while the part is
operating.
SID Slave ID Number. Used to assign each slave a pin of Port 3 or 4 to use for passing
programming verification acknowledgement.
PALE Programming ALE Input. Accepted by the 87C196KB when it is in Slave Programming
Mode. Used to indicate that Ports 3 and 4 contain a command/address.
PROG Programming. Falling edge indicates valid data on PBUS and the beginning of
programming. Rising edge indicates end of programming.
PACT Programming Active. Used in the Auto Programming Mode to indicate when programming
activity is complete.
PVAL Program Valid. This signal indicates the success or failure of programming in the Auto
Programming Mode. A zero indicates successful programming.
PVER Program Verification. Used in Slave Programming and Auto CLB Programming Modes.
Signal is low after rising edge of PROG if the programming was not successful.
AINC Auto Increment. Active low signal indicates that the auto increment mode is enabled. Auto
Increment will allow reading or writing of sequential EPROM locations without address
transactions across the PBUS for each read or write.
Ports 3 Address/Command/Data Bus. Used to pass commands, addresses, and data to and from
slave mode 87C196KBs. Used by chips in Auto Programming Mode to pass command,
and 4
addresses and data to slaves. Also used in the Auto Programming Mode as a regular
(Programming
system bus to access external memory. Should have pullups to V
CC
when used in slave
Mode)
programming mode.
7
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