Intel U3000, P4000 User Manual

Intel® Celeron® Mobile Processor P4000 and U3000 Series

Specification Update

November 2010

Document Number: 324456-005

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Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel

reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

Intel processor numbers are not a measure of performance. Proce ssor numbers differentiate features within each processor family, not across different processor families. See http://www.intel.com/products/processor_number for details.

The processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

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2 Specification Update

Revision History ........................................................................................................4

Preface......................................................................................................................5

Summary Tables of Changes......................................................................................7

Identification Information.......................................................................................14

Errata......................................................................................................................17

Specification Changes..............................................................................................43

Specification Clarifications ......................................................................................43

Documentation Changes..........................................................................................44

Specification Update 3

Revision History

Revision Version Description Date

-001 -001 Initial Release March 2010

• Updated K-0 Stepping Microcode Update

-002 -001

-003 -001

-004 -001 • Added new processor sku P4600 October 2010

-005 -001

• Updated C-2 Stepping Microcode Update

• Fixed AAZ69

• Added Errata AAZ10S-11S

• Added Errata AAZ96-AAZ99

• Added Revision/V ersion to cl arify if there are ev er multiple releases within a month

• Added Errata AAZ100-103

• Updated Errata AAZ32 and AAZ76

July 2010

August 2010

November 2010

Specification Update

Preface

This document is an update to the specifications contained in the Affected Documents table below. This document is a compilation of device and documentation errata, specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools.

Information types defined in Nomenclature are consolidated into the specification update and are no longer published in other documents.

This document may also contain information that was not previously published.

Affected Documents

Intel® Celeron® Mobile Processor P4000 and U3000 Series Datasheet

Summary Tables of Changes

The following tables indicate the errata, specification changes, specification clarifications, or documentation changes which apply to the processor. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. These tables uses the following notations:

Codes Used in Summary Tables

Stepping

X: Errata exists in the stepping indicated. Specification Change or

Clarification that applies to this stepping. (No mark) or (Blank box): This erratum is fixed in listed stepping or specification change

does not apply to listed stepping.

Page

Status

Row

(Page): Page location of item in this document.

Doc: Document change or update will be implemented. Plan Fix: This erratum may be fixed in a future stepping of the product. Fixed: This erratum has been previously fixed. No Fix: There are no plans to fix this erratum.

Change bar to left of table row indicates this erratum is either new or modified from the previous version of the document.

Each Specification Update item is prefixed with a capital letter to distinguish the product. The key below details the letters that are used in Intel’s microprocessor Specification Updates:

Specification Update 7

AAZ

Errata (Sheet 1 of 5)

Summary Tables of Changes

Number

Status ERRATA

C-2 K-0

AAZ1 X X No Fix The Processor May Report a #TS Instead of a #GP Fault

REP MOVS/STOS Executing with Fast Strings Enabled and

Steppings

AAZ2 X X No Fix

Crossing Page Boundaries with Inconsistent Memory Types May Use an Incorrect Data Size or Lead to Memory-Ordering Violations

Code Segment Limit/Canonical Faults on RSM May Be Serviced

AAZ3 X X No Fix

before Higher Priority Interrupts/Exceptions and May Push the Wrong Address onto the Stack

AAZ4 X X No Fix

AAZ5 X X No Fix

Performance Monitor SSE Retired Instructions May Return Incorrect Values

Premature Execution of a Load Operation Prior to Exception Handler Invocation

AAZ6 X X No Fix MOV To/From Debug Registers Causes Debug Exception

AAZ7 X X No Fix

AAZ8 X X No Fix

AAZ9 X X No Fix

AAZ10 X X No Fix

AAZ11 X X No Fix

AAZ12 X X No Fix

AAZ13 X X No Fix

AAZ14 X X No Fix

AAZ15 X X No Fix

AAZ16 X X No Fix

AAZ17 X X No Fix

AAZ18 X X No Fix

AAZ19 X X No Fix

AAZ20 X X No Fix

Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR Image Leads to Partial Memory Update

Values for LBR/BTS/BTM Will Be Incorrect after an Exit from SMM

Single Step Interrupts with Floating Point Exception Pending May Be Mishandled

Fault on ENTER Instruction May Result in Unexpected Values on Stack Frame

IRET under Certain Conditions May Cause an Unexpected Alignment Check Exception

General Protection Fault (#GP) for Instructions Greater than 15 Bytes May Be Preempted

General Protection (#GP) Fault May Not Be Signaled on Data Segment Limit Violation above 4-G Limit

LBR, BTS, BTM May Report a Wrong Address When an Exception/Interrupt Occurs in 64-bit Mode

MONITOR or CLFLUSH on the Local XAPIC's Address Space Results in Hang

Corruption of CS Segment Register during RSM While Transitioning from Real Mode to Protected Mode

Performance Monitoring Events for Read Miss to Level 3 Cache Fill Occupancy Counter May Be Incorrect

A VM Exit on MWAIT May Incorrectly Report the Monitoring Hardware as Armed

Performance Monitor Event SEGMENT_REG_LOADS Counts Inaccurately

#GP on Segment Selector Descriptor That Straddles Canonical Boundary May Not Provide Correct Exception Error Code

Specification Update

Summary Tables of Changes

Errata (Sheet 2 of 5)

Number

AAZ21 X X No Fix

AAZ22 XXNo Fix

AAZ23 X X No Fix IA32_MPERF Counter Stops Counting during On-Demand TM1

AAZ24 X X No Fix

AAZ25 X X No Fix

AAZ26 X X No Fix

AAZ27 X X No Fix

AAZ28 X X No Fix

AAZ29 X X No Fix

AAZ30 X X No Fix

AAZ31 X X No Fix Two xAPIC Timer Event Interrupts May Unexpectedly Occur

AAZ32 X X No Fix

AAZ33 X X No Fix

AAZ34 X X No Fix APIC Error “Received Illegal Vector” May Be Lost

AAZ35 X X No Fix

AAZ36 X X No Fix

AAZ37 X X No Fix IA32_PERF_GLOBAL_CTRL MSR May Be Incorrectly Initialized

AAZ38 X X No Fix

AAZ39 X X No Fix

AAZ40 X X No Fix

AAZ41 X X No Fix

AAZ42 X X No Fix

AAZ43 X X No Fix Performance Monitor Counters May Count Incorrectly

Steppings

Status ERRATA

C-2 K-0

Improper Parity Error Signaled in the IQ Following Reset When a Code Breakpoint Is Set on a #GP Instruction

An Enabled Debug Breakpoint or Single Step T rap May Be Taken after MOV SS/POP SS Instruction If It Is Followed by an Instruction That Signals a Floating Point Exception

The Memory Controller tTHROT_OPREF Timings May Be Violated during Self-Refresh Entry

Synchronous Reset of IA32_APERF/IA32_MPERF Counters on Overflow Does Not Work

Disabling Thermal Monitor While Processor is Hot, Then Reenabling, May Result in Stuck Core Operating Ratio

Writing the Local Vector Table (LVT) When an Interrupt is Pending May Cause an Unexpected Interrupt

xAPIC Timer May Decrement Too Quickly Following an Automatic Reload While in Periodic Mode

Changing the Memory Type for an In-Use Page Translation May Lead to Memory-Ordering Violations

Infinite Stream of Interrupts May Occur If an ExtINT Delivery Mode Interrupt is Received While All Cores in C6

EOI Transaction May Not Be Sent If Software Enters Core C6 during an Interrupt Service Routine

FREEZE_WHILE_SMM Does Not Prevent Event from Pending PEBS during SMM

DR6 May Contain Incorrect Information When the First Instruction after a MOV SS,r/m or POP SS Is a Store

An Uncorrectable Error Logged in IA32_CR_MC2_STATUS May Also Result in a System Hang

Performance Monitor Counter INST_RETIRED.STORES May Count Higher Than Expected

Sleeping Cores May Not Be Woken Up on Logical Cluster Mode Broadcast IPI Using Destination Field Instead of Shorthand

Faulting Executions of FXRSTOR May Update State Inconsistently

Performance Monitor Event EPT.EPDPE_MISS May Be Counted While EPT Is Disable

Memory Aliasing of Code Pages May Cause Unpredictable System Behavior

Specification Update 9

Errata (Sheet 3 of 5)

Summary Tables of Changes

Number

AAZ44 X X No Fix

AAZ45 X X No Fix

AAZ46 X X No Fix

AAZ47 X X No Fix

AAZ48 X X No Fix

AAZ49 X X No Fix

AAZ50 X X No Fix

AAZ51 X X No Fix

AAZ52 X X No Fix

AAZ53 X X No Fix

AAZ54 X X No Fix

AAZ55 X X No Fix

AAZ56 X X No Fix

AAZ57 X X No Fix

AAZ58 X X No Fix

AAZ59 X X No Fix

AAZ60 X X No Fix

AAZ61 X X No Fix

AAZ62 X X No Fix

AAZ63 X X No Fix

AAZ64 X X No Fix

Steppings

Status ERRATA

C-2 K-0

Performance Monitor Event Offcore_response_0 (B7H) Does Not Count NT Stores to Local DRAM Correctly

EFLAGS Discrepancy on Page Faults and on EPT-Induced VM Exits after a Translation Change

Back-to-Back Uncorrected Machine Check Errors May Overwrite IA32_MC3_STATUS.MSCOD

Corrected Errors with a Yellow Error Indication May Be Overwritten by Other Corrected Errors

Performance Monitor Events DCACHE_CACHE_LD and DCACHE_CACHE_ST May Overcount

Performance Monitor Events INSTR_RETIRED and MEM_INST_RETIRED May Count Inaccurately

A Page Fault May Not Be Generated When the PS Bit Is Set to "1" in a PML4E or PDPTE

BIST Results May Be Additionally Reported after a GETSEC[WAKEUP] or INIT-SIPI Sequence

Pending x87 FPU Exceptions (#MF) May Be Signaled Earlier Than Expected

VM Exits Due to "NMI-Window Exiting" May Be Delayed by One Instruction

VM Exits Due to EPT Violations Do Not R ecord Information about Pre-IRET NMI Blocking.

Multiple Performance Monitor Interrupts are Possible on Overflow of IA32_FIXED_CTR2

LBRs May Not be Initialized During Power-On Reset of the Processor

LBR, BTM or BTS Records May Have Incorrect Branch From Information After an Enhanced Intel SpeedStep® Technology Transition, T-states, C1E, or Adaptive Thermal Throttling

VMX-Preemption Timer Does Not Count Down at the Rate Specified

Multiple Performance Monitor Interrupts Are Possible on Overflow of Fixed Counter 0

VM Exits Due to LIDT/LGDT/SIDT/SGDT Do Not Report Correct Operand Size

DPRSLPVR Signal May Be Incorrectly Asserted on Transition between Low Power C-states

Performance Monitoring Events STORE_BLOCKS.NOT_STA and STORE_BLOCKS.STA May Not Count Events Correctly

Storage of PEBS Record Delayed Following Execution of MOV SS or STI

Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not Count Some Transitions

Specification Update

Summary Tables of Changes

Errata (Sheet 4 of 5)

Number

AAZ65 X X No Fix

AAZ66 X X No Fix LER MSRs May Be Unreliable

AAZ67 X X No Fix

AAZ68 X X No Fix

AAZ69 X X N/A

AAZ70 X Fixed

AAZ71 X X No Fix

AAZ72 X X No Fix

AAZ73 X X No Fix

AAZ74 X X No Fix

AAZ75 X X No Fix PCI Express x16 Root Port Incorrectly NAK's a Nullified TLP

Steppings

Status ERRATA

C-2 K-0

INVLPG Following INVEPT or INVVPID May Fail to Flush All Translations for a Large Page

MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a DTLB Error

Debug Exception Flags DR6.B0-B3 Flags May Be Incorrect for Disabled Breakpoints

This erratum is removed as it doesn not apply to the Intel Celeron P4000 and U3000 Mobile Processor Series

Delivery of Certain Events Immediately Following a VM Exit May Push a Corrupted RIP onto the Stack

A String Instruction That Re-maps a Page May Encounter an Unexpected Page Fault

Logical Processor May Use Incorrect VPID after VM Entry That Returns from SMM

MSR_TURBO_RATIO_LIMIT MSR May R eturn Intel® Turbo Boost Technology Core Ratio Multipliers for Non-Existent Core Configurations

PCI Express x16 Port Logs Bad TLP Correctable Error When Receiving a Duplicate TLP

AAZ76 X X No Fix

AAZ77 X Fixed Internal Parity Error May Be Incorrectly Signaled during C6 Exit AAZ78 X X No Fix PMIs during Core C6 Transitions May Cause the System to Hang

AAZ79 X X No Fix

AAZ80 X X No Fix

AAZ81 X Fixed TXT.PUBLIC.KEY is Not Reliable

AAZ82 X Fixed

AAZ83 X Fixed

AAZ84 X X No Fix

AAZ85 X X No Fix Processor Hangs on Package C6 State Exit AAZ86 X X No Fix A Synchronous SMI May Be Delayed

PCI Express Graphics Receiver Error Reported When Receiver with L0s Enabled and Link Retrain Performed

2-MB Page Split Lock Accesses Combined with Complex Internal Events May Cause Unpredictable System Behavior

Extra APIC Timer Interrupt May Occur during a Write to the Divide Configuration Register

8259 Virtual Wire B Mode Interrupt May Be Dropped When it Collides With Interrupt Acknowledge Cycle From the Preceding Interrupt

CPUID Incorrectly Reports a C-State as Available When this State is Unsupported

The Combination of a Page-Split Lock Access and Data Accesses That Are Split across Cacheline Boundaries May Lead to Processor Livelock

Specification Update 11

Errata (Sheet 5 of 5)

Summary Tables of Changes

Number

AAZ87 X X No Fix

AAZ88 X X No Fix PCI Express Cards May Not Train to x16 Link Width

AAZ89 X X No Fix

AAZ90 X X No Fix IO_SMI Indication in SMRAM State Save Area May Be Lost

AAZ91 X X No Fix

AAZ92 X X No Fix CKE May go Low Within tRFC(min) After a PD Exit

AAZ93 X X No Fix

AAZ94 X X No Fix

AAZ95 X X No Fix VM Entry Loading an Unusable SS Might Not Set SS.B to 1

AAZ96 X X No Fix

AAZ97 X X No Fix

AAZ98 X No Fix

AAZ99 X X No Fix

Steppings

Status ERRATA

C-2 K-0

FP Data Operand Pointer May Be Incorrectly Calculated After an FP Access Which Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit Address Size in 64-bit ModeFP Data Operand Pointer Ma y Be Incorrectly Calculated After an FP Access Which Wraps a 4Gbyte Boundary in Code That Uses 32-Bit Address Size in 64-bit Mode

The APIC Timer Current Count Register May Prematurely Read 0x0 While the Timer Is Still Running

FSW May Be Corrupted If an x87 Store Instruction Causes a Page Fault in VMX Non-Root Operation

Under Certain Low Temperature Conditions, Some Uncore Performance Monitoring Events May Report Incorrect Results

VM Entry to 64-Bit Mode May Fail if Bits 48 And 47 of Guest RIP Are Different

Accesses to a VMCS May Not Operate Correctly If CR0.CD is Set on Any Logical Processor of a Core

Performance Monitor Events for Hardware Prefetches Which Miss The L1 Data Cache May be Over Counted

Correctable and Uncorrectable Cache Errors May be Reported Until the First Core C6 Transition

VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]

AAZ100 X No Fix

AAZ101 X X No Fix

AAZ102 X X No Fix

AAZ103 X No Fix

DTSTemperature Data May Be Incorrect On a Return From the Package C6Low Power State

USB Devices May Not Function Properly With Integrated Graphics While Running Targeted Stress Graphics Workloads With Non-Matching Memory Configurations

VM Entry May Omit Consistency Checks Related to Bit 14 (BS) of the Pending Debug Exception Field in Guest-State Area of the VMCS

Intel Turbo Boost Technology Ratio Changes May Cause Unpredictable System Behavior

Specification Update

Summary Tables of Changes

Specification Changes

Number SPECIFICATION CHANGES

None for this revision of this specification update.

Specification Clarifications

Number SPECIFICATION CLARIFICATIONS

None for this revision of this specification update.

Documentation Changes

Number DOCUMENTATION CHANGES

None for this revision of this specification update.

§ §

Specification Update 13

Identification Information

Component Identification via Programming Interface

The Intel® Celeron® P4000 and U3000 Mobile Processor Series stepping can be identified by the following processor signatures:

Reserved

31:28 27:20 19:16 15:14 13:12 11:8 7:4 3:0

Notes:

1. The Extended Family, bits [27:20] are used in conjunction with the Family Code, spec ified in bits [11:8] , to

2. The Extended Model, bits [19:16] in conjunction with the Model Number, specified in bits [7:4], are used to

3. The Processor Type, specifie d in bits [13:12 ] indicates wh ether the proce ssor is an original OEM pr ocessor,

4. The Family Code corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX register

5. The Model Number corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the EAX register

6. The Stepping ID in bits [3:0] indicates the revision number of that model. See Table 1 for the processor

Extended

Family

00000000b 0010b 00b 0110 0101b xxxxb

indicate whether the processor belongs to the Intel386®, Intel486®, Pe ntium®, Pe ntium Pro®, P entium® 4, or Intel® Core™ processor family.

identify the model of the processor within the processor’s family.

an OverDrive

after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the Device ID register accessible through Boundary Scan.

after the CPUID instruction is executed with a 1 in the EAX register, and the model field of the Device ID register accessible through Boundary Scan.

stepping ID number in the CPUID information.

Extended

processor, or a dual processor (capable of being used in a dual processor system).

Model

Reserved

Processor

Type

Family

Code

Model

Number

Stepping

When EAX is initialized to a value of ‘1’, the CPUID instruction returns the Extended Family, Extended Model, Processor Type, Family C ode, Mode l Number and Step ping ID

value in the EAX register. Note that the EDX processor signature value after reset is equivalent to the processor signature output value in the EAX register.

Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX registers after the CPUID instruction is executed with a 2 in the EAX register.

The Intel® Celeron® P4000 and U3000 Mobile Processor Series can be identified by the following register contents:

Processor

Stepping

C-2 8086h 0044h 12h K-0 8086h 0044h 18h

Notes:

1. The Vendor ID corresponds to Bits 15:0 of the V endor ID R egister l ocated at offset 00–01h in the PCI function 0 configuration space.

2. The Device ID corresponds to Bits 15:0 of the Device ID Register located at Device 0 offset 02–03h in the PCI function 0 configuration space.

3. The Revision Number corresponds to Bits 7:0 of the Revision ID Register located at offset 08h in the PCI function 0 configuration space.

4. Correct Host Device ID requires firmware support.

Vendor ID

Device ID

Revision ID

Specification Update

+ 31 hidden pages

Intel U3000, P4000 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Intel® Celeron® Mobile Processor P4000 and U3000 Series

Contents

Revision History

Preface

Summary Tables of Changes

Identification Information