Intel U3000, P4000 User Manual

Document Number: 324456-005

Intel® Celeron® Mobile Processor

P4000 and U3000 Series

Specification Update

November 2010

2 Specification Update

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life sustaining, critical control or safety systems, or in nuclear facility applications.

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Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel

reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future

changes to them.

Intel processor numbers are not a measure of performance. Proce ssor numbers differentiate features within each processor family,

not across different processor families. See http://www.intel.com/products/processor_number for details.

The processor may contain design defects or errors known as errata which may cause the product to deviate from published

specifications. Current characterized errata are available on request.Contact your local Intel sales office or your distributor to

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*Other names and brands may be claimed as the property of others.

Specification Update 3

Revision History ........................................................................................................4

Preface......................................................................................................................5

Summary Tables of Changes......................................................................................7

Identification Information.......................................................................................14

Errata......................................................................................................................17

Specification Changes..............................................................................................43

Specification Clarifications ......................................................................................43

Documentation Changes..........................................................................................44

Revision History

Specification Update

Revision History

Revision Version Description Date

-001 -001 Initial Release March 2010

-002 -001

• Updated K-0 Stepping Microcode Update

• Updated C-2 Stepping Microcode Update

• Fixed AAZ69

• Added Errata AAZ10S-11S

July 2010

-003 -001

• Added Errata AAZ96-AAZ99

• Added Revision/V ersion to cl arify if there are ev er multiple releases

within a month

August 2010

-004 -001 • Added new processor sku P4600 October 2010

-005 -001

• Added Errata AAZ100-103

• Updated Errata AAZ32 and AAZ76

November 2010

Specification Update 5

Preface

This document is an update to the specifications contained in the Affected Documents

table below. This document is a compilation of device and documentation errata,

specification clarifications and changes. It is intended for hardware system

manufacturers and software developers of applications, operating systems, or tools.

Information types defined in Nomenclature are consolidated into the specification

update and are no longer published in other documents.

This document may also contain information that was not previously published.

Affected Documents

Summary Tables of Changes

The following tables indicate the errata, specification changes, specification

clarifications, or documentation changes which apply to the processor. Intel may fix

some of the errata in a future stepping of the component, and account for the other

outstanding issues through documentation or specification changes as noted. These

tables uses the following notations:

Codes Used in Summary Tables

Stepping

X: Errata exists in the stepping indicated. Specification Change or

Clarification that applies to this stepping.

(No mark)

or (Blank box): This erratum is fixed in listed stepping or specification change

does not apply to listed stepping.

Page

(Page): Page location of item in this document.

Status

Doc: Document change or update will be implemented.

Plan Fix: This erratum may be fixed in a future stepping of the product.

Fixed: This erratum has been previously fixed.

No Fix: There are no plans to fix this erratum.

Row

Change bar to left of table row indicates this erratum is either new or modified from the

previous version of the document.

Each Specification Update item is prefixed with a capital letter to distinguish the

product. The key below details the letters that are used in Intel’s microprocessor

Specification Updates:

Summary Tables of Changes

Specification Update

AAZ

Errata (Sheet 1 of 5)

Number

Steppings

Status ERRATA

C-2 K-0

AAZ1 X X No Fix The Processor May Report a #TS Instead of a #GP Fault

AAZ2 X X No Fix

REP MOVS/STOS Executing with Fast Strings Enabled and

Crossing Page Boundaries with Inconsistent Memory Types May

Use an Incorrect Data Size or Lead to Memory-Ordering

Violations

AAZ3 X X No Fix

Code Segment Limit/Canonical Faults on RSM May Be Serviced

before Higher Priority Interrupts/Exceptions and May Push the

Wrong Address onto the Stack

AAZ4 X X No Fix

Performance Monitor SSE Retired Instructions May Return

Incorrect Values

AAZ5 X X No Fix

Premature Execution of a Load Operation Prior to Exception

Handler Invocation

AAZ6 X X No Fix MOV To/From Debug Registers Causes Debug Exception

AAZ7 X X No Fix

Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR

Image Leads to Partial Memory Update

AAZ8 X X No Fix

Values for LBR/BTS/BTM Will Be Incorrect after an Exit from

SMM

AAZ9 X X No Fix

Single Step Interrupts with Floating Point Exception Pending

May Be Mishandled

AAZ10 X X No Fix

Fault on ENTER Instruction May Result in Unexpected Values on

Stack Frame

AAZ11 X X No Fix

IRET under Certain Conditions May Cause an Unexpected

Alignment Check Exception

AAZ12 X X No Fix

General Protection Fault (#GP) for Instructions Greater than 15

Bytes May Be Preempted

AAZ13 X X No Fix

General Protection (#GP) Fault May Not Be Signaled on Data

Segment Limit Violation above 4-G Limit

AAZ14 X X No Fix

LBR, BTS, BTM May Report a Wrong Address When an

Exception/Interrupt Occurs in 64-bit Mode

AAZ15 X X No Fix

MONITOR or CLFLUSH on the Local XAPIC's Address Space

Results in Hang

AAZ16 X X No Fix

Corruption of CS Segment Register during RSM While

Transitioning from Real Mode to Protected Mode

AAZ17 X X No Fix

Performance Monitoring Events for Read Miss to Level 3 Cache

Fill Occupancy Counter May Be Incorrect

AAZ18 X X No Fix

A VM Exit on MWAIT May Incorrectly Report the Monitoring

Hardware as Armed

AAZ19 X X No Fix

Performance Monitor Event SEGMENT_REG_LOADS Counts

Inaccurately

AAZ20 X X No Fix

#GP on Segment Selector Descriptor That Straddles Canonical

Boundary May Not Provide Correct Exception Error Code

Specification Update 9

Summary Tables of Changes

AAZ21 X X No Fix

Improper Parity Error Signaled in the IQ Following Reset When a

Code Breakpoint Is Set on a #GP Instruction

AAZ22 XXNo Fix

An Enabled Debug Breakpoint or Single Step T rap May Be Taken

after MOV SS/POP SS Instruction If It Is Followed by an

Instruction That Signals a Floating Point Exception

AAZ23 X X No Fix IA32_MPERF Counter Stops Counting during On-Demand TM1

AAZ24 X X No Fix

The Memory Controller tTHROT_OPREF Timings May Be Violated

during Self-Refresh Entry

AAZ25 X X No Fix

Synchronous Reset of IA32_APERF/IA32_MPERF Counters on

Overflow Does Not Work

AAZ26 X X No Fix

Disabling Thermal Monitor While Processor is Hot, Then Re-

enabling, May Result in Stuck Core Operating Ratio

AAZ27 X X No Fix

Writing the Local Vector Table (LVT) When an Interrupt is

Pending May Cause an Unexpected Interrupt

AAZ28 X X No Fix

xAPIC Timer May Decrement Too Quickly Following an

Automatic Reload While in Periodic Mode

AAZ29 X X No Fix

Changing the Memory Type for an In-Use Page Translation May

Lead to Memory-Ordering Violations

AAZ30 X X No Fix

Infinite Stream of Interrupts May Occur If an ExtINT Delivery

Mode Interrupt is Received While All Cores in C6

AAZ31 X X No Fix Two xAPIC Timer Event Interrupts May Unexpectedly Occur

AAZ32 X X No Fix

EOI Transaction May Not Be Sent If Software Enters Core C6

during an Interrupt Service Routine

AAZ33 X X No Fix

FREEZE_WHILE_SMM Does Not Prevent Event from Pending

PEBS during SMM

AAZ34 X X No Fix APIC Error “Received Illegal Vector” May Be Lost

AAZ35 X X No Fix

DR6 May Contain Incorrect Information When the First

Instruction after a MOV SS,r/m or POP SS Is a Store

AAZ36 X X No Fix

An Uncorrectable Error Logged in IA32_CR_MC2_STATUS May

Also Result in a System Hang

AAZ37 X X No Fix IA32_PERF_GLOBAL_CTRL MSR May Be Incorrectly Initialized

AAZ38 X X No Fix

Performance Monitor Counter INST_RETIRED.STORES May

Count Higher Than Expected

AAZ39 X X No Fix

Sleeping Cores May Not Be Woken Up on Logical Cluster Mode

Broadcast IPI Using Destination Field Instead of Shorthand

AAZ40 X X No Fix

Faulting Executions of FXRSTOR May Update State

Inconsistently

AAZ41 X X No Fix

Performance Monitor Event EPT.EPDPE_MISS May Be Counted

While EPT Is Disable

AAZ42 X X No Fix

Memory Aliasing of Code Pages May Cause Unpredictable

System Behavior

AAZ43 X X No Fix Performance Monitor Counters May Count Incorrectly

Errata (Sheet 2 of 5)

Number

Steppings

Status ERRATA

C-2 K-0

Summary Tables of Changes

Specification Update

AAZ44 X X No Fix

Performance Monitor Event Offcore_response_0 (B7H) Does Not

Count NT Stores to Local DRAM Correctly

AAZ45 X X No Fix

EFLAGS Discrepancy on Page Faults and on EPT-Induced VM

Exits after a Translation Change

AAZ46 X X No Fix

Back-to-Back Uncorrected Machine Check Errors May Overwrite

IA32_MC3_STATUS.MSCOD

AAZ47 X X No Fix

Corrected Errors with a Yellow Error Indication May Be

Overwritten by Other Corrected Errors

AAZ48 X X No Fix

Performance Monitor Events DCACHE_CACHE_LD and

DCACHE_CACHE_ST May Overcount

AAZ49 X X No Fix

Performance Monitor Events INSTR_RETIRED and

MEM_INST_RETIRED May Count Inaccurately

AAZ50 X X No Fix

A Page Fault May Not Be Generated When the PS Bit Is Set to

"1" in a PML4E or PDPTE

AAZ51 X X No Fix

BIST Results May Be Additionally Reported after a

GETSEC[WAKEUP] or INIT-SIPI Sequence

AAZ52 X X No Fix

Pending x87 FPU Exceptions (#MF) May Be Signaled Earlier

Than Expected

AAZ53 X X No Fix

VM Exits Due to "NMI-Window Exiting" May Be Delayed by One

Instruction

AAZ54 X X No Fix

VM Exits Due to EPT Violations Do Not R ecord Information about

Pre-IRET NMI Blocking.

AAZ55 X X No Fix

Multiple Performance Monitor Interrupts are Possible on

Overflow of IA32_FIXED_CTR2

AAZ56 X X No Fix

LBRs May Not be Initialized During Power-On Reset of the

Processor

AAZ57 X X No Fix

LBR, BTM or BTS Records May Have Incorrect Branch From

Information After an Enhanced Intel SpeedStep® Technology

Transition, T-states, C1E, or Adaptive Thermal Throttling

AAZ58 X X No Fix

VMX-Preemption Timer Does Not Count Down at the Rate

Specified

AAZ59 X X No Fix

Multiple Performance Monitor Interrupts Are Possible on

Overflow of Fixed Counter 0

AAZ60 X X No Fix

VM Exits Due to LIDT/LGDT/SIDT/SGDT Do Not Report Correct

Operand Size

AAZ61 X X No Fix

DPRSLPVR Signal May Be Incorrectly Asserted on Transition

between Low Power C-states

AAZ62 X X No Fix

Performance Monitoring Events STORE_BLOCKS.NOT_STA and

STORE_BLOCKS.STA May Not Count Events Correctly

AAZ63 X X No Fix

Storage of PEBS Record Delayed Following Execution of MOV SS

or STI

AAZ64 X X No Fix

Performance Monitoring Event FP_MMX_TRANS_TO_MMX May

Not Count Some Transitions

Errata (Sheet 3 of 5)

Number

Steppings

Status ERRATA

C-2 K-0

Specification Update 11

Summary Tables of Changes

AAZ65 X X No Fix

INVLPG Following INVEPT or INVVPID May Fail to Flush All

Translations for a Large Page

AAZ66 X X No Fix LER MSRs May Be Unreliable

AAZ67 X X No Fix

MCi_Status Overflow Bit May Be Incorrectly Set on a Single

Instance of a DTLB Error

AAZ68 X X No Fix

Debug Exception Flags DR6.B0-B3 Flags May Be Incorrect for

Disabled Breakpoints

AAZ69 X X N/A

This erratum is removed as it doesn not apply to the Intel

Celeron P4000 and U3000 Mobile Processor Series

AAZ70 X Fixed

Delivery of Certain Events Immediately Following a VM Exit May

Push a Corrupted RIP onto the Stack

AAZ71 X X No Fix

A String Instruction That Re-maps a Page May Encounter an

Unexpected Page Fault

AAZ72 X X No Fix

Logical Processor May Use Incorrect VPID after VM Entry That

Returns from SMM

AAZ73 X X No Fix

MSR_TURBO_RATIO_LIMIT MSR May R eturn Intel® Turbo Boost

Technology Core Ratio Multipliers for Non-Existent Core

Configurations

AAZ74 X X No Fix

PCI Express x16 Port Logs Bad TLP Correctable Error When

Receiving a Duplicate TLP

AAZ75 X X No Fix PCI Express x16 Root Port Incorrectly NAK's a Nullified TLP

AAZ76 X X No Fix

PCI Express Graphics Receiver Error Reported When Receiver

with L0s Enabled and Link Retrain Performed

AAZ77 X Fixed Internal Parity Error May Be Incorrectly Signaled during C6 Exit

AAZ78 X X No Fix PMIs during Core C6 Transitions May Cause the System to Hang

AAZ79 X X No Fix

2-MB Page Split Lock Accesses Combined with Complex Internal

Events May Cause Unpredictable System Behavior

AAZ80 X X No Fix

Extra APIC Timer Interrupt May Occur during a Write to the

Divide Configuration Register

AAZ81 X Fixed TXT.PUBLIC.KEY is Not Reliable

AAZ82 X Fixed

8259 Virtual Wire B Mode Interrupt May Be Dropped When it

Collides With Interrupt Acknowledge Cycle From the Preceding

Interrupt

AAZ83 X Fixed

CPUID Incorrectly Reports a C-State as Available When this

State is Unsupported

AAZ84 X X No Fix

The Combination of a Page-Split Lock Access and Data Accesses

That Are Split across Cacheline Boundaries May Lead to

Processor Livelock

AAZ85 X X No Fix Processor Hangs on Package C6 State Exit

AAZ86 X X No Fix A Synchronous SMI May Be Delayed

Errata (Sheet 4 of 5)

Number

Steppings

Status ERRATA

C-2 K-0

Summary Tables of Changes

Specification Update

AAZ87 X X No Fix

FP Data Operand Pointer May Be Incorrectly Calculated After an

FP Access Which Wraps a 4-Gbyte Boundary in Code That Uses

32-Bit Address Size in 64-bit ModeFP Data Operand Pointer Ma y

Be Incorrectly Calculated After an FP Access Which Wraps a 4-

Gbyte Boundary in Code That Uses 32-Bit Address Size in 64-bit

Mode

AAZ88 X X No Fix PCI Express Cards May Not Train to x16 Link Width

AAZ89 X X No Fix

The APIC Timer Current Count Register May Prematurely Read

0x0 While the Timer Is Still Running

AAZ90 X X No Fix IO_SMI Indication in SMRAM State Save Area May Be Lost

AAZ91 X X No Fix

FSW May Be Corrupted If an x87 Store Instruction Causes a

Page Fault in VMX Non-Root Operation

AAZ92 X X No Fix CKE May go Low Within tRFC(min) After a PD Exit

AAZ93 X X No Fix

Under Certain Low Temperature Conditions, Some Uncore

Performance Monitoring Events May Report Incorrect Results

AAZ94 X X No Fix

VM Entry to 64-Bit Mode May Fail if Bits 48 And 47 of Guest RIP

Are Different

AAZ95 X X No Fix VM Entry Loading an Unusable SS Might Not Set SS.B to 1

AAZ96 X X No Fix

Accesses to a VMCS May Not Operate Correctly If CR0.CD is Set

on Any Logical Processor of a Core

AAZ97 X X No Fix

Performance Monitor Events for Hardware Prefetches Which

Miss The L1 Data Cache May be Over Counted

AAZ98 X No Fix

Correctable and Uncorrectable Cache Errors May be Reported

Until the First Core C6 Transition

AAZ99 X X No Fix

VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL

[34:32]

AAZ100 X No Fix

DTSTemperature Data May Be Incorrect On a Return From the

Package C6Low Power State

AAZ101 X X No Fix

USB Devices May Not Function Properly With Integrated

Graphics While Running Targeted Stress Graphics Workloads

With Non-Matching Memory Configurations

AAZ102 X X No Fix

VM Entry May Omit Consistency Checks Related to Bit 14 (BS)

of the Pending Debug Exception Field in Guest-State Area of the

VMCS

AAZ103 X No Fix

Intel Turbo Boost Technology Ratio Changes May Cause

Unpredictable System Behavior

Errata (Sheet 5 of 5)

Number

Steppings

Status ERRATA

C-2 K-0

Specification Update 13

Summary Tables of Changes

§ §

Specification Changes

Number SPECIFICATION CHANGES

None for this revision of this specification update.

Specification Clarifications

Number SPECIFICATION CLARIFICATIONS

None for this revision of this specification update.

Documentation Changes

Number DOCUMENTATION CHANGES

None for this revision of this specification update.

Identification Information

Specification Update

Identification Information

Component Identification via Programming Interface

The Intel® Celeron® P4000 and U3000 Mobile Processor Series stepping can be

identified by the following processor signatures:

Notes:

1. The Extended Family, bits [27:20] are used in conjunction with the Family Code, spec ified in bits [11:8] , to

indicate whether the processor belongs to the Intel386®, Intel486®, Pe ntium®, Pe ntium Pro®, P entium®

4, or Intel® Core™ processor family.

2. The Extended Model, bits [19:16] in conjunction with the Model Number, specified in bits [7:4], are used to

identify the model of the processor within the processor’s family.

3. The Processor Type, specifie d in bits [13:12 ] indicates wh ether the proce ssor is an original OEM pr ocessor,

an OverDrive

processor, or a dual processor (capable of being used in a dual processor system).

4. The Family Code corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX register

after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the Device

ID register accessible through Boundary Scan.

5. The Model Number corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the EAX register

after the CPUID instruction is executed with a 1 in the EAX register, and the model field of the Device ID

6. The Stepping ID in bits [3:0] indicates the revision number of that model. See Table 1 for the processor

stepping ID number in the CPUID information.

When EAX is initialized to a value of ‘1’, the CPUID instruction returns the Extended

Family, Extended Model, Processor Type, Family C ode, Mode l Number and Step ping ID

value in the EAX register. Note that the EDX processor signature value after reset is

equivalent to the processor signature output value in the EAX register.

Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX

registers after the CPUID instruction is executed with a 2 in the EAX register.

The Intel® Celeron® P4000 and U3000 Mobile Processor Series can be identified by

the following register contents:

Notes:

1. The Vendor ID corresponds to Bits 15:0 of the V endor ID R egister l ocated at offset 00–01h

in the PCI function 0 configuration space.

2. The Device ID corresponds to Bits 15:0 of the Device ID Register located at Device 0 offset

02–03h in the PCI function 0 configuration space.

3. The Revision Number corresponds to Bits 7:0 of the Revision ID Register located at offset

08h in the PCI function 0 configuration space.

4. Correct Host Device ID requires firmware support.

Reserved

Extended

Family

Extended

Model

Reserved

Processor

Type

Family

Code

Model

Number

Stepping

31:28 27:20 19:16 15:14 13:12 11:8 7:4 3:0

00000000b 0010b 00b 0110 0101b xxxxb

Processor

Stepping

Vendor ID

Device ID

Revision ID

C-2 8086h 0044h 12h

K-0 8086h 0044h 18h

+ 31 hidden pages

Intel U3000, P4000 User Manual

Contents

Revision History

Preface

Summary Tables of Changes

Identification Information