Intel TAWAS Schematic

CR-1 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAG E1

8 2

[

1. COVER]

7

[2. BLOCK DIAGRAM] [3. SCH ANNOTATION & BRD INF]

D

[4. GPIO MAP] [5. USB TABLE] [6. CPU (1 OF 3)] [7. CPU (2 OF 3)] [8. CPU (3 OF 3)] [9. CPU THERMAL MONITORS AND FAN] [10. GMCH (1 OF 8)] [11. GMCH (2 OF 8)] [12. GMCH (3 OF 8)] [13. GMCH (4 OF 8)] [14. GMCH (5 OF 8)] [15. GMCH (6 OF 8)]

C

[16. GMCH (7 OF 8)] [17. GMCH (8 OF 8)] [18. CRESTLINE STRAPPINGS] [19. DDR DIMM 0] [20. DDR DIMM 1] [21. DDR TERMINATION AND THERMAL] [22. CK505 PAGE [ 1 OF 3 ]]]]] [23. CK505 PAGE [ 2 OF 3 ]]]]] [24. CK505 PAGE [ 3 OF 3 ]]]]] [25. CRT/VGA] [26. LVDS\LCD PANEL]

B

[27. S-VIDEO] [28. VGA SWTICH] [29. ICH8M (1 OF 5)] [30. ICH8M (2 OF 5)] [31. ICH8M (3 OF 5)] [32. ICH8M (4 OF 5)] [33. ICH8M STRAPS/ISOLATION] [34. ICH8M (5 OF 5)] [35. X1 MINI-PCIE 1] [36. X1 MINI-PCIE 2] [37. EXPRESS CARD CONN] [38. ICH8M DUAL SPI] [39. HDD CONNECTOR] [40.

ICH8M IDE - ODD CONNECTOR] [41. AUDIO CODEC] [42. AUDIO DECOUPLING & JACK SENSE & DMIC] [43. AUDIO SPEAKER & SUBWOOFER AMP] [44. AUDIO ANTI-POP,ANTI-THEFT CIRCUITRY] [45. AUDIO VREG] [46. LAN INTEL/NINEVEH] [47. LAN SWITCH/CONNECTORS]

8

7

6

45

[48. LAN POWER] [49. MODEM/MDC] [50. XDP] [51. KBD CONN]

. BLUETOOTH/LPC/TOUCHPAD/HOT KEY CONN]

[52 [53. CHASSIS UP SIGNAL CONN] [54. LOWER RIGHT CONN] [55. KEYBOARD CONTROLLER] [56. EC SIGNAL STUFFING OPTIONS] [57. KBC SPI/SEQUENCING] [58. MASTER SMBUS]

.TPM]

[59 [60. CORE_VR_POWER_MAP] [61. VREG: V_SM/SMVTT] [62. VREG: 1.5/1.05 CONTROLLER] [63. VREG: 1.05V OUTPUT] [64. VREG: 1.5V OUTPUT] [65. VREG: 5V/3.3V CONTROLLER] [66. VREG: 5V STANDBY OUTPUT] [67. VREG: 3.3V STANDBY OUTPUT] [68. VREG: RAIL SWITCHES 1 OF 2] [69. VREG: RAIL SWITCHES 2 OF 2] [70. VREG: V_1P25_M\V_1P05_M] [71. VREG: DISCHARGE CIRCUITRY] [72. VREG: POWER GOOD FOR CLPWRO] [73. VREG: BATTERY CHARGER PAGE 1OF 2] [74. VREG: BATTERY CHARGER PAGE 2 OF 2] [75. VREG: V_GFX CONTROLLER] [76. VREG: V_GFX OUTPUT] [77. VREG: VCCP ADP3207 CONTROLER] [78. VREG: VCCP PHASE 1 & 2] [79. VREG: VCCP DECOUPLING / 2X2 CONN] [80. MEDIA READE R CONTROLLER] [81. MEDIA READER SOCKET] [82. USB LEFT JACK] [83. PORT REP HDR] [84. MTG HOLES/JUMPERS] [85. EC GPIO MAP]

BPAGE DRAWING

[PAGE_TITLE=COVER]

65

tawas_b.sch_1.1

Fri Feb 09 14:58:59 2007

4 2

3

REVDE

SCRIPTION

REVISIONS

DF

DATECHK

T

TAWAS

FAB B

REV

TAPED OUT: 2-08-07

PBA D73802-200

IMERSION SILVER BUILD

NOTES:

1. THIS SCHEMATIC DOCUMENTS THE GENERIC PRODUCT WITH

2. RESISTORS ARE IN OHMS UNLESS OTHERWISE SPECIFIED.

3. VCC = +5V UNLESS OTHERWISE SPECIFIED.

4. * SUFFIX INDICATES ACTIVE LOW SIGNAL.

5. \I SUFFIX INDICATES SIGNAL EXITS HIERARCHICAL BLOCK.

BOM_RELEASE_DATE

DRN_BY

CHK_BY

ENGR_APVD

CUSTOM TEXT B-PAGE

6. THIS DOCUMENT ALSO EXISTS ON E LECTRONIC MEDIA.

SIGNATURE

?

3

2.0

ALL POSSIBLE CONFIGURATIONS. PLEASE REFER TO SPECIFIC PRODUCT PBA EPL FOR ITEMS S HOWN AS OPTIONAL IN THE SCHEMATIC.

INTEL

D77960-002

DOCUMENT_NUMBER

?

DATE

?

??

?

PB_NUMBER

inte

TITLE

TAWAS_FAB_B

CONFIDENTIAL

D89092

1

APVDDA

TE DATE

S

3065 BOWERS AVE SANTA CLARA, CA

95051

PAGE

REV

2.0

1/85

1

D

C

B

AA

CR-2 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAG E2

8

7

6

MEROM

45

ON_BOARD BATTERY

3

2

MODULE REV DETAILS

MODULE NAME

1

REV

DATE

ICH8M

USB

SPI

DMI X4

EC

FSB 667/

LPC

800MHZ

CONTROLER

LINK

CK 505

CARD READER CONTROLLER

PCI

533/667MHZ

SO_DIMM0

SO_DIMM1

SATA

HDD

PATA

ODD

CARD READER SLOT

PCIE

WLAN

PCIE

ROBSON/TV

PCIE

EXPRESS CARD SLOT

D

2GB

C

D

SVIDEO

VGA

CRESTLINE

HD AUDIO

VGA

TV

C

SPEAKER

AMP

MUX

MU

X

AUDIO CODEC

HEADPHONE JACK

LCI

GLCI

MICROPHONE JACK

ARRAY MICROPHONE

FLASH

B

RJ11

MDC

B

CIR

RJ45

PORT REPLICATOR

USB 1

TRANSFORMER

SIGNAL

PHY

LED

SPI FLASH

32MBIT

LAN

USB BUS

TOUCH PAD

KEYBOARD

TPM

A

USB

USB USB USB

LRCLRC URCURC

PCIE

CAMERA

XPRESS CARD

BLUE TOOTH

FINGER PRINT

A

[PAGE_TITLE=BLOCK DIAGRAM]

BPAGE DRAWING

tawas_b.sch_1.2

Wed Feb 07 17:18:03 2007

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7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

2

2.0

1

CR-3 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAG E3

VOLTAGE RAILS

POWER PLANE DESCRIPTION +VBAT

=>

D

V_5P0_STBY\G VCC V_3P3_STBY\G

AGE

VOLT 9V-12.5V

5V 5V

3.3V

7

654

3

28

1

S3COLD ACTIVE S0,S3,S4,S5

S0,S3,S4 S0 S0,S3,S4,S5

BATTERY RAIL IN MOVILE POWER MODE VR PERIPHERAL EC & PERIPHERAL

D

VCC3

V_SM V1.8S

=>

V_SM_VTT V_1P5_CORE V_1P25_CORE V_1P05_CORE

C

V_GFX

VCC_CORE

=>

THOSE W\ ARROWS ARE NOT CONFIRMED

POWER STATES

STATE

FULL ON

B

S3 (SUSPEND TO RAM)

S4 (SUSPEND TO DISK)

S5 / SOFT OFF

PCI D EVICES

DEVICE CARD READER

NET NAMING CONVENTIONS

SUFFIX

A

N =ACTIVE LOW SIGNAL

3.3V

1.8V

0.9V

1.5V

1.25V

1.05V

0.5V-1.325V

SIGNAL

IDSEL#

AD18

S0

S0,S3 S0

,S3

S0 S0 S0 S0 S0 S0

SLP_M#

HIGH HIGH

LOW

SLP_S3#

HIGH

LOW

LOWLOW

REQ/GNT# 00

REQ/GNT# A

PERIPHERAL

DDR CORE CARD READER DDR PULL UP CHIPSET POWER RAIL CHIPSET POWER RAIL CHIPSET POWER RAIL CPU CORE RAIL GFX CORE RAIL

SLP_S4#

HIGH

LOW

SLP_S5#

HIGH

LOW

+V*A

ON

OFF

+V*

ONON

ON

OFF

+V*S

ON

OFF

CLOCKS

ON

OFF

C

B

A

PREFIX H=HOST

M =DDR MEMORY TP=TEST POINT

[PAGE_TITLE=SCH ANNOTATION & BRD INFO

8

7

6

INTEL

CONFIDENTIAL

45

3

2

DOCUMENT NUMBER

PAGE

REV

1

PIN NAME GP[0] GP[1] GP[2] GP[3] GP[4]

D

GP[5] GP[6] GP[7] GP[8] GP[9] GP[10] GP[11] GP[12] GP[13] GP[14] GP[15] GP[16] GP[17] GP[18] GP[19] GP[20]

C

GP[21] GP[22] GP[23] GP[24] GP[25] GP[26] GP[27] GP[28] GP[29] GP[30] GP[31] GP[32] GP[33] GP[34] GP[35]

B

GP[36]

GP[38] GP[39] GP[40] GP[41] GP[42] GP[43] GP[44] GP[45] GP[46] GP[47] GP[48] GP[49] GP GP[51]

A

GP[52] GP[53] GP[54] GP[55]

CR-4 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAG E4

8

[50]

WELL MAIN MAIN MAIN MAIN MAIN MAIN MAIN MAIN RESUME RESUME RESUME RESUME RESUME RESUME RESUME RESUME MAIN MAIN MAIN MAIN MAIN MAIN MAIN MAIN RESUME MAIN RESUME RESUME RESUME RESUME RESUME RESUME MAIN MAIN MAI MAIN MAIN MAINGP[37] MAIN MAIN RESUM RESUME RESUME RESUME N/A N/A N/A N/A MAIN V_CPU_IO MAIN MAIN MAIN MAIN MAIN MAIN

8

TOL.

3.3V

3.3V 5V 5V 5V 5V

3.3V

N

3.3V

E

3.3V

3.3V N/A N/A N/A N/A

3.3V V_CPU_IO 5V

3.3V 5V

3.3V

PIN# AG12 AJ8 F8 G11

2

F1 B3 AJ9 AH9 AE16 AG19 AJ24 AG22 AC19 AH21 AF22 AE20 AJ14 AG83.3V AH12 AJ10 AE1 AJ12 AG10 E6 AJ27 AG18 AH27 AH25 AD16 AG17 AD12 AJ18 AH11 AE10 AG14 AG AF113.3V AG11 AF9 AJ11 AG AG15 AE15 AF15 N/A N/A N/A N/A AD10 AG29 E18 C18 B19 F18 A11 C10

13

16

1

7

PLTRST

7

DEFAULT

IN

OUT

I/O I/O

IN

NATIVE

OU

NATIVE

IN IN IN I/O

OUT

IN IN IN IN

OUT IN

NATIVE

IN

NATIVE IN OUT

RIGHT SIDE FROM DATASHEET

LEFT SID E FROM SCHEMATIC

USAGE (NETNAME)

IN

BM_BUSY_N

IN

EC_EXTSMI_N P_INTE_N

IN

P_INTF_N

IN IN

P_INTG_N

IN

P_INTH_N

IN

HP_AMP_EN

IN

EC_RUNTIME_SCI_N

IN

EC_WAKE_SCI_N

IN

TP

IN

TP SMB_ALERT_N

IN

GP12_MFG_MODE_N ENERGY_DET_GPIO13

IN

TP

IN

PM_STPPCI_ICH_N PM_DPRSLPVR_R

OUT

RF_KILL_N FWH_TBL_N

IN

BOARD_ID0 PORT_REP_DETECT

OUT

IN

SATA0GP FWH_WP_N TP

OUT

TP PM_STPCPU_ICH_N

T

TP

OUT

TP

OUT

TP USB_OC5_N USB_OC6_N USB_OC7_N PM_CLKRUN_N

OUT

TP TP

OUT OUT

CK_O BOARD_ID1

IN

BOARD_ID4 TP

IN IN

BOARD_ID2 USB_O USB_OC2_N USB_OC3_N

USB_OC4_N N/A N/A N/A N/A

IN

BOARD_ID3

H_PWRGD

P_REQ_N<1>

TP

P_REQ_N<2>

TP

P_REQ_N<3>

P_GNT_N<3>

6

E_SATA_N

C1_N

6

45

NOTES

FUNCTIONALITY NUXED WITH GPIO MY NOT BE USED FOR DESKTOP

DETECTS WHETHER PORT REPLICATOR IS CONNECTED

FUNCTIO

NALITY NUXED WITH GPIO MY NOT BE USED FOR DESKTOP

TRISTATED,UNABLE TO ACTIVELY DRIVING HIGH,NEED PULL UP

BPAGE DRAWING

tawas_b.sch_1.4

Wed Feb 07 17:18:04 2007

5

4 2

3

2

MODULE REV DETAILS

MODULE NAME

1

REV

DATE

D

C

B

A

[PAGE_TITLE=GPIO MAP]

PAGE

INTEL

CONFIDENTIAL

3

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

REV

4

2.0

1

CR-5 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE5

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

1

REV

DATE

D

USB PORT

USB_0

USB_1

C

B

USB_2

USB_3

USB_4

USB_5

USB_6

USB_7

SIGNAL NAME

USB_0_DN/DP

USB_1_DN/DP

USB_2_DN/DP

USB_3_DN/DP

USB_4_DN/DP

USB_5_DN/DP

USB_6_DN/DP

USB_7_DN/DP

GOING TO

USB JACK (CHASSIS DN SIG)

USB

USB JACK (CHASSIS UP SIG)

FINGER P (CHASSIS DN SIG)

REPLICATOR PORT

MINIPCIE FOR ROBSON

MINIPCIE FOR WLAN

EXPRESS CARD

JACK (CHASSIS UP SIG)

D

C

B

USB_8

A

8

USB_9

7

6

USB_8_DN/DP

USB_9_DN/DP

5

4 2

BLUETOOTH

CAMERA (INV CONN)

[

BPAGE DRAWING

tawas_b.sch_1.5

Wed Feb 07 17:18:04 2007

3

PAGE_TITLE=USB TABLE]

CONN

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

A

PAGE

REV

5

2.0

1

CR-6 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAG E6

8

D

C

H_STPCLK_N

29

B

IN

A

7

H_A_N<16..3>

10

BI

H_ADSTB0_N

10

BI

H_REQ_N<4..0>

10

BI

H_A_N<35..17>

10

BI

H_ADSTB1_N

10

BI

H_A20M_N

29

IN

H_FERR_N

29

OUT

H_IGNNE_N

29

R

2

R_STPCLK_N

HS_TAWAS

GND_1

GND_2

GND_3

IN

29

IN

29

IN

29

IN

HS20

1OF1

EMPTY

H_INTR H_NMI

H_SMI_N

TP_CPU_RSVD01 TP_CPU_RSVD02 TP_CPU_RSVD03 TP_CPU_RSVD04 TP_CPU_RSVD05 TP_CPU_RSVD06 TP_CPU_RSVD07 TP_CPU_RSVD08 TP_CPU_RSVD09 TP_CPU_RSVD10

R14P

1

5%

0

CH

402

1

2

3

REV=1

6

U1PR

3 4 5 6 7 8 9 10 11 12 13 14 15 16

0 1 2 3 4

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

AA4 AB2 AA3

D22

A[3]#

L5

A[4]#

L4

A[5]#

K5

A[6]#

M3

A[7]#

N2

A[8]#

J1

A[9]#

N3

A[10]#

P5

A[11]#

P2

A[12]#

L2

A[13]#

P4

A[14]#

P1

A[15]#

R1

A[16]#

M1

ADSTB[0]#

K3

REQ[0]#

H2

REQ[1]#

K2

REQ[2]#

J3

REQ[3]#

L1

REQ[4]#

Y2

A[17]#

U5

A[18]#

R3

A[19]#

W6

A[20]#

U4

A[21]#

Y5

A[22]#

U1

A[23]#

R4

A[24]#

T5

A[25]#

T3

A[26]#

W2

A[27]#

W5

A[28]#

Y4

A[29]#

U2

A[30]#

V4

A[31]#

W3

A[32]# A[33]# A[34]# A[35]#

V1

ADSTB[1]#

A6

A20M#

A5

F

ERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD[01]

N5

RSVD[02]

T2

RSVD[03]

V3

RSVD[04]

B2

RSVD[05]

C3

RSVD[06]

D2

RSVD[07] RSVD[08]

D3

RSVD[09]

F6

RSVD[10]

ADDR GROUP 0

ADDR GROUP 1

PROCHOT#

THERMAL

TH

ERMTRIP#

ICH

HCLK

RESERVED

F4

1O

DEFER#

CONTROL

RESET# RS[0]# RS[1]# RS[2]#

BPM[0]# BPM[1]# BPM[2]# BPM[3]#

XDP/ITP SIGNA LS

THERMDA THERMDC

BCLK[0] BCLK[1]

MEROM_SKT_NOHS

J4

REV=1

ADS# BNR#

BPRI#

DRDY# DBSY#

BR0#

IERR# INIT#

LOCK#

TRDY#

HIT#

HITM#

PRDY# PREQ#

TRST#

DBR#

TCK TDI TDO TMS

IC

H1 E2 G5

H5 F21 E1

F1

D20 B3

H4

C1 F3 F4 G3 G2

G6 E4

AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C2

D21 A24 B25

C7

A22 A21

0

45

H_ADS_N H_BNR_N H_BPRI_N

H_DEFER_N H_DRDY_N H_DBSY_N

H_BREQ_N

H_IERR_N H_INIT_N

H_LOCK_N

H_CPURST_N

H_RS_N<2..0>

0 1 2

H_TRDY_N

H_HIT_N H_HITM_N

XDP_BPM_N<4..0>

0 1 2 3 4

XDP_BPM_N<5> XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST_N

XDP_DBRESET_N

H_PROCHOT_N

H_THERMDA H_THERMDC

PM_THRMTRIP_N

CK_H_CPU_DP CK_H_CPU_DN

BI BI BI

IN BI BI

BI

IN

BI IN

IN

BI BI

OUT

BI

IN

OUT

IN IN

6

50

6

50

IN

24 24

IN

10 10 10

10

10 10

10

29

33

10

50

10

10 10

50

6

50

6

50

31

9 9

12

29

3

1

2

50

XDP_TCK

XDP_TRST_N

V_1P05_CPU

R1PR

56 5%

CH 402

R5PR

1

54.9 1%

CH

2

603

V_1P05_CPU

R11PR

1

68 5%

CH

2

603

R9PR

1

2

54.9

1%

CH

603

R10PR

2

1

649

1%

CH

603

IN

V_1P05_CPU

R4PR

1

54.9 1%

CH 603

678

50 79

2

MODULE REV DETAILS

NAME

MODULE

TAWAS_CORE

1

V

RE

1.02.01 2-05-07

E

DAT

D

678

50 79

IN

R2PR

1

54.9 1%

CH

22

603

C

50

OUT

50

IN

50

678

50 79

IN

77

BI

IN

B

A

BPAGE DRAWING

tawas_b.sch_1.6

Wed Feb 07 17:18:05 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

6

2.0

1

[PAGE_TITLE=CPU (1 OF 3)]

CR-7 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAG E7

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

TAWAS_CORE

1

REV

DATE

2-05-071. 02.01

D

U1PR

ROM_SKT_NOHS

BI

C

H_DSTBN_N<0>

10

BI

H_DSTBP_N<0>

10

BI

H_DINV_N<0>

10

BI

10

BI

B

H_DSTBN_N<1> H_DSTBN_N<3>

10

BI

H_DSTBP_N<1>

10

BI

H_DINV_N<1>

10

BI

H_GTLREF

7

IN

CPU_TEST1

7

IN

CPU_TEST2

7

IN

CPU_TEST4

7

IN

CPU_BSEL0

23

OUT

CPU_BSEL1

23

OUT

CPU_BSEL2

23

A

OUT

TP_CPU_TEST3

TP_CPU_TEST5 TP_CPU_TEST6

E22

0

F24

1

E26

2

G22

3

F23

4

G25

5

E25

6

E23

7

K24

8

G24

9

J24

10

J23

11

H22

12

F26

13

K22

14

H23

15

J26 H26 H25

N22

16

K25

17

P26

18

R23

19

L23

20

M24

21

L22

22

M23

23

P25

24

P23

25

P22

26

T24

27

R24

28

L25

29

T25

30

N25

31

L26 M26 N24

AD26

C23 D25 C24

AF26

AF1 A26

B22 B23 C21

ME

D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]#

D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]#

GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6

BSEL[0] BSEL[1] BSEL[2]

REV=1

DATA GRP 0

DATA GRP 2DATA GRP 3

DSTBN[2]# DSTBP[2]#

DATA GRP 1

DSTBN[3]# DSTBP[3]#

MISC

2OF4

D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]#

DINV[2]#

D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]#

DINV[3]#

COMP[0] COMP[1] COMP[2] COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

IC

SLP# PSI#

Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22

AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20

R26 U26 AA1 Y1

E5 B5 D24 D6 D7 AE6

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

H_D_N<47..32>H_D_N<15..0>

H_DSTBN_N<2> H_DSTBP_N<2> H_DINV_N<2>

H_D_N<63..48>H_D_N<31..16>

H_DSTBP_N<3> H_DINV_N<3>

COMP0 COMP1 COMP2 COMP3

H_DPRSTP_N H_DPSLP_N H_DPWR_N H_PWRGD H_CPUSLP_N H_PSI_N

OUT

1010

BI

10

BI

10

BI

10

BI

10

BI

10

BI

10

BI

10

BI

7

IN

7

IN

7

IN

7

IN

12

29

BI BI BI

IN

77 29 10

10

R8PR

77

1

1KCH5%

402

H_PWRGD_XDP

2

29

BI

50

BI

7

OUT

5079

7

IN

7

IN

7

IN

7

IN

7

IN

7

IN

CPU_TEST4

68

IN

COMP0

COMP1

COMP2

COMP3

CPU_TEST1

CPU_TEST2

V_1P05_CPU

C1PR

1

10%

.1UF

16V

EMPTY

603

2

1

R15PR

1K 1%

CH

2

603

R16PR

1

2K 1%

CH

2

603

R17PR

1

27.41% 603

R18PR

1

54.9CH1% 603

R19PR

1

27.4 603

R3PR

1

54.9 603

R6PR

1

1K

6031%EMPTY

1

R7PR

1K

EMPTY603

H_GTLREF

OUT

7

2

CH

2

1% CH

2

1% CH

2

1%

D

C

B

A

BPAGE DRAWING

tawas_b.sch_1.7

Wed Feb 07 17:18:07 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

7

2.0

1

[PAGE_TITLE=CPU (2 OF 3)]

CR-8 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAG E8

8

D

C

B

VCCP

8717879

IN IN

A10 A12 A13 A15 A17 A18 A20

B10 B12 B14 B15 B17 B18 B20

C10 C12 C13 C15 C17 C18

D10 D12 D14 D15 D17 D18

E10 E12 E13 E15 E17 E18 E20

F10 F12 F14 F15 F17 F18 F20 AA7

AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20

AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18

A7 A9

B7 B9

C9

D9

E7 E9

F7 F9

A

7

U1PR

MEROM_SKT_NOHS

VCC[001]

VCC[068]

VCC[002]

VCC[069] VCC[070]

VCC[003]

VCC[071]

VCC[004]

VCC[072]

VCC[005]

VCC[073]

VCC[006]

VCC[074]

VCC[007]

VCC[075]

VCC[008]

VCC[076]

VCC[009]

VCC[077]

VCC[010]

VCC[078]

VCC[011]

VCC[079]

VCC[012]

VCC[080]

VCC[013]

VCC[081]

VCC[014]

VCC[082]

VCC[015] VCC[016]

VCC[083]

VCC[017]

VCC[084]

VCC[018]

VCC[085]

VCC[019]

VCC[086]

VCC[020]

VCC[087]

VCC[021]

VCC[088] VCC[089]

VCC[022]

VCC[090]

VCC[023]

VCC[091]

VCC[024]

VCC[092]

VCC[025]

VCC[093]

VCC[026]

VCC[094]

VCC[027]

VCC[095]

VCC[028]

VCC[096]

VCC[029]

VCC[097]

VCC[030]

VCC[098]

VCC[031]

VCC[099]

VCC[032]

VCC[100]

VCC[033] VCC[034] VCC[035]

VCCP[01] VCCP[02]

VCC[036]

VCCP[03]

VCC[037]

VCCP[04]

VCC[038]

VCCP[05]

VCC[039]

VCCP[06]

VCC[040]

VCCP[07]

VCC[041]

VCCP[08]

VCC[042]

VCCP[09]

VCC[043]

VCCP[10]

VCC[044]

VCCP[11]

VCC[045]

VCCP[12]

VCC[046]

VCCP[13]

VCC[047]

VCCP[14]

VCC[048]

VCCP[15]

VCC[049]

VCCP[16]

VCC[050] VCC[051]

VCCA[01]

VCC[052]

VCCA[02]

VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067]

REV=1

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

VCCSENSE

VSSSENSE

3OF4

6

62

H_

VID<6..0>

VCCP

2329

32

678

OUT

5079

1

C2PR

220U 20%

2.5V TANT

2

SM

1

77 79

OU

T

2

1

2

8

16

1718

V_1P05_CPU

F

C3PR

.01UF 10% 25V

R

X7 402

R13PR

100 1%

EMPTY 402

78

71

79

1415

10 63

71

77

V_1P5_CORE

1

C4PR

10.0UF 20%

6.3V

2

X5R 1206

1

2

IN

R12PR

100 1%

EMPTY 402

V_1P05_CORE

68

IN

1832373940

16

IN

VCCP

VCC_SENSE

VSS_SENSE

FB1PR

1

7

FB2PR

N

UNK 330

1.5A BROAD

2

FB

UNK 330

1.5A BROAD

2

FB

50 79

IN

OUT

N

77

AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20

G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21

B26 C26

AD6

0

AF5

1

AE5

2

AF4

3

AE3

4

AF3

5

AE2

6

AF7

AE7

IC

62 64

87178 79

45

71

3

U1

ME

ROM_SKT_NOHS

VSS[001]

VSS[082] VSS[083]

VSS[002]

VSS[084]

VSS[003]

VSS[085]

VSS[004] VSS[005]

VSS[086]

VSS[006]

VSS[087] VSS[088]

VSS[007] VSS[008]

VSS[089]

VSS[009]

VSS[090]

VSS[010]

VSS[091]

VSS[011]

VSS[092] VSS[093]

VSS[012] VSS[013]

VSS[094]

VSS[014]

VSS[095]

VSS[015]

VSS[096] VSS[097]

VSS[016]

VSS[098]

VSS[017]

VSS[099]

VSS[018] VSS[019]

VSS[100] VSS[101]

VSS[020]

VSS[102]

VSS[021]

VSS[103]

VSS[022]

VSS[104]

VSS[023]

VSS[105]

VSS[024]

VSS[106]

VSS[025]

VSS[107]

VSS[026]

VSS[108]

VSS[027]

VSS[109]

VSS[028]

VSS[110]

VSS[029]

VSS[111]

VSS[030]

VSS[112]

VSS[031]

VSS[

VSS[032]

VSS[114]

VSS[033]

VSS[115]

VSS[034]

VSS[116]

VSS[035]

VSS[117]

VSS[036]

VSS[118]

VSS[037]

VSS[119]

VSS[038]

VSS[120]

VSS[039]

VSS[121]

VSS[040]

VSS[122]

VSS[041] VSS[042]

VSS[123]

VSS[043]

VSS[124] VSS[125]

VSS[044]

VSS[126]

VSS[045]

VSS[127]

VSS[046]

VSS[128]

VSS[047]

VSS[129]

VSS[048]

VSS[130]

VSS[049]

VSS[131]

VSS[050]

VSS[132]

VSS[051]

VSS[133]

VSS[052]

VSS[134]

VSS[053]

VSS[135]

VSS[054]

VSS[136]

VSS[055]

VSS[137]

VSS[056]

VSS[138]

VSS[057]

VSS[139]

VSS[058]

VSS[140]

VSS[059]

VSS[141]

VSS[060]

VSS[142]

VSS[061]

VSS[143]

VSS[062]

VSS[144]

VSS[063]

VSS[145]

VSS[064]

VSS[146]

VSS[065]

VSS[147]

VSS[066] VSS[067]

VSS[148] VSS[149]

VSS[068]

VSS[150]

VSS[069]

VSS[151]

VSS[070]

VSS[152]

VSS[071]

VSS[153]

VSS[072]

VSS[154]

VSS[073] VSS[074]

VSS[155]

VSS[075]

VSS[156]

VSS[076]

VSS[157]

VSS[077]

VSS[158]

VSS[078]

VSS[159]

VSS[079]

VSS[160]

VSS[080]

VSS[161]

VSS[081] VSS[162]

VSS[163]

PR

113]

2

MODULE REV DETAILS

MODULE NAME

TAWAS_CORE

REV

CAD NOTE:

PLACE ON TOP SIDE IN

CPU CAVITY

V_1P05_CPU

C5PR

.1

UF 10% 16V X7R 603

C7PR

.1UF 10% 16V X7R 603

C9PR

.1UF 10% 16V EMPTY 603

1

C6PR

.1UF 10% 16V

2

X7R 603

1

C8PR

.1UF 10% 16V

2

R

X7 603

1

C10PR

.1UF 10% 16V

2

EMPTY 603

1

2

1

2

1

2

CAD NOTE:

PLACE ON TOP SIDE SOUTH OF

CPU

1

DATE

2-05-071. 02.01

D

6

7

IN

8

50 79

C

B

A

4OF4

REV=1

IC

[PAGE_TITLE=CPU (3 OF 3)]

8

7

6

5

4 2

BPAGE DRAWING

tawas_b.sch_1.8

Thu Feb 08 10:56:06 2007

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

8

2.0

1

CR-9 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAG E9

8

7

6

45

3

VCC3

2

MODULE REV DETAILS

MODULE NAME

1

REV

DATE

VCC3

D

R25

10K

5%

R27

1

H_THERMDA

6

OUT

H_THERMDC

6

IN

499 603

R28

1

499CH1% 603

2

1%

CH

1

C6

1000P

F 10% 50V

2

X7R 603

2

CH 402

ADT_THERM_DXP

ADT_THERM_DXN

ADT_THM_N

U2

ADM1032

2

D+

3

D-

4

THERM*

5

GN

SCLK

SDATA

ALERT*

D

VDD

IC

1

8 7

THRM_ALERT_N

6

1

C5

0.

1UF 20% 16V

2

Y5V 402

1

R26

10K 5%

CH 402

2

1

R24

10K

5% CH

402

2

SMB_THRM_CLK

SMB_THRM_DATA

1

2

R29

1A

0

EM

603

PTY

PM

_THRM_N

OUT

55

BI

55

BI

33

31

C

D

C

V_3P3_STBY\G

1

R45

10K 5%

2

CH 402

CPU_FAN_TACH

B

26

3233

45616265666869

707576777883

IN

V_5P0_STBY\G

R460BU

10K

5% CH

402

1

C93

.1

UF 10% 10V

2

X5R 402

CPU_FAN_PWM_N

C94

4.7UF 10%

6.3V EMPTY 603

1

C943

1UF

20%

16V

2

Y5V 805

OUT

A36295-007

J39

1X3HDR

1 2 3

HDR

IN

55

31

32 333740 44 50 52

22 26 54 55 56 65 67 68 69 72 75 77

B

3

Q100

D

A

CPU_FAN_PWM

55

IN

1

BSS138N

FET

S

G

2

A

[PAGE_TITLE=CPU THERMAL MONITORS AND FAN]

BPAGE DRAWING

tawas_b.sch_1.9

Thu Feb 08 17:24:51 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

9

2.0

1

CR-10 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE10

8

7

6

45

3

U1UB

H_D_N<63..0>

7

D

77

32

2329

15

16

17

18

6263

71

V_1P05_CORE

81014

IN

H_RCOMP

10

OUT

C

1

24.9 603

1

54. 402

1

54. 402

R34UB

R35UB

9

R36UB

9

2

1% CH

2

1%

CH

H_SCOMP

2

H_SCOMP_N

OUT

10

BI

COMPS

V_1P05_CORE

161718

2329

32

B

A

8101415

IN

6263

7177

32

1

R32UB

221 1%

CH

2

603

1

R33UB

100 1%

2

CH 603

15

16

17

182329

71

77

H_SWING

1

C49UB

0.1UF 20% 16V

2

Y5V 402

V_1P05_CORE

8

1014

IN

6263

OUT

1

2

10

R37UB

1K 1%

CH 603

10 10

50

H_SWING

IN

H_RCOMP

IN

H_SCOMP

IN

H_SCOMP_N

IN

H_CPURST_N

6

OUT

H_CPUSLP_N

7

OUT

H_VREF

1

2

R38UB

2K

1%

CH 603

1

C53UB

.1UF 10% 10V

2

X5R 402

E2

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

AD12

32 33 34 35 36

AC14

37

AD11

38

AC11

39 40 41 42 43 44 45 46 47 48 49

AJ14

50 51

AE11

52

AH12

53 54 55 56 57 58 59 60 61 62

AH13

63

M10 N12

P13

W10

AE3 AD9 AC9 AC7

AB2 AD7 AB1

AC6 AE2 AC5 AG3 AJ9 AH8

AE9

AJ5 AH5 AJ6 AE7 AJ7 AJ2 AE5 AJ3 AH2

H_D#_0

G2

H_D#_1

G7

H_D#_2

M6

H_D#_3

H7

H_D#_4

H3

H_D#_5

G4

H_D#_6

F3

H_D#_7

N8

H_D#_8

H2

H_D#_9 H_D#_10 H_D#_11

N9

H_D#_12

H5

H_D#_13 H_D#_14

K9

H_D#_15

M2

H_D#_16 H_D#_17

Y8

H_D#_18

V4

H_D#_19

M3

H_D#_20

J1

H_D#_21

N5

H_D#_22

N3

H_D#_23

W6

H_D#_24

W9

H_D#_25

N2

H_D#_26

Y7

H_D#_27

Y9

H_D#_28

P4

H_D#_29

W3

H_D#_30

N1

H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42

Y3

H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63

B3

H_SWING

C2

H_RCOMP

W1

H_SCOMP

W2

H_SCOMP#

B6

H_CPURST#

E5

H_CPUSLP#

B9

H_AVREF

A9

H_DVREF

HOST

BPAGE DRAWING

Wed Feb 07 17:18:09 2007

CRESTLINE 1.0

8

7

6

5

4 2

H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8

H_A#_9 H_A H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35

H_ADS#

H_ADSTB#_0 H_ADSTB#_1

H_BNR# H_BPRI# H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR# H_DRDY#

H_HIT# H_HITM# H_LOCK# H_TRDY#

H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3

H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3

H_DSTBP#_0 H_DS

TBP#_1 H_DSTBP#_2 H_DSTBP#_3

H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4

H_RS#_0 H_RS#_1 H_RS#_2

1OF10

tawas_b.sch_1.10

3

J13 B11 C11 M11 C15 F16 L13 G17

#_10

C14 K16 B13 L16 J17 B14 K19 P15 R17 B16 H20 L19 D1

7 M17 N16 J19 B18 E19 B17 B15 E17 C18 A19 B19 N19

G12 H17 G20 C8 E8 F12 D6 C10 AM5 AM7 H8 K7 E4 C6 G10 B7

K5 L2 AD13 AE13

M7 K3 AD2 AH11

L7 K2 AC2 AJ10

M14 E13 A11 H13 B12

E12 D7 D8

IC

[PAGE_TITLE=GMCH (1 OF 8)]

2

H_A_N<35..3>

3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

30

31

32

33

34

35

H_ADS_N

H_ADSTB0_N

H_ADSTB1_N

H_BNR_N H_BPRI_N H_BREQ_N H_DEFER_N

H_DBSY_N CK_H_MCH_DP CK_H_MCH_DN

H_DPWR_N

H_DRDY_N

H_HIT_N

H_HITM_N

H_LOCK_N

H_TRDY_N

H_DINV_N<3..0>

0 1 2

3

H_DSTBN_N<3..0>

0 1 2

3

H_DSTBP_N<3..0>

0 1 2

3

H_REQ_N<4..0>

0 1 2

3

4

H_RS_N<2..0>

0 1 2

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

1

MODULE REV DETAILS

MODULE NAME

TAWAS_CORE

BI

BI BI BI BI

OU

T

BI

OUT

BI IN IN

OUT

BI BI BI IN

OUT

BI

OUT

DOCUMENT_NUMBER

1.02.01 2-05-07

6

6 6 6 6 6 6 6 6

24 24 7

6

6 6

7

6

D89092

REV

PAGE

10

1

DATE

REV

2.0

D

C

B

A

D

C

B

A

28

CR-11 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE11

8

_BKLTCTL

L

26

OUT

L_BKLTEN

26

OUT

L_CTRL_CLK

1226

OUT

L_CTRL_DATA

1226

OUT

L_DDC_CLK

26

BI

L_DDC_DATA

26

BI

26

R41UB

1

R43UB

1

150 402

OUT OUT OUT

46UB

R

1

25 25

1% CH

2

1%

CH

26 26 26 26

26 26 26

2

1% CH

2

BI BI

OUT

LVDS_IBG

BI BI BI BI

BI BI BI

27

OUT

27

OUT

27

OUT

R42UB

1

150 402

CRT_DDC_CLK CRT_DDC_DATA

402

1.3KCH1% 603

402

CRT_BLUE CRT_GREEN CRT_RED

R48UB

1

39

R47UB

1

R49UB

1

39

R63UB

2

1

2.

1%

43K

CH

402

BOM NOTE:

MOD TO 2.37K OHM 1% IPN A93548-283

150 402

28 28 28

R44UB

2

1

1%

150

CH

402

150

402

R45UB

2

1

1%

150

CH

402

CRT_HSYNC

OUT

CRT_VSYNC

OUT

8

R40UB

L_VDDEN

1

0 603

TP_LVDS_VBG

LA_CLK_DN LA_CLK_DP LB_CLK_DN LB_CLK_DP

LA_DATA0_DN LA_DATA1_DN LA_DATA2_DN

LA_DATA0_DP LA_DATA1_DP LA_DATA2_DP

LB_DATA0_DN LB_DATA1_DN LB_DATA2_DN

LB_DATA0_DP LB_DATA1_DP LB_DATA2_DP

TVA_DAC TVB_DAC TVC_DAC

2

1%

CH

HSYNC

2

5% CH

CRTIREF

2

VSYNC

2

5% CH

2

1A CH

7

L_VDD_EN_R

7

6

U1UB

CRESTLINE 1.0

J40

L_BKLT_CTRL

H39

L_BKLT_EN

E39

L_CTRL_CLK

E40

L_CTRL_DATA

C37

L_DDC_CLK

D35

L_DDC_DATA

K40

L_VDD_EN

L41

LVDS_IBG

L43

LVDS_VBG

N41

LVDS_VREFH

N40

LVDS_VREFL

D46

LVDSA_CLK#

C45

LVDSA_CLK

D44

LVDSB_CLK#

E42

LVDSB_CLK

G51

LVDSA_DATA#_0

E51

LVDSA_DATA#_1

F49

LVDSA_DATA#_2

G50

LVDSA_DATA_0

E50 L50

LVDSA_DATA_1

F48

LVDSA_DATA_2

G44

LVDSB_DATA#_0

7

B4

LVDSB_DATA#_1

B45

LVDSB_DATA#_2

E44

LVDSB_DATA_0

A47

LVDSB_DATA_1

A45

LV

DSB_DATA_2

E27

TVA_DAC

G27

TVB_DAC

K27

TVC_DAC

F27

TVA_RTN

J27

TVB_RTN

L27

TVC_RTN

M35

TP_TV_DCONSEL_0

TP_TV_DCONSEL_1

P33

H32 G32 K29 J29 F29 E29

K33 G3 F33 C32 E33

5

TV_DCONSEL_0 TV_DCONSEL_1

CRT_BLUE CRT_BLUE# CRT_GREEN CRT_GREEN# CRT_RED CRT_RED#

CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC

LVDS

TV

VGA

PEG_COMPI PEG_COMPO

PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8

PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15

PCI-EXPRESS GRAPHICS

PEG_RX_10

PEG_RX_11

PEG_RX_12

PEG_RX_13

PEG_RX_14

PEG_RX_15

PEG_TX#_0

PEG_TX#_1

PEG_TX#_2

PEG_TX#_3

PEG_TX#_4

PEG_TX#_5

PEG_TX#_6

PEG_TX#_7

PEG_TX#_8

PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15

PEG_TX_10

PEG_TX_11

PEG_TX_12

PEG_TX_13

PEG_TX_14

PEG_TX_15

3OF10

6

PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9

PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9

45

R39UB

2

VCC_PEG

16

17

IN

N43

PEG_COMP

M43

TP_PEG_RX_N<0>

J51

TP_PEG_RX_N<1>

L51

TP_PEG_RX_N<2>

N47

TP_PEG_RX_N<3>

T45

TP_PEG_RX_N<4>

T50

TP_PEG_RX_N<5>

U40

TP_PEG_RX_N<6>

Y44

TP_PEG_RX_N<7>

Y40

TP_PEG_RX_N<8>

AB51

TP_PEG_RX_N<9>

W49

TP_PEG_RX_N<10>

AD44

TP_PEG_RX_N<11>

AD40

TP_PEG_RX_N<12>

AG46

TP_PEG_RX_N<13>

AH49

TP_PEG_RX_N<14>

AG45

TP_PEG_RX_N<15>

AG41

TP_PEG_RX<0>

J50

TP_PEG_RX<1> TP_PEG_RX<2>

M47

TP_PEG_RX<3>

U44

TP_PEG_RX<4>

T49

TP_PEG_RX<5>

T41

TP_PEG_RX<6>

W45

TP_PEG_RX<7>

W41

TP_PEG_RX<8>

AB50

TP_PEG_RX<9>

Y48

TP_PEG_RX<10>

AC45

TP_PEG_RX<11>

AC41

TP_PEG_RX<12>

AH47

TP_PEG_RX<13>

AG49

TP_PEG_RX<14>

AH45

TP_PEG_RX<15>

AG42

TP_P_TXN0

N45 U39

TP_P_TXN1 TP_P_TXN2

U47 N51

TP_P_TXN3

R50

TP_P_TXN4

T42

TP_P_TXN5

Y43

TP_P_TXN6

W46

TP_P_TXN7 TP_P_TXN8

W38

TP_P_TXN9

AD39 AC46

TP_P_TXN10 TP_P_TXN11

AC49

TP_P_TXN12

AC42

TP_P_TXN

AH39 AE49 AH44

M45 T38 T46 N50 R51 U43 W42 Y47 Y39 AC38 AD47 AC50 AD43 AG39 AE50 AH43

TP_P_TXN14 TP_P_TXN15

TP_P_TXP0 TP_P_TXP1 TP_P_TXP2 TP_P_TXP3 TP_P_TXP4 TP_P_TXP5 TP_P_TXP6 TP_P_TXP7 TP_P_TXP8 TP_P_TXP9 TP_P_TXP10 TP_P_TXP11 TP_P_TXP12 TP_P_TXP13 TP_P_TXP14 TP_P_TXP15

13

1

9

1%

24. CH

603

61

71

IC

3

1

R52UB

1K 1%

CH 603

2

1

R54UB

3.

24K

1% CH

603

2

1

R55UB

1K 1%

CH 603

2

V_SM SM_RCOMP

11

12

14

15

1617

1920

IN

SM_RCOMP_N

12

OUT

2

V_SM

BOM NOTE:

MOD TO 3.01K OHM 1%

IPN A93550-095

1

C57UB

.01UF 10%

25V

2

X7R 402

MODULE REV DETAILS

MODULE NAME

TAWAS_CORE

111214 151617

IN

SM_RCOMP_VOH

1

2

C54UB

.01UF

10% 25V X7R 402

2

C55UB

2.2UF 10%

6.

X5R 603

SM_RCOMP_VOL

1

C58UB

2.2UF 10%

6.3V

2

X5R 603

1

2

R61UB

1%

20

CH

402

R62UB

1

2021%

402

CH

1

REV

1.02.01 2-05-07

12

OUT

3V

12

OUT

DATE

19 206171

12

OUT

D

C

B

A

[PAGE_TITLE=GMCH (2 OF 8)]

BPAGE DRAWING

tawas_b.sch_1.11

Wed Feb 07 17:18:10 2007

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

11

2.0

1

CR-12 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE12

8

11

14

ORE

15161719

19

20

61

11 11

11 11 20

21

19

21

20

21

19

21

20

21

19

21

20 20 19 19

1

R3UB

4.7K 5%

EMPTY

2

402

1

R4UB

4. 5%

2

EM 402

20

6171

D

C

71

V_1P25_C

12

1617

IN

18

32

68

CK_96M_DREF_DN

1224

IN

CK_96M_DREF_DP

1224

IN

B

71

V_1P25_C

12

16

17

IN

68

1832

1

2

CK_DREF_100M_SS_DN

12

24

IN

CK_DREF_100M_SS_DP

12

24

IN

1

VCC3

A

R67UB

10K 402

R68UB

10K 402

R69UB

10K 402

R70UB

10K 402

R71UB

10K 402

1

2

CK_

5% CH

PM_EXTTS0_N

2

5% CH

PM_EXTTS1_N

2

5% CH

L_CTRL_CLK

2

5% CH

2

L_CTRL_DATA

5% CH

2

OE_MCH_N

8

V_SM

IN

DDR_REF

IN

IN IN

BI BI

M_CLK_DDR_DN<4>

OUT

M_CLK_DDR_DN<3>

OUT

M_CLK_DDR_DN<1>

OUT

M_CLK_DDR_DN<0>

OUT

M_CLK_DDR_DP<4>

OUT

M_CLK_DDR_DP<3>

OUT

M_CLK_DDR_DP<1>

OUT

M_CLK_DDR_DP<0>

OUT

7K

PTY

R6

UB

4.

7K

5% EMPTY

402

R7UB

4.7K 5%

EMPTY 402

12

IN

121921

IN

12

IN

11

IN

11

IN

7

SM_RCOMP_VOL SM_RCOMP_VOH

SM_RCOMP_N SM_RCOMP M_ODT<3..2>

M_ODT<1..0>

M_CS_N<3..2>

M_CS_N<1..0>

M_CKE<4..3>

M_CKE<1..0>

U1UB

24

20

21

26

7

CRESTLINE 1.0

6

R73UB

1

2

1K

1%

EMPTY

402

R74UB

1

2

1K1%

EMPTY

402

2

1

0

3

4

1

0

BD39

BG37

BG20

BK16

BG16

AV23

BA25

BB23

AV29

SM_CK_0

SM_CK_4

SM_CK_1

SM_CK_3

AY32

AW30

AW25

BA23

BE29

AW23

SM_CK#_4

SM_CK#_0

SM_CK#_1

SM_CK#_3

SM_CKE_0

SM_CKE_1

SM_CKE_3

SM_CKE_4

SM_CS#_0

SM_CS#_1

DDR

MUXING

R27UB

2

5%CH0

3

BE13

SM_CS#_2

SM_CS#_3

1

402

2

1

0

BJ14

BJ15

BH18

SM_ODT_0

SM_ODT_1

SM_ODT_2

SM_MCH_VREF

3

BK31

BL15

BE16

BK14

SM_ODT_3

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH

L31 B

SM_RCOMP_VOL

H48

K44

H47

C42

AW4

B42

AR49

PEG_CLK

SM_VREF_0

SM_VREF_1

PEG_CLK#

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

CLK

RSVD

RSVD1

RSVD2

RSVD3

RSVD4

P37

R35

N35

P36

TP_MCH_RSVD_1

TP_MCH_RSVD_2

TP_MCH_RSVD_4

TP_MCH_RSVD_3

RSVD11

RSVD10

RSVD12

RSVD5

RSVD6

AR13

AR12

TP_MCH_RSVD_6

TP_MCH_RSVD_5

RSVD13

RSVD7

RSVD8

RSVD9

RSVD14

37

J12

D20

AN13

AM12

AR37

AL36

AM36

AM

TP_MCH_RSVD_14

TP_MCH_RSVD_11

TP_MCH_RSVD_10

TP_MCH_RSVD_9

TP_MCH_RSVD_8

TP_MCH_RSVD_7

TP_MCH_RSVD_12

TP_MCH_RSVD_13

23

BI

23

BI

23

BI

RSVD21

RSVD20

H10

B51

TP_MCH_RSVD_21

TP_MCH_RSVD_20

MCH_BSEL0 MCH_BSEL1 MCH_BSEL2

RSVD22

RSVD23

RSVD24

RSVD25

RSVD26

RSVD27

RSVD28

BF23

BJ20

BF19

BJ18

BK18

BH20BK22

P_MCH_RSVD_26

P_MCH_RSVD_23

T

TP_MCH_RSVD_25

T

TP_MCH_RSVD_28

TP_MCH_RSVD_27

TP_MCH_RSVD_24

TP_MCH_RSVD_22

SVD35

RSVD31

RSVD30

RSVD32

RSVD33

RSVD29

RSVD34

BH39

BE24

BJ29

BG23

BC23

BD24

TP_MCH_RSVD_33

TP_MCH_RSVD_32

TP_MCH_RSVD_34

TP_MCH_RSVD_29

TP_MCH_RSVD_30

TP_MCH_RSVD_31

RSVD41

R

RSVD36

RSVD42

RSVD43

RSVD44

RSVD37

RSVD38

D47

C48

BK20

AW20

TP_MCH_RSVD_38

TP_MCH_RSVD_35

TP_MCH_RSVD_36

TP_MCH_RSVD_37

RSVD45

RSVD39

RSVD40

A35

B37

B34 K45

C44

B36

C34

B44

TP_MCH_RSVD_42

TP_MCH_RSVD_41

TP_MCH_RSVD_40

TP_MCH_RSVD_39

TP_MCH_RSVD_45

TP_MCH_RSVD_44

TP_MCH_RSVD_43

[PAGE_TITLE=GMCH (3 OF 8)]

6

5

45

CK_96M_DREF_DP

_96M_DREF_DN

CK CK_DREF_100M_SS_DP CK_DREF_100M_SS_DN CK_PE_100M_3GPLL_DP CK_PE_100M_3GPLL_DN

303030

30

OUT

DMI_IT_MR_0_DN

DMI_IT_MR_3_DN

DMI_IT_MR_2_DN

DMI_IT_MR_1_DN

AN47

AN46

AN42

AJ38

DMI_RXN_0

DMI_RXN_1

DMI_RXN_2

DMI_RXN_3

303030

30

OUT

DMI_IT_MR_3_DP

DMI_IT_MR_2_DP

DMI_IT_MR_1_DP

DMI_IT_MR_0_DP

AN41

AJ39

AN45

AM47

DMI_RXP_0

DMI_RXP_1

DMI_RXP_2

DMI_RXP_3

30

303030

OUT

DMI_MT_IR_1_DN

DMI_MT_IR_3_DN

DMI_MT_IR_2_DN

DMI_MT_IR_0_DN

AM40

AJ41

AM44

AJ46

DMI_TXN_0

DMI_TXN_1

DMI_TXN_2

DMI_TXN_3

303030

30

OUT

DMI_MT_IR_1_DP

DMI_MT_IR_2_DP

DMI_MT_IR_0_DP

AM39

AJ42

AJ47

DMI_TXP_0

DMI_TXP_1

DMI_TXP_2

DMI

CFG

CFG_1

CFG_3

CFG_4

CFG_2

CFG_0

C23

N27

P27

C21

N24

TP_MCH_CFG_4

TP_MCH_CFG_3

4 2

CFG_5

CFG_6

CFG_7

CFG_8

CFG_9

CFG_10

L23

C20

G23

F23

R24

J20

N23

TP_MCH_CFG_7

TP_MCH_CFG_6

TP_MCH_CFG_10

TP_MCH_CFG_11

TP_MCH_CFG_8

Wed Feb 07 17:18:11 2007

CFG_11

3

6870

12

24

IN

12

24

IN

12

24

IN

12

24

IN

24

IN

24

IN

OUT

DMI_MT_IR_3_DP

AM43

DMI_TXP_3

G

RAPHICS VID

CFG_12

CFG_13

E23

J23

BPAGE DRAWING

tawas_b.sch_1.12

CFG_20

CFG_14

CFG_15

CFG_16

CFG_17

CFG_18

CFG_19

K23

L35

L32

M20

M24

N33

E20

TP_MCH_CFG_14

TP_MCH_CFG_15

TP_MCH_CFG_17

TP_MCH_CFG_18

3

V_1P25_M

1617

IN

3

210

B39

A39

E36

C38

E35

GFX_VID_0

GFX_VID_1

GFX_VID_2

GFX_VID_3

GFX_VR_EN

PM NC

PM_EXT_TS#_0

PM_EXT_TS#_1

PWROK

RSTIN#

PM_DPRSTP#

THERMTRIP#

L39

L36

J36

DPRSLPVR

N20

G36

AV20

AW49

RST_IN_MCH+_N

100 402

PM_BM_BUSY#

G41

2

R51UB

1

1K 1%

CH

2

402

1

C56UB

.1UF 10% 16V

2

X7R 603

R9UB

1

0

402

CLPWROK_MCH_R

AM50

AM49

AN49

AK50

AT43

CL_CLK

CL_DATA

CL_RST#

CL_VREF

CL_PWROK

ME

NC_1

NC_2

NC_4

NC_5

NC_3

BL50

BK50

BL49

BJ51

BK51

TP_MCH_NC3

TP_MCH_NC5

TP_MCH_NC2

TP_MCH_NC1

TP_MCH_NC4

H_DPRSLPVR

PM_THRMTRIP_N

R50UB

PLTRST_N

2

1

DELAY_VR_PWRGOOD

5%

PM_EXTTS1_N

CH

PM_EXTTS0_N H_DPRSTP_N PM_BMBUSY_N MCH_CFG_20 MCH_CFG_19

MCH_CFG_16

MCH_CFG_13 MCH_CFG_12 MCH_CFG_9 MCH_CFG_5

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

MODULE REV DETAILS

NAME

MODULE

TAWAS_CORE

MCH_CLVREF

1

R53UB

390 5%

BOM NOTE:

2

CH

REPLACE R53UB WIT H 392 OHM A93550-408

603

G_VID<3..0>

INT_GFX_ENABLE

CL_CLK0

CL_DATA0

CLPWROK

2

5%

CL_RST0_N

CH

MCH_CLVREF

H35K36

G39

G40

CLK_REQ#

ICH_SYNC#

SDVO_CTRL_CLK

SDVO_CTRL_DATA

MI

SC

NC_6

NC_7

NC_8

NC_9

NC_11

NC_10

NC_12

E1

BJ1A5C51

BK1

BL3

BL2

TP_MCH_NC11

TP_MCH_NC10

TP_MCH_NC8

TP_MCH_NC12

TP_MCH_NC6

TP_MCH_NC7

TP_MCH_NC9

IN

TP_SDVO_CTRLCLK

TP_SDVO_CTRLDATA

CK_OE_MCH_N

MCH_ICH_SYNC_N

MCH_TEST1_R

MCH_TEST2_R

A37

R32

1

2

IC

TEST_1

2OF10

NC_13

NC_14

NC_15

NC_16 TEST_2

BK2

B50

A50

A49

TP_MCH_NC13

TP_MCH_NC15

TP_MCH_NC14

TP_MCH_NC16

31

IN

6

OUT

34 37

IN

31

IN

122021

IN

121921

IN

7

IN

31

OUT

18

OUT

18

OUT

18

OUT

18

OUT

18

OUT

18

OUT

18

OUT

DOCUMENT_NUMBER

D89092

12

29

29 77

V

RE

OUT OUT OUT OUT

OUT

OUT OUT

R57UB

20K 5%

CH 402

77

52 59

55

1

E

DAT

2-05-071. 02.01

D

75

14

75

31

72

IN

31

12

IN

12

24

1

2

31

R56UB

0 5%

CH 402

C

B

A

PAGE

REV

12

2.0

1

CR-13 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE13

8

D

M_A_DQ<63..0>

19

BI

C

B

AR43

0

AW44

1

BA45

2

AY46

3

AR41

4

AR45

5

AT42

6

AW47

7

BB45

8

BF48

9

BG47

10

BJ45

11

BB47

12

BG50

13

BH49

14

BE45

15

AW43

16

BE44

17

BG42

18

BE40

19

BF44

20

BH45

21

BG40

22

BF40

23

AR40

24

AW40

25

AT39

26

AW36

27

AW41

28

AY41

29

AV38

30

AT38

31

AV13

32

AT13

33

AW11

34

AV11

35

AU15

36

AT11

37

BA13

38

BA11

39

BE10

40

BD10

41

BD8

42

AY9

43

BG10

44

AW9

45

BD7

46

BB9

47

BB5

48

AY7

49

AT5

50

AT7

51

AY6

52

BB7

53

AR5

54

AR8

55

AR9

56

AN3

57

AM8

58

AN10

59

AT9

60

AN9

61

AM9

62

AN11

63

A

7

SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63

U1UB

CRESTLINE 1.0

DDR SYSTEM MEMORY A

4OF10

SA_BS_0 SA_BS_1 SA_BS_2

SA_CAS#

SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6

SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13

SA_RAS#

SA_RCVEN#

SA_WE#

6

M_B_DQ<63..0>

20

BI

M_A_DM<7..0>

0 1 2

3 4 5 6 7

M_A_DQS_DP<7..0>

0 1 2

3 4 5 6 7

M_A_DQS_DN<7..0>

0 1 2

3 4 5 6 7

M_A_A<13..0>

0 1 2

3 4 5 6 7 8 9 10 11 12 13

M_A_BS<0> M_A_BS<1> M_A_BS<2>

M_A_CAS_N

M_A_RAS_N

M_A_WE_N

OUT OUT OUT

OUT OUT

OUT

19 21 19 21 19 21

19 21

19

BI

19

BI

21

19

BI

19 21

BB19 BK19 BF29

BL17

AT45 BD44 BD42 AW38 AW13 BG8 AY5 AN6

AT46 BE48 BB43 BC37 BB16 BH6 BB2 AP3 AT47 BD47 BC41 BA37 BA16 BH7 BC1 AP2

BJ19 BD20 BK27 BH28 BL24 BK28 BJ27 BJ25 BL28 BA28 BC19 BE28 BG30 BJ16

BE18 AY20

BA19

TP_SA_RCVEN_N

IC

45

AP49

0

AR51

1

AW50

2

AW51

3

AN51

4

AN50

5

AV50

6

AV49

7

BA50

8

BB50

9

BA49

10

BE50

11

BA51

12

AY49

13

BF50

14

BF49

15

BJ50

16

BJ44

17

BJ43

18

BL43

19

BK47

20

BK49

21

BK43

22

BK42

23

BJ41

24

BL41

25

BJ37

26

BJ36

27

BK41

28

BJ40

29

BL35

30

BK37

31

BK13

32

BE11

33

BK11

34

BC11

35

BC13

36

BE12

37

BC12

38

BG12

39

BJ10

40 41 42 43 44

BK10

45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

BL9 BK5 BL BK9

BJ8 BJ6 BF4 BH5 BG1 BC2 BK3 BE4 BD3 BJ2 BA3 BB3 AR1 AT3 AY2 AY3 AU2 AT2

SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42

5

SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63

3

U1UB

CRESTLINE 1.0

SYSTEM MEMORY B

DDR

5OF10

SB_BS_0 SB_BS_1 SB_BS_2

SB_CAS#

SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7

SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6

SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7

SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13

SB_RAS#

SB_RCVEN#

SB_WE#

IC

AY17 BG18 BG36

BE17

AR50 BD49 BK45 BL39 BH12 BJ7 BF3 AW2

AT50 BD50 BK46 BK39 BJ12 BL BE2 AV2 AU50 BC50 BL45 BK38 BK12 BK7 BF2 AV3

BC18 BG28 BG25 AW17 BF25 BE25 BA29 BC28 AY28 BD37 BG17 BE37 BA39 BG13

AV16 AY18

BC17

7

2

0 1 2

3 4 5 6 7

0 1 2

3 4 5 6 7 0 1 2

3 4 5 6 7

0 1 2

3 4 5 6 7 8 9 10 11 12 13

TP_MB_RCVEN_N

1

MODULE REV DETAILS

MODULE NAME

TAWAS_CORE

M_B_BS<0> M_B_BS<1> M_B_BS<2>

M_B_CAS_N

M_B_DM<7..0>

M_B_DQS_DP<7..0>

M_B_DQS_DN<7..0>

M_B_A<13..0>

M_B_RAS_N

M_B_WE_N

REV

1.02.01 2-05-07

20

21

OUT

20

21

OUT

20

21

OUT

20

21

OUT

20

OUT

20

BI

20

BI

20

BI

20

21

OUT

20

21

OUT

DATE

D

C

21

B

A

BPAGE DRAWING

tawas_b.sch_1.13

Wed Feb 07 17:18:12 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

13

2.0

1

[PAGE_TITLE=GMCH (4 OF 8)]

CR-14 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE14

8

7

6

45

3

BOM NOTE:

REPLACE C63UB AND C64UB WITH

1823

D

62637177

IN

29

32

V_1P05_CORE

81015

16

17

C

BOM NOTE:

75

V_GFX

15

IN

71 76

REPLACE C68UB WITH 0.47UF IPN 602433-015

1

C67UB

C68UB

220UF

4700PF

20%

2.5V

50V

2

PTY

EM

X7

2

7343

R

603

B

BOM NOTE:

REPLACE C73UB AND C74UB WITH

V_1P05_M

14

70

IN

A

0.22UF IPN 602433-021

1

72UB

C

22UF 20%

6.3V

2

X5R 805

0.22UF IPN 602433-021

1

C62UB

1

C59UB

220UF

22U

T

1U

F

3V

73UB

2

1

2

F

20%

6.3V X5R 805

C70UB

10UF 20%

6.3V X5R 805

1

2

C

2200PF 5% 25V COG 603

20%

2.5V TAN

2

SM

1

C69UB

20%

6.

2

X5R 603

1

C

2200PF 5% 25V

2

COG 603

74UB

U1UB

CRESTLINE 1.0

C63UB

2200P 5% 25V COG 603

C60UB

22U

F

20%

6.3V X5R 805

1

2

1

F

2

1

C71UB

.1

UF 10% 10V

2

X5R 402

5UB

C7

.1UF 10% 10V X5R 402

1

2

1

2

C64UB

2200P 5% 25V COG 603

1

2

1

2

F

C

.1UF 10% 10V X5R 402

C61UB

.1 10%

10V X5R 402

76UB

1

C65UB

.1

UF 10% 10V

2

X5R 402

UF

1

C77UB

.1UF 10% 10V

2

X5R 402

AB33 AB36 AB37 AC33 AC35 AC36 AD35 AD36 AF33 AF36 AH33 AH35 AH36 AH37 AJ33 AJ35 AK33 AK35 AK36 AK37 AD33 AJ36 AM35 AL33 AL35 AA33 AA35 AA36 AP35 AP36 AR35 AR36

AL24 AL26 AL28 AM26 AM28 AM29 AM31 AM32 AM33 AP29 AP31 AP32 AP33 AL29 AL31 AL32 AR31 AR32 AR33

Y32 Y33 Y35 Y36 Y37 T30 T34 T35 U29 U31 U32 U33 U35 U36 V32 V33 V36 V37

VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8 VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31 VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 VCC_NCTF_39 VCC_NCTF_40

CC_NCTF_41

V VCC_NCTF_42 VCC_NCTF_43 VCC_NCTF_44 VCC_NCTF_45 VCC_NCTF_46 VCC_NCTF_47 VCC_NCTF_48 VCC_NCTF_49 VCC_NCTF_50

VCC_AXM_NCTF_1 VCC_AXM_NCTF_2 VCC_AXM_NCTF_3 VCC_AXM_NCTF_4 VCC_AXM_NCTF_5 VCC_AXM_NCTF_6 VCC_AXM_NCTF_7 VCC_AXM_NCTF_8 VCC_AXM_NCTF_9 VCC_AXM_NCTF_10 VCC_AXM_NCTF_11 VCC_AXM_NCTF_12 VCC_AXM_NCTF_13 VCC_AXM_NCTF_14 VCC_AXM_NCTF_15 VCC_AXM_NCTF_16 VCC_AXM_NCTF_17 VCC_AXM_NCTF_18 VCC_AXM_NCTF_19

VCC NCTF

POWER

VCC AXM NCTF

VSS NCTF

VSS SCBVCC AXM

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8

VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_

NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21

VSS_SCB1 VSS_SCB2 VSS_SCB3 VSS_SCB4 VSS_SCB5 VSS_SCB6

VCC_AXM_1 VCC_AXM_2 VCC_AXM_3 VCC_AXM_4 VCC_AXM_5 VCC_AXM_6 VCC_AXM_7

T27 T37 U24 U28 V31 V35 AA19 AB17 AB35 AD19 AD37 AF17 AF35 AK17 AM17 AM24 AP26 AP28 AR15 AR19 AR28

A3 B2 C1 BL1 BL51 A51

AT33 AT31 AK29 AK24 AK23 AJ26 AJ23

BOM NOTE:

REPLACE C79UB WITH

IPN C71601-001

12

75

V_1P05_M

IN

1

C79UB

F

330U 20%

6.3V TANT

2

7343

G_VID<3..0>

14

70

1

2

C80UB

22UF 20%

6.

3V X5R 805

2

MODULE REV DETAILS

MODULE NAME

TAWAS_CORE

V_SM

2

0

1

2

3

C81UB

22UF 20%

6.3V X5R 805

R77UB

1

22K 402

R78UB

1

22K 402

R79UB

1

22K 402

R80UB

1

22K 4025%CH

IN

111215

11

2

5% CH

2

5% CH

2

5% CH

2

C78UB

.1UF 10% 10V X5R 402

1.02.01

16 17

1

REV

19 206171

VCC3

2-05-07

DATE

D

C

B

A

6OF10

IC

BPAGE DRAWING

tawas_b.sch_1.14

Wed Feb 07 17:18:14 2007

8

7

6

5

4 2

3

[PAGE_TITLE=GMCH (5 OF 8)]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

14

1

REV

2.0

CR-15 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE15

8

7

6

45

3

D

7576

IN

V_GFX

14

1571

7

AB19

AC16

Y28

U17

U19

U20

U23

U26

V16

V17

V19

T18

T19

T22

T23

T25

U15

T21

U16

T17

U21

V20

V23

V24

V21

Y23

Y15

Y16

Y17

Y19

Y20

Y24

Y26

Y21

AC17

Y29

AB16

AA16

AA1

AC19

AD15

AD16

AD17

AF16

AF19

AJ19

AH15

AH16

AH17

AJ16

AJ17

AL21

AL23

AM21

AM20

AP15

AP17

AP16

AM16

AM23

AM19

AM15

AL16

AK16

AK19

AL17

AL19

AL20

AR21

AP21

AP23

AP24

AP19

AP20

V28

AR23

AR24

AR26

AR20

V26

BC39

AW45

BD17

BD4

AW8

BE39

Y31

V29

C

VCC_SM_LF5

VCC_SM_LF4

VCC_SM_LF3

VCC_SM_LF2

VCC_SM_LF6

VCC_SM_LF1

U1UB

VCC_AXG_NCTF_1

VCC_AXG_NCTF_2

VCC_AXG_NCTF_9

VCC_AXG_NCTF_8

VCC_AXG_NCTF_7

VCC_AXG_NCTF_6

VCC_AXG_NCTF_5

VCC_AXG_NCTF_4

VCC_AXG_NCTF_3

VCC_AXG_NCTF_10

VCC_AXG_NCTF_17

VCC_AXG_NCTF_16

VCC_AXG_NCTF_15

VCC_AXG_NCTF_14

VCC_AXG_NCTF_13

VCC_AXG_NCTF_12

VCC_AXG_NCTF_11

VCC_AXG_NCTF_24

VCC_AXG_NCTF_23

VCC_AXG_NCTF_22

VCC_AXG_NCTF_21

VCC_AXG_NCTF_20

VCC_AXG_NCTF_19

VCC_AXG_NCTF_18

VCC_AXG_NCTF_31

VCC_AXG_NCTF_30

VCC_AXG_NCTF_29

VCC_AXG_NCTF_28

VCC_AXG_NCTF_27

VCC_AXG_NCTF_26

VCC_AXG_NCTF_25

VCC_AXG_NCTF_38

VCC_AXG_NCTF_37

VCC_AXG_NCTF_35

VCC_AXG_NCTF_32

VCC_AXG_NCTF_36

VCC_AXG_NCTF_34

VCC_AXG_NCTF_33

VCC_AXG_NCTF_45

VCC_AXG_NCTF_44

VCC_AXG_NCTF_43

VCC_AXG_NCTF_42

VCC_AXG_NCTF_41

VCC_AXG_NCTF_40

VCC_AXG_NCTF_39

VCC_AXG_NCTF_52

VCC_AXG_NCTF_51

VCC_AXG_NCTF_50

VCC_AXG_NCTF_49

VCC_AXG_NCTF_48

VCC_AXG_NCTF_47

VCC_AXG_NCTF_46

VCC_AXG_NCTF_59

VCC_AXG_NCTF_57

VCC_AXG_NCTF_56

VCC_AXG_NCTF_55

VCC_AXG_NCTF_54

VCC_AXG_NCTF_53

VCC_AXG_NCTF_61

VCC_AXG_NCTF_63

VCC_AXG_NCTF_64

VCC_AXG_NCTF_58

VCC_AXG_NCTF_65

VCC_AXG_NCTF_60

VCC_AXG_NCTF_62

VCC_AXG_NCTF_72

VCC_AXG_NCTF_70

VCC_AXG_NCTF_68

VCC_AXG_NCTF_66

VCC_AXG_NCTF_67

VCC_AXG_NCTF_69

VCC_AXG_NCTF_71

VCC_AXG_NCTF_73

VCC_AXG_NCTF_75

VCC_AXG_NCTF_77

VCC_AXG_NCTF_79

VCC_AXG_NCTF_80

VCC_AXG_NCTF_82

VCC_AXG_NCTF_83

VCC_AXG_NCTF_81

VCC_AXG_NCTF_78

VCC_AXG_NCTF_76

VCC_AXG_NCTF_74

VCC SM LF

VCC GFX NCTF

VCC_SM_LF1_C VCC_SM_LF2_C VCC_SM_LF3_C VCC_SM_LF4_C VCC_SM_LF5_C VCC_SM_LF6_C VCC_SM_LF7_C

AT6

VCC_SM_LF7

2

MODULE REV DETAILS

NAME

MODULE

TAWAS_CORE

BOM NOTE:

REPLACE C84UB AND C85UB WITH 0.22UF IPN 602433-021

1

2

C83UB

.1UF 10% 10V X5R 402

2

C84UB

2200PF 5% 25V COG 603

1

2

C85UB

2200PF 5% 25V COG 603

1

C82UB

.1UF 10%

10V X5R 402

IC

F10

7O

RE

1.02.01 2-05-07

1

C86UB

.47UF 10%

6.3V

2

X5R 402

1

2

1

V

C87UB

1.00UF

20%

6.3V X5R 402

1

2

C88UB

1.00UF 20%

6.3V X5R 402

E

DAT

D

C

CRESTLINE 1.0

CORE

VCC

POWER

VCC SM

B

VCC_3

VCC_4

VCC_2

VCC_1

AT35

AT34

V_1P05_CORE

81014

161718

2329

32

62

IN

63

7177

VCC_9

VCC_8

VCC_7

VCC_6

VCC_5

AC32

AK32

AJ28

AH28

AJ31

AC31

AH32

VCC_10

AH31

VCC_11

AH29

VCC_12

AF32

VCC_13

R30

VCC_SM_1

VCC_SM_5

VCC_SM_4

VCC_SM_3

VCC_SM_2

VCC_SM_8

VCC_SM_7

VCC_SM_6

VCC_SM_15

VCC_SM_14

VCC_SM_13

VCC_SM_12

VCC_SM_11

VCC_SM_9

VCC_SM_10

VCC_SM_22

VCC_SM_21

VCC_SM_19

VCC_SM_18

VCC_SM_17

VCC_SM_16

VCC_SM_20

VCC_SM_29

VCC_SM_28

VCC_SM_27

VCC_SM_26

VCC_SM_25

VCC_SM_24

VCC_SM_23

5

BG35 AH19

BJ33

BJ32

BG32

BE35

BE32

BD35

BA3

AW35

AY35

BA32

BA33

BB33

BC32

AU33

AU35

AV33AW33

AU32

BC33

BF33

BC35

BD32

BE33

BF34

BG33

BH32

BH34

BH35

VCC_SM_36

VCC_SM_35

VCC_SM_34

VCC_SM_33

VCC_SM_32

VCC_SM_31

VCC_SM_30

BK32

BL33

BK35

BK34

BK33

BJ34

AU30

VCC_AXG_5

VCC_AXG_4

VCC_AXG_3

VCC_AXG_2

VCC_AXG_1

R20

T14

W13

W14

Y12

A

11

12

1416

17

19206171

14

1571

7576

V_SM

IN

V_GFX

IN

VCC GFX

VCC_AXG_12

VCC_AXG_11

VCC_AXG_9

VCC_AXG_8

VCC_AXG_7

VCC_AXG_6

VCC_AXG_10

VCC_AXG_14

AA20

AA23

AA26

AA28

AB24

AB29

AC20

AB21

AC21

VCC_AXG_21

VCC_AXG_17

VCC_AXG_15

VCC_AXG_16

AC23

AC26

AC28

AC24

VCC_AXG_25

VCC_AXG_20

AC29

AD20

AD23

AD24

AD28

AF26

AF21

AA31

VCC_AXG_26

VCC_AXG_24

VCC_AXG_23

VCC_AXG_22

VCC_AXG_19

VCC_AXG_18

VCC_AXG_13

VCC_AXG_33

VCC_AXG_31

VCC_AXG_27

VCC_AXG_32

VCC_AXG_34

VCC_AXG_30

VCC_AXG_29

VCC_AXG_28

AH20

AH23

AH24

AH26

AN14

AJ20

AH21

AD31

B

A

[PAGE_TITLE=GMCH (6 OF 8)]

BPAGE DRAWING

tawas_b.sch_1.15

Wed Feb 07 17:18:15 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

15

2.0

1

D

C

62 16 18

B

A

CR-16 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE16

8

71

16

OUT

16

V_3P3S_TVDAC

IN

656554-002

OUT

FB4UB

1SM2

FB

11

2

R23UB

2

1

1A

0

603

16

R24UB

1

0

R25UB

1

CH

2

1A CH

2

1ACH0

V_3P3S_TVDACC

OUT

V_3P3S_TVDACB

OUT

2

1

C25UB

.1UF 10% 10V X5R 402

C29UB

.1UF 10% 10V X5R 402

C35UB

.1UF 10% 10V X5R 402

1

2

1

2

1

2

C26UB

220PF

10% 50V X7R 402

C30UB

220PF

10% 50V X7 402

C36UB

220PF

10% 50V X7R 402

8

7

BOM NOTE:

REPLACE C90UB WITH .022UF IPN A36096-073

V_3P3S_TVDAC

16

18

62

IN

V_1P25_CORE

12

68

16171832

IN

V_3P3S_TVDACA

VCCA_TVDAC

C24UB

F

10U 20% 16V Y5V 1210

R

1

C39UB

C34UB

.1UF

220PF 10%

10% 10V

50V

2

X7R

X5R

402 402

BOM NOTE:

REPLACE C26UB, C30UB, C39UB C

36UB, WITH .022UF IPN A36096- 073

32

37

39

406264

71

6171

7

6870

81618

1920

6

SM

FB1UB

2

1

FB

656554-002

L1U

B

10UH

2

1

IND

B

L2U

10UH

1

2

IND

BOM NOTE:

REPLACE C9UB, C101UB WITH IPN TBD

17

6870

16

17

IN

15

17

V_1P25_M

12

IN

V_1P5_CORE

R72UB

1

0

1A

CH

2

603

1

R76UB

0 5%

EMPTY

2

402

11

12

14

IN

6

1

2

18

16

18

17

18

1

2

1

C9UB

470UF 20% 4V TAN

2

7343

C101UB

470UF 20% 4V TANT 7343

16

IN

12

IN

70 68 12 16

16

V_SM

1

C89UB

.1UF 10% 10V X5R

2

402

1

T

2

1

2

VCC3

V_1P25_S_PEGPLL

V_1P25_M

1

2

R60UB

21A1

0

CH

603

V_1P5_CORE

IN

V_1P5S_QDAC

IN

V_1P25_M

IN

V_1P25_S_PEGPLL

IN

R75UB

1

0

603

VCC3

R17UB

1

C90UB

220PF

0

10%

5%

50V

EMPTY

2

R

X7

402

C98UB

UF

.1 10% 10V X5R 402

C102UB

.1

UF 10% 10V X5R 402

C11UB

1

C6UB

100UF

22UF

20%

10V

6.3V

TANT

2

X5R

7343

805

VCCA_SM_CK

1

C18UB

1UF 20%

6.3V

2

X5R 603

C47UB

.1UF

10% 10V X5R 402

DESIGN NOTE:

CHECK FOR CORRECT V ALUE

2

VCCD_LVDS

1A CH

V_3P3S_CRTDAC

16

1617

1

C7UB

4.7UF 10%

6.

2

X5R 603

1

C19UB

1UF 20%

6.3V

2

X5R 603

1

2

C41UB

10UF

20%

6.3V X5R 805

5

R59

UB

1

2

1A

0

CH

603

VCCA_TVDAC

IN

V_1P25_DPLLA

V_1P25_DPLLB

V_1P25M_HPLL

IN

V_1P25M_MPLL

IN

V_1P8_TXLVDS

IN

1

C2UB

1000P 10% 50V

2

X7R 402

1

C12UB

22UF 20%

3V

6.

2

X5R 805

1

C20UB

22UF 20%

6.3V

2

X5R 805

V_3P3S_TVDACA

16

IN

V_3P3S_TVDACB

16

IN

V_3P3S_TVDACC

16

IN

V_1P5S_TVDAC_R

C52UB

220PF

10%

50V

C

31UB

X7R

.1UF

402

10% 10V X5R 402

1

C40UB

1.00UF 20%

6.3V

2

X5R 402

C21UB

.1UF 10% 10V X5R 402

C32UB

.1UF

1

2

V_3P3S_SYNC

R18UB

1

0 5%

2

EM

PTY

402

1

C3UB

.1

F

10% 10V

2

X5R 402

1

C8UB

1.00UF

20%

6.3V

2

X5R 402

1

10% 10V

2

X5R 402

1

2

45

1

C91UB

.1UF 10% 10V

2

X5R 402

J32

VCCSYNC

A33

VCCA_CRT_DAC_1

B33

VCCA_CRT_DAC_2

A30

VCCA_DAC_BG

B32

VSSA_DAC_BG

B49

V

CCA_DPLLA

H49

V

CCA_DPLLB

AL2

CCA_HPLL

V

AM2

VCCA_MPLL

A41

VCCA_LVDS

B41

UF

K50

K49

U51

AW18 AV19 AU19 AU18 AU17

AT22 AT21 AT19 AT18 AT17 AR17 AR16

BC29 BB29

C25 B25 C27 B27 B28 A28

M32 L29

N28

AN2

U48

J41 H42

LVDS

VSSA_

VCCA_PEG_BG

VSSA_PEG_BG

VCCA_PEG_PLL

VCCA_SM_1 VCCA_SM_2 VCCA_SM_3 VCCA_SM_4 VCCA_SM_5

VCCA_SM_7 VCCA_SM_8 VCCA_SM_9 VCCA_SM_10 VCCA_SM_11 V

CCA_SM_NCTF_1

VCCA_SM_NCTF_2

VCCA_SM_CK_1 VCCA_SM_CK_2

VCCA_TVA_DAC_1 VCCA_TVA_DAC_2 VCCA_TVB_DAC_1 VCCA_TVB_DAC_2 VCCA_TVC_DAC_1 VCCA_TVC_DAC_2

VCCD_CRT VCCD_TVDAC

VCCD_QDAC

VCCD_HPLL

VCCD_PEG_PLL

VCCD_LVDS_1 VCCD_LVDS_2

3

U1UB

CRESTLINE 1.0

CRT

L PL

VDS

AL

PEGASM A

POWER

K

AC

TV

D TV/CRT

LVDS

AXD

AXF

SM CK

PEG

DMI

VCC_RXR_DMI_1 VCC_RXR_DMI_2

VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8 VTT_9

VTT_10

VTT

VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22

VCC_AXD_1 VCC_AXD_2 VCC_AXD_3 VCC_AXD_4 VCC_AXD_5 VCC_AXD_6

VCC_AXD_NCTF

VCC_AXF_1 VCC_AXF_2 VCC_AXF_3

VCC_DMI

VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4

VCC_TX_LVDS

HV

VCC_HV_1 VCC_HV_2

VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4 VCC_PEG_5

VTTLF

VTTLF1 VTTLF2 VTTLF3

8OF10

1

R29UB

0

1A

EMPTY

2

603

BPAGE DRAWING

Wed Feb 07 17:18:16 2007

4 2

[PAGE_TITLE=GMCH (7 OF 8)]

tawas_b.sch_1.16

3

2

U13 U12 U11 U9 U8 U7 U5 U3 U2 U1 T13 T11 T10 T9 T7 T6 T5 T3 T2 R3 R2 R1

AT23 AU28 AU24 AT29 AT25 AT30

AR29

B23 B21 A21

AJ50

BK24 BK23 BJ24 BJ23

A43

C40

0

B4

AD51 W50 W51 V49 V50

AH50 AH51

A7 F2 AH1

IC

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

MODULE REV DETAILS

NAME

MODULE

TAWAS_CORE

RE

1.02.01 2-05-07

V_1P25_M

V_1P05_CORE

1

V_1P25M_MPLL_R

V_1P25M_AXD

V_1P25S_AXF

1

CH

1

2

FB2UB

MULTI

603

CH

C10UB

FB3UB

MU

LTI

603

C17UB

22UF 20%

3V

6. X5R

MOD R66UB TO 0.51 OHM 1%

805

IPN C49684-002

IN

2

22UF

20%

6.3V X5R 805

2

V

_1P25M_MPLL

R66UB

1

0

603

BOM NOTE:

17

V_1P25_CORE

V_1P8_SM_CK

V_1P8_TXLVDS

V_3P3S_HV

17

IN

16 17

IN

18

IN

VCC_PEG

MCH_VTTLF1 MCH_VTTLF2 MCH_VTTLF3

1

2

DOCUMENT_NUMBER

C37UB

.47UF 10%

3V

6. X5R 402

D89092

2

C38UB

.47UF 10%

6.3V X5R 402

1

V

DAT

12 161768

IN

70

810141517 18 29

32

62 637177

V_1P25M_HPLL

1

C5UB

.1

UF 10% 10V

2

X5R 402

1

C14UB

UF

.1

2

10% 10V

1A

2

X5R

CH

402

IN

1

C4UB

.1UF 10% 10V

2

X5R 402

11

17

IN

1

C33UB

.47UF 10%

6.3V

2

X5R 402

PAGE

16

1

E

23

OUT

71 12 16 183268

REV

2.0

D

16

C

17

B

A

CR-17 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE17

8

A13 A15 A17

A24 AA21 AA24 AA29 AB20 AB23

D

C

B

A

AB26 AB28 AB31 AC10 AC13

AC3 AC39 AC43 AC47

AD1 AD21 AD26 AD29

AD3 AD4 AD45 AD49

AD5 AD50

AD8 AE10 AE14

AE6 AF20 AF23 AF24 AF31

AG2 AG38 AG43 AG47 AG50

AH3 AH40 AH41

AH7

AH9 AJ11 AJ13 AJ21 AJ24 AJ29 AJ32 AJ43 AJ45 AJ49 AK20 AK21 AK26 AK28 AK31 AK51

AL1 AM11 AM13

AM3

AM4 AM41 AM45

AN1 AN38 AN39 AN43

AN5

AN7

AP4 AP48 AP50 AR1

AR2 AR39 AR44 AR47

AR7 AT10 AT14 AT41 AT49

AU1 AU23 AU29

AU3 AU36 AU49 AU51 AV39 AV48

AW1 AW12 AW16

1

8

CRESTLINE 1.0

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99

7

U1UB

VSS

9OF10

7

6

VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197

IC

VSS_198

AW24 AW29 AW AW5 AW7 AY10 AY24 AY37 AY42 AY43 AY45 AY47 AY50 B10 B20 B24 B29 B30 B35 B38 B43 B46 B5 B8 BA1 BA17 BA18 BA2 BA24 BB12 BB25 BB40 BB44 BB49 BB8 BC16 BC24 BC25 BC36 BC40 BC51 BD13 BD2 BD28 BD45 BD48 BD5 BE1 BE19 BE23 BE30 BE42 BE51 BE8 BF12 BF16 BF36 BG19 BG2 BG24 BG29 BG39 BG48 BG5 BG51 BH17 BH30 BH44 BH46 BH8 BJ11 BJ13 BJ38 BJ4 BJ42 BJ46 BK15 BK17 BK25 BK29 BK36 BK40 BK44 BK6 BK8 BL11 BL13 BL19 BL22 BL37 BL47 C12 C16 C19 C28 C29 C33 C36 C41

32

U1UB

C4 C50

D13 D24

D32 D39 D45 D49 E10 E16 E24 E28 E32 E47 F19 F36

F40 F50

G13 G16 G19 G24 G28 G29 G33 G42 G45 G48

H24 H28

H45 J11 J16

J24 J28 J33 J35 J39

K12 K47

L17 L20 L24 L28

L33 L49 M28 M42 M46 M49

M50

N11 N14 N17 N29 N32 N36 N39 N44 N49

P19

P23

P50 R4 T39 T43 T47 U41 U45 U50

6

C7

D3

F4

G1

G8

H4

J2

K8 L1

L3

M5

M9

N7

P2

P3

9

V2 V3

CRESTLINE 1.0

VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243

VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286

VSS

VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305

VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 V VSS_313

10 FO 10

SS_312

IC

6

5

45

W11 W39 W43 W47 W5 W7 Y13 Y2 Y41 Y45 Y49 Y5 Y50 Y11 P29 T29 T31 T33 R28

AA32 AB32 AD32 AF28 AF29 AT27 AV25 H50

32

1

2

Wed Feb 07 17:18:17 2007

4 2

3

15

1617

182329

7177

BOM NOTE:

REPLACE L3UB WITH 5.6NH

1

C99UB

1.00UF

20%

6.

3V

2

X5R 402

1

C103UB

1.00UF 20%

6.3V

2

X5R 402

1

C13UB

.1UF 10% 10V

2

X5R 402

R

30UB

2

1

C22UB

1000PF

10% 50V X7R 402

C27UB

10UF 20%

6.3V X5R 805

0 5%

EMPTY 402

[PAGE_TITLE=GMCH (8 OF 8)]

BPAGE DRAWING

tawas_b.sch_1.17

3

V_1P05_CORE

81014

OUT

6263

L3U

B

3.9NH 2

1

IND

1

C100UB

22.000UF 20%

6.3V

2

X5R 805

1

C1UB

10UF

20%

6.3V

2

X5R 805

1

C15UB

22.000UF 20%

3V

6.

2

X5R 805

L5UB

1UH

2

1

IND

1

C23UB

F

220U 20%

2.5V TAN

T

2

SM

L6UB

90NH

2

1

IND

1

C28UB

220UF 20%

2.

5V

TANT

2

SM

2

1

C92UB

4.7UF 20%

6.

3V

2

X5R 805

V_1P25_M

V_1P25M_AXD

R64UB

1

MU

LTI

CH

1210

R65UB

1

5%

1

CH

402

V_SM

V_1P8_TXLVDS

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

MODULE REV DETAILS

MODULE NAME

TAWAS_CORE

1

2

C93UB

4.7UF 20%

6.3V X5R 805

2

C94UB

1.0UF 10%

16V X5R 805

BOM NOTE:

REPLACE C96UB WITH 0.47UF

IPN 602433-015

2

V_1P25_CORE

BOM NOTE:

REPLACE R64UB WITH .1UH 1210

V_1P25S_AXF

L4UB

2

1

1UH

IND

2

V_1P8_SM

V_1P8_SMCK_RC

_CK

OUT

V_1P05_CORE

VCC_PEG

OUT

DOCUMENT_NUMBER

D89092

1

REV

1

C96UB

4700PF 20% 50V

2

X7

R

603

16 68 70

12

IN

16

OUT

12

16

IN

OUT

V_SM

IN

1

C16UB

10UF

20%

3V

6.

2

X5R 805

16

OUT

1112141516 17 19

IN

206171

16

8

10 1415161718

IN

23 29

32

11

16

1

DATE

2-05-071. 02.01

1

2

18 326871

16

61 71

111214 16

17 19

62 63

PAGE

17

C97UB

220UF 20%

2.5V TANT SM

15 20

71 77

REV

2.0

D

C

B

A

CR-18 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE18

8

12

MCH_CFG_5

D

7

12

1

R15UB

92K

3. 1%

EMPTY

2

603

6

MCH_CFG_9MCH_CFG_16

12

INININ

1

R16UB

92K

3. 1%

EMPTY

2

603

1

2

R21UB

3.92K 1%

EMPTY 603

45

NEED TABLES FOR EACH STRAPPING

12

INININ

MCH_CFG_12

1

2

R28UB

3.92K 1%

PTY

EM 603

406264

71

V

CC3

MCH_CFG_19

12

C

1

2

R22UB

3.92K 1%

PTY

EM 603

12

MCH_CFG_13

1

2

R26UB

3.92K 1%

PTY

EM 603

816323739

IN

3

VCC3

V_1P5_CORE

.002 1206

2

1

5% CH

FB5UB

R1

R2UB

200MA 200 UNKN

UB

CH

1

FB

BOM NOTE:

V_1P05_CORE

C51UB

.1UF 10%

10V X5R 402

CR2UB

1

30V

T23

SO EM

PTY

0.2A

3

S

CHOTTKY

V_1P05_R_D

1

R8UB

10 5%

2

EMPTY 402

V_3P3S_TVDAC

1

R20UB

0

1A

2

EM

PTY

603

VCC

1

R10UB

10K 5%

2

1

C48UB

1UF 10%

25V

2

X5R 603

2

SHDN_TVDAC

1

2

CH 402

5

1

C95UB

1UF

20%

16V EMPTY 805

U2UB

SC1563

IN

SHDN

GND

2

B

R13UB

D

S

2

3

1

100 402

Q1UB BSS138N

T

FE

5% CH

SHDN_TVDAC_R

A

75 69 37 26

IN

31 55 72

SLP_S3_N

1

G

BOM NOTE:

REPLACE R11UB WITH 17.8K 603

PN A93550-134

I

4

V_3P3S_TVDAC_R2

OUT

ADJ

SM

1

R11UB

18.2K

3

1%

2

CH 603

TVDAC_ADJ2

R12UB

1

10K 1%

2

CH 603

R58UB

2

1

1ACH0

805

1

C50UB

20%

4.0V TANT

22

BOM NOTE:

REPLACE C50UB WITH 22UF

TANTLUM 202244-073

33UF

3528

1

8101415161718

OUT

63

71

16

OUT

77

62

23 29

32

62

12

IN

CHANGE C43UB TO 0.022UF

I

PN A36096-073

16

OUT

MCH_CFG_20

VCC3

V_1P25_S_PEGPLL

1

C44UB

.1UF 10% 10V

2

X5R 402

1

R14UB

3.92K 1%

2

EMPTY 603

2

MODULE REV DETAILS

MODULE NAME

TAWAS_CORE

CR1UB

30V

1

V_1P05_S_SD

10

402

2

1%

SCHOTTKY

1

3

V_1P05_CORE

T23

SO DIO

0.2A

V_3P3S_HV

1

46UB

C

.1UF 10% 10V

2

X5R 402

V_1P5S_QDAC

1

C43UB

FB6UB

2

5% CH

2A 220 UNK

1

FB

2

V_1P25_S_PEGPLL_RC

2

220PF

10% 50V X7R 402

N

V_1P25_CORE

1

C42UB

.1UF 10% 10V

2

X5R 402

1

R5UB

1

402

R

1

19UB

0 5%

EMPTY

2

402

IN

1

C45UB

10UF 20%

3V

6.

2

X5R 805

1

REV

1.02.01 2-05-07

OUT

16

OUT

16

OUT

121617 326871

32

62 63 81014 17

18 23 29 77

DATE

71

15 16

D

C

B

A

[PAGE_TITLE=CRESTLINE STRAPPINGS]

BPAGE DRAWING

tawas_b.sch_1.18

Wed Feb 07 17:18:18 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

18

2.0

1

CR-19 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE19

8

OUT

IN IN

IN

13

IN

BI

PM_EXTTS0_N

M_ODT<1>

M_ODT<0>

M_A_DQS_DP<7..0>

M_A_DQS_DN<7..0>

M_A_DM<7..0>

63

6261605958

182

194

192

DQ<61>

DQ<62>

DQ<63>

1221

21

12

D

21

13

BOM NOTE:

M_A_DQ<63..0>

565755545351525049

191

181

189

179

176

180

<59>

DQ<60>

DQ<55>

DQ<58>

DQ<57>

DQ<56>A7DQ

174

7

484746

45

4443424140

151

157

154

152

140

142

153

159

173

175

158

160

<53>

DQ<52>

DQ<51>

DQ<50>

DQ<49>

DQ<54>

DQ<48>

DQ

143

DQ<45>

DQ<44>

DQ<47>

DQ<46>

DQ<41>

DQ<42>

DQ<43>

6

38

393736353334323130

141

136

134

124

126

135

137

12576123

DQ<38>

DQ<39>

DQ<40>

DQ<33>

DQ<37>

DQ<36>

DQ<35>

DQ<34>

DQ<32>

746275

DQ<31>

DQ<30>

29

64

DQ<29>

282726242523222120

73

6361584656

DQ<28>

DQ<24>

DQ<23>

DQ<22>

DQ<27>

DQ<26>

DQ<25>

DQ<21>

191817161514131210

36

44575545433822

DQ<18>

DQ<19>

DQ<20>

DQ<17>

DQ<14>

DQ<13>

DQ<16>

DQ<15>

11

9

37

203523

25

DQ<9>

DQ<10>

DQ<11>

DQ<12>

87654

16

14619417

DQ<6>

DQ<7>

DQ<8>

3

1

2

7

DQ<5>

DQ<1>

DQ<2>

DQ<3>

DQ<4>

45

5

147

DM5

4

130

DM4

3

67

DM3

7

185

DM7

6

170

DM6

0

5

DQ<0>

3

7

6

5

7

6

186

DQS*<7>

188

DQS<7>

167

DQS*<6>

169

DQS<6>

5

146

DQS*<5>

148

DQS<5>

1

2

0

TP_NC2_J8

120

10

52

26

NC

DM0

DM1

DM2

4

129

2

MODULE REV DETAILS

MODULE NAME

TAWAS_CORE

1

REV

DATE

2-05-071. 02.01

D

3

4

3

131

68

DQS<4>

DQS*<3>

DQS*<4>

1

2

0

1

2

0

31

13

70

DQS<3>

11

51

49

29

DQS<2>

DQS<0>

DQS<1>

DQS*<0>

DQS*<1>

DQS*<2>

TP_NC1_J8

83

NC

TP_NCTEST_J8

TP_NC4_J8

163

114

119

69

50

IO

NC

ODT0

ODT1

NC/TEST

J1MY

C

13

21

IN

13

21

IN

13

21

IN

13

21

IN

13

21

BI

12

IN

12

IN

12

IN

12

IN

12

21

IN

12

21

IN

21

12

B

33 33

61

72

A

IN

12

21

IN

13

21

IN

13

21

IN

19

IN

19

50

IN

20

21

22

IN

21

22

20

IN

50

61

71

11

12

1415

IN

17

1920

16

DDR_REF

1220

IN

4869

71

20

31

3233

IN

3539

4647

83

6171

11

12

1415

IN

16

17

1920

8

SODIMM_202P

WE*

M_A_WE_N M_A_RAS_N M_A_CAS_N M_A_BS<2>

109

M_A_A<13..0>

M_CLK_DDR_DP<0> M_CLK_DDR_DN<0> M_CLK_DDR_DP<1> M_CLK_DDR_DN<1> M_CS_N<0> M_CS_N<1>

M_CKE<0> M_CKE<1> M_A_BS<0> M_A_BS<1> SA0_DIM0 SA1_DIM0 SMB_DATA_S SMB_CLK_S

V_SM

R1MY

1

2

5%

0

1

CH

402

2

V_3P3_M

V_SM

1

C2MY

2.2UF 10%

6.3V

2

X5R 603

CAS*

RAS*

113

108

R14MY

1K 1%

EMPTY 402

BA2

85

1

R13M

1K 1%

2

EMPTY 402

1

A13

A12

A1

A14

A15

86

89909392949798

84

116

P_J23_M_A_A15

P_J23_M_A_A14

T

131210

11

Y

M_VREF_DIMM0

1

C1MY

.1UF 10% 16V

2

X7R 603

7

A10/AP

105

91

9

C4MY

2.2UF

846

10%

6.3V X5R 603

CK0

A0A1A2A3A4A5A6A8A9

CK1

CK0*

CK1*

30

32

99

102

100

164

166

101

1

7

532

0

1

C3MY

.1UF 10% 16V

2

X7R 603

S0*

110

S1*

115

CKE1

CKE0

BA0

BA1

79

80

106

107

SA0

198

200

VDDSPD

VREF

SDA

SCL

SA1

1

195

197

199

VDD

88

103

104

112

111

VDD

96

95

82

81

87

118

117

61

14

71

GND

202

201

1920

V_SM

11

12

IN

1617

15 71

15

1617

1920

61

VSS

184

187

190

193

196

1

2

1

C5MY

.1UF 10%

10V X5R 402

C6MY

.1UF 10% 10V

2

X5R 402

V_SM

111214

IN

NOTE:

BOM

REPLACE C9MY WITH IPN C71601-001

183

VSS

177

178

1

2

VSS

172

VSS

168

171

C7MY

.1UF 10% 10V X5R 402

VSS

165

VSS

162

VSS

161

1

2

VSS

156

VSS

150

155

C8MY

.1UF 10%

10V X5R 402

VSS

149

145

1

C9MY

330UF 20%

6.3V TANT

2

7343

144

139

138

133

VSS

132

2

1

VSS

128

VSS

127

C10MY

2.2UF 10%

6.3V

X5R 603

122

VSS

787772

71

66

121

1

C11MY

2.2UF 10%

6.

3V

2

X5R 603

VSS

6560595453

1

2

VSS

4847424140

C12MY

2.2UF 10%

6.3V

X5R 603

VSS

393433

282724

1

C13MY

2.2UF 10%

6.3V

2

X5R 603

VSS

15

18

12

21

3

982

NC=203,204

B

1

C14MY

2.2UF 10%

6.3V

2

X5R 603

A

2

1

C

SA0_DIM0

19

OUT

SA1_DIM0

19

OUT

6

R4MY

1

10K 402

5

R3MY

5%

10K

CH

402

2

5% CH

BPAGE DRAWING

Wed Feb 07 17:18:19 2007

4 2

[PAGE_TITLE=DDR DIMM 0]

tawas_b.sch_1.19

INTEL

CONFIDENTIAL

3

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

19

2.0

1

CR-20 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE20

8

12

21

1221

D

1221

13

C

13

21

IN

13

21

IN

13

21

IN

13

21

IN

1321

BI

12

IN

12

IN

12

IN

12

IN

12

21

IN

12

21

B

1920

61

IN

12

21

IN

21

12

IN

13

21

IN

13

21

IN

20

IN

20

50

IN

19

212233

IN

212233

19

IN

50

12

14

15

16

17

61

DDR_REF

1219

IN

A

71

474869

19203132

IN

333539

46

7283 6171

12

14

15

11

IN

1719

20

16

PM_EXTTS1_N

OUT

M_ODT<3>

IN

M_ODT<2>

IN

M_B_DQS_DP<7..0>

IN

M_B_DQS_DN<7..0>

IN

M_B_DM<7..0>

13

IN

BI

J2MY

SODIMM_202P

M_B_WE_N M_B_RAS_N M_B_CAS_N M_B_BS<2>

M_B_A<13..0>

M_CLK_DDR_DP<3> M_CLK_DDR_DN<3> M_CLK_DDR_DP<4> M_CLK_DDR_DN<4> M_CS_N<2> M_CS_N<3>

M_CKE<3> M_CKE<4> M_B_BS<0> M_B_BS<1> SA0_DIM1 SA1_DIM1 SMB_DATA_S SMB_CLK_S

V_SM

11

IN

71

R2MY

2

1

0

5% CH

402

V_3P3_M

SM

V_

C16MY

2.2UF 10%

6.3V

2

X5R 603

606162

63

182

180

194

192

DQ<60>

DQ<61>

DQ<62>

DQ<63>

WE*

CAS*

RAS*

113

108

109

1

2

1

R16MY

1K 1%

2

EMPTY 402

1

8

7

M_B_DQ<63..0>

5857555654

59

174

191

181

189

179

176

DQ<56>A7DQ<59>

DQ<54>

DQ<55>

DQ<58>

DQ<57>

1

A14

A15

A1

A13

A12

BA2

86

85

89909392949798

84

116

P_J9_M_A_A15

TP_J9_M_A_A14

T

13

R15MY

1K 1%

EMPTY 402

M_VREF_DIMM1

C18MY

1

C15MY

.1UF 10% 16V

2

X7R 603

7

5352505149

173

175

158

160

<53> DQ

DQ<52>

DQ<51>

DQ<50>

A10/AP

91

105

101112

9

876

2.2UF 10%

6.3V X5R 603

4847454644

157

154

159

DQ<49>

DQ<48>

DQ<47>

5

432

1

2

152

DQ<46>

99

142

DQ<45>

100

140

DQ<44>

101

1

2

6

434142

153

DQ<43>

A0A1A2A3A4A5A6A8A9

102

151

DQ<42>

143

DQ<41>

CK0

30

40

141

DQ<40>

CK0*

32

3938363735

136

134

124

126

DQ<38>

DQ<39>

DQ<37>

DQ<36>

CK1*

CK1

164

166

137

DQ<35>

333230

34

135

12576123

DQ<33>

DQ<34>

S1*

S0*

115

110

31

292826272524232122

746275

64

DQ<32>

DQ<31>

DQ<29>

DQ<30>

CKE1

CKE0

79

80

DQ<28>

BA0

107

DQ<27>

BA1

106

73

6361584656

DQ<26>

DQ<25>

SA0

198

DQ<24>

SA1

200

DQ<23>

DQ<22>

SDA

195

1817151614

19

20

44575545433822

DQ<18>

DQ<19>

DQ<20>

DQ<21>

DQ<17>

DQ<16>

VDDSPD

VREF

SCL

1

197

199

DQ<15>

VDD

88

36

DQ<14>

VDD

112

131112

DQ<13>

VDD

103

10

37

203523

DQ<10>

DQ<11>

DQ<12>

VDD

96

104

111

9

25

DQ<9>

VDD

95

8

DQ<8>

VDD

117

16

DQ<7>

VDD

87

3

675

4

14619417

DQ<6>

DQ<5>

DQ<3>

DQ<4>

VDD

82

81

118

7

DQ<1>

DQ<2>

0

71

6171

1

Y

C17M

.1UF 10% 16V X7R 603

2

1

SA1_DIM1

20

OUT

SA0_DIM1

20

OUT

6

R5MY

10K

5%

402

CH

2

1

R6MY

5%

10K 402

CH

5

012

5

DQ<0>

61

45

5

147

5 DM

14

1214

VSS

196

12

11

4

130

DM4

VSS

193

11

VSS

190

187

IN

3

67

DM3

VSS

183

184

IN

7

6

170

185

DM7

DM6

GND

202

201

15

1617

1920

15

161719

20

BOM NOTE:

REPLACE C28MY WITH I

PN C71601-001

V_3P3_M

192031

IN

32 33 35 39

69

71

72 83

Wed Feb 07 17:18:20 2007

4 2

3

1

0

VSS

178

2

52

DM2

VSS

177

VSS

172

VSS

171

26

DM1

VSS

168

VSS

165

162

TP_NC2_J24

120

10

NC

DM0

VSS

156

149

150

155

161

V_SM

1

C19MY

.1

UF 10% 10V

2

X5R 402

V_SM

46 47 48

[PAGE_TITLE=DDR DIMM 1]

BPAGE DRAWING

tawas_b.sch_1.20

3

7

186

DQS*<7>

VSS

145

C20MY

.1UF 10% 10V X5R 402

7

188

S<7> DQ

VSS

144

1

C28MY

2

VSS

139

330UF 20%

6.3V TANT 7343

6

167

DQS*<6>

VSS

138

169

133

6

DQS<6>

VSS

1

2

VSS

132

5

146

148

DQS<5>

DQS*<5>

VSS

128

127

C21MY

UF

.1 10%

10V X5R 402

1

2

3

2

4

3

2

4

131

129

70

49

68

51

DQS<2>

DQS<3>

DQS<4>

DQS*<2>

DQS*<3>

DQS*<4>

VSS

787772

71

6560595453

66

122

121

1

C22MY

.1UF 10% 10V

2

X5R 402

1

C27MY

2.2UF

6.3V X5R 603

CUSTOM TEXT BPAGE

C26MY

2.2UF

10%

6.3V

2

X5R 603

INTEL

CONFIDENTIAL

MODULE REV DETAILS

MODULE NAME

TAWAS_CORE

1

0

1

0

31

11

13

29

DQS<0>

DQS<1>

DQS*<0>

DQS*<1>

VSS

393433

4847424140

1

C25MY

2.2UF 10%

6.3V

2

X5R 603

DOCUMENT_NUMBER

VSS

282724

1

2

D89092

VSS

C24MY

2.2UF 10%

6.3V

X5R 603

REV

TP_NC1_J24

TP_NC4_J24

114

83

69

NC

ODT0

VSS

15

18

21

1

2

1

119

ODT1

VSS

982

12

C23MY

2.2UF 10%

6.3V

X5R 603

1

50

NC

VSS

TP_NCTEST_J24

163

NC/TEST

VSS

3

PAGE

20

DATE

2-05-071. 02.01

D

IO

C

VSS

NC=203,204

B

A

REV

2.0

CR-21 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE21

8

D

V_SM_VTT

2161

IN

71

C

31MY

2

.1UF

X5R 402

C

33MY

2

.1UF

X5R 402

C35MY

2

.1UF10%

C

B

A

2

.1UF

2

.1UF

2

.1

2

.1UF

2

.1UF

2

.1UF

2

.1UF

2

.1UF

2

.1UF

2

.1UF

X5R 402

C

37MY

X5R 402

C39MY

X5R 402

C41MY

UF

X5R 402

C43MY

X5R 402

C45MY

X5R 402

C47MY

X5R 402

C49MY

X5R 402

C51MY

X5R 402

C53MY

X5R 402

C55MY

X5R 402

C

32MY

1

2

1

10%

10V

10%

10V

10%

10V

10%

10V

10%

10V

10%

10V

10%

10V

10%

10V

10%

10V

10%

10V

10%

10V

10%

10V

10%.1UF

10V X5R 402

C34MY

1

2

10%.1UF

10V X5R 402

C36MY

2

UF

10%.1

10V X5R 402

C38MY

2

10%.1UF

10V X5R 402

C40MY

2

.1UF 10%

10V X5R 402

C42MY

2

UF

10%.1

10V X5R 402

44MY

C

2

10%.1UF

10V X5R 402

C46MY

2

10%.1UF

10V X5R 402

C48MY

2

10%.1UF

10V X5R 402

C50MY

2

.1UF 10%

10V X5R 402

C52MY

2

10%.1UF

10V X5R 402

C54MY

2

10%.1UF

10V X5R 402

C56MY

2

10%.1UF

10V X5R 402

1

Q1MY

MMBT3904 XSTR

1

1220

8

OUT

7

2161

71

3

1

2

PM_EXTTS1_N

7

V_SM_VTT

IN

DDR_THERM2

DDR_THERM1

1

0

402

R8MY

5% CH

2

.063W

.

.063W

1

063W

C30MY

1000PF 10% 50V X7R 603

5%

A93565-001

5% 56

A93565-001

5%

A93565-001

5%IC56

A93565-001

PM_EXTTSD1_N

6

RP1MY

8

1

M_A_BS<2>

7

2

M_A_A<7>

6

3

M_A_A<11>

45

M_CKE<1>

56

SM

IC

RP

5MY

8

1

M_A_A<9>

7

2

M_A_A<12>

3

6

M_A_A<6>

45

IC

M_CKE<0>

SM

RP6MY

8

1 2

3

1

2 3

1

2 3

45

RP7MY

RP8MY

565%

SM

56

SM

7

6

54

8

7 6

54

8

7 6

M_A_A<3>

M_A_A<5>

M_A_A<4>

M_A_A<8>

M_A_A<2>

M_A_A<1>

M_A_A<0>

M_A_BS<1>

M_A_CAS_N

M_A_WE_N

M_A_BS<0>

M_A_A<10>

2

3

4

5

6

OUT OUT OUT OUT

D+

D-

THERM*

GND

13

12

13

12

13

U1MY

ADM1032

19

SDATA

ALERT*

VDD

SCLK

IC

5

71

VCC3

1

8 7

PM_EXTTSD0_N

6

2161

IN

1

2

SMB_CLK_S SMB_DATA_S

1

0

402

V_SM_VTT

C29MY

0.1UF 20% 16V Y5V 402

R7MY

2

5% CH

45

RP9MY

8

1

2

3

.063W

IC

A93565-001

RP10MY

1

2 3

45

063W

.

5%

IC

A93565-001

RP11MY

1

2

3

5%5456

.063W

IC

A93565-001

RP12MY

1

2 3

.

063W

IC

6

54

565%

SM

8

6

56

SM

8

6

SM

8

6

54

565%

SM

7

M_CS_N<1>

7

M_B_WE_N

7

M_B_BS<0>

7

M

M_ODT <0>

_A_RAS_N

M

M_ODT <1>

M_ODT <2>

M_B_A<13>

M_B_CAS_N

M_B_BS<1>

M_B_RAS_N

M_CS_N<2>

M_B_A<3>

M_B_A<0>

M_B_A<1>

_B_A<10>

A93565-001

RP2MY

1

8

M

_B_A<7>

7

.063W

19 20 22

IN

19 20 223350

BI

PM_EXTTS0_N

2

3

5%

IC

A93565-001

M_B_A<5>

6

M_B_A<2>

54

M_B_A<4>

56

SM

33

50

19

12

OUT

Wed Feb 07 17:18:21 2007

4 2

3

12 19

OUT

13 19

OUT

12 19

OUT

12 19

OUT

V_SM_VTT

216171

OUT OUT OUT OUT

12 20

13 20

12 20

13 20

IN

[PAGE_TITLE=DDR TERMINATION AND THERMAL]

BPAGE DRAWING

tawas_b.sch_1.21

3

2

063W

5%

.

IC

A93565-

5%

.

063W

IC

1

56

402

1

56

402

1

56

402

1

56

402

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

MODULE REV DETAILS

MODULE NAME

TAWAS_CORE

RP

3MY

1

8

7

6

56

SM

001

RP4MY

8

7

6 54

56

SM

A93565-001

R9MY

2

5% CH

R10MY

2

5% CH

2

R11MY

5% CH

2

R12MY

5% CH

M_B_A<12>

M_B_A<8>

M_B_A<6>

M_CKE<3>

M_B_BS<2>

M_B_A<9>

M_A_A<13>

M_CS_N<0>

M_CS_N<3>

M_ODT <3>

2

3

45

1

2

3

DOCUMENT_NUMBER

M_B_A<11>

M_CKE<4>

D89092

OUT OUT

OUT

OUT OUT OUT OUT

REV

13 20

12

13

12

12 20

1

DATE

2-05-071. 02.01

D

20

19

C

B

A

PAGE

REV

21

2.0

1

CR-22 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE22

8

VCC3

37

D

C

40

22

67686972 445052

9

2226

31

323337 54555665 7577

SLP_M_N

IN

R300CK

1K

402

404450525455 77

IN

1

2

V_3P3_STBY\G

IN

5% CH

IN

SLP_M

C112CK

1UF

20%

16V EMPTY 805

1

R97CK

10K

5% CH

2

402

1

SLP_M_CK_R

G

PFET_VDD_CLK_R

R301CK 10K 5%

CH 402

SLP_M

Q3

CK

MMBT3904 XSTR

56656768697275

V_3P3_STBY\G

9

2226

31

3233

B

19

20

2133

50

20

2133

50

19

A

2

S

D

3

202341-012

OUT

22

23

R105CK

1

0

EMPTY

603

R10CK

1

0

EM

603

Q2CK PMOSFET

100CK

R

1

0

603

VDD_CLK

1

C8CK

7UF

4. 20%

10V

2

Y5V 805

22

IN

BI

7

2

1A

2

1A

PTY

2

1A

CH

CK_PWRGD_R

CK_BSEL1

SMB_DATA_S

SMB_CLK_S

R104CK

1

0

603

R18CK

1

0

402

202341-012

103CK

R

1

0

603

R101CK

1

0

603

R102CK

1

0

603

2

1A

CH

2

5% CH

2

1A

CH

2

1A

CH

2

1A

CH

1

C10CK

.1UF 10% 16V

2

X7R 402

1

C13CK

4.7UF 20%

10V

2

Y5V 805

1

C2

.1UF 10% 16V

2

X7R 402

V

1

C4CK

.1UF 10% 16V

2

X7R 402

VDD_CK_VDD_REF

1

C1CK

.1UF 10% 16V

2

X7R 402

R12CK

1

1K

402

R61CK

1

0

402

R63CK

15%2

0

402

Y1CK

14.318MHZ

1

VDD_CK_VDD_PCI

VDD_CK_VDD_48

1

2

VDD_CK_VDD_SRC

1

CK

2

DD_CK_VDD_CPU

2

5% CH

2

5% CH

CH

2

XTAL

SM

6

C9CK .1UF 10% 16V X7R 402

C3

CK

.1UF 10% 16V X7R 402

TESTMODE_FSB1_CK505

SMB_DATA_CK505

SMB_CLK_CK505

OSC_CK14M_XTALOUT

OSC_CK14M_XTALIN

BOM NOTE:

MOD U1CK TO D31101-003

2

VDD_PCI

9

VDD_48

16

VDD_PLL3

39

VDD_SRC

55

VDD_CPU

61

VDD_REF

56

CKPWRGD/PWRDWN*

57

FSB/TESTMODE

63

SDA

64

SCL

59

XTAL_OUT

60

XTAL_IN

REV=1.01

31

IN

DESIGN NOTE:

U1CK

CK505_64PIN

REF/FSC/TESTSEL

R67CK

2

1

1K

5% CH

402

MANUFACTURING TEST REQUIREMENT

45

PCIF5/ITP_EN PCI4/SRC5_EN

PCI2/LTE PCI1/CR_B* PCI0/CR_A*

USB/FSA

VSS_PCI

VSS_48

VSS_REF

IO_VOUT

1of 2

CK_PWRGD_RCK_PWRGD

PCI3

OUT

CAD NOTE:

CLK PCI 2,4, 5: DO NOT STUB OFF MORE THAN 250 MILS

CLK PCI 2,4,5 (PULL-UP/PULL-DOWNS): OVERLAP PADS

62

7 6 5 4 3 1

10

8 11 58

48

IC

22

3

STRAP MODE STUFF UNSTUFF

SRC5_EN

23

IN

23

IN

40

DESI

R118CK.1 CHANGED FROM V_1P05_CORE TO V_3P3_STBY\G CHANGE TO VDD_CLK FOR FAB C

CK505_IO_VOUT_PIN48

LT ENABLED

LTE

LT DISABLED

SRC5 ENABLED

SC

ITP ENABLED ( SRC8 DISABLED)

ITP_EN

SRC8 ENABLED (ITP DISABLED)

CK_BSEL2

CK_BSEL0

676869727577 2226

31

323337

44505254555665

GN NOTE:

2

33

402

R5 DISABLED

1K

402

1K

402

9

IN

R2CK

1

5% CH

DESIGN NOTE:

BSEL BIASING RES

2

C12CK

27PF 5% 50V

1

COG 603

8

7

2

C11CK

27PF 5% 50V

1

COG 603

6

5

4 2

ALWAYS STUFF

BPAGE DRAWING

tawas_b.sch_1.22

Wed Feb 07 17:18:22 2007

3

[PAGE_TITLE=CK505 PAGE [ 1 OF 3 ]]

2

VCC3

2

R11CK

1

2

5% CH

2

CK_REF_R

CK_PCI5_R CK_PCI4_R CK_PCI3_R CK_PCI2_R CK_PCI1_R CK_PCI0_R

CK_USB_R

R13CK

1

2

5% CH

V_3P3_STBY\G

CK505_IO_VOUT_R

1

C26CK

100.0PF 5% 50V

2

COG 603

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

MODULE REV DETAILS

MODULE NAME

CK505_TAWAS 00.02.00 10-24-06

PCI2 PULLUP R65CK

PCI2 PULLDWN R66CK

P

CI4 PULLUP R4CK

I4 P ULLDWN R5CK

PC

PCI5 PULLDWN R24CK

1

R26CK

10K

5% CH

402

R24CK

10K

5% EMPTY

402

805

R118CK

1

0

OUT

OUT OUT OUT OUT OUT OUT

OUT

1A

CH

1

2

1

2

R4CK

10K 5%

EMPTY 402

R5CK

10K 5%

CH 402

R120CK

47K 5%

2

EMPTY 402

R121CK

1

47K 5%

EMPTY

2

402

24

24 24 24 24 24 24

24

2

R3CK

1

15

5% CH

2

805

VDD_CLK_R_INIT _IO

3

Q1CK

1

MMBT3904 XSTR

2

VDD_CLK_IO

DOCUMENT_NUMBER

D89092

1

REV

PCI2 PULLDWN R66CK

PCI2 PULLUP R65CK

PCI4 PULLDWN R5CK

PCI4 PULLUP R4CK

PCI5 PULLDWN R24CKPCI5 PULLUP R26CK

PCI5 PULLUP R26CK

2

1

R65CK

10K 5%

CH 402

R66CK

10K 5%

EMPTY 402

DATE

VCC3

1

R119CK

0 5%

2

EMPTY 402

R79CK

1

0

1A

EMPTY

2

603

23

OUT

PAGE

22

1

REV

2.0

D

C

B

A

CR-23 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE23

8

22

IN

D

DESIGN NOTE:

STUFF WITH 64 PIN PART

1

2

C

104CK

.1

UF 20% 50V EMPTY 805

C

110CK

.1UF 20% 50V

2

EMPTY 805

C

VDD_CLK_IO

CAD NOTE:

1

C

105CK

.1

UF 20% 50V

2

X7R 805

7

CK505 VDD_*_ IO BULK DCPL: PLACE AROUND CK505

NOTE:

CAD

1

C102CK

10UF 20%

6.3V

2

X5R 805

CK505 VDD_*_IO DCPL: PLACE (1) PER PIN

1

C

106CK

.1

UF 20% 50V

2

X7R 805

CK_PE_SRC8_R_DN

24

OUT

CK_PE_SRC8_R_DP

24

OUT

CK_H_MCH_R_DN

24

OUT

CK_H_MCH_R_DP

24

OUT

CK_H_CPU_R_DN

24

OUT

CK_H_CPU_R_DP

24

OUT

C108CK

10UF 20%

6.

3V X5R 805

C

103CK

.1UF 20% 50V X7R 805

C109CK

10UF 20%

6.3V

2

X5R 805

1

C

100CK

.1UF 20% 50V

2

X7R 805

6

C111CK

10UF 20%

6.

3V X5R 805

1

C21CK

.1UF 10% 16V

2

X7R 603

12 20 26 45 49 36

46 47

50 51

53 54

15 19 23 42 52 29

VDD_IO VDD_PLL3_IO VDD_SRC_IO VDD_SRC_IO VDD_CPU_IO VDD_SRC_IO

SRC8-/ITPSRC8+/ITP+

CPU1CPU1+

CPU0CPU0+

VSS_IO VSS_PLL3 VSS_SRC VSS_SRC VSS_CPU VSS_SRC

U1CK

CK505_64PIN

64 PIN PART ONLY

CPU_STOP*/SRC5PCI_STOP*/SRC5+

REV=1

45

SRC11-/CR_G* SRC11+/CR_H*

SRC10SRC10+

SRC9SRC9+

SRC7-/CR_E* SRC7+/CR_F*

S

RC6-

SRC6+

SRC4SRC4+

SRC3-/CR_D* SRC3+/CR_C*

SRC2-/SATASRC2+/SATA+

SRC1-/SE2 SRC1+/SE1

SRC0-/DOT96SRC0+/DOT96+

2of 2

DESIGN NOTE:

SRC 9 THROUGH 11 ARE ONLY AVAILABLE ON THE 64 PIN PART

32 33

35 34

31 30

43 44

40 41

37 38

28 27

25 24

22 21

18 17

14 13

IC

3

CK_PE_SRC11_R_DN CK_PE_SRC11_R_DP

CK_PE_SRC10_R_DN CK_PE_SRC10_R_DP

CK_PE_SRC9_R_DN C

K_PE_SRC9_R_DP

CK_PE_SRC7_R_DN CK_PE_SRC7_R_DP

CK_PE_SRC6_R_DN CK_PE_SRC6_R_DP

PM_STPCPU_N PM_STPPCI_N

CK_PE_SRC4_R_DN CK_PE_SRC4_R_DP

CK_PE_SRC3_R_DN CK_PE_SRC3_R_DP

CK_PE_SRC2_R_DN CK_PE_SRC2_R_DP

CK_PE_SRC1_R_DN CK_PE_SRC1_R_DP

CK_96M_DOT_R_DN CK_96M_DOT_R_DP

2

MODULE REV DETAILS

MODULE NAME

CK505_TAWAS 00.02.00 10-24-06

24

OUT

24

OUT

24

OUT

24

OUT

24

OUT

24

OUT

24

OUT

24

OUT

24

OUT

24

OUT

31

OUT

31

OUT

24

OUT

24

OUT

24

OUT

24

OUT

24

OUT

24

OUT

24

OUT

24

OUT

24

OUT

24

OUT

1

REV

DATE

D

C

B

DESIGN NOTE:

ADD PLANE STI CHING CAPS HERE

32

62

15

1617

1829

63

71

77

A

V_1P05_CORE

81014

IN

R106CK

CPU_BSEL0

CPU_BSEL1

CPU_BSEL2

1

0

402

R107CK

1

0

402

R108CK

1

0

402

EMPTY

7

IN

7

IN

7

IN

2

5% CH

2

5%

EMPTY

R109CK

1

1K 1%

2

EMPTY 402

2

R115CK

1

0 5%

CH

2

402

1

2

1

2

R110CK

1K

5% CH

402

R116CK

0 5%

EMPTY 402

1

2

1

2

R111CK

56 5%

EMPTY 402

R117CK

1K

5% CH

603

R112CK

1

402

R113CK

1

1K

402

R114CK

1

1K

402

2

5%CH1K

2

5% CH

2

5% CH

MCH_BSEL0

CK_BSEL0

MCH_BSEL1

CK_BSEL1

MCH_BSEL2

CK_BSEL2

12

BI

22

IN

12

BI

22

IN

12

BI

22

IN

B

A

[PAGE_TITLE=CK505 PAGE [ 2 OF 3 ]]

BPAGE DRAWING

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Wed Feb 07 17:18:23 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

23

2.0

1

CR-24 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE24

8

DESIGN NOTE:

7

6

45

3

SRC CLOCK TERMINATION

1

2

R28CK

2

5%

2

5%

1

33

402

1

33

402

R15CK

2

1

225%

CH

402

R122CK

2

1

22

5% CH

402

R16CK

15%2

22

CH

402

R23CK

1222

5% CH

402

R20CK

2

1

225%

CH

402

CLOCK EMI CAPS: DEFAULT EMPTY

1

C7CK

C5CK

F

22P

10PF 5%

5%

50V

2

EMPTY

EMPTY 402

402

1

33

402

R123CK

1

2

33

5% CH

402

1

33

402

R124CK

1

2

5%

33

CH

402

R36CK

15%2

33

CH

402

R34CK

2

1

5%

33

CH

402

CK_PE_SRC11_R_DN

23

D

C

B

IN

CK_PE_SRC11_R_DP

23

IN

CK_PE_SRC10_R_DN

23

IN

CK_PE_SRC10_R_DP

23

IN

CK_PE_SRC9_R_DN

23

IN

CK_PE_SRC9_R_DP

23

IN

CK_PE_SRC7_R_DN

23

IN

CK_PE_SRC7_R_DP CK_OE_MINICARD1_N

23

IN

CK_PE_SRC6_R_DN

23

IN

CK_PE_SRC6_R_DP

23

IN

CK_PE_SRC4_R_DN

23

IN

CK_PE_SRC4_R_DP

23

IN

CK_PE_SRC3_R_DN

23

IN

CK_PE_SRC3_R_DP

23

IN

CK_PE_SRC2_R_DN

23

IN

CK_PE_SRC2_R_DP

23

IN

CK_PE_SRC1_R_DN

23

IN

CK_PE_SRC1_R_DP

23

IN

A

CK_96M_DOT_R_DN

23

IN

CK_96M_DOT_R_DP

23

IN

DESIGN NOTE:

96M DOT CLOCK SIGNALS: STUFF 33 OHM R39CK AND R40CK FOR MCH GRAPH IC SKU'S EMPTY R39CK AND R40CK AND STUFF R93U B AND R98UB FOR MCH NON-GRAPHIC SKU'S

R90CK

2

5% CH

R92CK

2

5% CH

94CK

R

2

5% CH

R125CK

1

470 402

R126CK

1

470 402

R4

2

5% CH

R53CK

2

5% CH

R52CK

2

5% CH

R51CK

2

5% CH

R41CK

2

5% CH

R39CK

2

5% CH

5CK

1

470 402

1

33

402

1

33

402

5%

EMPTY

5% CH

1

402

1

402

1

402

1

402

1

402

1

402

CK_OE_EXPCARD_N

2

R91CK

2

5% CH

R

2

5% CH

R9

2

5% CH

CK_OE_MCH_N

1

470 402

CK_PE_100M_3GPLL_DN

93CK

CK_PE_100M_3GPLL_DP

1

33

402

CK_PE_100M_EXPCARD_DN

5CK

1

CK_PE_100M_EXPCARD_DP

33

DESIGN NOTE:

402

SRC 9 THROUGH 11 ARE ONLY AVAILABLE ON THE 64 PIN PART

TP_CK_OE_100M_EXT

2

33

R46CK

2

5% CH

33

R48CK

2

5% CH

33

R50CK

2

5% CH

33

R38CK

2

5% CH

33

R42CK

5% CH

CK_PE_100M_EXT_DN

CK_PE_100M_EXT_DP

1

33

402

CK_PE_100M_MINICARD2_DN

CK_PE_100M_MINICARD2_DP

1

33

402

CK_PE_100M_ICH_DN

CK_PE_100M_ICH_DP

1

33

402

CK_PE_100M_SATA_DN

CK_PE_100M_SATA_DP

1

33

402

CK_DREF_100M_SS_DN

1332

CK_DREF_100M_SS_DP

402

CK_96M_DREF_DN

33

R40CK

2

5% CH

1

33

402

CK_96M_DREF_DP

OUT

37

12

37

39

54

40

30

29

12

DESIGN NOTE:

HOST TERMINATION

DESIGN NOTE:

SINGLE ENDED CLOCK TERMINATION

31

24 24

31

24

34

2459 2452 24 2480 2455 2455

CLOCK

CK_14M_ICH

IN

CK_48M_USB_ICH

IN

CK_P_33M_ICH

IN

CK_P_33M_TPM

IN

CK_P_33M_LPC

IN

TP_CK_PCI2

IN

CK_P_33M_CRD

IN

CK_14M_EC

IN

CK_P_33M_KBC

IN

23

IN

23

IN

23

IN

23

IN

23

IN

23

IN

1

C15CK

22P 5% 50V

2

EM 402

CK_PE_SRC8_R_DN

CK_PE_SRC8_R_DP

CK_H_MCH_R_DN

CK_H_MCH_R_DP

CK_H_CPU_R_DN

CK_H_CPU_R_DP

22

PTY

F

IN

1

2

CK_REF_R

CK_PCI5_R

CK_PCI3_R

CK

_PCI2_R

CK_PCI1_R

CK_PCI0_R

CK_USB_R

DESIGN NOTE:

C6CK

22PF 5% 50V

PTY

EM 402

EMPTY

R30CK

EMPTY

R35CK

2

5% CH

R33CK

2

5% CH

2

MODULE REV DETAILS

MODULE NAME

CK505_TAWAS 00.02.00 10-24-06

CK_14M_ICH

R14CK

15%2

CK_14M_EC

22

CH

402

R19CK

R21CK

R25CK

EMPTY

R17CK

R22CK

1

2

CK_P_33M_CRD

1

2

CK_P_33M_ICH

22

5% CH

402

CK_P_33M_KBCCK_PCI4_R

2

CK_P_33M_TPM

1

5% 22 CH

402

CK_P_33M_LPC

T

1

2225%

402

CK_OE_MINICARD2_N

CK_OE_SATA_N

2

1

2

5% 2 CH

402

2

1

CK_48M_USB_ICH

5%

22

CH

402

1

C18CK

C17CK

10PF

5%

50V

2

EMPTY

402

P_CK_PCI2

1

2

CK_H_XDP_DN

CK_PE_100M_MINICARD1_DN

CK_H_XDP_DP

CK_PE_100M_MINICARD1_DP

CK_H_MCH_DN

CK_H_MCH_DP

CK_H_CPU_DN

CK_H_CPU_DP

C14CK

10PF 5% 50V EMPTY 402

OUT

1

2

OUT

C16CK

10PF 5% 50V EMPTY 402

24

24 55

24

24 5522

24 59

24 52

24

40

31

24

50

39

50

39

10

6

1

REV

DATE

31

D

80

34

33

31

1

C20CK

10PF 5% 50V

2

EMPTY 402

C

B

A

[PAGE_TITLE=CK505 PAGE [ 3 OF 3 ]]

BPAGE DRAWING

tawas_b.sch_1.24

Fri Feb 09 14:30:22 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

24

2.0

1

CR-25 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE25

8

7

6

45

3

VCC

D

1

2

C11GD

F

10P 5% 50V COG 402

FB3GD

1

2

CRT_L1_RED

FB

1

2

D

28

OUT

RT_RED_CONN

C

1

R11GD

150 1%

CH

2

402

C1GD

22PF 5% 50V COG 402

FB9G

MULTI

2

FB

1

C12GD

10PF 5% 50V

2

COG 402

1

F1GD

THRMSTR

1.10

1

2

V_5P0_S_VGA_D

1

MODULE REV DETAILS

MODULE NAME

TAWAS_CORE

GD

CR1 B

13013F

2

SM

D36654-001

1.02.01

1

V_5P0_S_VGA

DIO

REV

2-05-07

1

C4GD

.1UF 10% 10V

2

PTY

EM 402

DATE

OUT

D

25

FB2GD

2

1

CRT_GREEN_CONN

28

OUT

R10GD

1

150 1%

CH

2

402

C

CRT_BLUE_CONN

28

OUT

1

R9GD

150 1%

2

CH 402

C9GD

10PF 5% 50V

2

COG 402

FB1GD

1

C5GD

10PF 5% 50V

2

COG 402

CRT_L1_GREEN

FB

2

CRT_L1_BLUE

FB

2528

OUT

2528

OUT

CRT_HSYNC_CONN

CRT_

B

V_5P0_S_VGA

25

IN

VCC3

3

D

Q2GD BSS1

38N

1

FET

S

G

2

VCC3

3

Q1GD

D

BSS1

1

FET

S

G

2

A

1

2

C13GD

.1UF 10%

10V X5R 402

2

1

C16GD

.1UF 10%

10V X5R 402

VCC3

1

2

[PAGE_TITLE=CRT/VGA]

8

7

6

5

FB5GD

MULTI

FB4GD

2

FB

1

C10GD

F

10P 5% 50V

2

COG 402

2

1

FB

C6GD

10P

F 5% 50V

2

CO

G

402

CRT_L2_RED

CRT_L2_GREEN

CRT_L2_BLUE

CRT_DDC_CLK_CONN

2528

IN

V_5P0_S_VGA

OUT

TP_J10_PIN11 TP_J10_PIN4

1

C2GD

22PF 5% 50V

2

G

CO 402

1

MULTI

1

C3GD

22PF 5% 50V

2

COG 402

VSYNC_CONN

C15G

100PF 5% 50V EMPTY 402

2

1

C14G

D

1

R7GD

2.2K 5%

CH 402

D

100PF 5% 50V

2

EM

PTY

402

R8GD

1

2.2K 5%

CH

2

402

1

2

CRT_DDC_CLK_ISO

CRT_DDC_DATA_ISO

38N

CRT_DDC_DATA

CRT_DDC_CLK

1

R6GD

R5GD

2.2K

2.2K 5%

5%

CH

2

402

BPAGE DRAWING

Wed Feb 07 17:18:25 2007

4 2

2528

IN

tawas_b.sch_1.25

CRT_DDC_DATA_CONN

1

2

OUT

C7GD

100PF 5% 50V EM 402

OUT

PTY

28

11

2528

C8GD

100PF 5% 50V

2

EMPTY 402

CRT_L2_RED

IN

CRT_L2_GREEN

IN

CRT_VSYNC_CONN

IN

CRT_HSYNC_CONN

IN

3

CUSTOM TEXT BPAGE

U1 TVS6V

1

2

3

U2GD TVS6V

1

2

3

INTEL

CONFIDENTIAL

J1

GD

16

1 9 2

10

3

11 4

12 5

13 6

14 7

15 8

17

6.0V

GD

6

5

4

EMPTY

6.0V

6

5

4

EMPTY

DOCUMENT_NUMBER

RCPT

CRT_L2_BLUE

TP_U62_PIN4

IN

CRT_DDC_DATA_CONN

TP_U63_PIN5

CRT_DDC_CLK_CONN

D89092

1

PAGE

25

VCC3

IN

25 28

REV

2.0

C

B

A

CR-26 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE26

8

D

71

73

C

B

7

SLP_S3_N

18

3137

55697275

45

61

6265666869

77

7883

IN

INTERMEDIATE_BUS_POWER

61

62636566686970

IN

7475767778

L_BKLTEN

11

IN

V_5P0_STBY\G

9

3233

IN

707576

L_VDDEN

11

IN

6

VCC3

1

G

L_VDDEN_N

BSS138N

R15GD

1

100K

603

R14GD

1

1.

0M

5%

2

CH 603

3

INV_SRC_CTRL

D

S

2

Q4GD

FET

2

L

_VDDEN_N_R

5% CH

GD

Q6 BSS138N

FET

VCC

3

D

S

2

1

C17GD

1000P 10%

50V

2

X7R 603

R19GD

INV_SRC_CTRL_DEL AY

2

1

5%

100K

CH

603

1

R18GD

1M 1%

2

CH 603

1

C30G

.1UF 10% 10V

2

X5R 402

1

G

1

2

1

R13GD

100K

5%

402

CH

525558

5255

58

D

4044505254

3

D

Q3GD IRLML5103TR

1

F

FE

T

S

G

2

11

IN

11

IN

45

D

C22G

1000PF 10% 50V X7R 603

R12GD

1

100 5% 402

2

33

BI

33

BI

5255

BI

555665676869727577 2231323337 9

IN

1

C33GD

0.1UF 20%

16V

2

Y5V 402

BOM NOTE:

REPLACE WITH 22UF TANTLUM 202244-073

L_DDC_CLK L_DDC_DATA

INV_SRC_FB

3

D

1

S

G

2

CH

SMB_BAT2_DATA

SMB_BAT2_CLK EC_KEY_INT_N

V_3P3_STBY\G

1

2

C20GD

33UF

20%

4.0V TANT

3528

C18GD

0. 20% 16V

212

Y5V 402

1

R16GD

2.2K 5%

2

CH 402

Q5GD IRLML5103TR

FET

R4GD

1

2

0

5%

EMPTY

402

1

C32GD

0.1UF 20% 16V

2

Y5V 402

C21GD

1UF

0. 20% 16V Y5V 402

1

R17GD

2. 5%

2

CH 402

A

BKLTEN

55 11 55

INV_SMB_INT_N

2K

3

FB10GD

2

1

FB

EC_LAMP_STAT

OUT

L_BKLTCTL

IN

DAC_BRIG

IN

0

402

VCC3

41 41

L_VDD_VDL

R2GD

1

30 30

5%

EMPTY

1

2

INV_SMB_DATA

2

R3GD

1

0

402

U

BI

USB_9_DP

BI

C31GD

.1UF 10% 10V X5R

44

402

44

VCC3

INV_SRC

12

2

5%

EMPTY

SB_9_DN

OUT IN

OUT OUT

11

IN

11

IN

11

IN

11

IN

11

IN

11

IN

11

IN

11

IN

11

IN

11

IN

11

IN

11

IN

11

IN

11

IN

11

IN

11

IN

[PAGE_TITLE=LVDS\LCD PANEL]

2

1

C29GD

.1

UF 10% 10V

2

X5R 402

L_CTRL_DATA

BI

11

INV_SMB_CLK

L_CTRL_CLK

BI

DMIC_DATA

AUD_ AUD_DMIC_CLK

AUD_AMIC_R AUD_AMIC_L

1

C19GD

0.1UF 20% 16V

2

Y5V 402

LA_DATA0_DN LA_DATA0_DP

LA_DATA1_DN LA_DATA1_DP

LA_DATA2_DN LA_DATA2_DP

LA_CLK_DN LA_CLK_DP

LB_DATA0_DN LB_DATA0_DP

LB_DATA1_DN LB_DATA1_DP

LB_DATA2_DN LB_DATA2_DP

LB_CLK_DN LB_CLK_DP

1

MODULE REV DETAILS

MODULE NAME

TAWAS_CORE

TP_PIN5

TP_PIN25

A_GND_LVDS

REV

1.02.01 2-05-07

J3GD

2X15HDR_6MTG

IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO

REQ 4813

1OF1

REV=1

CONN

1

4022CH

J2GD

2X15HDR_6MTG

IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO

REQ 4813

1OF1

IO IO IO IO IO IO

0

CONNREV=1

R1GD

IO IO IO IO IO IO

5%

DATE

D

C

B

A

BPAGE DRAWING

tawas_b.sch_1.26

Wed Feb 07 17:18:26 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

26

2.0

1

CR-27 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE27

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

TAWAS_CORE

1

REV

1.02.01 2-05-07

DATE

D

UNKN 180

1.5A BROAD

C

27

TVB_DAC

11

OUT

TVA_DAC

11

OUT

2

1

R21GD

1

2

CH 402

R20GD

150 1%

CH 402

150 1%

B

TVC_DAC

11

27

OUT

R22G

1

150 1%

CH

2

402

FB7GD

2

1

C27GD

5.6

PF .5% 50V

2

COG 402

FB8G

1

C23GD

5.6PF

.5%

50V

2

G

CO

402

FB6GD

1

D

C26GD

PF

5.6

.5%

50V

2

COG

402

TVB_DAC_FILTERED

FB

UNK

N

180

1.5A BROAD

D

2

TVA_DAC_FILTERED

FB

UNKN

180

1.5A

BROAD

2

TVC_DAC_FILTERED

FB

1

C24GD

5.6PF .5% 50V

2

CO

G

402

TP_J13_PIN1

1

C25GD

5.6PF .5% 50V

2

COG 402

1

C28GD

PF

5.6 .5% 50V

2

COG 402

A

J4

GD

7 PIN MINI DIN

1

P1

2

P2

3

P3

4

P4

5

P5

6

P6

7

P7

P8 P9

89

CONN

6.0V

U3GD

V

TVS6

EMPTY

6

52

TP_U67_PIN5

4

TP_U67_PIN4

11

27

IN

TVA_DAC TVC_DAC

11

27

IN

TVB_DAC

11

27

IN

1

3

D

C

B

A

[PAGE_TITLE=S-VIDEO]

8

7

6

5

4 2

BPAGE DRAWING

tawas_b.sch_1.27

Wed Feb 07 17:18:27 2007

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

27

2.0

1

CR-28 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE28

8

D

2856

VGA_SW_EN_N

55

IN

C

PORT_CRT_EN_N

2856

IN

4.7K 402

IN

R1305

1

2

5% CH

7

PORT_CRT_EN_N

R1304

0

402

VCC

1

2

1

PRT_EN_N1

2

VCC

1

2

1

2

VGA_SW_EN_N_R

5%

EMPTY

R

1303 10K 5%

CH 402

PORT_CRT_EN

3

Q80

MMBT3904 XSTR

R1300

1K

5% CH

402

1

2

R1301 10K 5%

CH 402

6

EU28

STMAV340

GND

1B

2B

3B

4B

1C

2C

3C

4C

IC

CRT_RED_PORT

1 3

CRT_GREEN_PORT CRT_BLUE_PORT

5 7

CRT_RED_CONN

2 4

CRT_GREEN_CONN

6

CRT_BLUE_CONN

8

9

11

IN

11

IN

11

IN

1

C28

0.

1UF 20% 16V

2

Y5V 402

CRT_RED CRT_GREEN CRT_BLUE

1302

R

1

22K 5%

EMPTY

2

402

1

C29

C30

0.

1UF

20%

16V

2

Y5V

402

13

1A

12

2A

11

3A

10

4A

15

OE*

14

S

16

VCC

1OF1

REV=1

1

C31

0.

1UF

20%

16V

2

Y5V 402

VCC

1

C32

0.

1UF 20% 16V

2

Y5V

B

CRT_VSYNC

11

IN

402

EU29

74LVC2G125

8

VCC

1

1OE*

2

1A

7

2OE*

5

2A

6

1Y

3

2Y

4

GND

IC

CRT_VSYNC_PORT

CRT_VSYNC_CONN

OUT

83

25

CAD NOTE: PLACE C34 NEAR U31 VCC PIN

45

VCC

1

2

83

OUT

83

OUT

83

OUT

25

OUT

25

OUT

25

OUT

C34

0.

1UF

20%

16V Y5V 402

VCC=8 GND=4

2856

1

7

3

PORT_CRT_EN_N

IN

U31

74CBT3306

A

OE

B

IC

U31

74CBT3306

A

OE

B

IC

2

3

CRT_DDC_CLK_PORT

5

6

CRT_DDC_CLK_CONN

4.7K 402

CRT_DDC_CLK_ISO

R1306

1

2

5% CH

2

PRT_EN_N2

MODULE REV DETAILS

MODULE NAME

VCC

1

R1307

10K

5%

2

CH 402

3

Q81

1

MMBT3904 XSTR

2

25

IN

83

OUT

25

OUT

1

REV

DATE

D

C

B

U32

1

V

CC=8

GND=4

VCC=8 GND=45IC

74CBT3306

OE

IC

U32

74CBT3306

7

OE

CRT_DDC_DATA_ISO

2

A B

3

CRT_DDC_DATA_PORT

A B

6

CRT_DDC_DATA_CONN

OUT

25

IN

83

A

25

VCC

1

C33

0.1UF 20% 16V

2

Y5V 402

CRT_HSYNC

11

A

IN

EU30

74LVC2G125

8

VCC

1

1OE*

2

1A

7

2OE*

5

2A

1Y

2Y

GND

IC

CRT_HSYNC_PORT

6

CRT_HSYNC_CONN

3

4

OUT

83

25

CAD NOTE: PLACE C35 NEAR U32 VCC PIN

VCC

1

2

C35

0.1UF 20%

16V Y5V 402

[PAGE_TITLE=VGA SWTICH]

BPAGE DRAWING

tawas_b.sch_1.28

Wed Feb 07 17:18:28 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

28

2.0

1

CR-29 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE29

8

CR1LB

V_3P3_KSC

J1LB

1X2HDR

1

2

BAT54C

DIO

1

2

SOT23_C

525557586573

IN

83

LB_BAT_D

D

1

R34LB

1K

5% CH

2

603

LB

_BAT_J

HDR

C

B

A

8

7

3

V_3P0_BAT_VREG

1

2

7

R36LB

1.0M

5% CH

603

46

46 46 46

46

4249 4249

4249

42 49

4249

52

38

24 24

1

C1LB

0UF

1.

20%

10V

2

Y5V 603

R35LB

2

1

1%

20K

CH

603

ICH_INTVRMEN

33

IN

LAN100_SLP

33

IN

GLAN_CLK

IN

LAN_RSTSYNC

OUT

LAN_RXD0

IN

LAN_RXD1

IN

LAN_RXD2

IN

OUT OUT OUT

IN

V_1P5_FILTERED

3032

IN

OUT OUT

OU

T

IN IN

AUD_HDA_SDOUT

OUT

GP33_SOP_EN_N

33

IN

ICH_CONFIG_JMPR1

33

IN

VCC3

OUT

SATA_RXN0

38

IN

SATA_RXP0

38

IN

SATA_TXN0

OUT

SATA_TXP0

OUT

CK_PE_100M_SATA_DN

IN

CK_PE_100M_SATA_DP

IN

32 33

OUT

1

C3LB

1.0UF 20% 10V

2

Y5V 603

LAN_TXD0 LAN_TXD1 LAN_TXD2

LAN_ED_GPIO13

AUD_HDA_BIT_CLK AUD_HDA_SYNC

AUD_HDA_RST_N

AUD_HDA_SDIN0 AUD_HDA_SDIN1

R47LB

2

1

5%

10K

CH

402

HDD_LED_N

.01UF

C6LB

1

50V

C8LB

1

50V

603

.01UF

603

6

1

C4LB

10PF 5% 50V

2

COG 402

RTC_RST_N

R41LB

1

1%

24.9 CH

603

2

20% X7R

C5LB

1

50V

603

2

20% X7R

C7LB

1

.01UF

50V

603

6

R37LB

1

10M 603

32.768KHZ

Y2LB

1

RTC_X2

SM_INTRUDER_N

2

LB_GLAN_COMP

TP_HDA_SDIN2 TP_HDA_SDIN3

SATA_RXN0_C

SATA_RXP0_C

SATA_TXN0_C

SATA_TXP0_C

2

20% X7R

2

20% X7R

SM

5% CH

2

XTAL

NC=2,3

4

RTC_X1

TP_SATA_TXN1

TP_SATA_TXP1

TP_SATA_TXN2_C

TP_SATA_TXP2_C

LB_SATA_RBIAS

R49LB

1

24.9 1%

CH

2

603

1

C2LB

10PF 5% 50V

2

COG 402

AG25 AF24

AF23

AD22

AF25 AD21

B24

D22

C21 B21 C22

D21 E20 C20

AH21

D25 C25

AJ16 AJ15

AE14

AJ17 AH17 AH15 AD13

AE13

AE10 AG14

AF10

AF6 AF5 AH5 AH6

AG3 AG AJ4 AJ3

AF2 AF1 AE4 AE3

AB7 AC6

AG1 AG

4

2

RTCX1 RTCX2

RTCRST#

INTRUDER#

INTVRMEN LAN100_SLP

GLAN_CLK

LAN_RSTSYNC

LAN_RXD0 LAN_RXD1 LAN_RXD2

LAN_TXD0 LAN_TXD1 LAN_TXD2

EN

GLAN_COMPI GLAN_COMPO

HDA_BIT_CLK

HDA_SYNC

HDA_RST#

HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3

HDA_SDOUT

HDA_DOCK_EN#/ GPIO33 HDA_DOCK_RST#/GPIO34

SATALED#

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

SATA1RXN SATA1RXP SATA1TXN SATA1TXP

SATA2RXN SATA2RXP SATA2TXN SATA2TXP

SATA_CLKN SATA_CLKP

SATARBIAS# SATARBIAS

ICH8M

REV=1.05

ERGY_DETECT/GPIO13

1OF6

5

U5LB

FWH4/LFRAME#

LPC

RTC

LDRQ1#/GPIO23

CPUPWRGD/GPIO49

LAN / GLAN

CPU

IHDA

IDE

SATA

IC

45

LDRQ0#

A20GATE

A20M#

DPRSTP#

DPSLP#

FERR#

E5 F5 G8 F6

C4

G9 E6

AF13 AG26

AF26 AE26

AD24

L_FRAME_N

ICH_DRQ0_N TP_ICH_DRQ1_N

H_A20GATE H_A20M_N

LB_DPRSTP_N_R

LB_DPSLP_N_R

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

AG29

AF27

IGNNE#

AE24

INIT#

AC20

INTR

AH14

AD23 AG28

AA24

AE27

AA23

V1 U2 V3 T1 V4 T5 AB2 T6 T3 R2 T4 V6 V5 U1 V2 U6

AA4 AA1 AB3

Y6 Y5

W4 W3 Y2 Y3 Y1 W5

H_RCIN_N

H_NMI

LB_SMI_R_N

402

H_STPCLK_N

H_THERMTRIP_R

TP_ICH_AA2 3

IDE_PDCS1_N IDE_PDCS3_N

IDE_PDIOR_N IDE_PDIOW_N IDE_PDDACK_N INT_IRQ14 IDE_PDIORDY IDE_PDDREQ

Wed Feb 07 17:18:29 2007

RCIN#

PCLK#

ST

THRMTRIP#

DCS1# DCS3#

DIOR#

DIOW# DDACK# IDEIRQ

IORDY

DDREQ

SMI#

PECI

DD10 DD11 DD12 DD13 DD14 DD15

NMI

DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9

DA0 DA1 DA2

4 2

3

L_AD<3..0>

0 1 2

3

OUT

IN

OUT

R44LB

1

2

CH

402

0

5%

R40LB

2

1

CH

402

5%

0

H_PWRGD

OUT

H_IGNNE_N

OUT

H_INIT_N

OUT

H_INTR

402

H_SMI_N

2

5%

CH

IDE_PDA<2..0>

OUT

VCC3

OUT

OUT OUT

OUT OUT OUT

IN

IN IN IN

R48LB

10K

R42LB

1

0

IDE_PDD<15..0>

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 1 2

2CH1

5%

[PAGE_TITLE=ICH8M (1 OF 5)]

BPAGE DRAWING

tawas_b.sch_1.29

3

BI

52 55

55

55 56

6

7 6 6 6

55

6

36 36

36 36 36 36 36 36

33

36

OUT

24.9 603

59

R46LB

1

BI

1

R38LB

56.2 1%

EMPTY

2

603

2

1% CH

36

2

52 55 59

V_1P05_CORE

1

R43LB

R39LB

56.2

56 5%

1%

EMPTY

CH

2

603

402

H_DPRSTP_N

R45LB

2

1

5%

56

CH

402

PM_THRMTRIP_N

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

MODULE REV DETAILS

MODULE NAME

ICH8M_TW

H_DPSLP_N

H_FERR_N

V_1P05_CORE

DOCUMENT_NUMBER

OUT

IN

D89092

04.08.00 2-2-07

8

101415

32

62 637177

71277

7

6

101415

8 32

62 637177

6

12

1

REV

DATE

D

16 17

18 23 29

C

16 17

18 23 29

B

A

PAGE

REV

29

2.0

1

CR-30 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE30

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

ICH8M_TW

1

REV

04.08.00 2-2-07

DATE

D

PCI-Express

SPI

USB

U5LB

DM

I0RXN DMI0RXP DMI0TXN DMI0TXP

DMI1RXN DMI1RXP DMI1TXN DMI1TXP

DMI2RXN DMI2RXP DMI2TXN DMI2TXP

DMI3RXN DMI3RXP DMI3TXN DMI3TXP

DMI_CLKN DMI_CLKP

Direct Media Interfa ce

DMI_ZCOMP

DMI_IRCOMP

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P

USBRBIAS#

USBRBIAS

IC

V27

DMI_MT_IR_0_DN

V26

DMI_MT_IR_0_DP DMI_IT_MR_0_DN

U29 U28

D

MI_IT_MR_0_DP

DMI_MT_IR_1_DN

Y27 Y26

DMI_MT_IR_1_DP

W29

DMI_IT_MR_1_DN

W28

DMI_IT_MR_1_DP

DMI_MT_IR_2_DN

AB26 AB25

DMI_MT_IR_2_DP

AA29

DMI_IT_MR_2_DN

AA28

DMI_IT_MR_2_DP

AD27

DMI_MT_IR_3_DN

AD26

DMI_MT_IR_3_DP

AC29

DMI_IT_MR_3_DN DMI_IT_MR_3_DP

AC28

CK_PE_100M_ICH_DN

T26 T25

CK_PE_100M_ICH_DP

Y23

LB_DMI_IRCOMP

Y24

USB_0_DN

G3

USB_0_DP

G2

USB_1_DN

H5

USB_1_DP

H4

USB_2_DN

H2

USB_2_DP

H1

USB_3_DN

J3

USB_3_DP

J2

USB_4_DN

K5

USB_4_DP

K4 K2

USB_5_DN

K1

USB_5_DP

L3

USB_6_DN USB_6_DP

L2

USB_7_DN

M5

USB_7_DP

M4 M2

USB_8_DN USB_8_DP

M1

USB_9_DN

N3 N2

USB_9_DP

F2

LB_USB_RBIAS

F3

12

IN

12

IN

12

OUT

12

OUT

12

IN

12

IN

12

OUT

12

OUT

12

IN

12

IN

12

OUT

12

OUT

12

IN

12

IN

12

OUT

12

OUT

IN IN

R54LB

V_1P5_FILTERED

1CH2

24.9

1%

603

(JACK ON MB)

(JACK-CHASSIS UP SIG)

(FINGER R- CHASSIS DN SIG)

REPLICATOR PORT)

(

(MINIPCIE FOR ROBSON)

(MINIPCIE FOR WLAN)

(EXPRESS CARD )

(BLUETOOTH CONN)

(CAMERA (INV CONN)

1

R60LB

22.6 1%

CH

2

402

24 24

29

32

IN

54

BI

54

BI

53

BI

53

BI

53

BI

53

BI

54

BI

54

BI

82

BI

82

BI

40

BI

40

BI

39

BI

39

BI

37

BI

37

BI

52

BI

52

BI

26

BI

26

BI

ICH8M

REV=1.05

PERN1 PERP1 PETN1 PETP1

PERN2 PERP2 PETN2 PETP2

PERN3 PERP3 PETN3 PETP3

PERN4 PERP4 PETN4 PETP4

PERN5 PERP5 PETN5 PETP5

P

ERN6/GLAN_RXN PERP6/GLAN_RXP PETN6/GLAN_TXN PETP6/GLAN_TXP

SPI_CLK SPI_CS0#

_CS1#

SPI

SPI_MOSI SPI_MISO

OC0# OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43 OC5#/GPIO29 OC6#/GPIO30 OC7#/GPIO31 OC8# OC9#

4OF6

OUT OUT

IN IN

PCIE_RX1_DN PCIE_RX1_DP

PCIE_RX2_DN PCIE_RX2_DP

PCIE_RX3_DN PCIE_RX3_DP

PCIE_RX4_DN PCIE_RX4_DP

GLAN_RX_DN

GLAN_RX_DP GLAN_TX_C_DN GLAN_TX_C_DP

35

54

33 33

53

33

53

33

54 82

33 33 33 33 33 33

PCIE_TX1_C_DN PCIE_TX1_C_DP

PCIE_TX2_C_DN PCIE_TX2_C_DP

PCIE_TX3_C_DN PCIE_TX3_C_DP

PCIE_TX4_C_DN PCIE_TX4_C_DP

TP_PCIE_RXN5_DOCK

TP_PCIE_RXP5_DOCK

TP_PCIE_TXN5_C

TP_PCIE_TXP5_C

SPI_CLK_R SPI_CS0_R_N SPI_CS1_R_N

SPI_MOSI_R SPI_MISO

IN

USB_OC0_N

IN

USB_OC1_N

IN

USB_OC2_N

IN

USB_OC3_N

IN

USB_OC4_N

IN

USB_OC5_N

IN

USB_OC6_N

IN

USB_OC7_N

IN

USB_OC8_N

IN

USB_OC9_N

IN

39

C10LB

2

PCIE_TX1_DN

39

OUT

P

OUT

BI

OUT

CIE_TX1_DP

PCIE_TX2_DN

PCIE_TX2_DP

PCIE_TX3_DN

PCIE_TX3_DP

PCIE_TX4_DN

PCIE_TX4_DP

GLAN_TX_DN

GLAN_TX_DP

SPI_CLK

SPI_CS0_N

SPI_CS1_N

SPI_MOSI

39

37

C

B

37

40

54

46

35

3335

35

1

.1UF 10%

10V

X5R

12LB

C

1

.1UF

10%

10V

X5R

C

14LB

1

.1UF 10%

10V

X5R

C16LB

1

.1UF 10%

10V

X5R

C19LB

1

.1UF 10%

10V

X5R

R115LB

1

2

1%CH15

402

CAD NOTE:

PLACE CLOSE TO ICH <500 MILS

402

2

402

2

402

2

402

2

402

R75LB

2

15

402

X5R

.1UF

X5R

.1UF

X5R

.1UF110%

X5R

R57LB

1

C

10V

C11LB

10V

C13LB

10V

C15LB

10V

C18LB

10V

2

1%15 CH

1

1%

CH

9LB

2

10%.1UF

402

2

10%

402

2

10%.1UF

402

2

10%

402

2

402

R56LB

2

1

15

1% CH

402

39

37 37

40 40

54 54

46 46

P27 P26 N29 N28

M27 M26 L29 L28

K27 K26 J29 J28

H27 H26 G29 G28

F27 F26 E29 E28

D27 D26 C29 C28

C23 B23 E22

D23 F21

AJ19 AG16 AG15 AE15 AF15 AG17 AD12 AJ18 AD14 AH18

D

C

B

REV

2.0

A

VCC3

1

2

8

C17LB

0.1UF 20%

16V Y5V 402

C20LB

.1UF 10% 10V

2

X5R 402

BPAGE DRAWING

tawas_b.sch_1.30

Wed Feb 07 17:18:31 2007

7

6

5

4 2

3

[PAGE_TITLE=ICH8M (2 OF 5)]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

30

1

CR-31 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE31

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

ICH8M_TW

1

REV

04.08.00 2-2-07

DATE

D

I

CH8M

RESET#

N_DOCK#/GPIO12

3OF6

REV=1.05

SMB

GPIO

SYS

GPIO

MISC

333739

40 40

333739 3339 33 33

19

IN

CAD NOTE:

OUT

IN

V_3P3_M

1

2

402

HDA_SPKR

MCH_ICH_SYNC_N

R66LB

10K

5% EMPTY

402

R168LB

1

0

402

R

169LB

1

0

2

5%

EMPTY

2

5% CH

R80LB

5% EMPTY

2

1K

1

2

VCC3

402

R82LB

1

402

5%

R67LB

10K

5% EMPTY

603

1

R77LB

5% CH

2

402

2

CH

0

CH

100K

2

11

R81LB

10K

5% EMPTY

33 32

20

3539

4647

72

83

71

69 48

C

PM_STPPCI_N

23

OUT

PM_STPCPU_N

23

OUT

VCCP_CLK_EN

33

IN

ICH_VRMPWRGD

31

55

77

IN

OVERLAP PADS

B

42

12

33

59 55

6

50

12

33

1

0

2

70LB

R

402

5%10

402

33

5580

333739

4054

33

5559

9

33

55

IN

55

IN

5556

BI

48 39

BI

52

BI

52

BI

33

OUT OUT

33

IN

33

IN

402

33

IN

SMB_CLK_A ICH_SERIAL_POST

BI

SMB_DATA_A

BI

CL_RST1_N

BI

SMLINK_CLK_ME_EC

BI

SMLINK_DATA_ME_EC

BI

PM_RI_N

IN

LPCPD_N

OUT

XDP_DBRESET_N

IN

PM_BMBUSY_N

IN

SMB_ALERT_N

IN

74LB

R

2

CH

5%

BI

IN

BI

IN

EC_EXTSMI_N

EC_RUNTIME_SCI _N EC_WAKE_SCI_N LAN_PHYPC_GPIO12 RF_KILL_N FWH_TBL_N

FWH_WP_N

LB_SOP_EN CK_OE_SATA_N

ICH_CONFIG_JMPR2

BOARD_ID2 BOARD_ID3

PM_STPPCI_ICH_N PM_STPCPU_ICH_N

PM_CLKRUN_N

PCIE_WAKE_N SER_IRQ PM_THRM_N

TP__LB_GPIO20

TP_ICH_AJ22

TP_HP_AMP_EN

TP_LB_GPIO27

MCH_ICH_SYNC_R_N

TP_ICH8_TP3

AJ26 AD19 AG21 AC17 AE19

AF17

AD15

AG12

AG22

AE20 AG18

AH11

AE17 AF12 AC13

AJ20

AJ22

AJ8 AJ9

AH9 AE16 AC19

AG8 AH12 AE11 AG10 AH25 AD16 AG13

AF9 AJ11 AD10

AD9

AJ13

AJ21

F4

SMBCLK SMBDATA

LINKALERT#/CL_RST1# SMLINK0 SMLINK1

RI#

SUS_STAT#/LPCPD# SYS_

BMBUSY#/GPIO0

SMBALERT#/GPIO11

STP_PCI#/GPIO15

TP_CPU#/GPIO25

S

CLKRUN#/GPIO32

WAKE# SERIRQ THRM#

VRMPWRGD

TP7

TACH1/GPIO1 TACH2/GPIO6 TACH3/GPIO7 GPIO8 GLA TACH0/GPIO17 GP

IO18 GPIO20 SCLOCK/GPIO22 QRT_STATE0/GPIO27 QRT_STATE1/GPIO28 SATACLKREQ#/GPIO35 SLOAD/GPIO38 SDATAOUT0/GPIO39 SDATAOUT1/GPIO48

SPKR

MCH_SYNC#

TP3

S

ATA0GP/GPIO21 SATA1GP/GPIO19 SATA2GP/GPIO36

GPIO

SATA

SATA3GP/GPIO37

CLK

S4_STATE#/GPIO26

DPRSLPVR/GPIO16

Power MGT

MEM_LED/GPIO24

ALERT#/GPIO10

NETDETECT/GPIO14

Controller Link

WOL_EN/GPIO9

U5LB

CLK14 CLK48

SUSCLK

SLP_S3# SLP_S4# SLP_S5#

BATLOW#

PWRBTN#

LAN_RST#

RSMRST#

CK_PWRGD

CLPWROK

SLP_M#

CL_CLK0 CL_CLK1

CL_DATA0 CL_DATA1

CL_VREF0 CL_VREF1

CL_RST0#

PWROK

IC

AJ12 AJ10 AF11 AG11

AG9 G5

D3

AG23 AF21 AD18

AH27

AE23

AJ14

AE21

C2

AH20

AG27

E1

E3

AJ25

F23 AE18

F22 AF19

D24 AH23

AJ23

AJ27 AJ24 AF22 AG19

TP_SUS_CLK

TP_SLP_S5_N

LB_ICH_PWROK

PM_DPRSLPVR_R

BOARD_ID0 BOARD_ID1 BOARD_ID4

CK_14M_ICH CK_48M_USB_ICH

R71LB

1

402

1

R143LB

100K

5% CH

2

402

OUT

IN IN IN

IN IN

H_DPRSLPVR

2

CH

5%100

PM_BATLOW_R_N

PM_PWRBTN_N

PM_LAN_RST_R_N

CK_PWRGD

CLPWROK

SLP_M_N

CL_CLK0 CL_CLK1

CL_DATA0

CL_DATA1

CL_VREF0_ICH

L_VREF1_ICH

C

CL_RST0_N

GPIO_VSM_AMT_LED

SUSPWR_ACK AC_PRESENT

33 33 33 33

24 24

OUT

IN IN IN

OUT

OUTOUT

IN

BI BI

IN IN

BI

OUT

IN

12

33

55

33

22

12

22 56 69 70

33 33

77

12 39

12

33 33 56

SLP_S3_N

SLP_S4_N

S4_STATE_N

1

2

1

72

2

71

72

56

R93LB

100K

5% CH

402

R117LB

100K 5%

CH 402

OUT

R171LB

1

0

402

R170LB

1

0

402

1

2

26

37

18

61 71

55

69

2

5%

EMPTY

OVERLAP PADS

2

DELAY_VR_PWRGOOD

5% CH

V_3P3_STBY\G

R176LB

1K

5% EM

PTY

402

WOL_EN

55

69 72 75

ICH_VRMPWRGD

CAD NOTE:

PM_RSMRST_N

IN

OUT

31

IN

12

IN

55

IN

56 65 67 68 69 72 9

22 26

32 33 37 40 44 50 52 54 55 75 77

56

D

C

55 77

55

B

REV

2.0

A

BPAGE DRAWING

tawas_b.sch_1.31

Thu Feb 08 16:11:49 2007

8

7

6

5

4 2

3

[PAGE_TITLE=ICH8M (3 OF 5)]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

31

1

CR-32 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE32

8

7

6

45

3

VCC3

V_1P05_CORE

16

17

182329

7177

D

68

71

406264

71

16

1718

2329

32

77

C

1

C36LB

.1UF 10% 10V

2

X5R 402

8101415

IN

32

6263

12

IN

81618

81014

V_1P5_CORE

IN

V_1P05_CORE

IN

1

C63LB

220UF 20%

2.5V TAN

2

7343

V_1P25_CORE

T

161718

323739

15

6263

71

1

C32LB

.1UF 10% 10V

2

X5R 402

ICH8M

603

A13

VCC1_05[01]

R120LB

1

B13

C13

C14

VCC1_05[02]

VCC1_05[03]

1

2

5% CH

D14

VCC1_05[04]

VCC1_05[05]

E14

VCC1_05[06]

C

4.7UF 10%

6. X5R 603

LB_1P5_L

F14

VCC1_05[07]

40LB

3V

G14

VCC1_05[08]

2

L11

VCC1_05[09]

1

C28LB

22. 20%

6.3V X5R 805

L14

L12

VCC1_05[10]

L2LB

1

VCC1_05[11]

000UF

L16

VCC1_05[12]

1

2

1UH

IND

L17

VCC1_05[13]

C

.1UF 10% 10V X5R 402

2

L18

M11

VCC1_05[14]

VCC1_05[15]

CORE

39LB

M18

VCC1_05[16]

P11

VCC1_05[17]

1

2

P18

VCC1_05[18]

1

38LB

C

UF

.1 10% 10V

2

X5R 402

VCCDMIPLL_ICH

1

C

37LB

10UF 20%

6.3V

2

X5R 805

8

T11

U11

V11

T18

U1

V12

V14

VCC1_05[19]

VCC1_05[20]

VCC1_05[21]

VCC1_05[22]

VCC1_05[23]

VCC1_05[24]

VCC1_05[25]

C27LB

.01UF

10% 25V X7R 402

V17

V16

VCC1_05[26]

V18

R29

CC1_05[28]

VCC1_05[27]

V

VCCA3GP

C46LB

.1 10%

10V X5R 402

E7

F11

VCC3_3[23]

ATX

1

C47LB

.1

AC12

VCCHDA

UF 10% 10V

2

X5R 402

1

C65LB

.1

UF 10% 10V

2

X5R 402

TP_VCCSUS1_05_INT_ICH_2

TP_VCCSUS1_5_ICH_2

TP_VCCSUS1_5_ICH_1

TP_VCCSUS1_05_INT_ICH_1

AF20

J7

AC16

J6

AD11

VCCSUSHDA

VCCSUS1_05[1]

VCCSUS1_05[2]

VCCSUS1_5[1]

VCCSUS1_5[2]

C3

VCCSUS3_3[01]

1

2

AC18

VCCSUS3_3[02]

C66LB

.1UF 10% 10V X5R 402

AC22

AC21

VCCSUS3_3[03]

VCCSUS3_3[04]

AG20

VCCSUS3_3[05]

1

2

AH28

VCCSUS3_3[06]

C67LB

X5R 402

P7

P6

VCCSUS3_3[07]

.1UF 10% 10V

C1

VCCSUS3_3[09]

VCCSUS3_3[08]

N7

VCCSUS3_3[10]

P1

VCCSUS3_3[11]

1

2

P3

P2

VCCSUS3_3[13]

VCCSUS3_3[12]

C68LB

4.7UF 20%

16V

X5R

1206

P5P4R6R5R3

VCCSUS3_3[15]

VCCSUS3_3[14]

R1

VCCSUS3_3[16]

VCCSUS3_3[18]

VCCSUS3_3[17]

VCCPUSB VCCPSUS

UF

VCC3_3[24]

USB CORE

C45LB

.1

UF 10% 10V X5R 402

B4

B18A8B15B9C15

VCC3_3[17]

VCC3_3[16]

1

2

1

64LB

C

.1UF 10% 10V

2

X5R 402

D5

D13

E10

VCC3_3[18]

VCC3_3[19]

VCC3_3[20]

VCC3_3[22]

VCC3_3[21]

PCI IDE

C44LB

UF

.1 10% 10V X5R 402

W6

VCC3_3[10]

VCC3_3[11]

1

2

VCC3_3[13]

VCC3_3[12]

VCC3_3[14]

VCC3_3[15]

1

2

C31LB

UF

.1 10%

10V X5R 402

1

C30LB

.1UF 10% 10V

2

X5R 402

1

2

AC24

AC23

AF29

AE29

AE28

VCCDMIPLL

VCC_DMI[2]

VCC_DMI[1]

AD2

VCC3_3[01]

VCC3_3[02]

V_CPU_IO[2]

V_CPU_IO[1]

VCCP_CORE

AC8

VCC3_3[03]

AD8

AE8

VCC3_3[04]

VCC3_3[05]

AF8

VCC3_3[06]

U7V7W1Y7W7

AA3

VCC3_3[07]

VCC3_3[08]

VCC3_3[09]

ARX

REV=1.05

B

V_3P0_BAT_VREG

29

33

IN

1

C24LB

.1UF 10% 10V

2

X5R

VCC3

VCC

A

7577 566567 404450

9

2226

31 37

45

77

32 40

IN

3233 525455 686972

7883 66686970 92633

IN

61

6265

7576

71

6264 81618

IN

37

39

402

R119LB

1

2

5%

100

CH

603

V_3P3_STBY\G

V_5P0_STBY\G

V_1P5_CORE

2

CR2LB

1

2

CR3LB

1

R118LB

603

1

8

U5LB

C25LB

.1UF 10% 10V X5R 402

BAT54C

SOT23C DIO

BAT54C

SOT23C DIO

2

5%CH10

EF[1]

V5R

VCC1_5_B[01]

VCCRTC

AD25

1

C26LB

.1UF 10% 10V

2

X5R 402

3

VCC1_5_B[02]

V5REF_SUS

V5REF[2]

T7

G4

A16

AA26

AA25

VCC5REF

V5REF_SUS

1

2

3

7

VCC1_5_B[03]

VCC1_5_B[04]

AB27

AA27

C33LB

.1UF 10%

10V X5R 402

VCC1_5_B[09]

VCC1_5_B[05]

VCC1_5_B[06]

VCC1_5_B[07]

VCC1_5_B[08]

VCC1_5_B[10]

VCC1_5_B[11]

VCC1_5_B[13]

VCC1_5_B[12]

VCC1_5_B[16]

VCC1_5_B[14]

VCC1_5_B[15]

VCC1_5_B[17]

VCC1_5_B[18]

VCC1_5_B[21]

VCC1_5_B[19]

VCC1_5_B[20]

VCC1_5_B[22]

VCC1_5_B[23]

VCC1_5_B[26]

VCC1_5_B[24]

VCC1_5_B[25]

VCC1_5_B[28]

VCC1_5_B[27]

VCC1_5_B[29]

VCC1_5_B[30]

VCC1_5_B[31]

H24

H23

L23

K24

K25

L24

D29

E26

E27

F25

F24

G24

E25

D28

AB28

AB29

J23

J24

L25

N23

M24

M25

N25

N24

P24

P25

R24

V_1P5_FILTERED

C42LB

22.

000UF

20%

6.3V X5R 805

1

2

1

L3LB

2

V_1P5_S_APLL_ICH_R

R

1

5% CH

2

603

1

C

41LB

220UF 20%

2.5V

2

TANT

2

SM

1.5A BROAD

1

330

FB3LB FB

UNKN

2

C34LB

22.000UF 20%

6.3V X5R 805

10UH IND

122LB

1

C29LB

2.2UF 10%

6.3V

2

X5R 603

1

C35LB

10UF

20%

6.3V

2

X5R 805

6

VCC1_5_B[38]

VCC1_5_B[32]

VCC1_5_B[33]

VCC1_5_B[34]

VCC1_5_B[36]

VCC1_5_B[35]

VCC1_5_B[37]

VCC1_5_B[39]

T28

R25

R26

R27

T24

T23

T27

T29

29

OUT

V_1P5_S_APLL_ICH

1

C43LB

1UF 20%

6.3V

2

X5R 603

5

VCC1_5_B[40]

U24

30 32

VCC1_5_B[41]

VCC1_5_B[44]

VCC1_5_B[43]

VCC1_5_B[45]

VCC1_5_B[46]

VCCSATAPLL

VCC1_5_A[01]

VCC1_5_A[02]

VCC1_5_A[03]

VCC1_5_A[05]

VCC1_5_A[06]

VCC1_5_A[07]

VCC1_5_A[08]

VCC1_5_A[09]

VCC1_5_A[10]

VCC1_5_A[11]

VCC1_5_A[14]

VCC1_5_A[13]

AC2

AC3

C49LB

1UF 20%

6.3V X5R 603

AC4

AC5

VCC1_5_A[12]

AA6

AA5

AC9

AC10

VCC1_5_B[42]

U25

V25

V24

W25

Y25

V23

VCC1_5_A[04]

AJ6

AE7

AF7

AG7

AJ7

AH7

AC1

1

C48LB

1UF

20%

6.3V

2

X5R 603

1

2

4 2

VCC1_5_A[19]

VCCUSBPLL

VCC1_5_A[17]

VCC1_5_A[18]

D1

AD7

AC7

1

C51LB

.1UF 10% 10V

2

X5R 402

tawas_b.sch_1.32

VCC1_5_A[20]

F1

VCC1_5_A[15]

VCC1_5_A[16]

2

H7

G17

G1

1

C50LB

.1UF 10% 10V

2

X5R 402

BPAGE DRAWING

Wed Feb 07 17:18:34 2007

3

VCCLAN1_05[1]

VCC1_5_A[25]

W23

F17

TP_VCCLAN1_05_ICH_1

VCCLAN1_05[2]

G18

TP_VCCLAN1_05_ICH_2

VCCLAN3_3[1]

VCCLAN3_3[2]

G20

F19

VCC1_5_A[22]

VCC1_5_A[21]

VCC1_5_A[23]

VCC1_5_A[24]

L7

L6

M6

M7

1

2

1

C52LB

.1UF 10% 10V

2

X5R 402

[

PAGE_TITLE=ICH8M (4 OF 5)]

2

V_3P3_STBY\G

VCCCL1_5_INT_ICH

1

C69LB

1U 20%

6.3V

2

EMPTY 603

TP_VCCCL1_05_ICH

G21

F20

A22

G22

VCCCL1_5

VCCCL1_05

VCCCL3_3[2]

VCCCL3_3[1]

VCCSUS3_3[19]

GLAN POWER

VCCGLAN1_5[4]

VCCGLAN1_5[1]

VCCGLAN1_5[5]

VCCGLANPLL

VCCGLAN1_5[3]

VCCGLAN1_5[2]

B26

B28

A27

A24

A26

B27

1

C55LB

4.7UF 10%

3V

6.

2

X5R 603

L1LB

1UH

1

GLAN_PLL_R_L

C53LB

10UF

20%

6.3V X5R 805

CUSTOM TEXT BPAGE

IND

1

54LB

C

2.2UF 10%

6.3V

2

X5R 603

V_3P3_M

INTEL

CONFIDENTIAL

MODULE REV DETAILS

MODULE NAME

F

ICH8M_TW

IN

1

C70LB

.1

UF 10% 10V

2

EMPTY 402

V_3P3_M

04.08.00 2-2-07

9

222631

54 55 56 65 67 68 69 72 75

32

19 20

IN

48 69

IC

5665676869727577 5052

3337

V_3P3_STBY\G

9

2226

IN

31

32

6OF6

4044 5455

VCCGLAN3_3

VCC3

B25

V_1P5_FILTERED

2

GLAN_PLL_R

R121LB

1

5% CH

2

603

IN

1

C23LB

.1UF 10% 10V

2

X5R 402

IN

V_1P5_CORE

19 203132 33 35 39

71

69

DOCUMENT_NUMBER

IN

72 83

D89092

1

REV

33 374044 50 52

31

32 33 35 39

71

72 83

1

C58LB

.1UF 10% 10V

2

EMPTY 402

30 32

29

81618 323739 62 64

71

46 47 48

PAGE

32

1

DATE

77

46 47

REV

2.0

D

C

B

A

40

CR-33 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE33

8

CL VREF DIVIDERS

3233

37

56656768697275 9

2226

31

IN

404450525455 77

D

3233

29

C

R11LB

H_INIT_N

6

29

IN

1

330 402

B

SOP ENABLE STRAP

DESIGN NOTE:

SOP DISABLE/ENABLE

31

A

65676869 40445052

V_3P3_STBY\G

9

2226

31

37

IN

323337 545556 727577

SMB_CLK_A

31

33

IN

39

40

33

40

SMB_DATA_A

31

IN

39

8

V_3P3_STBY\G

CL_VREF1_ICH

1

C22LB

.1UF 10% 16V

2

X7R 603

V_3P0_BAT_VREG

IN

29

OUT

2

LB_H_INIT_QB

5% CH

LB_SOP_EN

IN

R129LB5%R130LB

1

2.2K 5%

CH

2

402

1

R83LB

3.24K 1%

CH

2

603

R85LB

1

453

1%

2

CH 603

ICH_INTVRMEN

VCC3

1

R12LB

1.3K 1%

CH

2

603

LB_H_INIT_QC

3

Q1LB

1

MMBT3904 XSTR

2

R146LB

1

2.2K

CH

1

2

2.2K

CH 402

32

2

402

5%

7

31

46474869

OUT

1

R50LB

390K

5% CH

2

603

R52LB

1

0 5%

EMPTY

2

402

1

2

1

LB_SOP_QB

7

71

7283

1920 3539

31

R13LB

330

5% CH

402

FWH_INIT_N

3

Q2LB

MMBT3904 XSTR

2

BSS138N

Q3LB

D

3

IN

VCC3

1

2

1

VCC

FET

3

Q4LB

8.2K 402

R78LB

1

3.24K 1%

CH

2

603

1

C21LB

.1UF 10% 16V

2

X7R 603

52

OUT

R167LB

10K

5% CH

402

GP33_SOP_EN_N

3

Q5LB

M

MBT3904

XSTR

2

VCC3

1

G

S

2

1

G

S

D

6

R89LB

LB_LRST_NV_3P3_M PM_LAN_RST_R_N

1

2

5%

174LB

R

1

CH

4.7K 5%

CH

2

402

CL_VREF0_ICH

1

R79LB

453

1%

2

CH 603

77

IN

BOM NOTE:

ALWAYS STUFF

29

OUT

R131LB

2.2K 5%

CH 402

1

2

R132LB

2.2K 5%

CH 402

SMB_CLK_S

1

2

SMB_DATA_S

BSS138N

FET

2

6

R175LB

1

402

V

2

5%330 CH

OUT

CCP_CLK_EN_N

404450

A95531-

IN

2

31

R172LB

1

330 5%

402

37

6265666869 7883

19 20

404450

1

C74LB

1.0UF

20%

10V Y5V 603

2

EMPTY

OUT

LB_VCCP_CLK_QB

31

323337

VCC3

1

R162LB

1K

5%

2

CH

J3LB

1X3HDR

402

HDR_CONF_JMPR1

1

2

HDR_SERIAL_POST HDR_CONF_JMPR2

3

HDR

004

DESIGN NOTE:

DEBUG O PTION TO BOOT IN NORMAL MODE [1-2] IF JUMPER IS NOT AVAILABLE

2226313233 525455566567686972

45

61 77

707576

21

22 50

21

22 50

33

37

39

40

33

37

39

40

5

77

54

53

54

82

1

75 2226 525455566567686972

VCC3

1

2

30

9

VCCP_CLK_EN

3

2

V_3P3_STBY\G

IN

USB_OC0_N

OUT

USB_OC1_N

OUT

USB_OC2_N

OUT

USB_OC3_N

OUT

USB_OC4_N

OUT

USB_OC5_N

OUT

USB_OC6_N

OUT

USB_OC7_N

OUT

USB_OC8_N

OUT

SB_OC9_N

U

OUT

BOM NOTE:

R50LB AND R51LB SHOULD BE 332K OHMS

IPN A93550-266

R173LB

1K 5%

PTY

EM 402

Q11LB

MMBT3904 EM

PTY

37

3233

402

OUT

R65LB

2

1

CH

5%

10K

402

R84LB

1

2

CH

5%

10K

402

R95LB

2

1

CH

10K

5%

402

R97LB

2

1

CH

5%

10K

402

R58LB

2

1

CH

5%

10K

402

3233

29

IN

29

OUT

31

676869727577

V_3P3_STBY\G

9

2226

31

IN

4044505254555665

31

OUT

R73LB

1

10K

R86LB

1

10KCH5%

R96LB

1

10K

R98LB

1

10K

R59LB

1

10K

V_3P0_BAT_VREG

LAN100_SLP

GPIO_VSM_AMT_LED

CONFIG/MFG MODE STRAPS

R157LB

1

2

2.2K

45

1

2

1

G

S

5% CH

402

R158LB

2

1

100

5% CH

402

160LB

R

1

5%

2.2K CH

402

R164LB

2.2K 5%

EMPTY 402

SMB_BAT2_CLK

SMB_BAT2_DATA

EMPTY

BSS138N

2

R159LB

1

BSS138N

3

EMPTY

Q9LB

10K 5%

2

CH 402

1

R161LB

10K 5%

2

CH 402

1

G

S

D

2

D

3

1

R166LB

0 5%

EMPTY

2

402

7577

V_3P3_STBY\G

9

IN

V_5P0_STBY\G

92632

IN

SMB_CLK_A

31

IN

SMB_DATA_A

31

IN

Q10LB

4 2

3

2

CH

5%

2

CH

5%

2

CH

5%

2

CH

5%

1

2

1

2

1

2

1

2

ICH_CONFIG_JMPR1

ICH_SERIAL_POST

2

ICH_CONFIG_JMPR2

DESIGN NOTE:

TO ICH

1

R165LB

2.2K 5%

2

EMPTY 402

BPAGE DRAWING

tawas_b.sch_1.33

Thu Feb 08 15:59:54 2007

3

2

MODULE REV DETAILS

MODULE NAME

4044

R51LB

390K

5% CH

603

R53LB

0 5%

EMPTY 402

R149LB

10K

5% CH

402

R154LB

2.7K 5%

PTY

EM 402

OUT

ICH8M_TW

77

697275

V_3P3_STBY\G

9

2226

31

323337

4054

29

31

IN

31

IN

5052545556656768

56

39

31

5559

5580

31 31 31 31 31

SUSPWR_ACK

31

IN

PM_RI_N

31

OUT

CL_RST1_N

31

IN

SMLINK_CLK_ME_EC

31

IN

SMLINK_DATA_ME_EC

31

IN

SMB_ALERT_N

31

OUT

PCIE_WAKE_N

3137

IN

PM_BATLOW_R_N

31

OUT

CK_OE_SATA_N

24

IN

PM_THRM_N

9

31

IN

SER_IRQ

31

IN

PM_CLKRUN_N

31

IN

VCC3

BOARD_ID0

OUT

BOARD_ID1

OUT

BOARD_ID2

OUT

BOARD_ID3

OUT

BOARD_ID4

OUT

P_GNT_N<3>

34

IN

SPI_CS1_N

3035

IN

P_GNT_N<0>

34

80

IN

1

10K

1

10K

1

R1LB

10K

5%

EMPTY

2

402

1

R6LB R7LB

10K

5%

CH

2

402

R106LB

5%

R109LB

5%

1

2

1

2

1

2

04.08.00 2-2-07

BOM NOTE:

EMPTY C90LB FOR ME,AMT

R87LB

2

1

CH

402

10K

5%

R91LB

1

2

CH

402

10K

5%

R100LB

1

2

CH

402

10K

5%

R103LB

2

1

CH

402

8.2K 5%

2

CH

402

2

402

R2LB

10K

5%

EMPTY 402

10K

5%

CH 402

R62LB

1K 5%

CH 402

CH

R3LB

10K110K 5%

EMPTY

2

402

1

R8LB

10K 5%

CH

2

402

1

2

1

8.2K

R64LB

5% EMPTY

603

BOOT SELECT STRAPS

DEVICE GNT#<0> CS1#

26 52 55 58

IN

26 52 55 58

IN

[PAGE_TITLE=ICH8M STRAPS/ISOLATION]

BOOT-

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

SPI 0 X PCI 1 0 FWH 1 1

DOCUMENT_NUMBER

D89092

R107LB

R108LB

1

1K

1

2

1

REV

10K

R155LB

1

R90LB

1

R92LB

1

R101LB

1

1K

2

402

5%

R4LB

5%

EMPTY 402

R9LB

10K

5%

CH 402

1

DATE

2

CH

5%

402

2

EMPTY

5%

402

2

CH

5%

402

2

5%

CH 402

CH

2

CH

402

1

R5LB

10K 5%

EMPTY

2

402

D

V

CC3

C

B

1

R10LB

10K 5%

CH

2

402

1

R61LB

1K 5%

EMPTY

2

603

A

PAGE

REV

33

2.0

1

CR-34 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE34

8

7

6

45

3

2

MODULE REV DETAILS

NAME

MODULE

ICH8M_TW

1

V

RE

04.08.00 2-2-07

E

DAT

VCC3

U5LB

P_AD<31..0>

80

BI

D

C

34

80

P_INTA_N

BI

P_INTB_N

34

IN

P_INTC_N

34

IN

P_INTD_N

34

IN

D20

0

E19

1

D19

2

A20

3

D17

4

A21

5

A19

6

C19

7

A18

8

B16

9

A12

10

E16

11

A14

12

G16

13

A15

14

B6

15

C11

16

A9

17

D11

18

B12

19

C12

20

D10

21

C7

22

F13

23

E11

24

E13

25

E12

26

D8

27

A6

28

E8

29

D6

30

A3

31

F9 B5 C5

A10

ICH8M

R

EV=1.05

AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD

12 AD13 AD14

PCI

AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31

terrupt I/F

In

PIRQA# PIRQB# PIRQC# PIRQD#

REQ0#

GNT0# REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 REQ3#/GPIO54 GNT3#/GPIO55

C/BE0# C/BE1#

C/BE2#

C/BE3#

PCIRST# DEVSEL#

PERR#

PLOCK#

SERR#

STOP#

TRDY#

FRAME#

PLTRST#

PCICLK

2OF6

PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5

IRDY#

PME#

P_REQ_N<0>

A4

P_GNT_N<0>

D7

P_REQ_N<1>

E18

TP_P_GNT_N<1>

C18

P_REQ_N<2>

B19

TP_P_GNT_N<2>

F18

P_REQ_N<3>

A11

P_GNT_N<3>

C10

P_C/BE_N<0>

C17

P_C/BE_N<1>

E15

P_C/BE_N<2>

F16

P_C/BE_N<3>

E17

P_IRDY_N

C8

P_PAR

D9

PAR

G6 D16 A7 B7 F10 C16 C9 A17

AG24 B10 G7

F8 G11 F12 B3

P_PCIRST_N P_DEVSEL_N P_PERR_N P_LOCK_N P_SERR_N P_STOP_N P_TRDY_N P_FRAME_N

PLTRST_N CK_P_33M_ICH P_PME_N

P_INTE_N P_INTF_N P_INTG_N P_INTH_N

IC

IN

OUT

IN

OUT

BI BI BI BI

BI BI

OUT

BI BI BI BI BI BI BI

OUT

IN BI

IN IN IN IN

34

80

33

80

34

34 33

80 80 80 80

34

80

34

80

34

80 34 34

80 34

80

34 34

80

12 343752 59 24

80

34 34 34 34

37

5259

IDE RESET LEVEL SHIFTER / PCIE PWRGD BUFFER

VCC3

1

R145LB

10K 5%

2

EMPTY 402

LB_PLTBUF_R_N_QB

1

C73LB

150PF 5% 50V

2

EMPTY 402

PLTRST_N

1234

IN

1

2

DESIGN NOTE:

C72LB VALUE IS BU

VCC3

1

R147LB

1K 5%

PTY

2

EM 402

3

Q6LB

1

MMBT3904 EMPTY

2

C

150PF 5% 50V EMPTY 402

VCC3 VCC

72LB

C79254-001

CAD NOTE:

PLACE COMPONENTS NEAR ICH

MINIMIZE PLTRST_N BRANCH LENGTH

BUF_PLT_RST_N

R141LB

2

1

5%CH0

402

BOM NOTE:

STUFF R141LB TO BYPASS PLTRST_N BUFFER CIRCUIT

1

2

Q7LB

2

3

FET

R148LB

10K

5% CH

402

IDE_RST_N

OUT

36 39

40 54 55

36

80

OUT

P_TRDY_N

34

80

OUT

P_IRDY_N

34

80

OUT

P_STOP_N

34

80

OUT

P_SERR_N

34

80

OUT

P_PERR_N

34

80

OUT

P_DEVSEL_N

34

80

OUT

P_LOCK_N

34

OUT

80

P_REQ_N<0>

34

OUT

P_REQ_N<2>

34

OUT

P_REQ_N<1>

34

OUT

P_REQ_N<3>

34

OUT

P_INTA_N

34

OUT

P_INTB_N

34

OUT

P_INTC_N

34

OUT

P_INTD_N

34

OUT

P_INTE_N

34

OUT

P_INTF_N

34

OUT

P_INTG_N

34

OUT

P_INTH_N

34

OUT

P_FRAME_N

34

402

R14LB

1

8.2K

R16LB

1CH2

8.2K

R18LB

1

8.2K

R20LB

1

8.2K

R22LB

1

8.2K

R24LB

1

8.2K

R26LB

1

8.2K5%

R28LB

1

8.2K

R30LB

1

8.2K

R32LB

1

8.2K

2

CH

5%

R15LB

2

1

402

5%

8.2K

R17LB

2

1

402

8.2K

2

CH

2

CH

2

CH

2

CH

2

CH

2

CH

2

CH

2

CH

5%

R19LB

2

1

402

8.2K

5%

R21LB

2

1

402

5%

8.2K

R23LB

2

1

402

8.2K

5%

R25LB

2

1

402

8.2K

5%

R27LB

2

1

402

8.2K

5%

R29LB

2

1

402

5%

8.2K

R31LB

2

1

402

5%

8.

2K

R33LB

2

1

402

8.2K

5%

D

CH

C

CH

B

L4

K7

U5LB

VSS[099]

ICH8M

A

REV=1.05

VSS[001]

3 A2

L5

L26

L13

L15

L27

L1

VSS[100]

VSS[101]

VSS[102]

VSS[104]

VSS[103]

VSS[003]

VSS[002]

VSS[004]

VSS[005]

VSS[006]

5

A5

AB1

AA2

AA7

A2

M16

M14

M13

M12

M15

VSS[110]

VSS[106]

VSS[112]

VSS[111]

VSS[109]

VSS[108]

VSS[107]

VSS[105]

VSS[010]

VSS[011]

VSS[012]

VSS[013]

VSS[014]

VSS[009]

VSS[007]

VSS[008]

AC25

AC26

AC27

AD17

AD20

AC14

AB24

AC11

M23

VSS[113]

015]

VSS[

AD28

N12

N13

M29

M28N1M17

M3

N11

VSS[119]

VSS[118]

VSS[120]

VSS[116]

VSS[115]

VSS[114]

VSS[117]

VSS[018]

VSS[019]

VSS[020]

VSS[021]

VSS[022]

VSS[016]

VSS[017]

AE1

AD4

AD6

AE2

AD3

AE12

AD29

N27

N26

N18

N17

N16

N14

N15

VSS[123]

VSS[121]

VSS[122]

025]

VSS[023]

VSS[024]

VSS[

AD1

AE22

AE25

VSS[124]

VSS[026]

AE5

VSS[125]

VSS[027]

AE6

VSS[126]

VSS[028]

AE9

N6N5N4

VSS[127]

VSS[130]

VSS[129]

VSS[128]

VSS[030]

VSS[031]

VSS[032]

VSS[029]

AF3

AF18

AF16

AF14

P12

VSS[131]

VSS[033]

AF4

P13

VSS[132]

034]

VSS[

AG5

P23

P28

P29

P15

P17

P16

P14

VSS[134]

VSS[139]

VSS[138]

VSS[136]

VSS[135]

VSS[133]

VSS[137]

VSS[035]

VSS[036]

VSS[037]

VSS[038]

VSS[039]

VSS[040]

VSS[041]

AG6

AH2

AH10

AH13

AH16

AH19

AF28

R11

VSS[140]

VSS[042]

AH22

7

R18

R16

R15

R14

R13

R12

R1

VSS[146]

VSS[145]

VSS[144]

VSS[143]

VSS[142]

VSS[141]

VSS[043]

VSS[044]

VSS[045]

VSS[046]

VSS[047]

VSS[048]

5

AH3

AH4

AH8

AJ

AH24

AH26

VSS[147]

VSS[049]

B11

B14

VSS[148]

VSS[050]

VSS[149]

VSS[051]

B17B2B20

T15

T14

T13

T12R4R28

VSS[150]

VSS[052]

U12

VSS[157]

VSS[156]

VSS[155]

VSS[154]

VSS[153]

VSS[152]

VSS[151]

VSS[053]

VSS[054]

VSS[055]

VSS[056]

VSS[057]

VSS[058]

VSS[059]

B22B8C24

C26

C27C6D12D15

U13T2T17T16

158]

VSS[

VSS[060]

U26

U17

U16

U15

U14

U23

161]

VSS[164]

VSS[162]

VSS[

VSS[160]

VSS[159]

VSS[163]

VSS[061]

VSS[062]

VSS[063]

VSS[064]

VSS[065]

VSS[066]

D2

D4

D18

E24

E21

V29

V15

U27

V13

V28

W2

U5

U3

VSS[172]

VSS[171]

VSS[170]

VSS[169]

VSS[167]

VSS[166]

VSS[165]

VSS[168]

VSS[073]

VSS[071]

VSS[072]

VSS[067]

E4

VSS[074]

VSS[068]

VSS[069]

VSS[070]

G1

F7

E9

F28

F15

E23

F29

W26

VSS[173]

075]

VSS[

E2

W27

VSS[174]

VSS[076]

G10

AB23

W24

A28

AD5

AB6

AB5

Y29

Y28

AB4

Y4

VSS[180]

VSS[179]

VSS[177]

VSS[176]

VSS[175]

VSS[178]

VSS[077]

VSS[078]

VSS[079]

VSS[080]

VSS[081]

VSS[082]

G13

G19

G23

G25

G26

G27

A2

A1

U4

VSS[182]

VSS[181]

VSS[183]

VSS[184]

VSS_NCTF[03]

VSS_NCTF[02]

VSS_NCTF[01]

VSS[083]

VSS[084]

VSS[085]

VSS[086]

VSS[088]

VSS[089]

VSS[090]

VSS[087]

H6

H3

J1

H25

H28

H29

J25

J26

A29

J27

AJ29

AH29

B29

AJ2

B1

AJ1

AH1

AJ28

IC

VSS_NCTF[12]

VSS_NCTF[11]

VSS_NCTF[10]

VSS_NCTF[09]

VSS_NCTF[07]

VSS_NCTF[06]

VSS_NCTF[05]

VSS_NCTF[04]

VSS_NCTF[08]

VSS[091]

VSS[092]

VSS[093]

VSS[094]

VSS[095]

VSS[096]

VSS[098]

VSS[097]

5OF6

K3

K6

J4

J5

K23

K28

K29

B

A

[PAGE_TITLE=ICH8M (5 OF 5)]

BPAGE DRAWING

tawas_b.sch_1.34

Wed Feb 07 17:18:36 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

34

2.0

1

CR-35 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE35

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

ICH8M_TW

1

REV

04.08.00 2-2-07

DATE

D

V_3P3_M

1920

31

CAD NOTE:

R99LB

SPI1_MOSI_RFLASH

2

1

5% CH

2

SPI1_SCK_RFLASH

5%47 CH

464748

R104LB

25%1

47

EMPTY

402

CAD NOTE:

<500 MILS

32333539

7283

SPI2_MOSI_RFLASH

2

1

47

5%

EMPTY

69

71

7283

SPI2_SCK_RFLASH

R

110LB

19203132333539 69

IN

5 6 1

3

7

2

C56LB

0.

1UF 20% 16V

1

Y5V 402

8

U4LB

SPI_FLASH

VCC

SI

SCK

CS*

WP*

HOLD*

IN

5 6 1

3

7

VSS

4

V_3P3_M

SI

SCK

CS*

WP*

HOLD*

SPI1_MISO_FLASHR

2

SO

IC

BOM NOTE:

USE 32 MB 8PIN PART

IPN: D64145-002 CHANGE IN MODFILE

2

C57LB

0.1UF 20%

16V

1

PTY

EM 402

8

U3LB

SPI_FLASH

VCC

2

SPI2_MISO_FLASHR

SO

VSS

EMPTY

4

CAD NOTE:

PLACE CLOSE TO FLASH <500 MILS

R

88LB

2

1

1%

15

CH

402

CAD NOTE:

PLACE CLOSE TO FLASH <500 MILS

R

111LB

SPI2_MISO_FLSH_R2

2

1

15 1%

EMPTY

402

SPI

_MISO

R

112LB

1

2

0

5%

EMPTY

402

CAD NOTE:

LIMIT STUB LENGTH T O SPI_MISO

TO LESS THAN 500 MILS

30

OU

T

464748

PLACE CLOSE TO FLASH <500 MILS

SPI_MOSI

30

IN

SPI_CLK

30

C

464748

IN

19203132333539 69

IN

SPI_CS0_N

V_3P3_M

R140LB

SPI1_WP_PWR

1

3.3K

5% CH

2

402

SPI1_HOLD_PWR

R139LB

1

3.3K

5% EMPTY

2

402

30

71

7283

47

402

R102LB

1

402

B

1

3.3K

2

R114LB

3.3K

5%

2

EMPTY 402

SPI2_WP_PWR

SPI2_HOLD_PWR

R113LB

5%

EM

PTY

402

IN

SPI_CS1_N

3033

LIMIT STUB LENGTH

A

D

C

B

A

[PAGE_TITLE=ICH8M DUAL SPI]

8

7

6

BPAGE DRAWING

tawas_b.sch_1.35

Wed Feb 07 17:18:38 2007

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

35

2.0

1

CR-36 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE36

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

ICH8M_TW

1

REV

04.08.00 2-2-07

DATE

D

1

R123LB

8.

2K

5%

CH

2

603

R124LB

4.7K 5%

CH 402

ODD_LED_N

CDROM_CSEL

TP_LB_ODD_49

TP_LB_ODD_50

VCC

1

2

R125LB

4.7K 5%

CH 402

1

2

IDE_PDIORDY IDE_PDDACK_N INT_IRQ14

IDE_PDA<1>

IDE_PDA<0> IDE_PDA<2> IDE_PDCS1_N IDE_PDCS3_N

R134LB

10K

5% EMPTY

402

1

R128LB

470 5%

2

CH 603

OUT

29 29

IN

29

IN

29

IN

29

IN

29

IN

29

IN

VCC3

1

C

AUD_CD_A_L

43

OUT

AUD_CD_A_R

43

OUT

AUD_CD_A_GND

43

OUT

BUF_PLT_RST_N

3439

405455

IN

IDE_RST_N

34

IN

IDE_PDD<15..0>

29

B

VCC

BI

1

FB

FB1LB EMPTY

2

2LB

FB

2

R142LB

R144LB

EMPTY

29

29 29

2

5%CH33

2

5%

IN

IN IN

IDE_RST_R_N

1

402

1

33

402

IDE_PDDREQ

IDE_PDIOR_N IDE_PDIOW_N

8 7 9 6 10 5 11 4 12 3 13 2 14 1 15 0

J2LB

2X12X13SCSIRA

1 2

3 4 5 6 7 8 9

10 11 12 13 14 15 16 17 18 19

21 22 23 24 25

NC=51,52

DSUB

26 27 28 29

30 31 32 33 34 35 36 37 38

39 40 41 42 43 44 4520 46 47 48 49 50

2

IDE_PDIAG_N

D

C

B

V_5_S_ODD_PWR

1

2

C59LB

.1UF 10% 10V X5R 402

1

2

C60LB

.1UF 10%

10V X5R 402

1

2

C61LB

22UF 20%

16V

X5R

1210

1

C62LB

22UF 20% 16V

2

X5R 1210

A

[PAGE_TITLE=ICH8M IDE - ODD CONNECTOR]

BPAGE DRAWING

tawas_b.sch_1.36

Wed Feb 07 17:18:38 2007

8

7

6

5

4 2

3

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CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

36

2.0

1

CR-37 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE37

8

V_3P3_STBY\G

IN

1

EXPCRD

C479

.1

UF

71

D

64 62 40 39 32 18 16 8

IN

EXPCRD

6972

18

26

IN

31

55

75

1234

IN

5259

2

V_1P5_CORE

1

2

SLP_S3_N

PLTRST_N

C478

.1

UF 10% 10V

X5R 402

10%

10V X5R 402

R806

1

0

402

EXPCRD

EMPTY

VCC3

EXPCRD

1

C480

.1 10% 10V

2

X5R 402

2

5%

UF

EXPC_SHDN_N

7

1

EXPCRD

2

EXPCRD

U26

TPS2231RGP

2

3.3VIN

17

AUXIN

12

1.5VIN

1

STBY*

6

SYSRST*

20

SHDN*

18

RCLKEN

7

GND

21

EP

C

REV=1

EXPCRD

R495BU

1A

0

CH

603

EXPCRD

B

30

USB_7_DN

BI

1

90OHM

ACM2012

L17

4

EMPTY

EXPC_USB_DN

L17

EXPCRD

R494BU

1A

0

CH

603

EXPCRD

2

3

BI

2226 3337 65676869

IN

727577 5052545556 9

IN

SMB_CLK_A

BI

USB_7_DP

V_3P3_STBY\G

402

SMB_DATA_A

EXPCRD

R495

1

1K

EMPTY

2

5%

402

EXPCRD

R494

1

1K

R809

EXPCRD

10K

402

2

5%

EMPTY

1

5% CH

2

24

30

31

32

4044

A

31

3339

40

31

3339

40

EXPC_USB_DP

90OHM

ACM2012EMPTY

R810

1

10K

EXPCRD

5% CH

2

402

SMB_CLK_EXPC

SMB_DATA_EXPC

CK_PE_100M_EXPCARD_DN

IN

CK_PE_100M_EXPCARD_DP

IN

[PAGE_TITLE=EXPRESS CARD CONN]

8

7

481

C

10UF 20% 16V Y5V 1210

3.3VOUT

AUXOUT

1.5VOUT

PERST* CPUSB*

CPPE*

1OF1

6

V_3P3_S_EXPC

EXPCRD

1

C482

.1

UF 10% 10V

2

X5R 402

3

15

11

8 9 10 19

OC*

4

NC

5

NC

13

NC

14

NC

16

NC

IC

6

CARD_PERST_NEXPC_STBY_N

CARD_PERST_N

37

OUT

V_3P3_A_EXPC

1

C483

EXPCRD

10UF 20% 16V

2

Y5V 1210

1

C484

EXPCRD

.1UF 10% 10V

2

X5R 402

CARD_CPPE_N

CARD_CPUSB_N

EXPC_OC_N

EXPCRD

EXPRESS CARD HOST

2

USB_D-

3

USB_D+

7

SMB_CLK

8

SMB_DATA

13

PERST*

18

REFCLK-

19

REFCLK+

1

GND1

20

GND2

23

GND3

26

GND4

27

GND_27

28

GND_28

REV 1

5

OUT

EXPCRD

J18

37

V_1P5_S_EXPC

1

C485

10UF

1

20%

16V

2

Y5V

1210

2

MBT3904DUAL

R417BU

2

1

10K

5% CH

402

CPUSB*

WAKE*

CLKREQ*

CPPE*

PETP0 PETN0 PERP0 PERN0

1_5V

3_3VAUX

3_3V 3_3V2 RSVD1 RSVD2

1_5V

IO

U51BU

3

VCC3

EXPCRD

4

CPPE_CPUSB_EXPC_TIED

1

2

3

EXPCRD

R412BU

10K

5% CH

402

EXPCRD

R805

1

10K 5%

CH

2

402

CPPE_CPUSB_EXPC_AND

6

25

XSTR

1

EXPCRD

45

37

OUT

EXPCRD

C486

.1

UF 10% 10V

VCC3

X5R 402

R411BU

1

10K

EXPCRD

5% CH

2

402

MBT3904DUAL

CARD_CPPE_CPUSB_AND

EXPCRD

U50BU

3

6

52

XSTR

4

1

CPPE_CPUSB_TIED

EXPCRD

R415BU

2

1

5%10K CH

402

EXPCRD

R416BU

2

1

10KCH5% 402

VCC3

R808

10K

5%

33 39

CH

402

40 54

CUSTOM TEXT BPAGE

CARD_CPUSB_N

4

11

16

17

25

24

22

21

10

12

14

15

5

6

9

4 2

PCIE_WAKE_N

CARD_CPPE_N

PCIE_TX2_DP PCIE_TX2_DN PCIE_RX2_DP PCIE_RX2_DN

V_1P5_S_EXPC V_3P3_A_EXPC

V_3P3_S_EXPC

BPAGE DRAWING

Wed Feb 07 17:18:40 2007

tawas_b.sch_1.37

31

OUT

30

IN

30

IN

30

OUT

30

OUT

37

IN

37

IN

37

IN

3

2

VCC3

EXPCRD

1

C806

.1UF 10% 10V

2

X5R 402

1

EXPCRD

2

CK_OE_EXPCARD_N

INTEL

CONFIDENTIAL

MODULE REV DETAILS

MODULE NAME

CC3

V

C805

R413BU

1

.1UF 10% 10V X5R 402

EXPCRD

1K

5%

2

CH 402

R807BU

1

402

3

U52BU

1

MMBT3904 XSTR

2

EXPCRD

OUT

EXPRESS CARD SHIELD

DOCUMENT_NUMBER

EXPCRD

EXPC_SHDN_N

2

5%CH0

24

EXPCRD

J18X

1

NC

2

NC

IO

D89092

REV

1

DATE

D

C

B

A

PAGE

REV

37

2.0

1

CR-38 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE38

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

1

REV

DATE

D

DESIGN NOTE:

PINOUT MIRRORED ON VV BOARD (1=22, 2=21)

1

SATA_TXP0

29

IN

SATA_TXN0

29

IN

BI

V_3P3_S_HDD_PWR

38

IN

SATA_RXN0 SATA_RXP0

BOM NOTE:

R413 SHOULD BE

4.3 OHM IPN A93549-058

R413

PC_V3P3

2

1

5.10

5% CH

402

29 29

C

2 3 4 5 6 7 8

9 10 11

2X11HDR_2MT

IO IO IO IO IO IO IO IO IO IO IO

REQ 4863

1OF1

REV=1

J7

24

IO

23

IO

22

IO

21

IO

20

IO

19

IO

18

IO

17

IO

16

IO

15

IO

14

IO

13

IO

12

IO

PC_V5

V_5_S_HDD_PWR

R412

1

2

V_5_S_HDD_PWR

5%

1

CH

603

38

IN

38

IN

CONN

D

C

VCC

100UF

10V

FB12

1

2

FB

FB13

1

2

EMPTY

PTY

B

VCC3

I61

C351

10U 10% 16V

X5R

1206

F

V_3P3_S_HDD_PWR

B

1

C349

.1UF 10% 10V

2

X5R 402

1

C350

10UF 10% 16V

2

X5R

1206

1

2

OUT

38

OUT

V_5_S_HDD_PWR

1

2

C355

UF

.1 10% 10V X5R 402

1

C354

UF

.1 10% 10V

2

X5R

2

402

C353

22UF 20%

16V

X5R

1210

1

C352

20%

EM

2

7343

38

A

[PAGE_TITLE=HDD CONNECTOR]

BPAGE DRAWING

tawas_b.sch_1.38

Wed Feb 07 17:18:41 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

38

2.0

1

CR-39 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE39

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

1

REV

DATE

D

VCC3

1

C446

22U 20%

2

X5R

J14

MINI_PCIE

+1.5V +1.5V +1.5V +3.3V +3.3V

GND GND GND GND GND GND GND GND GND GND GND GND

CONN

48 6 28 2 52 24

38 36

32

30 22 20

16 14 12 10 8

35 29 27 21 15 9 50 40

34 26 18 4

BUF_PLT_RST_N RF_KILL_N

BI

IN

IN OUT OUT

IN

IN OUT

OUT

IN

OUT

BT_CHCLK

PCIE_TX1_DP PCIE_TX1_DN PCIE_RX1_DP PCIE_RX1_DN

CK_PE_100M_MINICARD1_DP CK_PE_100M_MINICARD1_DN

CK_OE_MINICARD1_N PCIE_WAKE_N

LED_WLAN_N

TP_PCIE_PIN51 CL_RST1_N CL_DATA1 CL_CLK1

TP_PCIE_PIN41 TP_PCIE_PIN39

TP_PCIE_PIN19 TP_PCIE_PIN17

BT_DATA

R475

402

2

1

0

5% CH

402

TP_PCIE_PIN55 TP_PCIE_PIN56

R476

2

1

5%

0

CH

30 30

C

30 30 24 24 24 31

33

37

4054

4055

31

33

31 31

B

52

33

PETP0

31

PETN0

25

PERP0

23

PERN0

13

REFCLK+

11

REFCLK-

7

CLKREQ*

1

WAKE*

46

LED_WPAN*

44

LED_WLAN*

42

LED_WWAN*

51

RESERVED

49

RESERVED

47

RESERVED

45

RESERVED

43

RESERVED

41

RESERVED

39

RESERVED

37

RESERVED

19

RESERVED/UIM_C4

17

RESERVED/UIM_C8

5

RESERVED

3

RESERVED

53

MECH_53

54

MECH_54

55

MECH_55

56

MECH_56

+3.3VAUX

USB_D+ USB_D-

SMB_DATA

SMB_CLK

PERST*

W

_DISABLE*

UIM_VPP

UIM_RESET

UIM_CLK

UIM_DATA

UIM_PWR

REV=1

16V

1210

2

1

F

2

1

C452

22UF 20%

16V

X5R

1210

1

2

R477

402

1

5%

0

C447

UF

.1 10% 10V X5R 402

2

CH

C453

.1UF 10% 10V X5R 402

SMB_DATA_A

1

C448

UF

.1 10% 10V

2

X5R 402

V_1P5_CORE

1

2

40

37 31

33

2

CH

R478

5%

C460

.1UF 10% 10V X5R 402

SMB_CLK_A

1

2

BI

34 36 40 54 55

V_3P3_M

1

2

1

402

31

C458

22UF 20%

16V

X5R

1210

0

1

C454

.1UF 10% 10V

2

X5R 402

IN IN

C459

UF

.1 10% 10V X5R 402

81618

32 37

40 62 64

IN

192031 48 69

71

32 33 35 72 83

IN

USB_6_L_DP

USB_6_L_DN

31

33 37

IN

40

46 47

71

0

402

1

4

EMPTY

90OHM

ACM2012

1

402

5% CH

R481

2

L13

1

USB_6_DP

90OHM

ACM2012

L13

2

3

0

R

EMPTY

482

USB_6_DN

2

CH 5%

30

BI

30

BI

C

B

D51601-001

J5BU

PCIE_MINI_CLIP

NC

REV=1.0

HDR

REV

2.0

A

MINIPCIE FOR WLAN

8

7

6

5

4 2

[PAGE_TITLE=X1 MINI-PCIE 1]

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DOCUMENT_NUMBER

D89092

PAGE

39

1

CR-40 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE40

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

1

REV

DATE

D

J1

5

MINI_PCIE

30 30

C

24 24 24

54

31

33

3739

39

55

PCIE_TX3_DP

IN

PCIE_TX3_DN

IN

PCIE_RX3_DP

OUT

PCIE_RX3_DN

OUT

CK_PE_100M_MINICARD2_DP

IN

CK_PE_100M_MINICARD2_DN

IN

CK_OE_MINICARD2_N

IN

PCIE_WAKE_N

OUT

LED_WLAN_N

OUT

B

PETP0 PETN0 PERP0 PERN0 REFCLK+ REFCLKCLKREQ* WAKE*

LED_WPAN* LED_WLAN* LED_WWAN*

RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED/UIM_C4 RESERVED/UIM_C8 RESERVED RESERVED

MECH_53 MECH_54 MECH_55 MECH_56

REV=1

+1.5V +1.5V +1.5V +3.3V +3.3V

+3.3VAUX

USB_D+ USB_D-

SMB_DATA

SMB_CLK

PERST*

W_DISABLE*

UIM_VPP

UIM_RESET

UIM_CLK

UIM_DATA

UIM_PWR

GND GND GND GND GND GND GND GND GND GND GND GND

CONN

VCC3

1

2

BUF_PLT_RST_N

C449

22UF 20% 16V X5R 1210

1

2

C455

22UF 20%

16V

X5R

1210

D

C450

.1UF 10%

10V X5R 402

C456

.1UF 10%

10V X5R 402

1

C451

.1UF 10% 10V

2

X5R 402

V_1P5_CORE

0

402

1

34 36 39

R480

54 55

V_3P3_STBY\G

1

C461

F

22U 20%

16V

2

X5R

1210

5% CH

2

1

402

R479

0

1

C462

.1UF 10% 10V

2

X5R 402

SMB_DATA_A

2

SMB_CLK_A

CH 5%

1

C457

.1UF 10% 10V

2

X5R 402

IN

81618

32 37 39

62 64

USB_5_L_DP

USB_5_L_DN

313337

71

44

90OHM

ACM2012

39

EMPTY ACM2012

5%

0

CH

402

R484

L14

1

4

USB_5_DP

EMPTY

L14

3

2

R483

402

0

90OHM

CH 5%

USB_5_DN

BI

C

30

IN

1

2

C463

.1UF 10%

10V X5R 402

BI

68 69 72 75 77 9

22 263132 33 37

IN

50 52 54 55 56 65 67

31

33 37 39

IN

1

2

1

2

B

D51601-001

J6BU

PCIE_MINI_CLIP

NC

REV=1.0

HDR

A

MINIPCIE FOR ROBSON

[PAGE_TITLE=X1 MINI-PCIE 2]

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REV

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2.0

1

CR-41 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE41

8

D

42

OUT

IN

1

CH

AUD_SPDIF_IN

AUD_

SPDIF_OUT

BOM NOTE:

EMPTY ALL COMPONENTS IF NO SPDIF OUT & SPDIF IN SUPPORT

STUFF IF NEED SPDIF OUT &SPDIF IN SUPPORT

M1AU

2

MULTI

603

2

C

54

B

BOM NOTE:

DEFAULT: STUFF 0 OHM (A93552-004, 0603)

OPTIONAL: FERRITE BEAD (693286-014, 0603)

VCC3

A

1

IN

C4AU

10UF 20%

6.3V X5R 805

10%

C56AU

1

EMPTY

C2AU

10PF

EM

.

25V

402

50V PTY 402

01UF

5%

2

1

2

R57AU

1

0

402

AUD_SPDIF_OUT_R

C3A

100PF

EMPTY

2

C5AU

.1UF 10% 16V

1

X7R 603

PORT

2

5% CH

AUD_PORT_E_R_REP

2

5% CH

1

22K

5%

2

CH

402

42

2

MODULE REV DETAILS

MODULE NAME

ICH8M AUDIO

MIC I N PORT B

A

SPDIF IN & SPDIF-OUT

2W STEREO SPEAKER- PORT D

2W SUBWOOFER- MONO-OUT

44 83

BI

83

44

BI

1

R64AU

22K

5% CH

2

402

AUD

41

42 43 44 45

IN

7

UD_CODEC_VREF

A

42

IN

AUD_LINK_BCLK

42

OUT

AUD_LINK_SDI0_R

42

OUT

AUD_LINK_SDO

AUD_LINK_SYNC

42

IN

AUD_LINK_RST_N

4244

IN

42

IN

43

IN

2

5%

EM

PTY

1

U

5%

50V

2

402

IN

AUD_SPDIF_IN_CDC

R1AU

1

2

5%

10

EMPTY

402

42

41

42434445

IN

41

42434445

IN

V_AUD_DIGITAL

C1AU

2

5%

10PF

50V

EMPTY

402

AUD_PC_BEEP

AUD_CD_IN_L

AUD_CD_GND

AUD_CD_IN_R

AUD_SPDIF_OUT_CDC

AUD_SENSE_A

OUT

AUD_SENSE_B

OUT

V_AUD_ANALOG

TP_AUD_GPIO3

6

BOM NOTE:

1

27

VREF

6

BITCLK

8

SDATAIN

5

SDATAOUT

10

SYNC

11

RESET*

12

PCBEEP

18

CDL

19

CDGND

20

CDR

47

SPDIFI/EAPD

48

SPDIFO

13

SENSE_A

34

SENSE_B

25

AVDD1

38

AVDD2

3

GPIO3

1

DVDD-CORE

9

DVDD-IO

USE ALC262-VC2: D47950-005

U1AU

ALC262

1

DMIC-CLK

MONO_OUT

VREFOUTBL

VREFOUTCL

VREFOUTBR

VREFOUTEL

VREFOUTFL

GPIO2/DMIC-DATA

JACKAL

JACKAR

JACKBL

JACKBR

JACKCL

JACKCR

JACKDL

JACKDR

JACKEL

JACKER

JACKFL

JACKFR

GPIO0

GPIO1

NC_45

DCVOL

JDREF

AVSS1

AVSS2

DVSS1

DVSS2

AUD_PORT_A_L

39

41

AUD_PORT_A_R

AUD_PORT_B_L

21

22

AUD_PORT_B_R

TP_AUD_PORT_C_L

23

TP_AUD_PORT_C_R

24

AUD_PORT_D_L

35

AUD_PORT_D_R

36

AUD_PORT_E_L

14

AUD_PORT_E_R

15

AUD_PORT_F_L

16

17

AUD_PORT_F_R

AUD_GPIO0

43

TP_AUD_GPIO1

44

45

AUD_DMIC_CLK_CDC

46

AUD_MONO_OUT

37

AUD_MIC1VREFL

28

TP_AUD_LINE1VREF

29

AUD_MIC1VREFR

32

TP_AUD_LINE2VREF

31

30

AUD_MIC2VREF

33

AUD_FILTER_33

AUD_JDREF

40

26

42

AUD_DMIC_DATA_CDC

2

4

7

IC

45

44

BI

44

BI

44

BI

44

BI

43

BI

43

BI

44

BI

44

BI

OUT

402

43

OUT

44

OUT

44

OUT

44

OUT

R3AU

1

2

20K

1% CH

402

AU

D

R81AU

2

1

5%

0

EMPTY

402

R82AU

2

1

5%

0

EMPTY

402

3

C69AU

100UF

2

1

AUD_PORT_E_L_C A UD_PORT_E_L_RE P

20%

6.3V TANT 6032

C70AU

100UF

2

1

AUD_PORT_E_R_C

6.

20%

3V TANT 6032

44

R79AU

AUD_DMIC_CLK

2

1

0

5%

EMPTY

R80AU

AUD_DMIC_CLK_HDR

2

1

5%

0

EMPTY

1

402

AUD

AUD_DMIC_DATA

AUD_DMIC_DATA_HDR

R2AU

IN

OUT

5%10K CH

26

42

HEADPHONE

ARRAY MIC

R61AU

1

0

402

R62AU

1

0

402

R63AU

26

OUT

V_AUD_ANALOG

2

1

REV DATE

1.03.00 11-23-06

D

C

B

A

CAD NOTE:

PLACE NEXT TO PIN 9 AND 1

CAD NOTE:

PLACE NEXT

TO PIN 9 AND 1

[PAGE_TITLE=AUDIO CODEC]

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2.0

1

CR-42 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE42

8

AZAL

IA BUS TERMI NATION

29

IN

49

29

D

IN

49

29

IN

49

29

IN

49

29

IN

AUD_HDA_RST_N

AUD_HDA_BIT_CLK

AUD_HDA_SYNC

AUD_HDA_SDOUT

C

41

44

IN

44

IN

OUT

41

7

R4AU

1

2

33

5% CH

402

R5AU

2

1

5%

33

CH

402

R6AU

2

1

33

5% CH

402

R7

AU

2

1

5%

33

CH

402

R8

AU

1

2

33

5% CH

402

AUD_AMIC_R_HDR

AUD_AMIC_L_HDR

AUD_DMIC_DATA_HDR

AUD_DMIC_CLK_HDR

IN

AUD_LINK_RST_N

AUD_LINK_BCLK

AUD_LINK_SYNC

AUD_LINK_SDO

AUD_LINK_SDI0_RAUD_HDA_SDIN0

C6AU

6

41

44

OUT

41

OUT

CAD NOTE:

OUT

PLACE RESISTOR NEAR ICH

41

OUT

PLACE RESISTOR NEAR CODEC

CAD NOTE:

41

VCC3

1

.1UF

10% 10V

2

X5R 402

AUD

J1

AU

1X8HDR2NC

1

2

3 4 5 6 7 8

HDR

NC=9,10

B

DIGITAL MIC & 2ND MIC HEADER

45

83

44

54

R83AU

HDA_SPKR

31

IN

1

10K 402

3

JACK DETECT NETWORK

D_HP_JACK_SENSE_REP

AU

IN

AUD_HP_JACK_SENSE

IN

AUD_MIC_JACK_SENSE

IN

MBT3904DUAL

HDA_SPKR_R

2

5% CH

CAD NOTE:

PLACE NEAR TO PIN 13 OF CODEC

VCC3

R84AU

1

10K 5%

CH

2

402

HDA_SPKR_XTR

Q7AU

52

R65AU

1

39.2K 402

R10AU

1

39.2K 402

R11AU

1

20K 402

86AU

R

1

2

5%

0

CH

402

3

6

XSTR

4

1

2

AUD_SENSE_B

1%

CH

2

1%

CH

2

1%

CH

1

2

HDA_SPKR_XTR_R

2

MODULE REV DETAILS

MODULE NAME

ICH8M AUDIO

41

OUT

AUD_SENSE_A

R85AU

10K

5% CH

402

1

REV

1.03.00 11-23-06

41

OUT

DATE

D

C

B

EC_SPKR

CAD NOTE: CAD NOTE:

PLACE NEXT TO PIN 38 PLACE NEXT TO PIN 25

C7AU

10UF 20%

6.3V X5R 805

1

C8AU

.1UF 10% 10V

2

X5R 402

2

1

A

2

1

C9AU

10UF

20%

6.3V

2

X5R 805

AUD

C10AU

.1UF 10%

10V X5R 402

V_AUD_ANALOG

C11AU

.1UF

10% 10V X5R 402

AUD

41

43 44 45

OUT

C12AU

10UF

6.3V

1

20%

2

X5R 805

VREF SUPPLY

CAD NOTE:

PLACE NEAR PIN 27

1

2

AUD_CODEC_VREF

OUT

41

1

2

R87AU

10K 5%

EMPTY 402

AUD_SPKR

402

R12AU

2

1

AUD_PC_BEEP_PN1

5%

10K

R13AU

CH

1

100

5%

2

CH 402

55

IN

C14AU

1

2

AUD_PC_BEEP

20%

0.1UF

C13AU

.01UF 10% 25V EMPTY 402

16V Y5V 402

2

1

OUT

41

A

PC BEEP

SUPPLY DECOUPLING

[PAGE_TITLE=AUDIO DECOUPLING & JACK SENSE & DMIC]

8

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REV

42

2.0

1

D

C

41

IN

41

IN

45

V_AUD_ANALOG

43 41

IN

42 44

B

BOM NOTE:

DEFAULT:A93552-004 (0OHM) OPTION:602433-075(10UF)

AUD_MONO_OUT

41

IN

A

CR-43 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE43

8

DESIGN NOTE:

GAI

N=20LOG{300K/(37.5K+R) }

R51AU

1

113K

402

R52AU

1

113K

402

1

AUD_PORT_D_L_C

1

AUD_PORT_D_R_C

20%

AUD

AUD_PORT_D_L

A

UD_PORT_D_R

C18AU

2

UF

.1 50V X7R 805

C19AU

2

AUD_PORT_D_R_8_R

UF

.1

20%

50V X7R 805

2

20% .1UF

2

20%

1

AUD_PORT_D_L_5_R

1

C20AU

50V X7R 805

C21AU

UF

.1 50V X7R 805

AUD_MONO_OUT_R

R72AU

1

100K

402

5% EMPTY

1

EMPTY

M16AU

MULTI

2

603

AUD_MONO_OUT_C

R73AU

100K

5% EMPTY

402

2

1

2

AUD_LFE_OUT

AUD_AMP_SD

IN

AUD_LFE_OUT_C

1

C28AU

1

2

AUD_LFE_AMP_IN_N

20%

.1UF

50V

EMPTY

805

AUD

DESIGN NOTE:

GAIN=20LOG[2/(1+R/150K)]

20%

C27AU

2

EMPTY

4344

.1UF

50V

805

7

VCC

C16AU

AUD_PORT_D_L_5

2

1%

CH

AUD_PORT_D_R_8

2

1% CH

R48AU

AUD_PORT_D_L_C_R

2

1

1%

113K

CH

402

R49AU

1

2

1%

113K

CH

402

C

22AU

2

10%

.22UF

10V

EMPTY

402

R50AU

1

2.67K EMPTY

402

R16AU

1

2

2.67K

1%

EMPTY

402

AUD_MONO_OUT_PIN3

AUD

402

R46AU

2

1

AUD_LFE_OUT_C_R

5%

0

EMPTY

402

R47AU

1

0

402

1

C17AU

10UF

20%

3V

6.

2

X5R 805

A

UD_PORT_D_R_C_R

1

2

1

1%

2

3

4

R56AU

1

2

5%

0

EMPTY

AUD_LFE_AMP_IN_N_R

2

5%

EMPTY

6

CAD NOTE:

1

ACE NEAR TO PIN 14 AND 15

PL

.1U

F 10% 10V

2

X5R 402

14 15

10

EU3AU

SSM2304

REV=1 VDD VDD

NC NC

GAIN

4

INL+ INL-

INR+ INR-

SD*

OUTL+ OUTL-

OUTR+ OUTR-

GND GND GND

5

9 8

3

AUD_SPKR_AMP_L_FB_DP

AUD_SPKR_AMP_L_FB_DN

6 7

1 2

AUD_SPKR_AMP_R_FB_ DP

12

AUD_SPKR_AMP_R_FB_ DN

11

13 16 17

IC

R55AU

AUD_AMP_SD_AMP

AUD_AMP_SD

1

2

0

5% CH

402

IN

INTERNAL SPEAKER POWER AMP

DESIGN NOTE:

V_AUD_ANALOG

7

C24AU

.1UF

6

EMPTY

5 8

SD*

GAIN

INP

INN

GND_9

REV=1

LOW PASS: FC=270HZ

IN

1

10% 10V

2

402

AUD

EU4AU

S

SM2301

1OF1

41

OUTP

VDD

GND

OUTN

EMPTY

42 43 44 45

5

7

8

U5AU

AD8541

NC

+

VCC-

AUD_AMP_SD_LFE

AUD

VCC+

OUT

NC

EMPTY

1

26

3

4

9

SUBWOOFER POWER AMP

45

GN NOTE:

DESI

600OHM 1A

M9AU

MULTI

M10AU

MULTI

11AU

M

MULTI

M12AU

MULTI

2

AUD_SPKR_AMP_L_DP

FB

AUD_SPKR_AMP_L_DN

2

FB

1

C59AU

1000PF

10% 50V

2

R

X7 402

AUD_SPKR_AMP_R_D P

2

AUD_SPKR_AMP_R_D N

2

1

C61AU

1000PF

10% 50V

2

X7

R

402

C60AU

1000PF

C62AU

1000PF

OUT

1

10% 50V

2

X7R 402

OUT

1

10% 50V

2

X7

R

402

43 44

BOM

1

NOTE:

EMPTY WHOLE CIRCUITRY IF NO SUBWOOFER SUPPORT

VCC

C26AU

EMPTY

1

.1UF

10% 10V

2

402

DESI

GN NOTE:

600OHM 1A

M13AU

AUD_LFE_AMP_DP

MULTI

M14AU

MULTI

2

EMPTY

2

AUD_LFE_AMP_DN

EMPTY

C64AU

1000PF

10% 50V

EMPTY

402

1

2

C63AU

1000PF

EMPTY

10% 50V

402

1

C25AU

10UF

20%

6.3V

2

EMPTY

805

AUD_LFE_AMP_FB_ DP

AUD

AUD_LFE_AMP_FB_ DN

OUT

C29AU

6.3V X5R 402

C30AU

3V

6. X5R 402

C

2

6.3V

1UF

31AU

X5R 402

1UF

2

1

AUD_CD_GND_C

1

AUD_CD_IN_L_C

1

AUD_CD_IN_R_C

1

R19AU

4.7K 5%

2

CH 402

AUD

MODULE REV DETAILS

MODULE NAME

ICH8M AUDIO

1X6HDR2MTG

1 2 3 4 5 6

R38AU

AUD_CD_A_GND

1

2.2K25% CH

402

R39AU

AUD_CD_A_L

2

1

5%

4.7K CH

402

R40AU

AUD_CD_A_R

2

1

5%

4.7K CH

402

1

R20AU

4.7K

5%

2

CH 402

3

OUT

43

43 43

43

OUT

41

OUT

41

OUT

43

AUD_SPKR_AMP_R_D P

IN

AUD_SPKR_AMP_R_D N

IN

AUD_SPKR_AMP_L_DP

AUD_SPKR_AMP_L_DN

AUD_LFE_AMP_DP

43

IN

AUD_LFE_AMP_DN

43

IN

SPEAKER CONNECTOR

AUD_CD_GND

AUD_CD_IN_L

AUD_CD_IN_R

2

10% 1UF

2

10%

R18AU

2.2K 5%

CH

402

1

2

CD-IN. CONNECT TO ODD HEADER

1

REV

1.03.00 11-23-06

J2AU

IO1 IO2 IO3 IO4 IO5 IO6

HDR

NC=7,8

DATE

IN

D

C

36

B

36

A

BPAGE DRAWING

[PAGE_T

8

7

ITLE=AUDIO SPEAKER & SUBWOOFER AMP]

6

5

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1

CR-44 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE44

8

U

R22A

1

V_AUD_ANALOG

41

424344

IN

45

AUD_MIC1VREFL

41

D

C

IN

V_AUD_ANALOG

IN

AUD_MIC1VREFR

IN

AUD_PORT_B_L

AUD_PORT_B_R

41

424344

41 45

41

402

100

402

0

EMPTY

R23AU

1

R25AU

1

0

402

R26AU

1

100 402

2

5%

2

5% CH

5%

EMPTY

5% CH

4.7UF 20%

4.7UF

2

MIC1 AND MIC1 BIAS

AUD_MIC1VREFL_R

R21AU

C34AU

1

2

6.

3V X5R 805

C35AU

2

1

20%

6.3V X5R

R24AU

805

AUD_MIC1VREFR_R

7

4.7K 5% CH

402

4.7K

402

1

2

AUD_PORT_MIC1_L

AUD_PORT_MIC1_R

1

5% CH

2

1

2

AUD

C32AU

X5R 805

1

2

AUD

10U 10% 10V

F

C33AU

10UF 10% 10V X5R 805

OUT

6

5556656768 2226313233

37

40505254

69727577

54

AUD_AMP_SD

4344

IN

54

AUD_POP_MUTE

44

IN

9

IN

V_3P3_STBY\G

AUD_AMP_SD_R

R66AU

1

470 402

Q4AU

IMH21

5

R67AU

1

220K

402

2

5% CH

AUD_HP_JACKL

AUD_HP_JACKR

1

4

3

6

5% CH

1

2

XSTR

2

Q6AU

MBT3906

M XSTR

3

AUD_POP_MUTE

1

C105AU

1000PF 10% 50V

2

X7R 402

AUD

OUT

2

44 54

45

44

OUT

AUD_LINK_RST_N

41

42

IN

1

10K

402

3

R93AU

MBT3904DUAL

2

5%

AUD_LINK_RST_PIN5

CH

1

R91AU

10K

5% EMPTY

402

2

Q10AU

10K

402

AUD_LINK_RST_PIN6

3

52

4

AUD_LINK_RST_PIN3

VCC3

5% CH

1

2

6

AUD_GPIO0_PIN2

XSTR

1

MODULE REV DETAILS

MODULE NAME

402

R89AU

1

0

ICH8M AUDIO

R90AU

2

AUD_LINK_RST_PIN1

5% CH

R92AUR88AU

1

2

10K

5% CH

402

10K

5% CH

402

AUD_GPIO0

1.03.00

1

2

AUD_AMP_SD

1

REV

3

Q9AU

MMBT3904 XSTR

2

IN

1

DATE

11-23-06

D

43

OUT

44

41

C

IN

AUD_PORT_A_L

AUD_PORT_A_R

41

B

41

HEADPHONE

R60AU

2

AUD_MIC2VREF

41

IN

A

41

IN

41

IN

INTERNAL MIC BIAS

1

402

AUD

AUD_PORT_F_L

AUD_PORT_F_R

8

5%CH0

2

1

AUD_MIC2VREF_R

C67AU

10UF 10%

10V X5R 805

C65AU

2

20%

4.7UF

6.3V X5R 805

C66AU

2

4.7UF

20%

6.3V X5R 805

C36AU

100UF

1

TANT 6032

C37AU

100UF

1

20%

TANT 6032

CR3AU

3

AUD_PORT_F_L_BIAS

.45V SOT23A DIO

AUD_PORT_F_L_HDR_C

1

AUD_PORT_F_R_HDR_C

1

2

AUD_HP_JACKL_R

6.

3V20%

2

AUD_HP_JACKR_R

6.

3V

AUD_PORT_F_R_BIAS

2

1

[PAG

7

R41AU

2

1

AUD_HP_JACKL

0

5% CH

402

R42AU

2

1

AUD_HP_JACKR

5%

0

CH

402

R43AU

22K

5% CH

402

1

2

R44AU

1

22K

5% CH

2

402

OUT

44

54

44 54

IN

AUD_POP_MUTE

44

AUD_PORT_E_L_REP

Q5AU

IMH21

5

AUD

AUD_PORT_E_R_REP

1

4

2

XSTR

3

6

OUT

41

83

41

83

AUD

2.2K

2.2K 402

R58AU

1

402

R59AU

1

2

5% CH

2

5% CH

402

R75AU

1

402

R76AU

1

0

R77AU

1

0

R78AU

1

0

2

5%CH0

AUD_AMIC_L

2

5%

EMPTY

AUD_AMIC_R

2

5%

EMPTY

AUD_AMIC_R_HDR

2

5% CH

AUD_AMIC_L_HDR

OUT

42

26

42

AUD

ANTI-POP CIRCUITRY

E_TITLE=AUDIO ANTI-POP,ANTI-THEFT CIRCUITRY]

6

5

4 2

54

HP_JACK_DETECT

IN

BPAGE DRAWING

Wed Feb 07 17:18:48 2007

tawas_b.sch_1.44

0

402

R74AU

1

AUD_HP_JACK_SENSE

3

AUD_HP_JACK_AND

2

5% CH

Q1AU FE

T

1

2

42

IN

B

AUD

A

PAGE

INTEL

CONFIDENTIAL

3

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

REV

44

2.0

1

CR-45 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE45

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

ICH8M AUDIO

REV

1.03.00

1

DATE

11-23-06

D

CAD NOTE:

PLACE ETCH RE SISTORS UNDER CODEC

R29AU

2

1

0OHM

SM

CR5AU

C40AU

10UF 10% 16V

X5R

1206

1N4148

3

1

SOT23 EMPTY

CAD NOTE:

USE LARGE SHAPE UNDER VREG FOR THE RMALS

ADD VIAS FOR THERMAL RELIEF TO OTHER LAYERS

U8AU

C83150-001

LD1117DT

2

IN

GND

1

2

OUT

SM

AUD_VREG_OPT_GND

C41AU

0.

1UF

20%

16V Y5V 402

3

R32A

1

150 1%

2

CH 402

1

R33AU

453

1%

2

CH 402

1

U

2

AUD

V_AUD_FILTERED

C42AU

0.1UF 20% 16V Y5V 402

1

2

AUD

C43AU

1U

20%

6.

3V X5R 603

1

F

1

C106AU

000UF

22. 20%

6.3V

2

X5R 805

V_5P0_STBY\G

6265666869

C

V_AUDIO

69

IN

1

CH

2

M15AU

MULTI

CR4AU MRA4003T3

SM EMPTY

926323361

IN

707576777883

2

603

1

V_AUDIO_R

1

B

CAD NOTE:

PLACE GROUND:: 12V DECOUPLING SITE AS

CLOSE AS POSSIBLE TO AUDIO VREG

2

AUD

1

C45AU

470PF 10% 50V

2

X7R 402

A

CAD NOTE:

PLACE GROUND::AUD-GROUND DECOUPLING S ITE A S CLOSE AS POSSIBLE TO AUDIO TRIPLE-STACK CONNECTOR

AUD

0OHM

SM

R31AU

AUD

1

2

1

0OHM

SM

C107AU

000UF

22. 20%

6.3V X5R 805

2

R30AU

AUD

41

42 43 44

1

2

C109AU

000UF

22. 20%

6.3V X5R 805

.01UF

C47AU

1

C50AU

1

OUT

2

10% 25V X7R 402

2

10% 25V X7R 402

C48AU

1

.01UF

25V X7R

.01UF

C51AU

1

402

25V X7R 402

AUDAUD

AUD AUD

2

V_AUD_ANALOG

CAD NOTE:

ADD SEVERAL VIAS AFTER ETCH RESISTOR TO V_AUD_ANALOG

1

C108AU

000UF

22. 20%

6.3V

2

X5R 805

C46AU

2

1

10%

.01UF

25V X7R 402

C49AU

2

1

.01UF

10% 25V X7R 402

AUD

CAD NOTE:

DISTRIBUTE THREE NEAR THE REAR AUDIO JACK. ONE NEA R THE FRONT PANEL AUDIO CONNE CTOR. REMAINING ALONG ANTI-ETCH BETWEEN ANALOG / DIGITAL GROUND

10%

2

AUD

D

C

B

A

[PAGE_TITLE=AUDIO VREG]

8

7

6

5

4 2

BPAGE DRAWING

tawas_b.sch_1.45

Wed Feb 07 17:18:49 2007

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

45

2.0

1

CR-46 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE46

8

GLAN_RX_C_DP

46

OUT

GLAN_RX_C_DN

46

OUT

GLAN_TX_DP

30

IN

GLAN_TX_DN

30

D

R8LN

1

2

1%

1.4K

CH

402

R11LN

1

2

1%

1.4K

CH

402

CAD NOTE:

PLACE CLOSE TO LAN

IN

LAN_KMRN_RCOMP_P LAN_KMRN_RCOMP_N

LAN_RBIAS_P

LA

48

OUT

LAN_CTRL_1P8

48

OUT

TP_LAN_ATEST_P

TP_LAN_ATEST_N

R10LN

1

0

1A

2

EMPTY 603

C

GLCI TERMINATION

GLAN_RX_DP

30

OUT

GLAN_RX_DN

30

OUT

B

CAD NOTE:

PLACE CLOSE TO LAN

Y DETECT CIRCUIT

ENERG

46

A

LAN_MDI0_DP_Q

BI

LAN_MDI1_DP_Q

BI

LAN_MDI0_DP

46

BI

47

LAN_MDI1_DP

46

BI

47

BOM NOTE:

REMOVE ALL C OMPONENTS TO DIABLE ENERGY DETECT CICUITRY

0.1UF

0.

.01UF

1UF

1

16V

1

16V

C37LN

1

25V

C38LN

1

25V

C8LN

2

20% Y5V

402

C

9LN

2

20% Y5V

402

2

LAN_ED_MDI0_DP_R

10% X7R

402

2

LAN_ED_MDI1_DP_R

10% X7R

402

LAN_MDI0_DP_Q

LAN_MDI1_DP_Q

GLAN_RX_C_DP

GLAN_RX_C_DN

8

TP_LAN_RSVDJ6

TP_LAN_RSVDJ7

N_CTRL_1P0

TP_THERM_D_P

TP_THERM_D_N

TP_LAN_JTAG_TCK

TP_LAN_JTAG_TDI

TP_LAN_JTAG_TDO

TP_LAN_JTAG_TMS

10K

BI

7

R22LN

1

402

R26LN

1

402

46

7

H2

GLAN_TXP/NC

J2

GLAN_TXN/NC

J4

GLAN_RXP/NC

H4

GLAN_RXN/NC

J6

RSVD_J6/NC

J7

RSVD_J7/NC

G7

KBIAS_P/RBIAS100

H7

KBIAS_N/RBIAS10

E7

RBIAS_P/NC

E6

RBIAS_N/NC

C3

CTRL_10/NC

B2

CTRL_18/NC

A2

THERM_D_P/NC

A3

THERM_D_N/NC

A7

IEEE_TEST_P/NC

B7

IEEE_TEST_N/NC

G1

JTAG_TCK/ISOL_TCK

H1

JTAG_TDI/ISOL_TI

G3

JTAG_TDO/TOUT

G2

JTAG_TMS/ISOL_EXEC

REV=1

46

IN

46

IN

R

1

200K

1%

EMPTY

2

603

2

5%

CH

2

5%

CH

R27LN

1

100K

5%

CH

2

603

24LN

3.92K

3

GLAN LAN CLOCK TERMINATION

46

IN

CAD NOTE:

PLACE CLOSE TO LAN

LAN CRYSTAL

46

OUT

46

IN

CAD NOTE:

PLACE CLOSE TO LAN

DIFFERENTIAL PAIR TERMINATIONS

4647

46474883

48

46474883

4748

LAN_MDI3_DN

BI

LAN_MDI3_DP

BI

LAN_MDI2_DN

BI

LAN_MDI2_DP

BI

LAN_MDI1_DN

BI

LAN_MDI1_DP

BI

LAN_MDI0_DN

BI

LAN_MDI0_DP

BI

CAD NOTE:

PLACE CLOSE TO LAN

LAN_V_1P8

IN

LAN_V_1P0

IN

LAN_V_1P8

IN

V_3P3_M_LAN_SW

IN

R12LN

1

100

402

IN

2

1%

CH

71

72 83 192031 35 39

45

OUT OUT OUT OUT

OUT OUT OUT

OUT

32 33

47 48 69

OUT

46

47

BI

46 47

BI

46 47

BI

46 47

BI

46 47

BI

46 47

BI

46 47

BI

46 47

BI

29

IN

29

IN

29

IN

29 29 29 46 29

IN

47 47 47

46

IN

46

29

6

U5LN

NINEVEH0P99B

B8

MDI_PLUS0/TDP

MDI_MINUS0/TDN

MDI_PLUS1/RDP

MDI_MINUS1/RDN

MDI_PLUS2/NC

MDI_MINUS2/NC

MDI_PLUS3/NC

MDI_MINUS3/NC

LED0/LINK_UP* LED1/ACT_LED*

LED2/SPEED_LED*

RSVD_A6/ADV10-LAN_DIS*

1

R23LN

100K 5%

2

CH 603

LAN_ED_MDI

1

C39LN 10PF 5%

LAN_ED_VREF

50V

2

COG 402

R28LN

1

2

1%

CH

603

5

4

V+

3

OUT

V-

+

LMV2011

2

BOM NOTE:

I

C

PN: D78252-001

JTXD0 JTXD1 JTXD2 JRXD0 JRXD1 JRXD2

JKCLK/JCLK

JRSTSYNC

XTAL1/ X1 XTAL2/X2

TEST_EN

RSVD

RSVD_C5/NC

1of 2

1

C36LN

.1UF 10% 10V

2

X5R 402

U6LN

1

IC

HANGE TO LV331IDBVRG4

LAN_MDI0_DP

B9

LAN_MDI0_DN LAN_MDI1_DP

D9 D8

LAN_MDI1_DN LAN_MDI2_DP

F9 F8

LAN_MDI2_DN LAN_MDI3_DP

H8 H9

LAN_MDI3_DN

D1

LAN_TXD0 LAN_TXD1

F3

LAN_TXD2

F1

LAN_RXD0

D3

LAN_RXD1

D2

LAN_RXD2

C1

GLAN_CLK_R

E2

LAN_RSTSYNC

E3

A4

LAN_LED_LNK_ACT_N

B4

LAN_LED_1000_N

A5

LAN_LED_100_N

LAN_XTAL_DP

H6

LAN_XTAL_DN

H5

TP_LAN_TEST_EN

B6

TP_LAN_RSVDB5

B5

TP_RSVD_A6

A6

TP_LAN_TEST2

C5

IC

1

R25LN

1.5K 5%

2

CH 603

LAN_ED_GPIO13

CONNECT TO GP IO13 ON ICH8 M

V_3P3_M

2

GLAN_CLK_R

LAN_XTAL_DP

LAN_XTAL_DN

R14LN

1

49.9 1%

1

R15LN

CH

2

49.9

402

1%

2

CH 402

LAN_DTAP0

1

C32LN

.1UF 10% 10V

2

X5R 402

B1 D7 D4 E4 E8 E5 G4 F7

H3

C2 D5 F5 G5

F2 B3

MODULE REV DETAILS

MODULE NAME

TAWAS_INTEL_LAN

R6LN

1

2

5%

33

CH

402

Y1LN

25.000MHZ

1

2

SM XTAL

R16LN

1

49.9 1%

CH

2

402

LAN_DTAP1

1

2

V1P0_OUT/NC VDD1P0/VCCR VCC VCC/VCC VDD1P0/VCCT VCCF1P0/VCC VCC1P0/VCCA2 VDD1P0/VCCA VCCFC1P0/VCC

VCC1P8/NC VCC1P8/NC VCC1P8/NC VCC1P8/NC

VCC3P3/VCCP VCC3P3/VCC

1

R17LN

2

49.9 1%

2

CH 402

C33LN

.1UF 10%

10V X5R 402

U5LN

NINEVEH0P99B

R18LN

49.9 1%

CH 402

LAN_DTAP2 LAN_DTAP3

1

2

REV=1

[PAGE_TITLE=LAN INTEL/NINEVEH]

6

5

4 2

BPAGE DRAWING

tawas_b.sch_1.46

Wed Feb 07 17:18:50 2007

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

1

REV

01.01.00 10-31-06

LAN_CLK

G

N

C5L

2

1

5%

27PF

50V

COG

603

R20LN

1

49.9 1%

1

R19LN

CH

2

49.9 402

1%

2

CH 402

C34LN

.1UF 10% 10V X5R 402

VSS/NC

VSS

VSS/VSSP

VSS/VSS VSSA/NC VSSA/NC

VSSA/VSSA2

VSSA/VSS

VSSA/NC VSSA/VSS VSSA/VSS VSSA/VSS VSSA/VSS VSSA/VSS VSSA/VSS VSSA/VSS VSSA/VSS VSSA/VSS

VSSA/VSSR

VSSA/NC VSSA/VSS

2of 2

PAGE

1

DATE

29

OUT

1

2

C

27P 5% 50V COG 603

4LN

D

F

C

1

R21LN

49.9 1%

2

1

C35LN

.1UF 10% 10V

2

X5R 402

B

CH 402

A1 C4 E1 F4 J9 J8 J5 J3 J1

A

G9 G8 G6 F6 E9 D6 C9 C8 C7 C6 A9 A8

IC

REV

46

2.0

CR-47 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE47

8

7283

4647

39 19

20

31

323335 4869

71

D

47

7283

4647

39

31

1920

323335

4869

71

46 46 46 46 46 46 46 46

46 46

C

46

_3P3_M

V

IN

LAN_ENE_REP_N_ R

IN

V_3P3_M

IN

LAN_MDI0_DP

BI

LAN_MDI0_DN

BI

LAN_MDI1_DP

BI

LAN_MDI1_DN

BI

LAN_MDI2_DP

BI

LAN_MDI2_DN

BI

LAN_MDI3_DP

BI

LAN_MDI3_DN

BI

LAN_LED_LNK_ACT_N

IN

LAN_LED_100_N

IN

LAN_LED_1000_N

IN

2

1

R13LN

10K

5% CH

603

B

CONNECT TO SOME GPIO

L

IN

AN_ENE_REP_N

56

402

1

0

R5LN

5% CH

LAN_ENE_REP_N_R

2

MAGNETICS CENTER TAP DECOUPLING

LAN_VCT

1

2

A

CAD NOTE:

PLACE ONE CAP NEAR EACH TDCT PIN OF MAGNETICS MODULE

C41LN

.1UF 10% 10V X5R 402

1

2

C42LN

.1UF 10% 10V X5R 402

1

C43LN

.1UF 10% 10V

2

X5R 402

I159

8

7

EU1LN

TS3L500

0LED1

1LED1

2LED1

0LED2

1LED2

2LED2

0B

1B1

2B1

3B1 4B1 5B1 6B1 7B1

0B2

1B2 2B2

3B 4B 5B2 6B2 7B2

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

48

1

47 43 42

22 23 52

46 45 41 40

2 2

29

25 26 51

6 9

21 24 28 55 53 49 44

57

IC

17

SEL

4

VCC

10

VCC

18

VCC

27

VCC

56

VCC

50

VCC

38

VCC

2

A0

3

A1

7

A2

8

A3

11

A4

12

A5

14

A6

15

A7

19

LED0

20

D1

LE

54

LED2

5

NC

REV=1

1OF1

RJ45 LED TERMINATIONS AND DECOUPLING

47

OUT

47

1

C44LN

.1UF 10% 10V

2

X5R 402

LAN_LED_1000_M_N

47

IN

LAN_LED_100_M_N

IN

LAN_LED_LINK_ACT_M_N

47

IN

CAD NOTE:

PLACE DECOUPLING CAP CLOSE TO RJ45

7

6

LAN_MDI0_REP_DP LAN_MDI0_REP_DN LAN_MDI1_REP_DP LAN_MDI1_REP_DN LAN_MDI2_REP_DP LAN_MDI2_REP_DN LAN_MDI3_REP_DP LAN_MDI3_REP_DN

LAN_LED_LINK_REP_N LAN_LED_100_REP_N LAN_LED_1000_REP_N

37 36 32 31

LAN_MDI0_SW_M_DP LAN_MDI0_SW_M_DN LAN_MDI1_SW_M_DP LAN_MDI1_SW_M_DN LAN_MDI1_M_DN LAN_MDI2_SW_M_DP

35

LAN_MDI2_SW_M_DN

34 30

LAN_MDI3_SW_M_DP LAN_MDI3_SW_M_DN

1

13 16

39

LAN_LED_LINK_ACT_M_N

33

LAN_LED_100_M_N

LAN_LED_1000_M_N

R1LN

1

330 5% 402

R2LN

1

402

R3LN

1

330 402

47

OUT

47

OUT

47

OUT

LAN_AMBER

2

1

CH

C2LN

.1UF 10% 10V

2

X5R 402

LAN_GREEN

2

5%330

1

CH

C1LN

.1UF 10% 10V

2

X5R 402

2

LAN_YELLOW

5%

1

CH

C49LN

.1UF

10% 10V

2

X5R 402

BI BI

BI

BI BI BI

BI

LAN_VCT

1

2

3

4

5

6

7

8

9

10

11

12

4748

REV=1

IN

OUT

47 83 47 83 47 83 47 83 47 83 47 83 47 83 47 83

83 83 83

TD+

TD-

TDCT

TD+

TD-

TD+

TD-

TDCT

TD+

TD-

200MA

200

FB2LN

2

FB

U7LN

H5120

1OF1

LAN_AGND

47

1

LAN_V_1P8

TX+

TX-

TXCT

TX+

TX-

TX+

TX-

TXCT

TX+

TX-

XFMR

C40LN

2

1500PF

R

X7

RJ45 ESD DIODES

BI

47

BI

CAD NOTE:

PLACE BETWEEN MAGNETICS AND RJ45

[PAG

E_TITLE=LAN SWITCH/CONNECTORS]

6

5

45

BOM NOTE:

IN

24

23

22

21

20

19

47 48

18

17

16

15

14

13

1

R29LN 75 5%

2

CH 402

1

10%

603

LAN_MDI0_M_DP

TP_ESD_1

LAN_MDI0_M_DN

LAN_MDI2_M_DN

TP_ESD_3 TP_ESD_4

LAN_MDI2_M_DP

1

R30LN 75 5%

2

CH 402

1

R31LN

R32LN

75

5%

CH

2

CH

402

CMT

U

1LN

TVS6V

1

6

52

3

1

U3LN TVS6V

4

DIO

6

52

3

4

DIO

Wed Feb 07 17:18:51 2007

4 2

3

LAN

D81513-001

J1LN

RJ45_STRADDLE

LAN_MDI0_M_DP LAN_MDI0_M_DN LAN_MDI1_M_DP

LAN_MDI2_M_DP LAN_MDI2_M_DN LAN_MDI3_M_DP LAN_MDI3_M_DN

IN

LAN_MDI1_M_DP

TP_ESD_2

LAN_MDI1_M_DN

LAN_MDI3_M_DP

LAN_MDI3_M_DN LAN_MDI2_REP_DN

BPAGE DRAWING

tawas_b.sch_1.47

1

0+

2

0-

3

1+

4

1-

5

2+

6

2-

7

3+

8

10

9

3-

SHIELD_1 SHIELD_2

LAN_AGND

REV=1 CONN

47

BIBI

83

47

BI

83

47

BI

83

47

BI

83

1OF1

PORT REPLICATOR ESD DIODES

BI

CAD NOTE:

PLACE CLOSE TO PORT REPLICATOR CONNECTOR

3

2

A1

A2

A3

B1

B2

B3

LAN_MDI0_REP_DP

TP_ESD_5

LAN_MDI0_REP_DN

LAN_MDI2_REP_DP

TP_ESD_7

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

MODULE REV DETAILS

MODULE NAME

TAWAS_INTEL_LAN

4LN

R

LAN_LED_PWR

1

0

603

2

V_3P3_M_LAN_SW

1A CH

LAN_AMBER

LAN_GREEN

TP_J1LN_B1

LAN_YELLOW

U

2LN

TVS6V

1

6

52

3

1

U4LN TVS6V

4

DIO

6

52

3

4

DIO

DOCUMENT_NUMBER

D89092

REV

01.01.00

IN

47

IN

LAN_MDI1_REP_DP

TP_ESD_6

LAN_MDI1_REP_DN

LAN_MDI3_REP_DP

TP_ESD_8

LAN_MDI3_REP_DN

1

DATE

10-31-06

D

46 4846 48 83

IN

47

C

B

47 83

BI

47 83

BI

A

47 83

BI

47 83

BI

PAGE

REV

47

2.0

1

1P8 VOLT REG

D

46

LAN_CTRL_1P8

IN

CR-48 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE48

8

1

C12LN

.01UF 10%

25V

2

X7R 402

CAD NOTE:

PLACE AT LEAST 1 CM2 MOUNTING PAD FOR COLLECTOR PLACE CXLN CLOSE TO XSTR

Q3LN

1

BCP6 XSTR

234

7

1

C14LN

0.1UF 20%

16V

2

Y5V 402

9T1

1

C18LN

C28LN

10UF

20%

6.3V

2

X5R

805

CAD NOTE:

PLACE DECOUPLING CLOSE TO NIN EVEH

V_3P3_M_LAN_SW

C16LN

4.

7UF

10%

6.3V X5R 603

PL PNP EMI TTER

1

C

4.7UF 10%

6.3V

2

X5R 603

6

CAD NOTE:

ACE CLOSE TO

1

47LN

2

C48LN

4.7UF 10%

6.3V

X5R 603

46 47 48

IN

LAN_V_1P8

1

C19LN

.1UF 10% 10V

2

X5R 402

1

C20LN

C21LN

.1UF

470PF

10%

10V

2

50V

2

X5R

X7R

402

OUT

1

C22LN

470PF 10% 50V

2

X7R 402

45

46 47 83

3

LAN_AGND

47

IN

1

C30LN

1000PF 10%

50V

2

X7

R

402

2

MODULE REV DETAILS

MODULE NAME

TAWAS_INTEL_LAN

120OHM@100MHZ

693286-013

FB1LN

1

2

C31LN

1000PF

10% 50V X7R 402

1

C3LN

10UF

20%

6.

3V

2

X5R 805

1

REV

DATE

10-31-0601.01.00

D

2

FB

1P0 VOLT REG

C

LAN_CTRL_1P0

IN

B

ENERGY DETECT CIRCUIT - PHY POWER CONTROL

31 19 20

32

33

35

39 46 47 69 71 72 83

A

31

V_3P3_M

IN

LAN_PHYPC_GPIO12

IN

CONNECT TO GPIO12 ON ICH8M

1

C13LN

.

01UF 10%

25V

2

EMPTY 402

Q4LN

1

BCP69T1 XSTR

CAD NOTE:

PLACE AT LEAST 1 CM2 MOUNTING PAD FOR COLLECTOR PLACE CXLN CLOSE TO XSTR

234

3

LAN_PHYPC_EN_N

D

1

S

G

2

R9LN

1

1.0M

5%

2

CH 603

Q2LN BSS138N

FE

T

1

C

10UF

20%

6.

2

X5R 805

CAD NOTE:

R7LN

1

100K

402

V_3P3_M_LAN_SW

1

C15LN

C17LN

0.1UF

4.7UF

20%

10%

16V

2

6.3V

2

X5R 603

CAD NOTE:

PLACE CLOSE TO PNP EMI TTER

Y5V 402

IN

46 47 48

LAN_V_1P0

1

29LN

3V

1

C23LN

10UF 20%

6.

3V

2

X5R

2

805

C45LN

4.7UF 10%

3V

6.

X5R 603

1

C46LN

C24LN

.1UF 10% 10V X5R 402

C25LN

.1

UF 10% 10V

2

X5R 402

4.7UF 10%

3V

6.

2

X5R 603

1

C26LN

470PF

10%

50V

2

X7R 402

PLACE DECOUPLING CLOSE TO NIN EVEH

R33LN

1

2

1A

0

EMPTY

805

Q1LN

PMOSFET

3

D

2

C6LN

1000PF

10% 50V X7R 603

LAN_EDC_3P3EN_N

S

1

G

C7LN

22.000UF

1

20%

6.3V

2

X5R 805

1

2

5% CH

BOM NOTE:

STUFF R34LN, REMOVE Q1LN, Q2LN, R9LN, C6LN, C7LN TO DISABLE PHY POWER CONTROL AND DISABLE ENERGY DETECT CIRCUITRY

V_3P3_M_LAN_SW

C27LN

470PF 10% 50V X7R 402

OUT

46

46 47 48

LAN 3.3V DECOUPLING

46474846

V_3P3_M_LAN_SW

IN

1

C10LN

0.1UF 20% 16V

2

Y5V 402

CAD NOTE:

PLACE DECOUPLING CLOSE TO NIN EVEH

C

1

C11LN

4.7UF 10%

6.3V

2

X5R 603

B

A

BPAGE DRAWING

[PAGE_TITLE=LAN POWER]

8

7

6

5

4 2

tawas_b.sch_1.48

Wed Feb 07 17:18:53 2007

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

48

2.0

1

CR-49 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE49CR-45: @TAWAS_LIB.TAWAS(SCH_1):PAGE45

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

1

REV

DATE

D

MDC

D85589-001

J1

BU

R

J11_STRADDLE

C

SHEILD

SHIELD

1

2

3

4

LAN_RJ11_RING

LAN_RJ11_TIP

CONN

MDC

J51SA

MDC_TARGET

NC

MD

B

CPCB OUTLINE WITH KEEPOUTS AND 2 STAND OFF TARGETS

J51X1

MDC_STANDOFF

GND

J51

MDC_STANDOFF

GND

A

HDR

X2

HDR

MDC

EMPTY

MD

MDC

C

2942

IN

2942

IN

29

OU

T

2942

IN

2942

IN

AUD_

HDA_SDOUT

AUD_HDA_SYNC

AUD_HDA_SDIN1

AUD_HDA_RST_N

AUD_HDA_BIT_CLK

MDC

402

MDC

402

VCC3

MDC

R

1046

5%

33

CH

402

MDC

R1038

33

402

33

5% CH

R1040

5%

33

CH

BROAD 100

0.1A 1K

FB50

LAN_RJ11_RING_FB

MDC

FB

BROAD 100

0.1A 1K

FB51

LAN_RJ11_TIP_FB

FB

C988BU

MDC

4.7UF 10%

6.3V

EMPTY 603

AUD_HDA_SDOUT_MDC

R1042

AUD_HDA_SYNC_MDC

5%

AUD_HDA_SDIN1_MDC

CH

MDC

R1012

AUD_HDA_RST_MDC_N

33

5% CH

402

AUD_HDA_BIT_CLK_MDC

C987

.1

MDC

10%

10V X5R 402

J4

1X

2HDR

1

2

HDR

C

MDC

UF

B

MDC

J51

2X6HDR_MDC

1

3 5 7 9

11

2 4 6 8 10 12

HDR

NC=19,20 GND=13,14,15,16,17,18

A

[PAGE_TITLE=MODEM/MDC]

8

7

MDC CONNECTOR FOR MODEM CARD

BPAGE DRAWING

tawas_b.sch_1.49

Wed Feb 07 17:18:54 2007

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

49

2.0

1

CR-50 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE50

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

TAWAS_CORE

1

REV

1.01.00 12-13-06

DATE

6

IN

33

V_1P05_CPU

21

22

21

22

CAD NOTE:

1

2

19

20

1920

PLACE NEAR XDP CONNECTOR]

1

C2DB

C1DB

.1UF

10%

10V

2

X5R

X5R 402

402

SMB_CLK_S

IN

SMB_DATA_S

IN

J1DB

XDP_SSA

6

50

IN

6

50

IN

6

50

IN

6

50

IN

6

50

IN

6

IN

CK_H_XDP_DN

24

R3DB

0

5%

2

1

CH

402

IN

R2DB

0

15%2

CH

402

5079

XDP_BPM_N<0>

XDP_BPM_N<1>

XDP_BPM_N<2>

XDP_BPM_N<3>

XDP_BPM_N<4>

XDP_BPM_N<5>

TP_100M_CLK_DP

TP_100M_CLK_DN

CK_H_XDP_DP

IN

SMB_CLK_XDP

SMB_DATA_XDP

V_1P05_CPU

678

IN

9 7 6 4

3 1

16 18

13 15

22 24

14

28

REV=1

BPM0* BPM1* BPM2* BPM3* BPM4

*

BPM5*

100M_CLK_DP 100M_CLK_DN

XDP_H_CLK_DP XDP_H_CLK_DN

SCL SDA

VTT

NC

TDO TDI TMS TCK

TRST*

PWRGOOD

RESET*

DBR*

TESTIN*

GND GND GND GND GND GND GND GND

CONN

23 29 31 30 25

10

RST_SNS1

19 21

TP_XDP_OBS20

12

2 5 8 11 17 20 26 27

H_PWRGD_XDP

R1DB

1%

2

CH

R4DB

2

CH

1%

XDP_TRST_N

54.9

1

603

1

603

54.9

XDP_TDO XDP_TDI XDP_TMS XDP_TCK

7

IN

V_1P05_CPU

6

50

IN

6

IN

6

IN

6

IN

6

IN

R6

DB

5%

100

H_CPURST_N

2

1

CH

402

6

7850 79

IN

678

IN

50 79

V_3P3_STBY\G

1

2

6

10

IN

R5DB

1K

5% CH

402

IN

XDP_DBRESET_N

56 65 67 68 69 72 9

22 263132 33

37

40 44 52 54 55

75 77

IN

D

631

C

B

678

5079

V_1P05_CPU

678

5079

IN

CAD NOTE:

PLACE TDO TERMINATION NEAR CONNECTOR

2

R10DB 51 5%

CH 402

1

XDP_TDO

6

50

IN

1

2

R13DB 51 5%

CH 402

2

1

R14DB 51 5%

CH 402

V_1P05_CPU

IN

1

R7DB 51 5%

CH 402

2

1

R8DB

R15DB

51

5%

CH

402

2

402

2

XDP_BPM_N<0>

XDP_BPM_N<1>

XDP_BPM_N<2>

XDP_BPM_N<3>

XDP_BPM_N<4>

OUT OUT OUT OUT OUT

6

50

6

50

6

50

6

50

6

50

A

D

785079

C

B

A

CAD NOTE:

PLACE BPM TERMIN ATION NEAR CPU

[PAGE_TITLE=XDP]

8

7

6

5

4 2

BPAGE DRAWING

tawas_b.sch_1.50

Wed Feb 07 17:18:55 2007

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

50

2.0

1

CR-51 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE51

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

1

REV

DATE

D

C

B

A

KB CONNECTOR

UT PER REV 0.75

PINO

D

C

KBC_SCANIN<7..0>

55

OUT

IN

KBC_SCANOUT<15..0>

9

0

5 1

2 4 7 8 6 3 12 13 14 11 10 15

6 0 1

3

2

5 4

7

55

CONN_1X25_FPC

TP_J34_PIN25

J34

1

2

3 4 5 6 7 8 9

10 11 12 13 14 15 16 17 18

19 20 21 22 23 24 25

B

CONN

A

BPAGE DRAWING

tawas_b.sch_1.51

Wed Feb 07 17:18:56 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

51

2.0

1

[PAGE_TITLE=KBD CONN]

CR-52 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE52

8

BOM NOTE:

BLUETOOTH CONNECTOR

REPLACE WITH BM10B-SRSS-TB WHEN AVAILABLE

PINS 11 AND 12 ARE GROUND

D

30 30

55 39

USB_8_DP

BI

USB_8_DN

BI

BT_CHCLK

39

OUT

BLUETOOTH_ON

IN

BT_DATA

IN

LED_BLUETOOTH

55

OUT

BLUETOOTH CONNECTOR

PINOUT PER REV 0.75

C

VCC3

2

MODULE REV DETAILS

NAME

MODULE

C394

.1UF 10% 10V X5R 402

3

J48

CONN_1X16_FPC

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

HDR

L_AD<3..0>

295559 31 31 33 1234 24

IN IN IN IN IN IN

45

VCC3

1

2

L_FRAME_N FWH_WP_N FWH_TBL_N FWH_INIT_N PLTRST_N CK_P_33M_LPC

C986

10.0UF 20%

6.3V EMPTY 805

1

2

3 2 1 0

7

1

C365

.1UF 10% 10V

2

X5R 402

TP_J46_PIN9

TP_J46_PIN10

J46

1X

10HDR

1 2

3 4 5 6 7 8 9

10

6

BOM NOTE:

LPC CONNECTOR

REPLACE WITH FFC_CONN16 WHEN AVAILABLE

NS 13 TO 18 ARE GROUND

PI

295559

BI

37

59

HDR

LPC CONNECTOR

PINOUT PER REV 0.75

1

V

RE

E

DAT

D

C

6573 2955 5758 83

B

IN

V_3P3_KSC

1

2

33

5558

C399

UF

.1 10%

10V X5R 402

BI

BI OUT OUT OUT OUT

IN

SMB_BAT2_DATA

SMB_BAT2_CLK EC_KEY_INT_N EC_PWRSW_N EC_SPESW_N EC_LID_N

HDD_LED_N

26

5558 26 33

5783 55 55 29

LED&HOTKEYS CONNECTOR

PINOUT PER REV 0.75

A

[PAGE_TITLE=BLUETOOTH/LPC/TOUCHPAD/HOTKEY CONN]

8

R500 10K 1%

CH 402

VCC

1

C988

10.0UF

20%

6.3V

22

EMPTY 805

120_OHM@100MHZ

693286-013

FB48

2

1

KBC_TP_DATA

KBC_TP_CLK

V_3P3_STBY\G

EC_KEY_INT_N

SMB_BAT1_DATA

SMB_BAT1_CLK

FB49

2

1

FB

C379

.1UF 10%

10V X5R 402

FB_TP_DATA FB_TP_CLK

J52

653065-004

12

11

10

9 8 7 6 5 4 3 2 1

2X6HDR

B

HDR

R501

10K 1%

CH 402

R706 10K 1%

CH 402

R705

10K 1%

CH 402

R704

10K 1%

CH 402

J47

1X12 PWR

1

2

3 4 5 6 7 8 9

10 11 12

HDR

NC=13,14

55

BI

55

BI

77 9

2226

31

323337

404450

IN

545556656768697275

IN

5573

IN

5573

IN

TOUCH PAD CONNECTOR

A

BPAGE DRAWING

tawas_b.sch_1.52

Wed Feb 07 17:18:57 2007

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

52

2.0

1

CR-53 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE53

8

7

RICH CREEK SPEC:

D

CHASSIS UP SIGNAL

OUT OUT

BI BI

USB_OC1_N USB_OC2_N

USB_1_DP USB_1_DN

USB_2_DP USB_2_DN

3033 3033

30 30

C

6

10

9 8 7 6 5 4 3 2 1

J53 CONN

1OF1

IO IO IO IO IO IO IO IO IO IO

REV=1

CONN_10P_FPC

GND GND GND GND

45

14 13 12 11

3

2

MODULE REV DETAILS

MODULE NAME

1

REV

DATE

D

C

B

A

BPAGE DRAWING

[PAGE_TITLE=CHASSIS UP SIGNAL CONN]

8

7

6

5

4 2

tawas_b.sch_1.53

Wed Feb 07 17:18:59 2007

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

53

1

REV

2.0

B

A

CR-54 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE54

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

1

REV

DATE

D

PINOUT PER REV 0.75

VCC_USB

697382

C

31

3233

40445052

B

IN

40

C1005

C922

10UF

.1UF 10%

10% 16V

10V

X5R

EMPTY

1206

402

555665676869

V_3P3_STBY\G

9

2226

IN

37 727577

C1010

.1UF 10% 10V EMPTY 402

1

3 5 7 9

11 13 15 17 19

NC=21,22

J50

2X10HDR_2NC

HDR

2 4 6 8 10 12 14 16 18 20

4055

VCC3

C139

C1004

0UF

10.

.1UF 10%

20%

6.3V

10V

EMPTY

EMPTY 402

805

OUT

343639

IN

30

OUT

30

OUT

30

IN

30

IN

24

IN

24

IN

30

BI

30

BI

30

BI

30

BI

3033

OUT

3033

OUT

44

IN

44

IN

44

IN

42

IN

44

IN

44

IN

41

OUT

41

IN

31

333739

AUD_SPDIF_IN AUD_SPDIF_OUT PCIE_WAKE_N BUF_PLT_RST_N

PCIE_RX4_DP PCIE_RX4_DN

PCIE_TX4_DP PC

IE_TX4_DN

CK_PE_100M_EXT_DP CK_PE_100M_EXT_DN

USB_0_DP USB_0_DN

USB_3_DP USB_3_DN

USB_OC0_N

USB_OC3_N

HP_JACK_DETECT

AUD_HP_JACKR

AUD_HP_JACKL

AUD_MIC_JACK_SENSE AUD_PORT_MIC1_R AUD_PORT_MIC1_L

AUD

J54

2X17SMHDR

1

2

3 4 5 6

7 8 9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

C

B

HDR

IO POWER - CHASSIS DOWN POWER

A

8

7

CHASSISDOWNSIGNAL/IO EXPANSION CONN

A

[PAGE_TITLE=LOWER RIGHT CONN]

BPAGE DRAWING

tawas_b.sch_1.54

Wed Feb 07 17:19:00 2007

6

5

4 2

3

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CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

54

2.0

1

CR-55 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE55

8

C307

1

.1UF

10V

X5R

R347

1

2

C308

.1UF 10% 10V X5R 402

R405BU 0

1A

CH 603

1

0

402

A11

A3

VCC1_2

VCC1_1

V_3P3_KSC

29525557

D

IN

58657383

1

C305

.1UF 10% 10V

2

X5R

2

402

1

2

FB5

EMPTY

1

R4

1

04BU

0

FB6

1A

EMPTY

CH

2

603

2

10%

402

2

5% CH

B27

A13

VCC1_4

VCC1_3

1

0

402

A36

B46

A59

VCC1_7

VCC1_6

VCC1_5

7

348

R

C306

A69

VCC1_8

6

575757

A79

VCCO/BAT

FLASH_OE_N

A33

FRD*

OUT

FLASH_WE_N

B32

FWR*

OUT

FLASH_CE_N

A35

FCS*

57

BI

LASH_D<7..0>

F

A24

B24

FD1

FD0

2

5% CH

2

.1UF 10%

10V

X5R

1

402

A18

B66

B72

DAC_VCC

ADC_VCC

VCC1/PLL

57

T OU

LASH_A<19..0> KBC_SCANIN<7..0> KBC_SCANOUT<15..0>

F

121110

9

87654321076543210

A27

A29

B28

A30

B29

B34

A37

B35

A38

B36

A39

B37

A28

B26

A25

B25

A26

FD5

FD4

FD3

FD2

FD6

A31

FA5

FA4

FA3

FA2

FA1

FD7

FA0

B39

1

10

FA9

FA8

FA7

FA6

FA12

FA

FA1

A41

FA13

51

IN

19181716151413

A42

A44

B43

B47

A50

B42

A43

B40

FA18

FA17

FA16

FA15

FA14

FA19/GPIO32

KSI0/SGPIO40

KSI1/SGPIO41

A4B4B3

KSI3/SGPIO43

KSI2/SGPIO42

KSI4/SGPIO44

B2

KSI5/SGPIO45

B1

KSI6/SGPIO46

51

OUT

B48

KSI7/SGPIO47

A23

B20

B21

1/SGPIO31

KSO2/SGPIO32

KSO0/SPGIO30

KSO

C

304

2

1

V_3P3_KSC

IN

B

A

[PAGE_TITLE=KEYBOARD CONTROLLER]

22.000UF

.1UF

10V X5R 402

C303

1

.1UF

10V X5R 402

C302

1

.1UF

10V X5R 402

C301

1

.1

UF

10V X5R 402

C400BU

1

10%

.1UF

10V X5R 402

C401BU

1

.1UF 10%

10V X5R 402

C402BU

1

10%.1UF

10V X5R 402

C403BU

1

10%

.1UF

10V X5R 402

C404BU

1

20%

6.3V X5R 805

8

10%

EU1

2

10%

2

10%

2

10%

2

KBC1122

PCI_CLK

B10

CK_P_33M_KBC

IN

24

OUT7/SMI*

CLKRUN*

A8

B61

M_CLKRUN_N

EC_EXTSMI_R_N

P

BI

1

31

2

33

80

EC_EXTSMI_N

31

IN3/TIN6W

IN2/TIN5W

GPIO39/SPDIN/TIN4

OUT8/KBRST

CLOCKI

B9

A12

B62

A66

A63

K_14M_EC

H_RCIN_N

C

EC_PWRSW_D_N

BV_3P3_CHG

T

V_5P0_STBY_PWRGD_EC

IN

OU

OUT

IN

R1277

IN

57

0

24

5%

697374

56

CH 402

29

OUT

7

D_1

LAD_0

LA

LFRAME*

LAD_3

LAD_2

OUT0/PWM3

OUT10/PWM0

OUT11/PWM1

OUT9/PWM2

A65

B76

B60

R400BU

0 5%

CH 402

CPU_FAN_PWM

OUT

9

A20

EC_SPKR

OUT

42

SER_IRQ

B7

A7

A5

A6

B6

B8

L_FRAME_N

SER_IRQ

3

012

BI

31

33

59

L_AD<3..0>

BI

LGPIO60/SPDOUT

LGPIO64/SPDIN

LGPIO70/SPCLK

LRESET*

LDRQ0*

GPIO84/LPCPD*

B5

A9

B55

B11

TP_EC_B55

TP_EC_B75

ICH_DRQ0_N

LPCPD_N

BUF_PLT_RST_N

INININ

OUT

31

343639

295259

29

59

4054

LGPIO77/1_8432MHZ_IN

GPIO73/MSCLK/SPDOUT

GPIO74/MSDATA/SPCLK

SA_GPIO0

SA_GPIO1

5

A68

B75

A62

TP_EC_A62

A60

B57

B56

B6

_EC_A68 TP

TP_EC_B65

EC_MSCLK

EC_18432MHZ

R403BU

BI

4.7K 5%

EMPTY

R1276

402

BI

55

EC_MSDATA

V_3P3_KSC

IN

BI

6

55

W

A20/GPIO33

A21/GPIO34

IN0

GPIO0/KSO16

GPIO1/KSO17

F

GPIO15/FANTACH1

GPIO16/FANTACH2

GPIO19/FANTACH3

B52

CPU_FAN_TACH

0

5%

CH

402

IN

9

PWRGD

A64

B30

B59

A61

DELAY_VR_PWRGOOD

EC_WAKE_SCI_R_N

1

OUT

2

OUT

EC_WAKE_SCI_N

31

56

A52

B50

A46

A32

1

R368

ALL_SYS_PWRGD_R

R365

5%

0

CH

5%

402

CH

N_SYS_PWR

402

E

EC_LID_N

EC_3P3M_CTRL

2

OUT

EC_KEY_INT_N

EC_SPESW_N

69

IN

ICH_VRMPWRGD

2652

52

IN

OUT

31

52

65

77

0

GPIO36/32KHZ_OUT/A20M

A80

1

_A20GATE_R H

2

H_A20GATE

OUT

2956

GPIO10/IRMODE/IRRX3B

GPIO20/PS2CLK/8051RX

GPIO21/PS2DAT/8051TX

B49

A55

A56

P_S4_N

EC_8051RX

SLP_S3_N

SL

EC_8051TX

T OU

IN

BI

55

31

55

61

71

HW_PROTECT*/DBM_GPIO10

GPIO9/IRTX2W

B23

IN

18

26

31

37

697275

FA22/GPIO35

B31

PM_RSMRST_R_N

PM_RSMRST_N

31

GPIO6/IRMODE/IRRX3AW

A54

VGA_SW_EN_N

OUT

R373

0 5%

CH

402

28

BI

A48

PM_PWRBTN_R_N

PWR_LED*/GPIO41

OUT

555555

BAT_LED*/GPIO40

A49

_DBG_LED_N EC

SENSOR0/DBM_GPIO8

B63

A67

TP_EC_B63

TP_EC_A67

OUT

5

45

52

565256

BI

IN

151413

121110

9

B19

KSO3/SGPIO33

B18

KSO4/SGPIO34

B17

KSO5/SGPIO35

B16

KSO6/SGPIO36

A17

KSO7/SGPIO37

87654321076543210

B15

KSO8/GPIO26

A16

KSO9/GPIO27

A15

KSO10/GPIO28

B14

KSO11/GPIO29

A14

KSO12/OUT8/KBRST

A53

B13

GPIO4/KSO14

KSO13/GPIO18

KBC_TP_DATA

B41

B51

GPIO5/KSO15

GPIO81/IMDAT

KBC_TP_CLK

GFX_PMON_OUTPUT_EC

BATT_THERMAL1_EC

A74

A75

B12

A76

GPIO80/IMCLK

ADC4/DBM_GPIO4

ADC2/DBM_GPIO2

ADC0/DBM_GPIO0

SOR1/DBM_GPIO9

IRTX/GPIO71

IRRX/GPIO72

GPIO8/IRRX2W

VCC1_RST*

TXD/GPIO63

RXD/GPIO62

RI*/GPIO75

TEST_PIN/FPGM

SEN

B64

_3P3_STBY\G V

IN

EC_SCI*/GPIO24

A1

A2

B58

B44

B45

A10

A45

A40

A47

TP_EC_A47

R1278

EC_RUNTIME_SCI_ R_N

0

5%

CH

402

LAN_ENE_REP_EC_N

LED_WLAN_N

LED_BLUETOO TH

IN

OUT

39

52

40

SUSPWR_ACK_EC

R1234

EMPTY

BLUETOOTH_ON

T

IN

EC_RUNTIME_SCI_N

OUT

OU

56

OUT

52

31

10K

5%

402

PORT_CRT_EN_EC_N

OUT

56

4 2

DCD*/GPIO68

DTR*/GPIO67

CTS*/GPIO66

RTS*/GPIO65

DSR*/GPIO64

A34

B33

A22

B22

B38

WOL_EN_EC

AC_PRESENT_EC

BATT_PRTCT_EC_R

EC_LAMP_STAT

PORT_REP_DETECT_EC

T

IN

OUT

OU

565656

26

56

GPIO14/I2C2B_CLKW

A21

SMB_BAT2_CLK

26

33

5258

Wed Feb 07 17:19:01 2007

3

2952555758657383

56

565626

56

OUT

BATT_DISA_EC

A73

ADC5/DBM_GPIO5

I2C1B_CLK/CLK/GPIO78/EMCLK

A57

SMB_THRM_CLK

9

OUT

BATT_CHGA_EC

B69

ADC6/DBM_GPIO6

I2C1A_DATA/GPIO44

B54

SMB_BAT1_DATA

5273

OUT

SLP_M_N_EC

A72

ADC7/DBM_GPIO7

I2C1A_CLK/GPIO76

A58

SMB_BAT1_CLK

BIBIBIBIBI

5273

OUT

DAC_BRIG

A71

DAC0

DBM_AGND

B68

56

OUT

ICHRG_EC

VCHRG_EC

B67

A70

DAC2

DAC1

VSS/PL

A19

1

2

A77

AGND

XOSEL

A78

XOSEL

PGND

1

R383

0 5%

CH 402

IN

V_3P3_STBY\G

EC_1

B70

B71

ADC3/DBM_GPIO3

ADC1/DBM_GPIO1

I2C1B_DATAGPIO77/EMDATA

GPIO13/I2C2B_DATAW

B53

A51

SMB_THRM_DATA

SMB_BAT2_DATA

BI

9

26

33

5258

BPAGE DRAWING

tawas_b.sch_1.55

3

IN

KBC_XTAL1

B73

XTAL1

V_3P3_KSC

KBC_XTAL2 B74

XTAL2

1OF1

55

SKT

55

REV=1

1

R380

1K

402

IN

BI

55 55 55

2

1

R381

5%

1K

EMPTY

402

1

R382

5%

10M 603

CH

32.768KHZ

XTAL

SM

Y7BU

1

C309

12P

F 5% 50V

2

COG 402

PM_PWRBTN_R_N

C402

2

.1UF 10%

10V

X5R

1

402

R401BU

EC_8051TX

5%

EMPTY

R402BU

EC_8051RX

5%

EMPTY

402

BI BI BI

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

MODULE REV DETAILS

MODULE NAME

2

5% CH

2

NC=2,3

4

1

C310

5% 50V

2

COG 402

CR9

30V

SCHOTTKY

3

SOT23 DIO

0.2A

2952555758657383

12P

F

1

IN

R501BU

2

5% CH

PM_PWRBTN_N

V_3P3_KSC

1

R1056

330 5%

CH 402

2

CR39

MULTI

1

EC_DBG_LED_N

1

10K 402

NEED RED LED FIND IPN AND

EMPTY

SYMBOL

603

PINOUT PER REV 0.75

0

402

0

EC_8051TX_DBG

EC_8051RX_DBG

EC_18432MHZ EC_MSDATA EC_MSCLK

J62

1X8HDR2NC

1

2

3 4 5 6 7 8

HDR NC=9,10

DOCUMENT_NUMBER

D89092

1

REV

V_3P3_STBY\G

OUT

DESIGN NO TE:

PAGE

1

DATE

D

IN

C

31

B

55

OUT

A

REV

55

2.0

CR-56 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE56

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

1

REV

DATE

D

R420BU

65

28

31

33

V_5P0_STBY_PWRGD

IN

OUT

IN

PORT_CRT_EN_N

SUSPWR_ACK

V_5P0_STBY_PWRGD_EC

0

5% CH

402

R422BU

0

402

5%

PTY

EM

PORT_CRT_EN_EC_N

R423BU

5%

0

EMPTY

402

SUSPWR_ACK_EC

OUT

55

IN

55

IN

BATT_THERMAL1

TP_EC_1

73

C

47

OUT

83

IN

31

B

IN

31

OUT

73

IN

LAN_ENE_REP_N

PORT_REP_DETECT

WOL_EN

AC_PRESENT

BATT_PRTCT_EC

R424BU

0

402

R425B

0

402

R426BU

0

402

R427BU

0

402

R428B

0

402

LAN_ENE_REP_EC_N

5%

PTY

EM

U

PORT_REP_DETECT_EC

5%

EMPTY

WOL_EN_EC

5%

EMPTY

AC_PRESENT_EC

5%

EMPTY

U

BATT_PRTCT_EC_R

5%

EMPTY

OUT

55

IN

55

IN

55

73

OUT

73

OUT

74

OUT

74 55

OUT

2955

OUT

BATT_DISA

BATT_CHGA

ICHRG

VCHRG

H_A20GATE

A

31

55

OUT

31

6970

71

72

SLP_M_N

22

OUT

R429BU

0

402

R430BU

0

402

R431BU

0

402

R432BU

0

402

R433BU

0

402

R434BU

0

402

R435BU

0

402

R436BU

8.2K 402

R437BU

10K

402

R438BU

10K

402

EM

EMPTY

5%

PTY

5%

EM

5%

EM

5%

EMPTY

5%

EM

5%

EMPTY

5%

EMPTY

5% CH

5%

GFX_PMON_OUTPUT_ECGFX_PMON_OUTPUT

PTY

BATT_THERMAL1_EC

EC_1

BATT_DISA_EC

BATT_CHGA_EC

ICHRG_EC

VCHRG_EC

V_3P3_STBY\GEC_WAKE_SCI_N

SLP_M_N_EC

VCC3

5575

OUT

55

OUT

55

OUT

55

IN

55

IN

55

IN

67 68 69 72 75 9

22 263132 33

IN

40 44 50 52 54 55 65

55

IN

D

C

B

A

77

37

[PAGE_TITLE=EC SIGNAL STUFFING OPTIONS]

8

7

6

BPAGE DRAWING

tawas_b.sch_1.56

Wed Feb 07 17:19:03 2007

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

56

2.0

1

CR-57 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE57

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

1

REV

DATE

R694

100K

5% CH

402

XSTR

7 6 5 4

3 2

1 0

2

FLASH_D<7..0>

V_3P3_KSC

1

C

311

.1UF 10% 10V

2

X5R 402

C410B

1UF 20%

6.3V X5R 603

55

BI

D

29

52 55 57 58 65 73 83

IN

C

B

U

R408B

10K

402

EC_PWRSW_N

5% CH

52 83

IN

U

A

U6

D

55

IN

55

IN

55

IN

C

FLASH_A<19..0>

55

IN

B

FLASH_WE_N FLASH_CE_N FLASH_OE_N

19 17 10

18 16 15 14 13 12 11 9 8 7 6 5 4 3 2 1 0

2952555758657383

55

OUT

9 22 24 37 40 36

13

1

2

3

4

5

6

7

8 14 15 16 17 18 19 20 21

IN

EC

SST39VF080

WE* CE* OE* A19 A17 A10

A18 A16 A15 A14 A13 A12 A11 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

REV=1

V_3P3_KSC

_PWRSW_D_N

MBT3904DUAL

DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

VSS VSS

VDD VDD

1OF1

Q48BU

35 34 33

32 28 27 26 25

10

NC

11

NC

12

NC

29

NC

38

NC

23

39

30

31

IC

R695

100K 5%

CH 402

6

3

5

1

4

A

[PAGE_TITLE=KBC SPI/SEQUENCING]

8

7

6

BPAGE DRAWING

tawas_b.sch_1.57

Wed Feb 07 17:19:04 2007

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

57

2.0

1

CR-58 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE58

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

1

REV

DATE

D

C

DESIGN NOTE:

NOT REQUIRED PER SYSTEM TEAM DELETE FOR FAB C

B

83 73 65 57 55 52 29

A

IN

V_3P3_KSC

EC

1

R104BU

1

0 5%

2

EMPTY 402

1

R107BU

1

0 5%

2

EMPTY

2

402

EC

R105BU 0 5%

EMPTY 402

R108BU 0 5%

EMPTY 402

EC

0 5%

2

EMPTY 402

1

R109BU 0 5%

2

EMPTY 402

EC

1

R

106BU

EC

CAD NOTE:

EC

SSOP65 FOOTPRINT

9

U2

24C02

NM

A2 A1 A0

SDA

SCL

EMPTY V_3P3_KSC=8 GND=4 NC=7

SMB_BAT2_CLK

SMB_BAT2_DATA

5552

33

26

BI

33

26

BI

5552

D

C

B

A

[PAGE_TITLE=MASTER SMBUS]

8

7

6

5

4 2

BPAGE DRAWING

tawas_b.sch_1.58

Fri Feb 09 08:43:28 2007

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

58

2.0

1

CR-59 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE59

8

TPM 1.2

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

TPM1.2

2.0.0

1

REV

DATE

41.5.06

D

BOM NOTE:

VCC3

1

C7TM

C8TM .1UF

.1UF 20%

20%

25V

2

Y5V

603

CAD NOTE:

TPM VCC3 DECOUPLING: 0.1UF CAPS. PLACE ONE PER TPM POWER PIN (10,19,24,5)

TPM FEATURE: ST-MICRO: C6T M EMPTY ATMEL & SINOSUN: C6TM .1UF

1

C4TM

.1UF 20% 25V

2

Y5V 603

C6TM

.1UF 20% 25V EMPTY 603

C

CK_P_33M_TPM

24

IN

PLTRST_N

123437

52

B

VCC3

R14TM

2

1

5%

10K

EMPTY

402

M

LPCPD_N

31

IN

55

DESIGN NOTE:

TPM FEATURE: DEFAULT STUFF R12TM, EMPTY R14TM STUFFING OPTION TO ISOLATE LPCPD* FROM ICH

R12T

2

1

0

5% CH

402

IN

295255

31

33

55

L_AD<3..0>

BI

L_FRAME_N

295255

IN

SER_IRQ

BI

LPCPD_PN1_N

1

2

BOM NOTE:

TPM FEATURE: ST-MICRO: R7T M, R6TM, R10TM EMPTY ATMEL & SINOSUN: R7TM, R6TM, R1 0TM 0 OHM

VCC3

21 16

26

0

23

1

20

2

17

3

22 27

28

TPEV_TPM_CLKRUN_N

R11TM

4.7K 5%

CH 402

15

R7TM

1

2

TPM_NC_R_10

5%

0

EMPTY

402

VCC3

LCLK LRESET*

LAD0 LAD1 LAD2 LAD3

LFRAME* SERIRQ

LPCPD*

CLKRUN*/GPIO4

REV=1

10

NC

VCC3

19

VDD

VCC3

24

VDD

R10TM

1

2

5%

0

EMPTY

402

1

R6TM 0 5%

2

EM

PTY

402

TPM_NC_R_5

V3P0_BAT_TPM

U1TM

12

5

WPCT200

VSB

VBAT

GPIO0/XOR_OU T

GPIO1

GPIO2/GPX

TEST

GPIO3/BADD

1O

VSS

4

NC

11

VSS

18

VSS

25

F1

TPM_NC_25_R

BOM NOTE:

402

TPM FEATURE: ST-MICRO: R2T M EMPTY ATMEL AND SINOSUN: R2TM 0 OHM

R13TM

2

1

0

5%

EMPTY

402

BOM NOTE:

TPM FEATURE: ST-MICRO A ND SINOSUN: R13TM EMPT Y

XTALIN_TPM

13

NC

14

R2TM

EMPTY

TP_TPM_PIN_14

TP_TPM_PIN_1

1

TP_TPM_PIN_2

2

TP_TPM_PIN_6

6

TPM_TESTIO

8

BADDR

9

7

TPM_PRESENCE

TP_TPM_PIN_3

3

IC

2

5%

BOM NOTE:

STUFF FOR WINBOND ONLY

NC

PP

NC

1

0

ATMEL: R13TM 0 OHM

R3TM

2

1

5%

4.7K EMPTY

402

BOM NOTE:

TPM FEATURE:

T-MICRO: R3TM E MPTY

S ATMEL AND SINOSUN: R3TM 4.7K

C9TM

.1UF 10%

16V EMPTY 402

DESIGN NOTE:

TPM FEATURE: DEFAU LT EMPTY. STRAPS FOR PHYSICAL PR ESENCE.

VCC3

DESIGN NOTE:

TPM FEATURE:

1

PULL-UP STRAPPING FOR ENABLING TEST-MODE ON SINOSUN

R5TM

4.7K 5%

EMPTY 402

2

1

BOM NOTE:

R4TM

TPM FEATURE:

4.7K ST-MICRO A ND SINOSUN: EMPTY

5%

ATMEL: STUFF 4.7K

EMPTY 402

2

D

C

B

VCC3

A

R8TM

1

2

1K

5%

EMPTY

402

R9TM

2

1

0

5%

EMPTY

402

A

BPAGE DRAWING

[PAGE_TITLE=TPM]

8

7

6

5

4 2

tawas_b.sch_1.59

Wed Feb 07 17:19:06 2007

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

59

2.0

1

CR-60 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE60

8

MCH

D

X.X (VCCP)

1.25 (V_1P25_CORE)

1.8 (V_SM)

1.25 (V_1P25_PCIEXPRESS)

7

6

SIO

3.3 (VCC3)

5.0 (VCC)

3.3 STBY (V_3P3_STBY)

5.0 STBY (V_5P0_STBY)

X.X (V_FSB_VTT)

TEKOA

ICH

3

.3 (VCC3)

1.5 (V_1P5_ICH)

C

X.X (V_FSB_VTT)

3.

3 STBY (V_3P3_STBY)

3.3 STBY (V_3P3_EPW)

1.8 (LAN_V_1P8)

1.0 (LAN_V_1P0)

FWH

3

.3 (VCC3)

LAN

CK-505

3.3 (VCC3)

C6

HE

3.3 STBY (V_3P3_STBY)

45

VREG_12V_FILTERED (+12V FILTERED FROM 12V POWER-SUPPLY) VCCP (VTT, FOR CDM 1. XX - 1.XXV)(DERI VED FROM VREG_12V_FILTERED) V_FSB_VTT (X.XV DERIVED FROM V_SM) V_SM_VTT (X.XV DERIVED FROM V_SM) V_SM (1.8V DERIVED FROM 5VDUAL_FI LTERED) VREG_USB_BP_LEFT (5. 0V FROM 5VDUAL) VREG_USB_BP_RIGHT (5.0V FROM 5VDUAL) VREG_PS2 (5.0V FROM 5VDUAL) USB_FNT_PWR (5.0V FROM 5VDUAL) USB_FNT_34_PWR (5. 0V FROM 5VDUAL) V_3P3_PCI_VAUX (3.3V OR 3.3-STANDBY SOURCE) V_3P3_STBY ( 3.3V DERIVED FROM 5.0-STANDBY) V_BAT_VREG_R_CR (3.0V FROM THE BATTERY) V_3P0_BAT_VREG (~3.0V FROM THE BATTERY THROUGH A DIODE) 5VDUAL (5.0V DERIVED FROM VCC OR V_5P0_STBY) LAN_V_1P0 (1.0V DERIVED FROM V_3P3_EPW) LAN_V_1P8 (1.8V DERIVED FROM V_3P3_EPW) V_1P25_CORE (1. 25V DERIVED FROM VCC3) V_1P25_CL_MCH (1.25V DERIVED FROM V_SM) V_1P5_ICH (1.5V DERIVED FROM VCC3) V_1P05_ICH_CORE (1. 05V DERIVED FROM VCC3) V_1P25_PCIEXPRESS (1.25V DERIVED FROM V_1P25_CORE)

+12V (PLUS 12V FROM POWER-SUPPLY)

-12V (MINUS 12V FROM POWER-SUPPLY) VCC3 (3.3V FROM POWER-SUPPLY) VCC (5.0V FROM POWER-SUPPLY) V_5P0_STBY ( 5.0V STANDBY FROM POWER-SUPPLY)

3

2

MODULE REV DETAILS

MODULE NAME

1

REV

DATE

02-06-073.26.01SR_BV_CHR

D

C

5.0 (VCC)

12.0

B

X.X (VCCP)

1.

25 (V_1P25_CORE)

B

A

[PAGE_TITLE=CORE_VR_POWER_MAP]

BPAGE DRAWING

tawas_b.sch_1.60

Wed Feb 07 17:19:08 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

60

2.0

1

CR-61 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE61

8

71

737475

26626365 66686970 76

77

78

INTERMEDIATE_BUS_POWER

IN

D

69707576

V_5P0_STBY\G

61

7883

31

55

71

31

55

71

72

9263233

IN

62656668 77

1

2

SLP_S4_N

IN

SLP_S4_N

IN

V_SM_PWRGD

OUT

R283BV

100K

5% EMPTY

402

61

IN

BV_VSM_AVDD

IN

A_GND_VSM

2

1

61

100K

402

R66BV

0OHM

EMPTY SM

IN

100K

R59BV

1

C

2

220PF

45

C

B

A

8

1

C89BV

1.0UF 10% 16V

2

X5R 805

BV_VSM_REF

BV_VSM_AVDD

R67BV

2

1

5% CH

402

2

BV_VSM_VTT_PWROK

5% CH

109BV

1

10%

50V

EMPTY

402

110BV

C

1

1UF

6.3V X5R 402

7

BV_VSM_SS

2

10%

7

BOM NOTE:

DEFAULT STUFF W/ 0 OHM RESIST OR OPTIONAL STUFF W/ FB IPN: 651080-023

M18BV

1

LTI

MU

CH

EU

3BV

ISL88550A

17

VIN

1

TON

2

OVP/UVP

27

SHDNA*

7

STBY*

5

POK1

15

FB

6

POK2

28

TP0

8

SS

REV=1

6

M17BV

MULTI

1206

UGATE PHASE

BOOT

LGATE

VD

PGND1

ILIM

SKIP*

OUT

GND

AVDD

REF

VTTS

VTT

VTTI

REFIN

VTTR

PGND2

GND

2

1

2

D

C100BV

4.7UF 20%

6.3V X5R 805

18 19 20 21 22 23

4

25

16

24 26

3 9 12 13 14

10 11

29

1206

1

CH

2

1OF1

IC

1

2

C111BV

10UF

20%

6. X5R 805

1

C112BV

10UF

3V

20%

6.3V

2

X5R 805

CAD NOTE:

PLACE AT THE OUTPUT OF THE REGULATOR

6

ERMEDIATE_FILTERED_V_SM

INT

C106BV

BV_VSM_UGATE

BV_VSM_BOOT BV_VSM_LGATE

BV_VSM_ILIM

A_GND_VSM

1

C94BV

1UF 10%

6.3V

2

X5R 402

4.7UF

CAD NOTE:

PLACE CLOSE TO FET

BV_VSM_AVDD

5

1206

1

2

20% 25V X5R

OUT

1

2

C95BV

1UF 10%

6.

3V X5R 402

OUT

C90BV

4.7UF 20%

6.3V X5R 805

1

2

0

805

R58BV

1

61

1

C107BV

4.7UF 20% 25V

2

X5R

1206

D17848-001 (STL50NH3LL)

2

BV_VSM_UGATE_R

1A CH

R60BV

2

1

BV_VSM_BOOT_R

1

5% CH

603

R61BV

1

0

805

MOD TO IPN:D18314-001 STL100NH3LL

1

C91BV

4.7UF 20%

6.3V

2

X5R 805

CAD NOTE:

4.7UF CAPS FOR CH A

PLACE AT LEFT AND RIGHT ENDS OF VTT ISLANDS

45

1

C217BV

4.7UF 20% 25V

2

EMPTY

1206

5

Q18BV

D

4

S

G

FET 1 2

3

CAD NOTE:

PLACE CR21BV NEAR DRAIN AND

64.9K 402

OUT

4

R62BV

1

100K

402

G

R63BV

1

61

2

SOURCE OF FET Q19BV

5

D

S

1 2 3

2

1%

CH

2

1% CH

61

1

C92BV

4.7UF 20%

6.3V X5R 805

.22UF

BV_VSM_LGATE_R

2

1A

CH

BOM NOTE:

A_GND_VSM

BV_VSM_REF

C96BV

10V X7R 603

10%

1

C97BV

.1UF 10% 10V

2

X5R 402

OUT

BV_VSM_PHASE

CAD NOTE:

PLACE 4.7UF CAPS FOR CH B AT LEFT AND RIGHT ENDS OF VTT ISLANDS

Wed Feb 07 17:19:09 2007

4 2

3

1

C273BV

47UF 20%

16V

TANT

2

7343

Q19BV

FET

R64BV

1

182K 1%

EMPTY

2

402

1

2

BPAGE DRAWING

tawas_b.sch_1.61

1

CR21BV MBRS130LT3 SM DIO

2

C93BV

4.7UF 20%

6.3V X5R 805

1

2

1

2

1

2

C108BV

47UF 20% 16V TANT 7343

R65BV

2.2 5%

CH 805

BV_VSM_SN

C98BV

4700PF 20% 50V X7R 603

3

CAD NOTE:

PLACE +NODE NEAR HIGH-FET DRAIN PLACE GND SIDE CLOSE TO LOW-FET GND

BOM NOTE:

MOD TO 47UF-IPN:724613-076

L7BV

1UH

2

1

IND

2

MODULE REV DETAILS

MODULE NAME

V_SM

1

C99BV

C101BV

10UF

10UF 20%

20%

6.3V X5R 805

INTEL

6.3V

2

X5R 805

DDR_RE

V_SM_VTT

F

DOCUMENT_NUMBER

2

[PAGE_TITLE=VREG: V_SM/SMVTT]

CONFIDENTIAL

CUSTOM TEXT BPAGE

11121415161719 20

OUT

71

1

C88BV

330UF 20%

2.50V T

TAN

2

SM

OUT

D89092

1

REV

DATE

02-06-073.26.01SR_BV_CHR

D

C

B

12

19 20

71

21

A

PAGE

REV

61

2.0

1

CR-62 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE62

8

6364

IN

BV_FILTERED_1P5_1P05

7

6

R91BV

1

2

5%

3.3 CH

DESIGN NOTE: FIND 3.9 OHM PART

805

D

1

2

C133BV

4.7UF 20% 25V X5R

1206

45

2

C134BV

.1UF 20% 25V

1

Y5V 603

3

A_GND_1P5

62

63 64

IN

2

MODULE REV DETAILS

MODULE NAME

SR_BV_CHR

3.26.01

1

REV

DATE

02-06-07

D

OUT

BV_1P05_BST_R

62

C

BV_1P5_UGATE

64

OUT

64

8161832

78 26 70

6869

7576777883 9263233

BV_1P5_PHASE

IN

BV_1P5_LGATE

OUT

V_1P5_CORE

IN

BV_1P5_COMP

IN

BV_1P5_FB

IN

INTERMEDIATE_BUS_POWER

IN

SLP_S3_NEW

IN

V_5P0_STBY\G

IN

64

37

39

B

77

61

4064

71

64

61

6365666869

71

73747576

71

72

45

6566686970

INTERMEDIATE BUS POWER = 8.7V TO 12.6V

A

8

62

7

1

BV_1P5_LDO5

IN

CR15BV

.45V

3

SOT23A DIO

2

BV_1P5_BST_R

2

C130BV

.1

UF 10% 10V

1

X5R 402

R99BV

1M

402

BV_1P5_LDO5

C136BV

1UF 10%

6.3V X5R 402

1

2.

40

5%

2

CH 402

BV_1P5_LOD_COMP

1

C137BV

4.7UF 10%

6.3V

2

X5R 603

18

LDO5

23

BOOT1

31

VCC

BOM NOTE:

I

PN TO BE ADDED TO LIB

D78253-001

EU

5BV

PM6680

REV=1

VIN

BOOT2

1

R94BV

1

49.9 1%

CH

2

A_GND_1P5

62

6364

IN

C

135BV

1

.22UF

2

10% 10V X5R 402

2

1

R92BV

20 1%

CH 603

402

2

BV_1P5_BOOT1

BV_1P5_VCC

R182BV

HGATE2

22

HGATE1

21

PHASE1

PHASE2

LGATE2

15

LGATE1

R101BV

1

2

BV_1P5_CSENSE1

2K

1%

CH

402

R100BV

V_1P5_PWRGD

1

2

5%

1

100K

2

5% CH

CH

402

R142B

1

249K

1%

CH

2

402

BV_1P5_SHDN

V

626364

6

20

CSENSE1

29

OUT1

30

COMP1

28

FB1

26

PGOOD1

5

SHDN

4

EN2

25

EN1

17

V5SW

33

CNTR_PAD

IN

5

CSENSE2

PGND

SGND1

OUT2

COMP2

SGND2

FB2

PGOOD2

VREF

SKIP

FSEL

OPTION 1 OF 1

A_GND_1P5

4 2

NC

IC

1

2

OUT

19

9

10

11

13

12

14

1

8

2

16

7

27

32

24

3

6

R204BV

0OHM

EMPTY SM

62

BV_1P5_VIN

BV_1P5_BOOT2

BV_1P5_CSENSE2

BV_1P5_VREF

BV_1P5_SKIP

R97BV

1

0

5% CH

402

R153BV

0

402

R98BV

1

0 5%

EMPTY

2

402

[PAGE_TITLE=VREG:

BPAGE DRAWING

Fri Feb 09 11:37:19 2007

R93BV

1A

0

CH

603

R95BV

1

2K

402

BV_SGND_LDOFB

BV_1P05FB_LDOOUT

1

2

1

2

BV_1P5_LDO5

5%

EMPTY

tawas_b.sch_1.62

3

BV_1P05_BST_R

2

1

2

1% CH

1

C261BV

10UF 20%

6.3V

2

PTY

EM 603

BV_NC_1P05FB

C129BV

.1UF 10% 10V X5R 402

A_GND_1P5

C138BV

.1

UF 10% 10V

X5R 402

A_GND_1P5

IN

62

IN

BV_1P05_UGATE

BV_1P05_PHASE

BV_1P05_LGATE

V_1P05_CORE

BV_1P05_COMP

R249BV

2

1

5%

0

2

5% CH

1

2

100K

R248BV

0 5%

EMPTY 402

402

EM

R96BV

1

PTY

2

5% CH

IN

R252BV

1

2

5%

0

CH

402

62 63 64

62

1

2

R250BV

3.74K 1%

EMPTY 402

1

2

R247BV

1

0

402

64 62

IN

63

V_3P3S_TVDAC

R251BV

10K 1%

EMPTY 402

1.5/1.05 CONTROLLER]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

OUT

IN

63

OUT

810141516

IN

23 2932637177

63

IN

V_3P3S_TVDAC

BV_1P05_FB

BV_1P5_LDO5

V_1P05_PWRGD

16

18 62

A_GND_1P5

D89092

C

63

17 18

B

16

18 62

OUT

63

IN

62

IN

77

OUT

62 63

PAGE

62

IN

A

64

REV

2.0

1

CR-63 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE63

8

767778

71

D

6970

INTERMEDIATE_BUS_POWER

26

61

62

IN

656668 737475

7

BOM NOTE:

DEFAULT STUFF W/ 0 OHM RESIST OR OPTIONAL STUFF W/ FB IPN: 651080-023

M14BV

1

MULTI

CH

1206

M13BV

1

MULTI

1206

CH

2

CAD NOTE:

PLACE NEAR HIGH SI

DE FET

6

2

1

2

C128B

10UF 20% 25V X5R 1206

1

C131B

V

10UF 20% 25V

2

X5R

1206

1

C268B

V

10UF 20% 25V

2

X5R 1206

C239BV

220UF 20%

2. TANT

2

7343

5V

45

BV_FILTERED_1P5_1P05

CAD NOTE:

1

C271BV

PLACE +NODE NEA R HIGH SIDE FET DRAIN

220UF

PLACE GND SIDE CLOSE TO LOW FET GND

20%

2.

5V

TANT

2

7343

BOM NOTE:

MOD TO 47UF-IPN:724613-076

3

62 64

OUT

2

MODULE REV DETAILS

MODULE NAME

SR_BV_CHR

3.26.01

1

REV

DATE

02-06-07

D

21%1

CH

V

2

1% CH

BV_1P05_RIPPLE_BST

C158BV

1

4700PF

L10BV

1.4UH 2

1

IND

BV_1P05_C

626364

50V X7 402

3.92K

IN

402

R

R106B

1

2

10%

1

2

OMP_R

V

2

1% CH

1

2

R108BV

0 5%

EM

PTY

402

A_GND_1P5

BOM NOTE:

MOD C158BV TO 0.022UF IPN A36096-089

C161B

1

V

10UF

20%

6.3V

2

X5R 805

R109BV

0 5%

CH 402

C160BV

1

2

1

2

R111BV

1.82K 1%

CH 402

R103BV

11K 1%

CH 402

1

10UF

20%

6.3V

2

X5R 805

1

C162BV

2

220UF 20%

2.5V TANT 7343

V_1P05_CORE

1

C140BV

220UF 20%

2.5V T

TAN

2

7343

810141516 17 18

OUT

71

77

C

23 293262

B

A

C

BOM NOTE:

MOD TO NTMS4706N (I PN: D80658-001)

Q22BV

FDS6681Z

8

DRN

7

DRN

6

R102BV

BV_1P05_UGATE_R

2

ATE

0

805

626364

1

R104BV

1

0

805

1A

CH

2

1A CH

IN

BV_1P05_LGATE_R

A_GND_1P5

BV_1P05_UGATE

62

IN

BV_1P05_PHASE

62

OUT

BV_1P05_LG

62

B

IN

62

BV_1P05_COMP

OUT

A

OUT

BV_1P05_FB

62

DRN

5

DRN

IC

4

G

1

2

3

MOD TO D23508-001 (BSC079N03S)

1

V

C155B

100.0PF 5% 50V

2

COG 603

S S S G

5

D

Q23BV

S

FET

BOM NOTE:

C154BV

1

2200PF

50V X7 402

10%

R

1

2

3

4

2

C82128-001

1

CR16BV MBRS130LT3 SM

PTY

EM

2

BV_1P05_C

OMP_C

3.74K 402

1

R107BV

2.2 5%

2

CH 805

BV_1P05_SN

1

C159BV

4700PF 20% 50V

2

X7R 603

R110B

392

402

R105BV

1

[PAGE_TITLE=VREG: 1.05V OUTPUT]

BPAGE DRAWING

tawas_b.sch_1.63

Wed Feb 07 17:19:12 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

63

2.0

1

CR-64 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE64

8

BV_FILTERED_1P5_1P05

6263

IN

D

CAD NOTE:

PLACE NEAR HIGH SIDE FET

7

1

C209BV

10UF 20% 25V

2

X5R 1206 1206

1

2

C132BV

10UF 20% 25V X5R

6

45

3

2

MODULE REV DETAILS

MODULE NAME

SR_BV_CHR

3.26.01

1

REV

DATE

02-06-07

D

BOM NOTE:

C

R115BV

IN

OUT

BV_1P5_UGATE

BV_1P5_LGATE

805

BV_1P5_PHASE

62

R116BV

1

0

1

0

2

805

1A CH

B

MOD TO D80668-001

2

BV_1P5_UGATE_R

1A

BV_1P5_LGATE_R

CH

Q24BV

STS8DNH3LL

1

S1

2

G1

3

S2

4

G2

D1 D1 D2 D2

IC

8 7 6 5

1

CR17BV MBRS130LT3 SM EMPTY

2

40.2K

R117BV

1

2. 5%

CH

2

805

BV_1P5_SN

1

2

C181BV

BV_1P5_C

2

OUT

BV_1P5_COMP

BV_1P5_FB

8

1

C180BV

56PF 5% 50V

2

COG

A_GND_1P5

626364

IN

603

7

62

A

62

820.0PF

1

10% 50V X7R 402

6

OMP_C

R113B

1K

402

1

BV_1P5_RIPPLE_BST

R112BV

1

2

1% CH

402

L23BV

3.8UH 2

IND

2

C179BV

4700PF 20% 50V X7R 603

V

BV_1P5_COMP_R

2

1%

CH

4700PF

1

3.24K

C178BV

1

50V X7R 402

R114BV

1

402

2

10%

2

1% CH

C182BV

V_1P5_CORE

C164BV

1

10UF

20%

6.3V

2

X5R 805

1

C175BV

220UF 20%

2.5V TANT

2

SM

1

10UF

20%

6.3V

2

X5R 805

OUT

81618

32 37 39

40 62

71

C

B

R118BV

1

R119BV

1

0 5%

EMPTY

2

402

IN

A_GND_1P5

626364

5

0 5%

CH

2

402

R120BV

1

6.65K 1%

CH

2

1

2

402

R121BV

10K 1%

CH 402

BPAGE DRAWING

tawas_b.sch_1.64

Wed Feb 07 17:19:13 2007

4 2

3

[PAGE_TITLE=VREG: 1.5V OUTPUT]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

64

1

REV

2.0

A

CR-65 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE65

8

6667

IN

BV_FILTERED_5P0_3P3

7

6

R122BV

1

2

3.3 5% CH

DESIGN NOTE: FIND 3.9 OHM PART

805

D

1

C194BV

1.00UF

20%

6.3V

1

R126BV

49.

9

1% CH

2

402

BV_5P0_CSENSE5

BV_5P0_PGOOD3

BV_5P0_VREF

A_GND_5P0

2

X5R 402

BV_5P0_VCC

BV_5P0_BOOT5

5P0_SHDN

BV_

2

CR18BV .4

5V

3

SOT23A DIO

2

65

R132BV

1

1M

402

1

2

1

IN

2

5% CH

BV_5P0_BOOT5_R

C188BV

UF

.1 10% 10V X5R 402

BV_5P0_LDO5

R143BV

1

249K

1%

2

CH 402

402

1

2

100K

BV_3P3_BST_R

65

OUT

C

6263666869 7374757677

OUT

66

69707576

66

78

61

26

70

71

55

BV_5P0_UGATE

BV_5P0_PHASE

IN

BV_5P0_LGATE

V_5P0_STBY_PWRGD

V_5P0_STBY\G

9263233

IN

BV_5P0_COMP

IN

INTERMEDIATE_BUS_POWER

IN

EN_SYS_PWR

IN

66

56

45

61

626668

77

7883

B

656667

R124BV

0

1A

CH 603

133BV

R

1

A_GND_5P0

IN

C189BV

1

2

.22UF

10% 10V X5R 402

R125BV

1

2

1%

2K

CH

402

R123BV

1

2

5% CH

5%CH100K

402

65

OUT

656667

IN

1

31

18

23

22

21

15

20

17

29

30

26

27

5

4

25

32

C187BV

.1UF 10% 10V X5R 402

R202BV

2.

40

5% CH

402

BV_5P0_LDO_COMP

1

C195BV

4.

7UF

20%

3V

6.

2

X5R 805

VCC

LDO5

BOOT5

HGATE5

PHASE5

LGATE5

CSENSE5

V5SW

OUT5

COMP5

PGOOD5

PGOOD3

SHDN

EN3 EN5

VREF

OPTION

1

C193BV

7UF

4. 20% 25V

2

X5R 1206

BV_5P0_LDO5

BOM NOTE:

IPN TOBEADDEDTOLIB

EU6BV

D79024-001

PM6685

REV=1

P

GOOD_LDO3

LDO

CENTER_PAD

1OF2

45

2

1

VIN

BOOT3

HGATE3

PHASE3

LGATE3

CSENSE3

PGND

SGND1

OUT3

COMP3

SGND2

LDO3

SKIP

FSEL

3_SEL

C196BV

0.

1UF

20%

16V Y5V 402

OUT

IC

65

19

9

10

11

13

12

14

1

8

2

16

6

7

24

3

28

33

BV_5P0_VIN

BV_3P3_BOOT3

BV_3P3_CSENSE3

V_3P3_KSC_PWRGD

BV_5P0_SKIP

A

A_GND_5P0

656667

IN

A_GND_5P0

1

2

R127BV

0

603

R205BV

0OHM

SM

402

R131BV

0 5%

EMPTY 402

3

1

EMPTY

R130BV

1

0

1A

CH

402

65 66

IN

BV_3P3_BST_R

2

R128BV

2

1

2KCH1%

2

R129BV

100K

402

1

2

5% CH

R155BV

1

0

402

1

C210BV

10UF 20%

6.3V X5R 805

5%

EMPTY

67

2

C184BV

.1UF 10% 10V

1

X5R 402

2

5% CH

BV_5P0_VREF

BV_5P0_LDO5

2

1

2

IN

BV_5P0_LDO5

V_3P3_KSC

C185BV

4.7UF 20%

6.3V X5R 805

2

65

BV_3P3_UGATE

BV_3P3_PHASE

BV_3P3_LGATE

V_3P3_STBY\G

BV_3P3_COMP

IN

1

MODULE REV DETAILS

MODULE NAME

SR_BV_CHR

65

R154BV

1

2.8K 1%

2

EMPTY 402

A_GND_5P0

65

REV

3.26.01

OUTOUT

67

IN

OUT

67 68 69 72 75 9

22 263132 33

IN

40 44 50 52 54 55 56

67

IN

OUT

IN

02-06-07

67

29 52 55 57 58 73 83

65 66 67

DATE

D

C

B

77

37

A

[PAGE_TITLE=VREG: 5V/3.3V CONTROLLER]

BPAGE DRAWING

tawas_b.sch_1.65

Wed Feb 07 17:19:14 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

65

2.0

1

CR-66 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE66

8

BOM NOTE:

DEFAULT STUFF W/ 0 OHM RESIST OR OPTIONAL STUFF W/ FB IPN: 651080-023

77

78

73

D

747576

INTERMEDIATE_BUS_POWER

26

61

626365

IN

686970

71

7

1

M29BV

1

MULTI

CH

1206

CAD NOTE:

PLACE BY HIGH SIDE FETS

CH

2

M28BV

MULTI

1

2

6

2

1206

1

C183BV

C190BV

10UF 20% 25V X5R 1206 1206

10UF 20% 25V

2

X5R

BV_FILTERED_5P0_3P3

1

C240BV

220U 20%

2.5V TANT

2

7343

CAD NOTE:

PLACE +NODE NEA R HIGH FET DRAIN

1

C274BV

220UF

F

2

PLACE GND SIDE CLOSE TO LOW FET GND

20%

2.5V TANT

BOM NOTE:

7343

MOD TO 47UF-IPN:724613-076

C

R206BV

2

D63704-001

Q27BV

FET

5

Q26BV

D

FET

4

S

G

1 2

3

C82128-001

1

R19BV

C MBRS130LT3 SM EM

PTY

2

MOD TO D77965-001 (BSC094N03S)

R134BV

1

0

805

2

1A CH

65

IN

OUT

BV_5P0_UGATE

BV_5P0_PHASE

65

B

IN

BV_5P0_LGATE

65

R135BV

1

0CH1A

805

2

BV_5P0_LGATE_R

BOM NOTE:

BV_5P0_UGATE_R

D18314-001 5

D

4

S

G

1

2

BOM NOTE:

3

MOD TO D23508-001 (BSC079N03S)

35.7K 402

1

R141BV

2.2 5%

2

CH 805

BV_5P0_SN

1

2

1

NC=3

C200BV

4700PF 20% 50V X7R 603

1% CH

L12BV

5UH

1

IND

2

45

BV_5P0_RIPPLE_BST

R209BV

1

6.

65K 402

C241BV

1

4700PF210%

50V X7R 402

1

2

65 67

OUT

2

1%

CH

MOD C241BV TO 0.01UF IPN A36096-037

C207BV

F

10U

20%

6.3V X5R 805

1

R208BV

0 5%

CH

2

402

R207BV

0 5%

EMPTY 402

1

2

BOM NOTE:

C208BV

10UF

20%

6.3V X5R 805

3

1

2

1

C198BV

220UF 20%

2.5V TANT

2

7343

2

MODULE REV DETAILS

MODULE NAME

V_

5P0_STBY\G

BOM NOTE:

TO BE STUFFED WITH T520V227M006ATE015

IPN: 724613-066

REV DATE

83 9263233456162

OUT

68 69 70 75 76

1

02-06-073.26.01SR_BV_CHR

D

C

65

77

78

B

C206BV

2

OUT

BV_5P0_COMP

7

1

C205BV

100.0PF 5% 50V

2

COG

IN

A_GND_5P0

6567

603

6

A

65

8

1500PF

1

50V X7R 402

BV_5P0_COMP_C

10%

5

R140BV

1

562 402

2

BV_5P0_COMP_R

1%

CH

[PAGE_TITLE=VREG: 5V STANDBY OUTPU T]

BPAGE DRAWING

tawas_b.sch_1.66

Wed Feb 07 17:19:16 2007

4 2

3

CONFIDENTIAL

CUSTOM TEXT BPAGE

INTEL

DOCUMENT_NUMBER

D89092

A

PAGE

REV

66

2.0

1

CR-67 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE67

8

6566

BV_FILTERED_5P0_3P3

IN

D

7

CAD NOTE:

PLACE BY HIGH SIDE FETS

1

2

C191BV

10UF 20% 25V X5R 1206

1

2

6

C192BV

10UF 20% 25V X5R 1206

45

3

2

MODULE REV DETAILS

MODULE NAME

1

REV

DATE

02-06-073.26.01SR_BV_CHR

D

BV_3P3_RIPPLE_BST

R212BV

2

4700PF

C242BV

1

50V X7 402

1

1%

5.6K CH

402

2

10%

R

C

B

1

2

R214BV

0 5%

EMPTY 402

1

2

C11BV

R215BV

0 5%

CH 402

V_3P3_STBY\G

1

10UF

20%

6.3V

2

X5R 805

C12BV

1

F

10U

20%

6.3V

2

X5R 805

1

2

C13BV

220U 20%

6.3V TANT 7343

F

BOM NOTE:

TO BE STUFFED WITH IPN: 724613-067 T520V227M004ATE015

9

222631

OUT

54 55 56 65 68 69 72 75

32

33 374044 50 52

77

Q2BV

FET

5

Q1BV

D

4

S

G

FET 1 2 3

C82128-001

1

CR14BV MBRS130LT3 SM EMPTY

2

1

2

1

2

R5BV

2.2 5%

CH 805

V_3P3_SN

B

C10BV

4700PF 20% 50V X7R 603

51.1K 402

R213BV

1

NC=3

1% CH

2

L1BV

1

3.1UH

2

IND

D68922-001

0

805

R2BV

1

805

R1BV

2

1

1A

0

CH

2

BV_3P3_LGATE_R

1A CH

BV_3P3_UGATE_R

D18314-001

5

D

4

S

G

1

BOM NOTE:

2

3

TO BE STUFFED WITH D23508-001 (BSC079N03S)

BV_3P3_UGATE

65

IN

OUT

IN

BV_3P3_PHASE

BV_3P3_LGATE

C

65

B

C3

BV

2

C4BV

100.0PF 5% 50V COG 603

820.0PF

1

10% 50V X7R 402

65

BV_3P3_COMP BV_3P3_COMP_C

OUT

1

2

IN

A_GND_5P0

6566

A

R8BV

BV_3P3_COMP_R

2

1

453

1%

CH

402

A

[PAGE_TITLE=VREG: 3.3V STANDBY OUTPUT]

BPAGE DRAWING

tawas_b.sch_1.67

Wed Feb 07 17:19:17 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

67

2.0

1

CR-68 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE68

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

SR_BV_CHR

3.26.01

1

REV

DATE

02-06-07

D

71

73

SLP_S3_NEW

6269

71

C

72

IN

1

2

78

R263BV

100K

5% EMPTY

402

626365666970

IN

747576

77

Q5BV

MBT3904DUAL

R12BV

BV_SW1_S3_N_R

2

1

5%

8.2K CH

402

5

26

61

B

INTERMEDIATE_BUS_POWER

R13BV

1

19.6K 1%

2

CH 402

BV_SW1_S3_R

R15BV

1

4.7K

3

4

5%

6

2

CH 402

2

BV_SW1_S3

XSTR

1

404450

2

1

R14BV

10K 5%

CH 402

323337

83 61

6265666970

33

45

7576

77

78

77

9

2226

31

525455566567697275

12

16

17

70

92632

IN

BV_SW1_S3_N_R2

V_3P3_STBY\G

IN

V_1P25_M

IN

V_5P0_STBY\G

1

C15BV

1UF 10% 16V

2

X5R 603

BOM NOTE:

TO BE STUFFED WITH D80661-001

Q8BV

FDS6681Z

8

DRN DRN DRN DRN

S S S G

7 6 5

IC

BOM NOTE:

TO BE STUFFED WITH D50757-001 (FDS8896)

Q9BV

FDS6681Z

8

DRN DRN DRN DRN

S S S G

7 6 5

IC

Q28BV

FDS6681Z

8

DRN DRN DRN DRN

S S S G

7 6 5

VCC

1 2 3

1

4

2

VCC3

1 2

1

3 4

2

V_1P25_CORE

1 2 3 4

C265BV

220UF 20%

2.5V TANT 7343

C264BV

220UF 20%

6.3V TANT 7343

BOM NOTE:

TO BE STUFFED WITH T520V227M006ATE015 IPN: 724613-066

BOM NOTE:

TO

BE STUFFED WITH IPN: 724613-067 T520V227M004ATE015

1216171832

OUT

71

D

C

B

IC

BOM NOTE:

TO BE STUFFED WITH NTMS4706N IPN: D80658-001

A

DESIGN NOTE:

INTERMEDIATE BUS POWER = 8.7V - 12.6V

[

PAGE_TITLE=VREG: RAIL SWITCHES 1 OF 2]

BPAGE DRAWING

tawas_b.sch_1.68

Wed Feb 07 17:19:19 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

68

2.0

1

CR-69 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE69

8

61

D

71

DESIGN NOTE:

AC PRESENCE DETECT

C

62636566686970

77

78

BV_3P3_CHG

557374

IN

1

R286BV

5%

2

EM 402

100K

7

INTERMEDIATE_BUS_POWER

26

IN

73747576

S4_STATE_N

31

IN

Q60BV

MBT3904DUAL

R260BV

2

1

4.7K

5% CH

402

PTY

BV_3P3_G_N

72

5

BV_AND_GATE

71

6268

3

4

IN

6

2

6

2

XSTR

1

SLP_S3_NEW

1

4_STATE_R S

R259BV

1K 5%

CH 402

B

V_SW2_S4_N

BV_SLP_S3_N_R

1

R254BV

8.2K 5%

2

CH 402

R285BV

1

100K 5%

EMPTY

2

402

R257BV

R258BV

1

2

BV_SW2_S4_R

4.7K

5% CH

402

Q61BV

MBT3904DUAL

45

61

62656668

1

R255BV

10K 5%

CH

2

1

20K

5% CH

402

5

402

2

3

6

2

BV_SW2_S4_GT

XSTR

4

1

45

V_5P0_STBY\G

9263233

IN

707576777883

BV_SW2_S4_R2

1

C262BV

F

R256BV

4.

7K

402

2

1

5% CH

1U 10%

25V

2

X5R 603

3

BOM NOTE:

TO BE STUFFED WITH D80661-001

Q59BV

FDS6681Z

8

DRN

7

DRN

6

DRN

5

DRN

IC

VCC_USB

1

S

2

S

3

S

4

G

OUT

2

MODULE REV DETAILS

MODULE NAME

SR_BV_CHR

54 7

382

3.26.01

1

REV

DATE

02-06-07

D

C

26

61

71

62636566686970

737475767778

B

DESIGN NOTE:

DEFAULT STUFF R152BV

DO NOT STUFF BOTH

EC_3P3M_CTRL

55

IN

R210BV

19.6K 1%

CH 402

1

IN

SLP_M_N

BV_SW2_AUDIO_PFET_G

3

Q53BV

MMBT3904 XSTR

2

72

61

62636566686970

26 71

77

78

A

73747576

INTERMEDIATE_BUS_POWER

IN

22

1

31

5670

71

2

R211BV

3137

557275

SLP_S3_N

1826

IN

1

R287BV

100K

5%

2

EMPTY 402

8

BV_SW2_S3_R

2

1

5%

8.2K CH

402

7

402

R152BV

402

BOM NOTE:

TO BE STUFFED WITH

FDN360P D43720-001

INTERMEDIATE_BUS_POWER

IN

EC_3P3M_EN

OU

T

R264BV

1

2

5%

0

EMPTY

2

1

5%

0

CH

2

G

S

1

D

3

6

R261BV

8.2K 402

1

R265BV

100K 5%

EMPTY

2

402

PMOSFET Q46BV

Q29BV

MBT3904DUAL

5

1

2

BV_MCTRL_G

5% CH

5

R149BV

1

19.6K 1%

CH

2

402

3

4

V_AUDIO

BV_SW2_SM_N

6

XSTR

1

2

404450

R151BV

1

4.7K 5%

CH

2

402

R150BV

4.7K 5%

CH 402

BV_SW2_SM_N_G

45

OUT

BV_SW2_SM_R2

4 2

77 222631323337 525455566567687275

9

IN

V_3P3_STBY\G

BOM NOTE:

TO BE STUFFED WITH

TMS4706N IPN: D80658-001

N

Q21BV

FDS6681Z

8

DRN DRN DRN DRN

S S S G

7 6 5

1 2

V_3P3_M

3 4

IC

1

C216BV

1UF 10% 25V

2

X5R 603

[

PAGE_TITLE=VREG: RAIL SWITCHES 2 OF 2]

BPAGE DRAWING

tawas_b.sch_1.69

Wed Feb 07 17:19:20 2007

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

OUT

1

C263BV

220U

F

20%

6.3V TANT

2

7343

BOM NOTE:

TO BE STUFFED WITH IPN: 724613-067 T520V227M004ATE015

PAGE

69

1

71

72 83 192031 35 39

46

REV

2.0

32

47 48

B

33

A

CR-70 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE70

8

767778

71

6869

61

62

26 636566 737475

INT

IN

ERMEDIATE_BUS_POWER

D

77

78

6869 61

62

33

45

6566 7576 83

C

70

72 56 22

31 69 70

6970

71

22

31

72

56

17

71

72

12

16 68 70

B

92632

IN

BV_1P25_REF

IN

BV_1P25_AVDD

IN OUT

SLP_M_N

IN

SLP_M_N

IN

V_1P25_M

IN

70

V_5P0_STBY\G

1

2

1

2

IN

1

C16BV

1. 10% 16V

2

X5R 805

R147BV

78.7K 1%

CH 402

R148BV

100K 1%

CH 402

A_GND_1P25

0UF

1

2

100K

402

BV_1P25_VTT_FB

R17BV

100K

402

R24B

0OHM

EMPTY SM

R25BV

5% CH

V

220PF

7

BV_1P25CORE_R

5% CH

BV_1P25_VTT_PWROK

C

37BV

1

2

BV_1P25_SS

10%

50V

EMPTY

402

C38BV

2

1

1U

10%

F

6.3V

EMPTY

402

6

BOM NOTE:

DEFAULT STUFF W/ 0 OHM RESIST OR OPTIONAL STUFF W/ FB IPN: 651080-023

M15BV

1

MU

CH

EU

1BV

ISL88550A

17

VIN

1

TON

2

OVP/UVP

27

SHDNA*

7

STBY*

5

POK1

15

FB

6

POK2

28

TP0

8

SS

REV=1

1

LTI

1206

UGATE PHASE

LGATE

PGND1

SKIP*

REFIN

PGND2

1OF1

CH

2

BOOT

VD

ILIM

OUT

GND

AVDD

REF

VTTS

VTT

VTTI

VTTR

GND

1

2

1

2

M16BV

MULTI

1

2

D

IC

R145BV

649

1%

CH 402

R146BV

13K 1%

CH 402

1206

C27BV

4.7UF 20%

6.3V X5R 805

2

18 19 20 21 22 23

4

25

16

24 26

3

BV_1P25_VTTS

9 12 13 14

10 11

29

BV_1P25_UGATE

BV_1P25_BOOT BV_1P25_LGATE

BV_1P25_ILIM

A_GND_1P25 BV_1P25_AVDD

BV_1P25_VTTR

1

C33BV

1UF 1UF 10%

6.

2

X5R 402

3V

INTERMEDIAT E_FILTERED_1P25

1

C34BV

4.7UF

1206

20% 25V X5R

OUT

1

2

CAD NOTE:

PLACE CLOSE TO FET

R16BV

1

0CH1A

805

R18BV

1

603

R19BV

1

0

805

70

C31BV

10%

6.

3V X5R 402

C35BV

4.7UF 20% 25V X5R

1206

2

BV_1P25_BOOT_R

5% CH

2

1A CH

1

2

BV_1P25_UGATE_R

BV_1P25_LGATE_R

C215BV

4.7UF

EMPTY

20% 25V

1206

A_GND_1P25

45

1

2

STS8DNH3LL

1 2 3 4

C29BV

2

22UF

10%

.

10V X7R 603

1

C269B

V

.1UF 10% 10V

2

X5R 402

A

_GND_1P25

1

2

BV_1P25_REF

Q11BV

S1 G1 S2 G2

B

V_1P25_PHASE

1

R20BV

1

82.5K 402

C30BV

.1UF 10% 10V X5R 402

R21BV

1

100K

402

OUT

8

D1

7

D1

6

D2

5

D2

IC

C82128-001

1

CR20BV MBRS130LT3 SM DIO

2

1%

CH

2

1% CH

70

3

1

C272BV

470UF 20%

6.3V TANT

2

7343

BOM NOTE:

MOD TO D80668-001

70

OUT

R23BV

1

2

2. 5%

70

OUT

1

2

R22BV

182K 1%

EMPTY 402

CH

2

805

BV_1P25_SN

1

C32BV

4700PF 20% 50V

2

X7R 603

CAD NOTE:

PLACE NEAR DRAIN AND SOURCE OF FET

CAD NOTE:

PLACE +NODE NEAR HIGH-FET DRAIN PLAC CLOSE TO LOW-FET GND

1

C36BV

470UF 20%

6.

3V

TANT

2

7343

BOM NOTE:

MOD IN 47UF-IPN:724613-076

L3BV

5UH

2

1

IND

A

C39BV

10UF 20%

6.3V X5R 805

1

C40BV

10UF 20%

6.3V

2

X5R 805

1

2

E GND SIDE

2

MODULE REV DETAILS

MODULE NAME

SR_BV_CHR

3.26.01

1

REV

DATE

02-06-07

D

C

V_1P25_M

1

C24BV

C25BV

10UF

10U 20%

20%

6.3V

2

X5R

805

C26BV

220UF 20%

F

2.50V TANT

2

SM

OUT

16 17

68 70

12

B

V_1P05_M

OUT

14

A

CAD NOTE:

PLACE AT THE OUTPUT OF THE REGULATOR

BPAGE DRAWING

tawas_b.sch_1.70

Wed Feb 07 17:19:21 2007

8

7

6

5

4 2

3

[PAGE_TITLE=VREG: V_1P25_M\V_1P05_M]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

1

PAGE

70

REV

2.0

CR-71 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE71

8

INTERMEDIATE_BUS_POWER

7374757677

61

626365

26

IN

D

66686970

78

R167BV

1

0

603

VCC

IN

V_1P25_CORE

VCCP

SLP_S3_NEW

D

1

S

G

2

12

16

17

1832

68

8

7879

C

626869 72

EMPTY

3

2

BV_DISCH_IBP_D

1A

Q33BV BSS138N

FET

7

CR23BV

2

1

BV_DISCH_SLP_S3

R169BV

1

1M 1%

2

CH 603

BOM NOTE:

MOD TO A93539-021

3

BAT54C

SOT23C

DIO

1

2

C222BV

22.0UF 20%

16V ALUM 5MM

6

BV_DISCH_IBP

R168BV

1

100K

5%

2

CH 603

71

32 15

71

77

1

G

16 18

3237

39 40 6264

2329 1014 16

1718

6263

1

R171BV

47. 1%

2

CH 603

3

BV_DISCH_VCCP

D

S

2

8

IN

8

IN

5

Q35BV BSS138N

FET

V_1P5_CORE

V_1P05_CORE

1

G

1

BOM NOTE:

2

MOD TO NFET

5

IPN = D90007-001;(ON SEMI NTGS3446)

6

D

4

9

Q36BV BSS1

FET

SI3441

FET

S

38N

3

G

R172BV

1

90. 1%

CH

2

603

BV_DISCH_5P0

3

D

S

2

Q70BV

45

1

G

R173BV

1

470 5%

CH

2

603

BV_DISCH_1P25

3

D

Q37BV BSS138N

FET

S

2

3

1

R298BV

100K 5% CH

2

603

22

31

56697072

R180BV

1

100K 5%

2

CH 603

BV_DISCH_SLP_S4

3

D

Q34BV BSS138N

1

FET

S

G

2

1

2

R170BV

1M 1%

CH 603

2

BV_DISCH_SLP_M

SLP_M_N

IN

20

31

32 46

MODULE REV DETAILS

MODULE NAME

REV

3

D

Q68BV BSS138N

1

47486972 19

IN

333539

83

FET

S

G

2

V_3P3_M

1

G

1

2

1

R299BV

100 1%

2

CH 603

BV_DISCH_V_3P3_M

3

D

Q69BV BSS138N

FET

S

2

1

R300BV

1M 1%

CH 603

DATE

02-06-073.26.01SR_BV_CHR

D

C

B

16

71

31

55

61

20

61

19 11

12

14

15

16

17

2161

1575

14 76

71

32

37

39

4062

17

182329

32

6263

77

A

SLP_S4_N

IN

V_SM

IN

V_SM_VTT

IN

V_GFX

IN

64

V_1P5_CORE

81618

IN

V_1P05_CORE

8101415

IN

8

VCC3

1

R174BV

220 5%

2

CH

3

D

1

S

G

2

603

BV_DISCH_V_SM_VT T

Q

38BV

BSS138N

FET

[PAGE_TITLE=VREG: DISCHARGE CIRCUITRY]

CONFIDENTIAL

CUSTOM TEXT BPAGE

1

G

R179BV

1

150

5% CH

2

603

BV_DISCH_GFX

3

Q43BV

D

BSS138N

FET

S

2

BPAGE DRAWING

tawas_b.sch_1.71

Wed Feb 07 17:19:24 2007

3

R178BV

1

90.

G

9

1%

CH

2

603

BV_DISCH_3P3

3

D

Q42BV BSS138N

FET

S

2

4 2

R177BV

1

47.5

1

G

1%

2

CH 603

BV_DISCH_1P5

3

D

Q41BV BSS138N

FET

S

2

1

5

R176BV

1

470 5%

CH

2

603

BV_DISCH_1P05

C81974-001

7

3

Q40BV

D

BSS138N

1

FET

S

G

2

6

1

G

INTEL

R175BV

1

68 5%

2

CH 603

BV_DISCH_V_SM

3

D

Q39BV BSS138N

FE

T

S

2

DOCUMENT_NUMBER

D89092

PAGE

71

1

REV

2.0

B

A

CR-72 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE72

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

1

REV

DATE

02-06-073.26.01SR_BV_CHR

D

404450

75

404450

525455566567686972

77 2226

31

3233

37

C

IN

61

IN

BV_1P25_VTT_PWROK

V_SM_PWRGD

71

70 72

B

A

71

83

69

31

3233

464748

V_3P3_M

1920

IN

3539

R282BV

402

R262B

1

0

402

566970

R307BV

1

8.2K 402

2

1

0

5% CH

V

2

BV_INT_SEL

5% CH

22

31

IN

404450

2

5% CH

1

2

SLP_M_N

1

2

R308BV

4.7K 5%

CH 402

R277BV

1

10K

402

R288BV

100K 5%

EM

PTY

402

7577

9

222631323337 525455566567686972

R279BV

1

330

402

V_3P3_STBY\G

9

IN

MBT3904DUAL

2

BV_CLPWROK_1P25_VSM_R

5% CH

R278BV

2

1

10K

5% CH

402

V_3P3_STBY\G

IN

MBT3904DUAL

EC_EN_G_R

2

5% CH

1

C267BV

2.2UF 10%

6.3V

2

X5R 603

1

R253BV

10K

5% CH

2

402

Q62BV

BV_GATE_R1

1

R273BV

10K

5%

2

CH 402

Q64BV

5

1

2

BV_CLPWROK_1P25_VSM

3

461

XSTR

1

R274BV

10K

5%

2

CH 402

BV_CLPWROK_3P3M_EN

3

4612XSTR

R272BV

10K

5% CH

402

1

BV_CLPWROK_SLP_M_N

2

25

1

2

BV_CLPWROK_CR_R

1

2

D1BV

SOT23_C

D2BV

SOT23_C BAT54

10K 402

C280BV

2.2UF 10%

6.3V

X5R 603

3

DIO

BAT54C

DIO

C

R275BV

1

3

2

5% CH

BV_CLPWROK_CR

CLPWROK

1

R276BV

47K 5%

CH

2

402

7072

OUT

BV_1P25_VTT_PWROK

IN

123172

BV_PW

525455566567686972

ROK_AND

7577 2226

31

323337

9

IN

R302BV

1

8.2K5% 402

V_3P3_STBY\G

MBT3904DUAL

2

BV_PWROK_R

CH

R301BV

1

1K 5%

2

CH 402

BV_V_3P3_STBY_R

Q71BV

3

52

6

BV_SLP_S3_N_OR_CLPWROK

4

1

XSTR

SLP_S3_NEW

1

R303BV

10K 5%

CH

2

402

R304BV

8.2K 402

OUT

R305BV

2K

8. 402

1

25%1

CH

EMPTY

62 68 69

2

5%

71

SLP_S3_N

CLPWROK

R306BV

2

1

5%

0

EMPTY

402

IN

D

75 55 31 18 26 37 69

C

72 12 31

B

A

BPAGE DRAWING

tawas_b.sch_1.72

Wed Feb 07 17:19:25 2007

8

7

6

5

4 2

3

[PAGE_TITLE=VREG: POWER GOOD FOR CLPWROK

PAGE

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

REV

72

2.0

1

D

C

B

56

A

J5BV

1X9HDR2MTG

HDR

BOM NOTE:

IPN D81515-001

SR_IBP_GFX

CR-73 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE73

8

V_MAIN_PWR_IN

73

IN

USE 1K RESISTOR IPN A93555-049

V_PR_PWR_IN

83

IN

IBP_BATT_MON

73

IN

R266BV

20K

5% CH

402

Q63BV

IN

MBT3904DUAL

R271BV

2

1

2K

5%

8. CH

402

1

2

V_3P3_KSC

R240BV

1

100K

5%

2

CH 603

1

2

52

BATT_P_E

R289BV

100K

5% CH

402

R236BV

1

10K

5%

2

CH 805

R238BV

10K

5% CH

805

BATT_PRTCT_EC

IN

29525557 586583

1

BV_BC_BATTP

2

BATT_CHGA

3

4

BATT_DISA

5

SMB_BAT1_CLK

6

SMB_BAT1_DATA

7

BATT_THERMAL1

8 9

10 11

MPN: ALLTOP C144B6-10901

8

7

BOM NOTE:

MOD L26BV AND L28BV TO LF PART 651080-023

L26BV

1

2

BV_BC_V_PR_PWR_IN_1

1

C257BV

10U

F 20% 25V

2

X5R

1206

1

L28BV

FB

2

FB

BOM NOTE:

FOR R235BV AND R241BV

BOM NOTE:

MOD L27BV & L29BV TO 651080-023 (LF)

L27BV

1

2

FB

1

L29BV

1

2

FB

R270BV

1

7K

4. 402

IN IN IN IN

OUT

2

5% CH

56 56 52 55 52 55

56

2

1

2

1

2

3

4

R239BV

10K

5% CH

805

1

2

1

2

R267BV

10K 5%

CH 402

BATT_P_EC_N_R

6

XSTR

1

R237BV

10K 5%

CH 805

1

2

BATT_PRTCT_EC_B

BATT_P_EC_N

C255BV

1UF 10%

10V X5R 805

7

6

1

C258BV

.1UF 20% 50V

2

X7R 805

C254BV

10UF 20% 25V X5R 1206

OU

T

BOM NOTE:

MOD TO FDS6675BZ IPN: D 80662-001

BV_BC_R_TO_D_2

BV_BC_R_TO_D_1

1

C256BV

.1UF 20% 50V

2

X7R 805

73

8 7 6 5

R235BV

1

10K

5%

2

CH 805

R241BV

1

10K

5% CH

2

805

Q32BV

FDS6681Z

DRN DRN DRN DRN

IC

6

1.0UF

CR29BV

2

1

C295BV

16V X5R 805

R242BV

1

270K

402

BAT54C SOT23_C DIO

55697374

OUT

10%

1

S

2

S

3

S

4

G

2

1%

CH

1

2

1

2

3

CR28BV DIO

0.225W

3.3V

1

BV_BC_V_MAIN_PWR_IN_1

BV_3P3_CHG

73

74

OUT

BV_BC_CSSN

R162BV

0

1

5%

CH

402

2

IBP_BATT_MON

BATT_PRTCT_EC_B

1

C266BV

2.2UF 10%

6.3V

2

X5R 603

BV_BC_ENIN_2

R243BV

10K 1%

CH 402

BV_BC_VIN_1

R246BV

10K 1%

CH 402

R160BV

1

0.01 2010

5

BOM NOTE:

MOD TO D78080-001

1

2

74

OUT

BV_BC_CSSP

163BV

R

0

1

5%

CH

2

402

2

1%

CH

IN

EU

ADM1087

1

ENIN*

2

GND

3

VIN

REV=1

EU12BV

ADM1087

1

ENIN*

2

GND

3

VIN

REV=1

BV_BC_VIN_2

R244BV

270K

1%

BOM NOTE:

CH 402

MOD T O 280K IPN: A93548-487

INTERMEDIATE_B US_POWER

73

45

R234BV

1

100K

603

6

5

4

ENOUT_1

BV_BC_CEXT_1

11BV

ENOUT*

1O

VCC

CEXT

F1

IC

6

VCC

5

CEXT

ENOUT*

1OF1

R245B

1

1%

10K

CH

402

V

2

BV_BC_CEXT_2

4

IC

R233BV

1

100K

603

ENOUT_2

Q58BV

FDS6681Z

8

DRN

7

DRN

6

DRN

5

DRN

IC

BOM

MOD TO FDS6675BZ PFET IPN: D 80662-001

NOTE:

OUT

1

S

2

S

3

S

4

G

26

61

74 75 767778

62 63 65 66 68 69 70

3

2

5% CH

FDS6681Z

8 7 6 5

BV_3P3_CHG

2

5% CH

Q56BV

FDS6681Z

8

DRN

7

DRN

6

DRN DRN

IC

BV_POWER_IN_ISO_FET

Q57BV

DRN DRN DRN DRN

IC

1

C253BV

.1UF 10%

10V X5R 402

C252BV

.1UF

10%

10V X5R 402

S S S G

71

MOD TO FDS6675BZ PFET

IPN: D80662-001

1

S

2

S

3

S

4

G

BOM NOTE:

1 2 3 45

BOM NOTE:

MOD TO FDS6675BZ PFET IPN: D80662- 001

BOM NOTE:

MOD L30BV & L31BV TO 651080-023 (LF)

2

FB

2

FB

L30BV

L31BV

[PAGE_TITLE=VREG: BATTERY CHARGER PAGE 1OF 2]

BPAGE DRAWING

tawas_b.sch_1.73

Wed Feb 07 17:19:27 2007

4 2

3

CONFIDENTIAL

CUSTOM TEXT BPAGE

2

73

546982

IN

1

BV_CONN_FB_GND

1

INTEL

MODULE REV DETAILS

MODULE NAME

SR_IBP_GFX

DESIGN NOTE:

Q56BV,Q57BV,Q58BV NEED SO8 PFET SYMBOL ??

BRICK_DC_IN

V_MAIN_PWR_IN

OUT

VCC_USB

TP_NVDC2_FD

TP_AGND_NVDC2

DOCUMENT_NUMBER

12 11 10

9 8 7 6 5 4 3 2 1

D89092

OUT

IN

1X12HDR

74

55

HDR

IO IO IO IO IO IO IO IO IO IO IO IO

J3BV

BOM NOTE:

D77261-001

1

REV

69 73 74

REV=1

DATE

02-02-0702.00.00

D

C

B

A

PAGE

REV

73

2.0

1

SR_IBP_GFX

CR-74 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE74

8

74

IN

56

IN

A_GND_CHARGER

IN

BRICK_DC_IN

BV_3P3_CHG

VCHRG

R199BV

015%

402

56

EMPTY

IN

2

1

C238BV

.47UF 10%

6.3V

2

EMPTY 402

R191BV

1

0OHM

2

EM

PTY

SM

ICHRG

73

D

73 55 69

C

74

B

7

BRICK_DC_IN_SENSE

1

R314BV

0 5%

2

CH 402

1

R225BV

0.01 2010

R195BV

1

2

2K

5%

EMPTY

402

R311BV

2

1

5%

2K

CH

402

C290BV

2

1

.1UF

10%

16V X7R 603

74

IN

R313BV

2

1

0

5% CH

402

74

A_GND_CHARGER

IN

DESIGN NOTE:

FOR 3A CHARGE CURRENT AT 10MOHM SENSE RESISTOR SET VOLTAGE AT CHLIM PIN TO 0.6V

DESIGN NOTE:

FOR 10A INPUT CURRENT LIMIT AT 10MOHM SENSE RESI STOR SET ACLIM PIN EQUAL TO VREF

1

2

A_GND_CHARGER

1

R322BV

3.32K 1%

EM

2

PTY

402

R321BV

1

3.32K

1%

2

EMPTY 402

1

2

1

2

R312BV

25.5K 1%

CH 603

R320BV

10.0K

0.1% CH

402

R319BV

3.32K

1% CH

402

1% CH

2

1

2

R315BV

0 5%

CH 402

1

2

6

SYSPWRIN_SENSE

C225BV

10UF 20% 25V X5R

1206

1

2

1

2

OUTOUT

CR31BV

1N

1

SOT23 DIO

R318BV

0 5%

CH 402

R317BV

3.32K 1%

EMPTY 402

4148

74

3

EN

SYSPWRIN

BV_BC_DCIN

25 27 28

19

20

C270BV

25V X5R 603

DCIN ACSET DCSET

1

EN

2

CELLS

6

VREF

9

VAD

J

7

CHLIM

8

ACLIM

CSIP CSIN

A_GND_CHARGER

74

IN

2

A_GND_CHARGER

10%11UF

EU8BV

ISL6257

R

EV=1

OUT

IN

SGATE

ACPRN DCPRN

UGATE PHASE LGATE

VCOMP ICOMP

BGATE

1

VDD

VDDP B

OOT

PGND

CSOP CSON

AGNDAGND

C281BV

74

1UF

25V X5R 603

FB

IC

2

10%

TP_SGATE_6257

45

R325BV

1

100K

402

R326BV

1

100K

402

BV_ACPRN

18

26 23 24

BV_VDDP

13 14

BV_BOOT

15 16 12 11

BV_BC_FB

5

BV_BC_VCOMP

4

BV_BC_ICOMP

3

BV_BC_CSOP

21 22 17

TP_BGATE_6257

2910

2

1%

EM

PTY

2

1%

EMPTY

B

V_DCPRN

BV_VDD

1

2

BV_BC_DRVL

2

C282B

1UF 10%

25V

1

X5R 603

R327BV

4.

7

5% CH

805

C294BV

2

1UF

25V X5R 603

1

10%

1

V

2

R323BV

1

2.20 5%

2

CH 402

1

C248BV

10UF 20% 25V

2

X5R 1206

BV_BC_DRVH

CR30BV

2

3

1

402 BAT54C SOT23C DIO

BV_PHASE_IBP

R324BV

C285BV

1

25%1

220K

1000PF

CH

402

C284BV

.027UF 10%

16V X7R 603

A_GND_CHARGER

BV_BC_CSSP

3

R316BV

1

0

50V X7

R

402

IN

10%

2

5% CH

2

74

C283BV

1

1UF 10%

.

16V X7R 603

1

C286BV

470PF

50V

2

X7R 402

C287BV

1

3.01K 1%

2

CH 402

4

G

2

4

G

10%

IN

2

BOM NOTE:

M

OD TO D77965-001

(BSC094N03S)

5

D

Q45BV

S

FET

1 2 3

5

D

S

FET

1

Q47BV

2

3

BOM NOTE:

MOD TO D23508-001 (BSC079N03S)

1

C293BV

1.4 1%

2

EMPTY

1206

BV_BC_CSSN

73

MODULE REV DETAILS

MODULE NAME

SR_IBP_GFX

L22BV

5UH

2

1

INTERMEDIATE_BUS_POWER

NC=3

1

2

1

2

IND

C292BV

1.4 1%

EMPTY 1206

C291BV

.1UF 10% 50V EM

PTY

805

1

2

1

C275BV

2

220UF 20%

2.5V TANT 7343

C227B

10% 16V

X5R

1206

1

REV DATE

02.00.00 02-02-07

76 68 69 70 26

OUT

63 65 66

C228BV

10UF10UF 10% 16V

X5R

1206

220U 20%

2.5V TANT 7343

71

F

1

V

2

1

C276BV

2

BOM NOTE:

MOD TO 724613-076

73

IN

77

61

73 75

D

78

62

C

B

C288BV

BV_BC_CSIN

2

BRICK_DC_IN _SENSE

74

IN

A

SYSPWRIN_SENSE

74

IN

8

7

1

10%

.1UF

10V X5R 402

C289BV

2

1

1%

16.5 CH

402

BPAGE DRAWING

tawas_b.sch_1.74

Wed Feb 07 17:19:28 2007

6

5

4 2

[PAGE_TITLE=VREG: BATTERY CHARGER PAGE 2 OF 2]

INTEL

CONFIDENTIAL

3

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

74

1

REV

2.0

A

SR_IBP_GFX

CR-75 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE75

8

45

61

626566

77

7883

9263233

IN

68697076

V_5P0_STBY\G

7

D

77

6972 50525455 2226

31

32

33

37

4044

56656768

C

263137

5569

BOM NOTE:

MOD R31BV TO A93548-418 (324KOHM 1%)

75

B

77

78

71

A_GND_GFX

IN

737476

61

626365

26

IN

66686970

56

IN

A

V_3P3_STBY\G

9

IN

12

IN

SLP_S3_N

18

IN

72

R31BV

1

340K

1%

2

CH 402

INTERMEDIATE_BUS_POWER

GFX_PMON_OUTPUT

INT_GFX_ENABLE

75

BOM NOTE:

MOD R36BV TO

93548-259

A (402KOHM 1%)

R36BV

1

2

1%

40.2 CH

402

R34B

1

402

A_GND_GFX

IN

75

IN

R156BV

1

10K

5% CH

2

402

BOM NOTE:

DEFAULT:

FOR FAB A STUFF R268BV

R269BV

2

1

0

5%

PTY

EM

402

R268BV

1

0

402

15

71

75

R30BV

1

C44BV

200K 1000PF 10% 50V

2

R

X7 402

BV_GFX_RAMP_R

CH

402

1

2

V

2

1%CH1K

2

A_GND_GFX

75

INT_GFX_EN_R

2

5% CH

14

IN

76

1%

C43BV

100P

F 5% 50V COG 402

1

2

IN

GFX_PWRGD

V_GFX

1

R33BV

118K 1%

CH

2

402

C42BV

2.2UF 10%

3V

6.

X5R 603

1

2

A_GND_GFX

12

IN

14

R161BV

1

1K 1%

CH

2

402

R32BV

2

1

1%

200K

CH

402

R159BV

0OHM

EMPTY SM

6

1

2

1

2

C41BV

10UF 20%

3V

6. X5R 805

1

C51BV

.1UF 10% 10V

2

X5R 402

G_VID<3..0>

1

C50BV

150PF 5% 50V

2

COG 402

1

2

STUFF FOR PROPER MONITORING CAPABILITY

A93548-418 (324KOHM 1%)

BV_GFX_DELAY_PWRGD

R38BV

200K 1%

PTY

EM 402

BOM NOTE:

0 1 2 3

BV_GFX_RT

BV_GFX_RPM

BV_GFX_VRPM

BV_GFX_RAMP

BV_GFX_CLIM

BV_GFX_PMON

BV_GFX_PMONFS

BV_GFX_ST

1

C49BV

680PF

10%

50V

2

X7R 603

R26BV

10

5% CH

603

BOM NOTE:

IPN TOBEADDEDTOLIB D31112-001

29 28 27 26 25

24

BV_GFX_VCC

30 31 32

16 15 14 13

BV_GFX_SS

1

C48BV

.01UF 10% 25V

2

X7R 402

8 6 7 5 4

EU7BV

ADP3209

REV=1 VID0 VID1 VID2 VID3 VID4

VCC

EN PWRGD PG

DLY

RT RPM VRPM RAMP CLIM PM

ON PMONFS ST SS

CENTER_PAD

PVC

DRVH

DRVL PGND

COMP

FBRTN

CSSUM CSREF

SCCOMP

LLINE

75

OU

BST

GND

C

SW

FB

IC

T

1

C52BV

4.7UF 20%

6.3V

2

X5R 805

20 23 22 21

19 18

17 3

2 1

12 11 10 9

33

A_GND_GFX

45

BV_GFX_BST

BV_GFX_DRVH

BV_GFX_PHASE

BV_GFX_DRVL

BV_GFX_COMP

BV_GF

X_FB

BV_GFX_FBRTN

BV_GFX_CSSUM

BV_GFX_SCCOMP

BV_GFX_LLINE

1

2

1

2

BOM NOTE:

STUFF 0 OHM FOR 8M OHM LOADLINE (324KOHM 1% ??)

1

2

R47BV

0 5%

EMPTY 402

R48BV

0 5%

CH 402

C55BV

1000PF

10% 50V X7R 402

C220BV

1000P

3

76

OUT

76

OUT

76

OUT

76

OUT

C47BV

22PF

5% 50V COG 402

2

F

10%

50V

1

X7R 402

1

2

BOM NOTE:

BEST TIMING FOR 8M OHM LOADLINE PULSE INDUCTOR

R42BV

2

1

BV_GFX_COMP_R

2

20K

1%

CH

402

1

R158BV

2

1

1% CH

603

BV_GFX_VREG_CNTL_CSREF

1

C56BV

1000PF

2

10% 50V X7R 402

R157BV

1

15K

1%

EMPTY

402

A_GND_GFX

R45BV

1

1%

178K

CH

603

C57BV

2200PF

10% 50V X7R 402

C46BV

1

2

10%

470PF

50V

X7R 402

2

BV_GFX_FBRTN_VSS

BV_GFX_RT2BV_2

2

OUT

2

MODULE REV DETAILS

MODULE NAME

SR_IBP_GFX

R41BV

V_GFX

1

2

1%

1K

CH

402

C45BV

1

2

CAD NOTE:

10%

220PF

PLACE NEAR GFX CHIP VSS PIN

50V X7R 402

1

R181BV

20K 603

R46B

35.7K 1%

CH 402

R44BV

1

V

0OHM

2

EMPTY SM

2

1%

CH

75

76

1

2

BV_GFX_PWM_SENSE

CAD NOTE:

PLACE THERMISTOR CLOSE

2

TO NEAREST INDUCTOR

RT2BV THRMSTR

1

REV

14

OUT

BOM NOTE:

MOD R T2BV TO C14407-003

DATE

02-02-0702.00.00

157175 76

76

OUT

D

C

B

A

BPAGE DRAWING

tawas_b.sch_1.75

Wed Feb 07 17:19:30 2007

8

7

6

5

4 2

3

[PAGE_TITLE=VREG: V_GFX CONTROLLER]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

75

2.0

1

SR_IBP_GFX

CR-76 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE76

8

7374757677

INTERMEDIATE_BUS_POWER

26

61

626365

IN

71

45

D

66686970 78

6869707577

V_5P0_STBY\G

9263233

IN

61

626566

7883

BV_GFX_BST

75

IN

BV_GFX_DRVH

BV_GFX_PHASE

75

603

R50BV

1

0

CH

7

2

1A

1

CH

BAT54C SOT23C DIO

BV_GFX_BST_R

M19BV

MULTI

CR4BV

1

2

1206

3

2

C59BV

1UF

10% 25V X5R 603

2

M20BV

1

MU

CH

C

75

BV_GFX_DRVL

IN

LTI

6

2

BOM NOTE:

DEFAULT STUFF W/ 0 OHM RESIST OR

1206

OPTIONAL STUFF W/ FB IPN: 651080-023

C70BV

1UF

10% 25V X5R 603

GFX_INTERMEDIATE_F ILTERED

CAD NOTE:

PHASE RESISTORS: PLACE ALL 0 OHM GATE RESISTORS CLOSE TO FET

D38953-001 (BSC059N03S)

45

76

OUT

Q14BV

FDS6681Z

8

DRN

7

DRN

6

DRN

5

DRN

BOM NOTE:

STUFFED WITH NTMS4706N

IPN: D80658-001

4

IC

5

Q16BV

D

S

G

FET

1

2

3

S S S G

1 2 3 4

C82128-001

1

CR22BV MBRS130LT3 SM DIO

2

3

1

2

R55BV

2.2 5%

EMPTY 805

BV_GFX_SN

C84BV

4700PF 20% 50V EMPTY 603

C83BV

4.7UF 20% 25V X5R 1206

1

2

C81BV

C82BV

4.7UF

20%

25V

2

25V

2

X5R

1206

1

2

1

2

1

2

C221BV

4.7UF 20% 25V X5R 1206

0.53UH

R56BV

0OHM

EM

PTY

SM

L5BV

2

IND

2

MODULE REV DETAILS

MODULE NAME

SR_IBP_GFX

1

R57BV

1

2

BV_GFX_VREG_CNTL_CSREF

10 1%

CH

402

BV_GFX_PWM_SENSE

REV

V_GFX

1

DATE

02-02-0702.00.00

D

76 14

15

OUT

71

75

OUT

C

75

71

75

B

V_GFX

1415

IN

76

1

C85BV

22.000UF 22.000UF 20%

6.3V

2

X5R 805

1

C86BV

20%

6.3V

2

X5R 805

65 62

INTERMEDIATE_BUS_POWER

26

IN

61 63 66 68 69 70 71 73 74 75 76 77 78

BOM NOTE:

MOD TO 724613-076

1

C277BV

220UF 20%

2. TANT

2

7343

76

5V

BOM NOTE:

MOD TO 724613-076

GFX_INTERMEDIATE_F ILTERED

IN

1

C278BV

220UF 20%

2. TANT

2

7343

1

C279BV

220UF 20%

5V

2.5V TANT

2

7343

B

CAD NOTE:

A

BOM NOTE:

MOD CAPS TO C71601-001

8

PLACE ON TOP <NORTH SIDE> OF SOCKET

1

C76BV

220UF 20%

2.5V TANT

2

7343

7

1

2

C77BV

220UF 20%

2.5V TANT 7343

6

BPAGE DRAWING

tawas_b.sch_1.76

Wed Feb 07 17:19:32 2007

5

4 2

3

[PAGE_TITLE=VREG: V_GFX OUTPUT]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

76

1

REV

2.0

A

D

C

B

71

IT_VR_CSCOMP

A

CR-77 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE77

8

VCC3

31

55

VSS_SENSE

8

IN

A_GND_VR

77

IN

VCC_SENSE

8

IN

A_G

77

IN

H_DPRSLPVR

12

31

IN

R52VR

1

0

402

OUT

1

C8VR

1000PF 10%

50V

2

EMPTY 402

CAD NOTE:

PLACE CLOSE TO CONTROLLER

DESIGN NOTE:

VSS/VCCSENSE: 1X2 HEADER: NEVER STUFF

ND_VR

SUITCASE JUMPER

7678 26

61

62636566686970

IN

737475

2

IT_VR_CSCOMP_R IT_VR_PWM1_SENSE

5%

R53VR

1

CH

0 5%

EMPTY

2

402

1

2

8

2226

31

32

40445052545556

3337 75

R17VR

1

3K

5% CH

402

J1VR

1X2HDR

1

2

6277

33

OUT

2

EMPTY

CAD NOTE:

CONNECTION BETWEEN GND AND A_GND CLOSE TO CONTROLL ER.

DESIGN NOTE:

EMPTY SITES <PADS OVERLAP>

INTERMEDIATE_B US_POWER

77

IN

1

C13VR

820.0PF

C14VR

1000PF

10% 50V X7R 402

10%

50V

2

X7R 402

7

6567686972 9

IN

BOM NOTE:

MOD C7VR TO

A36096-064

(560PF)

C7VR

1

470PF

10% 50V X7R 402

R16VR

1

1K

402

A_G

ND_VR

BOM NOTE:

R6VR

1

200K

402

7

V_3P3_STBY\G

V_1P05_PWRGD

ICH_VRMPWRGD

VCCP_CLK_EN_N

2

VCC_SENSE_FB

C6VR

1

2

220PF

10%

1%

50V

CH

X7R

402

1

R11VR

0O

HM

2

EMPTY SM

R7VR

2

1

5%

0

CH

402

78

OUT

MOD R 6VR TO A93548-240 (196K 1%)

2

1%

CH

1

2

BOM NOTE:

MOD R 5VR TO A93548-097 (35.7KOHM)

2

IT_VR_COMP_ NODE1

1

2

IT_VR_COMP_RT

R5VR

39.2K

1% CH

402

C15VR

1000PF 10% 50V X7R 402

BOM NOTE:

MOD R15VR TO A93548-066 (33.2K 1%)

R15VR

2

1

15K

1%

CH

402

1000PF

50V

IT_VR_RAMP_R

1000P

2

RT1VR THRMSTR

UNKNOWN

1

6

1

R18VR

3K 5%

CH

2

402

BOM NOTE:

MOD C 1VR TO A36095-004 (18PF)

C3VR

1

402

R8VR

1

200K

402

77

7877

C16VR

1

F

50V

402

CAD NOTE:

PLACE THERMISTOR CLOSE TO NEAREST INDUCTOR

IT_VR_COMP

.01UF

25V

R14VR

1

499 402

2

10% X7R

2

1% CH

IN

2

10% X7R

BOM NOTE:

MOD R T1VR TO C14407-003

1%

CH

270K

V

2

402

C5VR

402

2

R10VR

1

270K

402

CCP_VREG_CNTL_CS REFVCCP_VREG_CNTL_ CSREF

C1VR

100P

R9VR

1

6

X7

CH

50V COG 402

1

10%

2

1%

4700PF

50V

F

5%

R

390PF

2

1%

CH

50V

133K

402

C9VR

2

1

IT_VR_SS

C4VR

2

603

R13VR

1

20% X7R

603

1

5%

COG

IT_VR_H_DPRS LPVR_R

2

IT_VR_CLIM

1% CH

IT_VR_VRPM

IT_VR_RPM

IT_VR_RT

IT_VR_RAMP

IT_VR_CSSUM

R54VR

1

0

603

79

77

IT_VR_DEL AY_PWRGD

IT_VR_ST

2

1A CH

5

8

BOM NOTE:

10

11

12

13

14

15

16

17

18

19

20

IT_VR_RPHT

IN IN

1

2

3

4

5

6

7

8

9

REV=1

1

130K

603

BOM NOTE:

32

H_VID<6..0> A_GND_VR

MOD EU1VR T0 C36044-001

EU1VR

ADP3207

EN

PWRGD VID5

PGDELAY

CLKEN*

FBRTN

FB

COMP

SS

DPRSTP*

STSET

DPRSLP

ILIMIT

TTSENSE

VRPM

RRPM

RT

RAMPADJ

LLSET

CSREF

CSSUM

CSCOMP

GND

R2VR

2

1

1%

130K

R3VR

CH

2

1%

CH

603

MOD R2VR/R3VR TO A93550- 170 (76.8K 1%)

45

2329

GND

VID6

VID4

VID3

VID2

VID1

VID0

PSI*

VCC

VRTT

DCM*

OD*

PWM3

PWM2

PWM1

SW3

SW2

SW1

45

61

62656668

161718

41

34

35

36

37

38

39

40

33

32

31

30

29

28

27

24

25

26

21

22

23

IC

69707576777883

15

6263

71

6

5

4

3

2

1

0

H_DPRSTP_N

H_PSI_N

IT_VR_CPU_VCC

IT_VR_TTSEN

IT_VR_VRTT

VR_OD_N

VR_PWM3_R

VR_PWM2_R

VR_PWM1_R

VR_SW2_R

VR_SW1_R

9263233

IN

81014

IN

7

IN

R21VR

1

2

5%

0

CH

402

R23VR

2

1

5%

0

CH

402

TP_VR_SW3

R24VR

1

2

5%

0

CH

402

R25V

1

0

402

Wed Feb 07 17:19:33 2007

4 2

3

V_5P0_STBY\G

V_1P05_CORE

1

R1VR

10 5%

2

CH 603

R12VR

61.9

1%

CH 402

3

Q1

VR

FET

1

2

VR_DCM_N

R22VR

2

1

5%

0

CH

402

VR

_PWM1

R

2

5% CH

BPAGE DRAWING

tawas_b.sch_1.77

VR_PWM2

3

1

2

1

2

1

2

C10V

4. 10% 10V

X5R

1206

7UF

H_PROCHOT_N

C2VR

4.7UF 10% 10V

X5R

1206

R

1

2

77

IN

OUT

V_1P05_PWRGD

5

1

IN

2

SD*

3

DRVLSD*

4

CROWBAR

V_5P0_STBY\G

5

1

IN

2

SD*

3

DRVLSD*

4

CROWBAR

IT_VR_PWM2_SENSE

CONFIDENTIAL

CUSTOM TEXT BPAGE

2

C11VR

10UF

20%

6.3V X5R 805

A_GND_VR

6

U1VR

ADP3419

REV=1

1O

F1

IN

U2VR

ADP3419

REV=1

1OF1

INTEL

1

MODULE REV DETAILS

MODULE NAME

SR_ADP3207 4.00.00 02-06-07

R19VR

1

2

6.49K

1%

CH

603

1

C12VR

UF

.1 10% 10V

2

X5R 402

BOM NOTE:

MOD RT2VR TO C14407-003

IN

10

BSTVCC

9

DRVH

8

SW

6

DRVL

7

GND

REV

R20VR

1

0 1A

2

CH

T_VR_TTSEN_R

I

603

2

RT2VR THRMSTR

UNKNOWN

1

62 77

IM_VR_1_BST

IM_VR_DRV_H1

IM_VR_SW1_OUT

IM_VR_DRV_L1

OUT

IC

OUT

26

32 334561

9 70 75 76 77 78 83

BSTVCC

DRVH

SW

DRVL

GND

62 65 66 68 69

IM_VR_2_BST

10

IM_VR_DRV_H2

9

IM_VR_SW2_OUT

8

IM_VR_DRV_L2

6

7

OUT

IC

OUT

DOCUMENT_NUMBER

D89092

1

PAGE

77

DATE

D

C

78

B

78

A

78

REV

2.0

CR-78 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE78

8

INTERMEDIATE_BUS_ POWER_PH

78

IN

6265

77

666869707576

7883

45

61

D

7576

C

71

70

INTERMEDIATE_BUS_POWER

6566 26

61

IN

6263 6869 7374 77

V_5P0_STBY\G

9263233

IN

1

2

IM_VR_1_BST

77

IN

IM_VR_DRV_H1

IM_VR_SW1_OUT

IM_VR_DRV_L1

77

C18VR

4.

7UF

20%

16V

X5R

1206

1

0.01 2010

1

0.01 2010

1

0.01 2010

603

78

R26VR

1

0

R49VR

R50VR

R51VR

7

2

1

CR1VR

BAT54C

3 SOT23C DIO

BOM NOTE:

MOD C26VR TO 108426-187

(1UF)

1

C26VR

.022UF 10%

25V

2

X7R 603

2

INTERMEDIATE_BUS_ POWER_PH

2

INTERMEDIATE_BUS_ POWER_PH

IN

2

IM_VR_1_BST_R

1A

CH

1%

CH

1%

CH

1%

CH

6

1

2

OUT

BOM NOTE:

MOD C27VR TO 644066-026

(1UF 25V)

C27VR

1UF 10% 16V X7R 1206

78

5

D

4

S

G

1

2

3

4

G

1

2

3

5

D

S

Q2VR

FET

Q4VR

FET

45

5

Q3VR

D

4

S

G

FET

1

2

3

5

Q5VR

D

4

S

G

FET

1

2

3

C75VR

220UF 20%

2.5V TANT 7343

BOM NOTE:

MOD C75VR TO 724613-076

1

CR4

VR MBRS130LT3 SM DIO

2

BOM NOTE:

MOD TO C82128-001

BOM NOTE:

MOD C28VR/C29VR/C30VR/C31VR

TO C34226-002 (4.7UF 25V)

1

C28VR

7UF

4. 20%

16V

2

X5R

1206

1

2

IT_VR_SW1_SN

1

2

C29VR

4.7UF 20% 16V X5R 1206

R30VR

2.2 5%

EMPTY 805

C32VR

4700PF 20% 50V EM 603

1

2

PTY

1

2

C30VR

4.7UF 20% 16V X5R 1206

R31VR

0OHM

PTY

EM SM

L2VR

.4UH

2

IND

2

MODULE REV DETAILS

MODULE NAME

SR_ADP3207 4.00.00 02-06-07

1

C31VR

4.7UF 20% 16V

2

X5R 1206

1

R32VR

1

2

VCCP_VREG_CNTL_CSREF

10CH1%

402

IT_VR_PWM1_SENSE

REV

VCCP

1

DATE

D

8

71

OUT

78 79

77

78

OUT

C

77

OUT

77

7883

76

V_5P0_STBY\G

45

61

62

B

9263233

IN

656668697075

77

IN

77

IM_VR_2_BST

IN

1

C33VR

4.7UF 20% 16V

2

X5R 1206

603

IM_VR_DRV_H2

IM_VR_SW2_OUT

IM_VR_DRV_L2

R37VR

1

0

SOT23C

2

IM_VR_2_BST_R

1A

CH

BAT54C

DIO

CR2VR

2

1

3

BOM NOTE:

MOD C19VR TO 108426-187

(1UF)

1

C19VR

.022UF 10%

25V

2

X7R 603

A

8

7

BOM NOTE:

MOD C20VR TO 644066-026

(1UF 25V)

1

C20VR

1UF 10% 16V

2

X7R 1206

6

C73VR

220UF 20%

2.5V TANT 7343

1

C74VR

220UF 20%

2.5V TANT

2

7343

1

R28VR

2.2 5%

EMPTY

2

805

IT_VR_SW2_SN

1

C21VR

4700PF 20% 50V

2

EMPTY 603

3

5

Q6VR

D

4

S

G

FET

1 2 3

5

D

Q8VR

4

S

G

FE

T 1 2 3

5

4

G

4 2

5

Q7VR

D

4

S

G

FE

1

2

3

5

Q9VR

D

S

FE

T 1 2 3

1

2

BOM NOTE:

T

MOD C73VR, C74VR TO 724613-076

1

CR3VR MBRS130LT3 SM

2

DIO

BOM NOTE:

MOD TO C82128-001

BPAGE DRAWING

tawas_b.sch_1.78

Wed Feb 07 17:19:35 2007

BOM NOTE:

MOD C28VR/C29VR/C30VR/C31VR

TO C34226-002 (4.7UF 25V)

1

C23VR

4.7UF 20% 16V X5R 1206

C22VR

4.7UF 20%

16V

2

X5R

1206

VCCP

VCCP_VREG_CNTL_CSREF

IT_VR_PWM2_SENSE

1

2

1

2

L1VR

2

IND

R41VR

0OHM

EMPTY SM

.4UH

C25VR

4.7UF 20%

16V

X5R

1206

1

2

10 1%

402

C24VR

4.7UF 20% 16V X5R 1206

R29VR

1

2

CH

[PAGE_TITLE=VREG: VCCP PHASE 1 & 2]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

OUT

1

PAGE

78

87178 79

78

77

REV

2.0

B

A

CR-79 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE79

8

VCCP

87178

IN

D

7

1

2

C34VR

22.000UF 20%

6.3V X5R 805

1

2

C45VR

22.000UF 20%

6.3V X5R 805

1

C56VR

22.000UF 20%

6.

2

X5R 805

6

1

3V

2

C66VR

22.000UF 20%

6.3V X5R 805

1

C67VR

22.000UF 20%

6.3V

2

X5R 805

1

2

C68VR

22.000UF 20%

6.3V X5R 805

1

2

C69VR

22.000UF 20%

6.

3V X5R 805

1

2

C70VR

22.000UF 20%

6.

3V X5R 805

45

1

C72VR

22.000UF 20%

6.3V

2

X5R 805

1

C35VR

22.000UF 20%

6.3V

2

X5R 805

3

1

2

C36VR

22.000UF 20%

6.3V X5R 805

1

2

C37VR

22.000UF 20%

6.3V X5R 805

1

C38VR

22.000UF 20%

6.3V

2

X5R 805

2

MODULE REV DETAILS

MODULE NAME

SR_ADP3207 4.00.00 02-06-07

1

2

C39VR

22.000UF 20%

6.3V X5R 805

1

2

C40VR

22.000UF 20%

6.3V X5R 805

1

C41VR

22.000UF 20%

6.3V

2

X5R 805

1

REV

DATE

D

1

2

C

1

2

1

B

C60VR

220UF 20%

2.5V TANT

2

7343

BOM NOTE:

MOD CAPS TO C71601-001

A

C42VR

22.000UF 20%

6.3V X5R 805

C51VR

22.000UF 20%

3V

6. X5R 805

1

2

1

2

1

2

C61VR

220UF 20%

2.5V TANT 7343

C43VR

22.000UF 20%

6.3V X5R 805

C52VR

22.000UF 20%

3V

6. X5R 805

1

2

1

2

1

2

C62VR

220UF 20%

2.5V TANT 7343

C44VR

22.000UF 20%

6.3V X5R 805

C53VR

22.000UF 20%

6.3V X5R 805

2

1

2

1

C63VR

220UF 20%

2.5V TANT 7343

C46VR

22.000UF 20%

6.3V X5R 805

C54VR

22.000UF 20%

6.3V X5R 805

1

2

1

2

1

2

C47VR

22.000UF 20%

6.3V X5R 805

C55VR

22.000UF 20%

6.3V X5R 805

C64VR

220UF 20%

5V

2. TANT 7343

1

2

1

2

1

2

C48VR

22.000UF 20%

6.3V X5R 805

C57VR

22.000UF 20%

6.3V X5R 805

C65VR

220UF 20%

2.5V TANT 7343

1

2

1

2

C49VR

22.000UF 20%

6.3V X5R 805

C58VR

22.000UF 20%

3V

6. X5R 805

1

C50VR

22.000UF 20%

6.3V

2

X5R 805

1

C59VR

22.000UF 20%

3V

6.

2

X5R 805

77 8

IN

8 6

IN

7 50

DESIGN NOTE:

H_VID<6..0>

V_1P05_CPU

R43VR

1

2

5%

47K

CH

402

R45VR

2

1

47K

5% CH

402

R47VR

1

2

5%

47K

CH

402

EMPTY FOR PRODUCTION

47K 402

R42VR

1

R44VR

1

R46VR

1

R48VR

1

2

6

5% CH

5

2

4

5% CH

3

2

5% CH

1

2

0

5% CH

C

B

A

BPAGE DRAWING

tawas_b.sch_1.79

Wed Feb 07 17:19:36 2007

8

7

6

5

4 2

3

[PAGE_TITLE=VREG: VCCP DECOUPLING / 2X2 CONN]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

79

1

REV

2.0

CR-80 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE80

8

VCC3

MH

R1

1

2

0

D

1A CH

603

FB1MH

1

2

EMPTY

1

C1MH

C2MH

.

10UF

01UF

20%

10%

25V

6.3V

2

EMPTY 805

X7

R

402

C

B

402

1

0

R3MH

55

PM_CLKRUN_N

31

BI

33

A

34

24

3334

34

2

5% CH

R4MH

IN

OUT

10K

5% CH

402

34

34 34 34 34 34 34 34 34

1

2

P_PCIRST_N

CK_P_33M_CRD

P_GNT_N<0>

P_REQ_N<0>

BI

34

IN

BI BI BI BI BI BI BI BI

34

OUT

34

OUT

8

7

CAD NOTE:

PLACE ONE GROUPING EACH AS CLOSE AS POSSIBLE TO PINS 22,52,83

C3MH

.1 10%

10V X5R 402

1

C4MH

UF

.

01UF

10%

25V

2

X7R 402

C5MH

.1 10%

10V X5R 402

1

UF

2

P_AD<31..0>

P_C/BE_N<3..0>

P_F

RAME_N P_IRDY_N P_TRDY_N P_DEVSEL_N P_STOP_N P_PERR_N P_SERR_N P_PAR

PM_CLKRUN_MR_R_N

R5MH

1

P_PME_N

P_INTA_N

2

P_PME_MR_R_N

0

5% CH

402

R6MH

1

2

P_INTA_MR_R_N

5%

0

CH

402

R7MH

1

2

P_PCIRST_MR_R_N

5%CH0

402

R8MH

P_GNT_R_N<0>

1

2

5%CH0

402

R9MH

1

2

5%

0

CH

402

7

C6MH .

01UF 10% 25V X7R 402

1

2

C7MH

.1 10%

10V X5R 402

18

R2MH

100 5%

CH 402

PCI_IDSEL_1394

P_REQ_R_N<0>

6

UF

VCC_3P3_MEDIA

22 52 83

3

31

4

30

5

29

6

28

7

27

8

26

9

25

10

24

23

24

22

25

21

26

20

27

19

28

18

29

17

30

16

32

15

33

14

34

13

35

12

36

11

37

10

38

9

39

8

93

7

94

6

95

5

96

4

97

3

98

2

99

1

100

0

1

3

12

2

21

1

31

0

2 13 14 15 16 17 18 19

20 86 87 88 89 90 91 92

3VCC 3VCC 3VCC

AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

C/BE3* C/BE2* C/BE1* C/BE0*

IDSEL FRAME* IRDY* TRDY* DEVSEL* STOP* PERR* SERR* PAR CLKRUN* PME* INTA* PCIRST* PCICLK GNT* REQ*

REV=1

D78091-001

U1MH

W83L528G

SDDSB*/SDPWR*

XDDSB*/XDPWR* XDLED/SMEXWP*

MSNSEL/CBENB

MSDSB*/MSPWR*

5

[PAGE_TITLE=MEDIA READER CONTROLLER]

72

SCI

73

SDD0

74

SDD1

75

SDCMD

76

SDD2

77

SDD3

78

SDCLK

79

SDWP

80 81

SDCD*

84

SMCD*

40 41 45

XDRB*

46

XDRE*

47

XDCE*

48

XDCLE

49

XDALE

50

XDWE*

51

XDWP*

53

XDD7

54

XDD6

55

XDD5

56

XDD4

57

XDD3

58

XDD2

59

XDD1

60

XDD0

MSD0 MSD1 MSBS MSD2

MSD3 MSCLK MSLED

XDCD*

VSS VSS

SDLED

61 63 64 65 66 67 68 69 70 71 85

11

62

42 43 44 82

IC

XDPWR*

I2CDAT I2CCLK

MSINS*

1OF1

45

_SCI

TP SD_DATA_0 SD_DATA_1 SD_CMD SD_DATA_2 SD_DATA_3 SD_CLK SD_WP_N SD_PWR_SEL_N SD_SENSE_N SM

_SENSE_WP_PU

XD_PWR_SEL_N

XD_RB_N XD_RE_N XD_CE_N XD_CLE XD_ALE XD_WE_N XD_WP_N XD_DATA_7 XD_DATA_6 XD_DATA_5 XD_DATA_4 XD_DATA_3 XD_DATA_2 XD_DATA_1 XD_DATA_0 GLOBAL_PWR_SEL_N M

SN_SEL MS_DATA_0 MS_DATA_1 MS_BS MS_DATA_2 MS_DATA_3 MS_CLK TP_MS_ACT_LED_N MS_PWR_SEL_N XD_SENSE_N

CR_EEPROM_DAT CR_EEPROM_CLK

SD_ACT_LED_N MS_SENSE_N

OUT

OUT OUT

IN

OUT

IN

IN IN

81

BI

81

BI

81

BI

81

BI

81

BI

81 81 80 81

80

81

BI

81

BI

81

BI

81

BI

81

BI

81 81

81

BI

81

BI

81

BI

81

BI

81

BI

81

BI

81

BI

81

BI

80

BI

81

BI

81

BI

81

BI

81

BI

81

BI

81

80 81

80 80 80 81

POWER-ON STRAPS

DESIGN NOTE:

SD FORMAT ENABLE

80

81

80 81

SD_PWR_SEL_N

OUT

DESIGN NOTE:

MMC FORMAT ENABL E

GLOBAL_PWR_SEL_N

OUT

Fri Feb 09 11:28:47 2007

4 2

3

VCC3

R53MH

4.7K 5%

CH 402

81

VCC3

R10MH

4.7K 5%

CH 402

DESIGN NOTE:

MS F ORMAT ENABLE

80

OUT

VCC3

DESIGN NOTE:

H

R11M

4.7K

XD FORMAT ENABLE

5% CH

402

80

OUT

BPAGE DRAWING

tawas_b.sch_1.80

3

MS_PWR_SEL_N

XD_PWR_SEL_N

2

R12MH

4.7K 5%

CH 402

80

DESIGN NOTE:

DISABLE EEPROM

OUT

VCC3

R13MH

80

4.7K 5%

CH 402

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

1

MODULE REV DETAILS

MODULE NAME

SD_ACT_LED_N

R14MH

4.7K 5%

CH 402

CR_EEPROM_DAT

R15MH

4.7K 5%

CH 402

DOCUMENT_NUMBER

REV

0.02.00W83L538G 10.17.06

DESIGN NOTE:

PCI IDSEL: 18 PCI INT: A/A PCI GNT/REQ: 0

DESIGN NOTE:

DISABLE CARDBUS

80

OUT

CR_EEPROM_CLK

80

OUTOUT

D89092

MSN_SEL

PAGE

1

80

DATE

R16MH

4.7K 5%

CH 402

R17MH

4.7K 5%

CH 402

REV

2.0

D

C

B

A

CR-81 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE81

8

D

CAD NOTE:

PLACE THIS POWER CONTROL CIRCUITRY AS CLOSE AS POSSIBLE TO CONNECTOR

VCC3

1

C

2

80

C8MH

22U 20%

6.3V X5R 1206

IN

F

1

C9MH

10.0UF

20%

3V

6.

2

EMPTY 805

SD_PWR_SEL_N

GLOBAL_PWR_SEL_N

0

402

0

402

R18MH

1

EMPTY

R19MH

1

B

A

8

7

2

Q1MH PMOSFET

2

5%

2

5% CH

S

1

D

G

3

7

6

81

80

81

80

81

80

81

80

81

80

81

80

81

80

81

80

1

R20M

H

0 1A

EMPTY 805

2

RT1MH

2

1

THRMSTR

0.5

657448-002

[

PAGE_TITLE=MEDIA READER SOCKET]

6

XD_VCC_PROTECTED

1

R21MH

0 1A

CH 805

2

SD_VCC_PROTECTED

1

R22MH

0 1A

CH 805

2

MS_VCC_PROTECTED

OUT

OU

T

OUT

5

80 80 80 80 80 80 80 80 80 80 80

81

80 80

81

80 80

81

80

81

80

81

80

81

80

81

80

81

80

81

CAD NOTE:

PLACE THESE COMPONENTS NEAR CONNEC TO R AVOID STUBS ON MS/SD DATA LINES

81

IN IN IN

OUT

BI

IN

BI

BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT

OUT

BI

IN

OUT

80

81

OUT

80

BI

80

BI

80

BI

80

BI

80

81

IN

45

CAD NOTE:

PLACE ALL TERMINATION RESISTOR S AS

SD_VCC_PROTECTED

XD_VCC_PROTECTED

MS_VCC_PROTECTED

SD_SENSE_N

SD_WP_N

SD_DATA_0

SD_DATA_1

SD_DATA_2

SD_DATA_3

SD_CLK

SD_CMD

XD_DATA_7 XD_DATA_6 XD_DATA_5 XD_DATA_4 XD_DATA_3 XD_DATA_2 XD_DATA_1 XD_DATA_0 XD_CE_N XD_RB_N XD_CLE XD_ALE XD_WE_N XD_RE_N XD_WP_N XD_SENSE_N

M

S_CLK

MS_BS

MS_DATA_3

MS_DATA_2

MS_DATA_1

MS_DATA_0

MS_SENSE_N

CLOSE AS POSSIBLE TO DEVI CE

R23MH

2

1

5%

0

CH

402

R25MH

2

1

0

5% CH

402

R27MH

2

1

5%

0

CH

402

R29MH

2

1

47 5%

CH

402

0

402

0

402

0

402

VCC3

R38MH

1

MS_SENSE_N

MS_BS

MS_DATA_3

MS_DATA_2

MS_DATA_1

MS_DATA_0

2

5%

100K

CH

402

1

100K

R40MH

402

2

1

100K

5% CH

402

1

100K

R42MH

402

2

1

100K

5% CH

402

1

100K

402

Fri Feb 09 11:29:31 2007

R39MH

R41MH

R43MH

4 2

3

R24MH

2

1

0

5% CH

402

R26MH

2

1

0

5% CH

402

R28MH

2

1

0

5% CH

402

R30MH

2

1

0

5% CH

402

R31MH

R32MH

1

R34MH

1

R36MH

1

5% CH

BPAGE DRAWING

1

47

402

2

5%

R33MH

CH

1

0

402

2

5%

R35MH

CH

1

0

402

2

5%

R37MH

CH

1

0

402

81

2

81

2

81

2

81

tawas_b.sch_1.81

2

5% CH

2

5% CH

2

5% CH

2

5% CH

80

OUT

80

OUT

80

BI

80

BI

80

BI

80

BI

80

IN

3

SD_WP_N

SD_SENSE_N

SD_CMD

SD_DATA_3

SD_DATA_2

SD_DATA_1

SD_DATA_0

SD_CLK_R SD_DATA_3_R SD_DATA_2_R SD_DATA_1_R SD_DATA_0_R SD_CMD_R SD_WP_R SD_SENSE_R_N

MS_CLK_R MS_BS_R MS_DATA_3_R MS_DATA_2_R MS_DATA_1_R MS_DATA_0_R

MS_SENSE_R_N

100K

402

100K

402

100K

402

2

33 19 28

34 30 38 37 36 31 41 40

18 17 16 15 14 13 12 11

5

3 6 7 8 4 9 1

27 21 26 24 22 23 25

2

10 20 29 32 35 39

VCC3

R44MH

2

1

5%

100K

R45MH

CH

402

2

1

5%

R46MH

CH

2

1

100K

5%

R47MH

CH

402

2

1

5%

R48MH

CH

2

1

100K

5%

R49MH

CH

402

2

1

5%

R50MH

CH

1

2

100K

5% CH

402

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

MODULE REV DETAILS

MODULE NAME

W83L538G 0.02.00 10.17.06

J1MH

NN_4IN1_RDR

CO

SD_VDD XD_VCC MS_VCC

SD_CLK SD_CD/DAT3 SD_DAT2 SD_DAT1 SD_DAT0 SD_CMD SD_WP SW_RSV

XD_D7 XD_D6 XD_D5 XD_D4 XD_D3 XD_D2 XD_D1 XD_D0 XD_CE* XD_R/B* XD_CLE XD_ALE XD_WE* XD_RE* XD_WP* XD_CD

MS_SCLK MS_BS MS_DATA3 MS_DATA2 MS_DATA1 MS_SDIO/DATA0 MS_INS

XD_GND1 XD_GND2 MS_VSS1 MS_VSS2 SD_VSS1 SD_VSS2 SD_GND

XD_WP_N

80

OUT

81

XD_SENSE_N

80

OUT

81

DOCUMENT_NUMBER

REV=1

D89092

100K

REV

NAIL

R51MH

1

402

R52MH

1

402

1

CONN

1

5% CH

NC NC

2

PAGE

81

DATE

42 43 44

VCC3

REV

2.0

D

C

B

A

CR-82 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE82

8

D

30

BI

30

BI

USB_4_DN

USB_4_DP

7

R388SA

1A

6030CH

752402-015

L12SA

90OHM

EMPTY ACM2012

L12SA

90OHM

EMPTYACM2012

R389SA

0

1A

603

CAD NOTE:

DO NOT CHANGE TO 402 OVERLAPPING FOOTPRINTS

CH

6

USB_4_R_DN

CR16SA

TVS6V

USB_4_R_DP

6.0V

VCC

EMPTY

45

BI

3

83

C

2

MODULE REV DETAILS

MODULE NAME

1

REV DATE

D

C

CHOKES AND ESD FOR REPLICATOR USB

USB_OC4_N

CAD NOTE:

PLACE AS CLOSE AS POSSIBLE

TO USB CONNECTOR

C66SA

470UF 20%

6.3V TANT 7343

VREG_USB MUST BE SPLIT AMONGST ALL USB CHANNELS. DO NOT DAISY CHAIN

OUT

30

OUT

33

83

B

A

1.50 RT8SA

THRMSTR

C92281-001

R101SA

15K

402

5% CH

R102SA

10K

5% CH

402

R103SA

10K

5% CH

402

B

5469

IN

73

VCC_USB V_USB_REP

A

USB OVERCURRENT AND VREG FOR USB LEFT JACK

BPAGE DRAWING

[PAGE_T

8

7

6

ITLE=USB LEFT JACK]

5

4 2

tawas_b.sch_1.82

Wed Feb 07 17:19:41 2007

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

82

2.0

1

CR-83 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE83

8

7

6

V_3P3_KSC

29525557586573

IN

45

3

D

DESIGN NOTE:

STUFF R111BU FOR FAB A VERIFY POR T_REP_DETECT IS NOT CONNECTED TO ICH

PORT_REP_DETECT

56

IN

C

72 69 47 39 33 31

V_3P3_M

19

B

IN

20 32 35 46 48 71 83

83 41

IN

44

45

61

C511BU

470PF

10% 50V EMPTY 402

AUD_PORT_E_L_REP

C500BU

470PF 10% 50V EMPTY 402

A

V_PR_PWR_IN

73

IN

83

C504BU

470PF

10% 50V EMPTY 402

VCC3

R111BU

4.7K 5%

EMPTY 402

464748

71

7283

62656668 7883

707576777883

V_5P0_STBY\G

9263233

IN

6265666869

LAN_LED_LINK_REP_N

47

IN

83

LAN_LED_1000_REP_N

4783

IN

4483 4483

31

32333539

69

45

61 77

C512BU

470PF

10% 50V EMPTY 402

C505BU

470PF

10% 50V EMPTY 402

69707576

C501BU

470PF 10% 50V EMPTY 402

AUD_PORT_E_R_REP

41

IN

AUD_PORT_E_L_REP

41

IN

AUD_HP_JACK_SENSE_ REP

42

IN

EC_PWRSW_N

525783

IN

LAN_LED_100_REP_N

4783

IN

LAN_LED_1000_REP_N

4783

IN

LAN_LED_LINK_REP_N

4783

IN

V_3P3_M

1920

IN

LAN_V_1P8

46474883

IN

V_5P0_STBY\G

9263233

OUT

LAN_LED_100_REP_N

47

IN

83

4883

LAN_V_1P8

46

IN

47

TP_RESERVED_23

TP_AUD_HD_SDO

TP_AUD_HD_SDI _A

TP_AUD_HD_BCLK

P_AUD_HD_SYNC_A

T

TP_AUD_HD_SDI _B

TP_AUD_HD_RST_N

RESERVED_49

TP_ TP_RESERVED_51 TP_RESERVED_53

L100BU 1

L101BU 1

FB

2

FB

2

C502BU

470PF 10% 50V EMPTY 402

C506B

470PF 10% 50V EMPTY 402

R500BU 10K 1%

CH 402

1

IO

3

IO

5

IO

7

IO

9

IO

11

IO

13

IO

15

IO

17 18

IO

19

IO

21

IO

23

IO

25

IO

27

IO

29

IO

31

IO

33

IO

35

IO

37

IO

39

IO

41

IO

43

IO

45

IO

47

IO

49

IO

51

IO

53

IO

55

IO

57

IO

61

MTG

62

AUD

MTG

J2BU

CONN_TAC_58P

REV=1

CONN

AUD_PORT_E_R_REP

IN

C503BU

470PF

10% 50V EMPTY 402

V_USB_REP

8283 82

IN IN

U

C507B

470PF

10% 50V EMPTY 402

EC_PWRSW_N

IN

83

U

V_USB_REP

CRT_RED_PORT

CRT_GREEN_PORT

CRT_BLUE_PORT

CRT_DDC_DATA_PORT

CRT_DDC_CLK_PORT

CRT_VSYNC_PORT

CRT_HSYNC_PORT

USB_4_R_DN USB_4_R_DP TP_RESERVED_38

LA LAN_MDI3_REP_DP LAN_MDI2_REP_DN LAN_MDI2_REP_DP LAN_MDI1_REP_DN LAN_MDI1_REP_DP LAN_MDI0_REP_DN LAN_MDI0_REP_DP

2

IO

4

IO

6

IO

8

IO

10

IO

12

IO

14

IO

16

IO IO

20

IO

22

IO

24

IO

26

IO

28

IO

30

IO

32

IO

34

IO

36

IO

38

IO

40

IO

42

IO

44

IO

46

IO

48

IO

50

IO

52

IO

54

IO

56

IO

58

IO

59

PEG

60

PEG

83 52

IN

57

USB_4_R_DP USB_4_R_DN

U

C508B

470PF

10% 50V EMPTY 402

N_MDI3_REP_DN

C510BU

470PF 10% 50V EMPTY 402

V_PR_PWR_IN

C509B

U

470PF 10% 50V EMPTY 402

OUT

OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT

2883

82 83

IN

28 83

82 83 82 83

47 47 47 47 47 47 47 47

73

BI

2883

BI

2883

BI

83

CRT_DDC_CLK_PORT

CRT_VSYNC_PORT

CRT_RED_PORT

CRT_BLUE_PORT

2

MODULE REV DETAILS

MODULE NAME

6.0V

U4BU TVS6

V

6

U3BU TVS6V

EMPTY

6.0V

EMPTY

CRT_HSYNC_PORT

52

V_5P0_STBY\G

4

6

CRT_GREEN_PORT

52

V_5P0_STBY\G

4

CRT_DDC_DATA_PORT

1

3

1

3

1

REV

DATE

D

C

B

28 83

BI

75 76 66 68 45

61

9

26

BI

32

33 62 65 69 70 77 78 83

83

77

75

69

28

66

BI

83

62

45

32 9 26

33

A

61 65

28

68

83 70 76 78

ESD DIODES FOR VGA

BPAGE DRAWING

[PAGE_TITLE=PORT REP HDR]

8

7

6

5

4 2

tawas_b.sch_1.83

Wed Feb 07 17:19:43 2007

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

83

2.0

1

CR-84 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE84

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

1

REV

DATE

D

CHINA_ROHS

LB4

LABEL

EMPTY

E1_SILK

LB7

LABEL

EMPT

Y

A19177-

001

C

LB1

LABEL

INTEL SERIAL NUMBER

B2_SI

LB8

LABEL

EMPTY

LK

MTG_HOLE_0VIAS

1375X250_TARGET

B

1000X187

LB3

LABEL

EMPTY

I

NTEL_LOGO

LB6

LABEL

EMPTY

BOM NOTE:

MOD LB3 TO C46042-001

PRODUCT ID LABEL

INTEL 3.0 LOGO

MOUNTING HOLES

ALIGHTMENT HOLES

HS7

MTG_HOLE

NC9

GND=1,2,3,4,5,6,7, 8

HS8

MTG_HOLE_7VIA

NC8

GND=1,2,3,4,5,6,7

HS6

GND1

EMPTY

HS11

MTG_HOLE_0VIAS

GND1

EMPTY

HS12

MTG_HOLE_0VIAS

GND1

EMPTY

HS13

MTG_HOLE_0VIAS

GND1

EMPTY

HS14

MTG_HOLE_0VIAS

GND1

EMPTY

HOLE1

TOOLING_HOLE

1

NC1

60N

EMPTY

GND=1,2,3,4,5,6,7

TOOLING_HOLE

1

HS9

G_HOLE

MT

NC9

GND=1,2,3,4,5,6,7, 8

HS10

MTG_HOLE

NC9

GND=1,2,3,4,5,6,7, 8

HS15

MT

G_HOLE_7VIA

NC8

HOLE2

NC1

60N

EMPTY

D

EMPTY

C

B

A

1000X187

LB2

LABEL

EMPTY

BOM NOTE:

MOD LB2 TO

C46042-001

CONFIG LABEL

[PAGE_TITLE=MTG HOLES/JUMPERS]

8

7

A

HOLE3

TOOLING_HOLE

1

NC1

89X148N

LABELS

BPAGE DRAWING

tawas_b.sch_1.84

Wed Feb 07 17:19:45 2007

6

5

4 2

3

EMPTY

I/O

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

SHIELD HOLES

HOLE4

TOOLING_HOLE

1

NC1

89X148N

EMPTY

DOCUMENT_NUMBER

D89092

PAGE

REV

84

2.0

1

PIN NAME GP[0] GP[1] GP[2] GP[3] GP[4] GP[5]

D

GP[6] GP[7] GP[8] GP[9] GP[10] GP[11] GP[12] GP[13] GP[14] GP[15] GP[16] GP[17] GP[18] GP[19] GP[20]

C

GP[21] GP[22] GP[23] GP[24] GP[25] GP[26] GP[27] GP[28] GP[29] GP[30] GP[31] GP[32] GP[33] GP[34] GP[35]

B

GP[36] GP[37] GP[38] GP[39] GP[40] GP[41] GP[42] GP[43] GP[44] GP[45] GP[46] GP[47] GP[48] GP[49] GP[50] GP[51]

A

GP[52] GP[53] GP[54] GP[55]

CR-85 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE85

PIN#

TOL.

WELL

3.3V

MAIN

3.3V

MAIN MAIN

3.3V

MAIN

3.3V

MAIN

3.3V

MAIN

3.3V

MAIN

3.3V

MAIN

3.3V

MAIN

3.3V

MAIN

3.3V

MAIN MAIN

3.3V

MAIN

3.3V

MAIN

3.3V

MAIN

3.3V

MAIN MAIN

3.3V

MAIN

3.3V

MAIN

3.3V

MAIN

3.3V

MAIN

3.3V

MAIN

3.3V

MAIN

3.3V

MAIN

3.3V

MAIN

3.3V

MAIN

3.3V

MAIN

3.3V

MAIN

3.3V

MAIN

3.3V

MAIN

3.3V

MAIN

3.3V

MAIN

3.3V

MAIN B43 MAIN

3.3V

MAIN

3.3V

MAI

3.

N

3V

MAIN

3.3V

MAIN

3.3V

MAIN

3.3V

MAIN

3.3V

MAIN

3.3V

MAIN

3.3V

MAIN

3.3V

MAIN MAIN

3.3V

MAIN

3.3V

MAIN

3.3V

MAIN

3.3V

MAIN

3.3V

MAIN

3.3V

MAIN

3.3V

MAIN

3.3V

MAIN

3.3V

MAIN

3.3V

MAIN

3.3V

MAIN

3.3V

PLTRST

A52

B50

A53

B51

B51 A54A54

A40

B23B23

B49

A51

A21

A21 A61 A61 B59 B59

B13

B52

A55

A55 A56

A56

B45

B15

A16

A15

B14

B43

B30

A32

A32 B3

B3

1

A80

A12

A12 A49

A4

A48

B54B54

1

9

7

USAGE (NETNAME)

S4/S5

EC_KEY_INT_N EC_SPESW_N

KBC_SCANOUT<14> KBC_SCANOUT<15> VGA_SW_EN_N

PORT_CRT_EN_N SLP_S3_N SLP_S4_N

SMB_BAT2_DATA SMB_BAT2_CLK CPU_VR_ON_R EC_WAKE_SCI_R_N

KBC_SCANOUT<13> CPU_FAN_TACH EC_8051_RX EC_8051_TX

EC_RUNTIME_SCI_N

KBC_SCANOUT<8> KBC_SCANOUT<9> KBC_SCANOUT<10> KBC_SCANOUT<11>

FLASH_A<19> 5VA_3VA_ON

PM H_A20GATE_R

AT_PWR_ON_N EC_DBG_LED_N PM_PWRBTN_R_N

SMB_DAT1_DATA

_RSMRST_R_N

654

NOTES

PIN NAME GP[56] GP[57] GP[58]

GP[60] GP[61] GP[62] GP[63] GP[64] GP[65] GP[66] GP[67] GP[68] GP[69] GP[70] GP[71] GP[72] GP[73] MAIN GP[74] GP[75] G

P[76]

GP[77]

GP[79] GP[80] G

P[81] GP[82] GP[83] GP[84]

WELL MAIN MAIN MAIN MAINGP[59] MAIN MAIN MAIN MAIN MAIN MAIN MAIN MAIN MAIN MAIN MAIN MAIN MAIN

MAIN MAIN MAIN MAIN MAINGP[78] MAIN MAIN MAIN MAIN MAIN MAIN

TOL.

3.3V

3.

3.3V

3.

3.3V

PLTRST

A1

A2 B38 A22 B22 A34 B33

A10 A45 A60 B57 B58 A58 B53 A57A57

B12 B4

1

B11

S4/S5

PIN#

A1 A2 B38 A22 B22 A34 B33

A10 A45 A60 B57 B58 A58

3V

B53

B12 B4

1

3V

B11

3

USAGE (NETNAME)

PM_LAN_ENABLE_R BLUETOOTH_ON EC_LAMP_STAT EC_BPSEL EC_FASTCHG EC_CELLSEL EC_PRECHG

LED_WLAN_N LED_BLUETOOTH_N EC_MSCLK EC_MSDATA TP SMB_DAT1_CLK SMB_THRM_DATA SMB_THRM_CLK

KBC_TP_CLK KBC_TP_DATA

LPCPD_N

NOTES

28

1

D

C

B

A

THERE ARE A TOTAL OF 48 PINS LABELLED "GPIO" AROUND EC THE

REST OF GPIO PINS ARE SPECIFIED WITH PREFIX SUCH AS XX_GPIO, SO NOT IN THE LIST

8

7

6

45

[

PAGE_TITLE=EC GPIO MAP]

INTEL

DOCUMENT NUMBER

CONFIDENTIAL

3

2

PAGE

REV

1

Intel TAWAS Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual