Intel TAWAS Schematic

CR-1 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAG E1

8 2

[

1. COVER]

7

[2. BLOCK DIAGRAM]
[3. SCH ANNOTATION & BRD INF]

D

[4. GPIO MAP]
[5. USB TABLE]
[6. CPU (1 OF 3)]
[7. CPU (2 OF 3)]
[8. CPU (3 OF 3)]
[9. CPU THERMAL MONITORS AND FAN]
[10. GMCH (1 OF 8)]
[11. GMCH (2 OF 8)]
[12. GMCH (3 OF 8)]
[13. GMCH (4 OF 8)]
[14. GMCH (5 OF 8)]
[15. GMCH (6 OF 8)]

C

[16. GMCH (7 OF 8)]
[17. GMCH (8 OF 8)]
[18. CRESTLINE STRAPPINGS]
[19. DDR DIMM 0]
[20. DDR DIMM 1]
[21. DDR TERMINATION AND THERMAL]
[22. CK505 PAGE [ 1 OF 3 ]]]]]
[23. CK505 PAGE [ 2 OF 3 ]]]]]
[24. CK505 PAGE [ 3 OF 3 ]]]]]
[25. CRT/VGA]
[26. LVDS\LCD PANEL]

B

[27. S-VIDEO]
[28. VGA SWTICH]
[29. ICH8M (1 OF 5)]
[30. ICH8M (2 OF 5)]
[31. ICH8M (3 OF 5)]
[32. ICH8M (4 OF 5)]
[33. ICH8M STRAPS/ISOLATION]
[34. ICH8M (5 OF 5)]
[35. X1 MINI-PCIE 1]
[36. X1 MINI-PCIE 2]
[37. EXPRESS CARD CONN]
[38. ICH8M DUAL SPI]
[39. HDD CONNECTOR]
[40.

ICH8M IDE - ODD CONNECTOR]
[41. AUDIO CODEC]
[42. AUDIO DECOUPLING & JACK SENSE & DMIC]
[43. AUDIO SPEAKER & SUBWOOFER AMP]
[44. AUDIO ANTI-POP,ANTI-THEFT CIRCUITRY]
[45. AUDIO VREG]
[46. LAN INTEL/NINEVEH]
[47. LAN SWITCH/CONNECTORS]

8

7

6

45

[48. LAN POWER]
[49. MODEM/MDC]
[50. XDP]
[51. KBD CONN]

. BLUETOOTH/LPC/TOUCHPAD/HOT KEY CONN]

[52
[53. CHASSIS UP SIGNAL CONN]
[54. LOWER RIGHT CONN]
[55. KEYBOARD CONTROLLER]
[56. EC SIGNAL STUFFING OPTIONS]
[57. KBC SPI/SEQUENCING]
[58. MASTER SMBUS]

.TPM]

[59
[60. CORE_VR_POWER_MAP]
[61. VREG: V_SM/SMVTT]
[62. VREG: 1.5/1.05 CONTROLLER]
[63. VREG: 1.05V OUTPUT]
[64. VREG: 1.5V OUTPUT]
[65. VREG: 5V/3.3V CONTROLLER]
[66. VREG: 5V STANDBY OUTPUT]
[67. VREG: 3.3V STANDBY OUTPUT]
[68. VREG: RAIL SWITCHES 1 OF 2]
[69. VREG: RAIL SWITCHES 2 OF 2]
[70. VREG: V_1P25_M\V_1P05_M]
[71. VREG: DISCHARGE CIRCUITRY]
[72. VREG: POWER GOOD FOR CLPWRO]
[73. VREG: BATTERY CHARGER PAGE 1OF 2]
[74. VREG: BATTERY CHARGER PAGE 2 OF 2]
[75. VREG: V_GFX CONTROLLER]
[76. VREG: V_GFX OUTPUT]
[77. VREG: VCCP ADP3207 CONTROLER]
[78. VREG: VCCP PHASE 1 & 2]
[79. VREG: VCCP DECOUPLING / 2X2 CONN]
[80. MEDIA READE R CONTROLLER]
[81. MEDIA READER SOCKET]
[82. USB LEFT JACK]
[83. PORT REP HDR]
[84. MTG HOLES/JUMPERS]
[85. EC GPIO MAP]

BPAGE DRAWING

[PAGE_TITLE=COVER]

65

tawas_b.sch_1.1

Fri Feb 09 14:58:59 2007

4 2

3

REVDE

SCRIPTION

REVISIONS

DF

DATECHK

T

TAWAS

FAB B

REV

TAPED OUT: 2-08-07

PBA D73802-200

IMERSION SILVER BUILD

NOTES:

1. THIS SCHEMATIC DOCUMENTS THE GENERIC PRODUCT WITH

2. RESISTORS ARE IN OHMS UNLESS OTHERWISE SPECIFIED.

3. VCC = +5V UNLESS OTHERWISE SPECIFIED.

4. * SUFFIX INDICATES ACTIVE LOW SIGNAL.

5. \I SUFFIX INDICATES SIGNAL EXITS HIERARCHICAL BLOCK.

BOM_RELEASE_DATE

DRN_BY

CHK_BY

ENGR_APVD

CUSTOM TEXT B-PAGE

6. THIS DOCUMENT ALSO EXISTS ON E LECTRONIC MEDIA.

SIGNATURE

?

?

3

2.0

ALL POSSIBLE CONFIGURATIONS.
PLEASE REFER TO SPECIFIC PRODUCT PBA EPL FOR
ITEMS S HOWN AS OPTIONAL IN THE SCHEMATIC.

INTEL

D77960-002

DOCUMENT_NUMBER

?

DATE

?

??

?

PB_NUMBER

inte

TITLE

TAWAS_FAB_B

CONFIDENTIAL

D89092

1

APVDDA

TE DATE

S

3065 BOWERS AVE
SANTA CLARA, CA

95051

PAGE

REV

2.0

1/85

1

D

C

B

AA

CR-2 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAG E2

8

7

6

MEROM

45

ON_BOARD BATTERY

3

2

MODULE REV DETAILS

MODULE NAME

1

REV

DATE

ICH8M

USB

SPI

DMI X4

EC

FSB
667/

LPC

800MHZ

CONTROLER

LINK

CK 505

CARD READER
CONTROLLER

PCI

533/667MHZ

533/667MHZ

SO_DIMM0

SO_DIMM1

SATA

HDD

PATA

ODD

CARD READER SLOT

PCIE

WLAN

PCIE

ROBSON/TV

PCIE

EXPRESS CARD SLOT

D

2GB

2GB

C

D

SVIDEO

SVIDEO

VGA

VGA

CRESTLINE

HD AUDIO

VGA

TV

C

SPEAKER

AMP

MUX

MU

X

AUDIO CODEC

HEADPHONE JACK

LCI

GLCI

MICROPHONE JACK

ARRAY MICROPHONE

FLASH

B

RJ11

MDC

B

CIR

RJ45

PORT REPLICATOR

USB 1

TRANSFORMER

SIGNAL

PHY

LED

SPI FLASH

32MBIT

LAN

USB BUS

TOUCH PAD

KEYBOARD

TPM

A

USB

USB USB USB

LRCLRC URCURC

PCIE

PCIE

CAMERA

XPRESS CARD

BLUE TOOTH

FINGER PRINT

A

[PAGE_TITLE=BLOCK DIAGRAM]

BPAGE DRAWING

tawas_b.sch_1.2

Wed Feb 07 17:18:03 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

2

2.0

1

CR-3 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAG E3

VOLTAGE RAILS

POWER PLANE DESCRIPTION
+VBAT

=>

D

V_5P0_STBY\G
VCC
V_3P3_STBY\G

AGE

VOLT
9V-12.5V

5V
5V

3.3V

7

654

3

28

1

S3COLD ACTIVE
S0,S3,S4,S5

S0,S3,S4
S0
S0,S3,S4,S5

BATTERY RAIL IN MOVILE POWER MODE
VR
PERIPHERAL
EC & PERIPHERAL

D

VCC3

V_SM
V1.8S

=>

V_SM_VTT
V_1P5_CORE
V_1P25_CORE
V_1P05_CORE

C

V_GFX

VCC_CORE

=>

THOSE W\ ARROWS ARE NOT CONFIRMED

POWER STATES

STATE

FULL ON

B

S3 (SUSPEND TO RAM)

S4 (SUSPEND TO DISK)

S5 / SOFT OFF

PCI D EVICES

DEVICE
CARD READER

NET NAMING CONVENTIONS

SUFFIX

A

N =ACTIVE LOW SIGNAL

3.3V

1.8V

1.8V

0.9V

1.5V

1.25V

1.05V

0.5V-1.325V

0.5V-1.325V

SIGNAL

IDSEL#

AD18

S0

S0,S3
S0

,S3

S0
S0
S0
S0
S0
S0

SLP_M#

HIGH HIGH

LOW

LOW

SLP_S3#

HIGH

LOW

LOW

LOWLOW

REQ/GNT#
00

REQ/GNT#
A

PERIPHERAL

DDR CORE
CARD READER
DDR PULL UP
CHIPSET POWER RAIL
CHIPSET POWER RAIL
CHIPSET POWER RAIL
CPU CORE RAIL
GFX CORE RAIL

SLP_S4#

HIGH

HIGH

LOW

LOW

SLP_S5#

HIGH

HIGH

LOW

+V*A

ON

ON

OFF

+V*

ONON

ON

OFF

OFF

+V*S

ON

OFF

OFF

OFF

CLOCKS

ON

OFF

OFF

OFF

C

B

A

PREFIX
H=HOST

M =DDR MEMORY
TP=TEST POINT

[PAGE_TITLE=SCH ANNOTATION & BRD INFO

8

7

6

INTEL

CONFIDENTIAL

45

3

2

DOCUMENT NUMBER

PAGE

REV

1

PIN NAME
GP[0]
GP[1]
GP[2]
GP[3]
GP[4]

D

GP[5]
GP[6]
GP[7]
GP[8]
GP[9]
GP[10]
GP[11]
GP[12]
GP[13]
GP[14]
GP[15]
GP[16]
GP[17]
GP[18]
GP[19]
GP[20]

C

GP[21]
GP[22]
GP[23]
GP[24]
GP[25]
GP[26]
GP[27]
GP[28]
GP[29]
GP[30]
GP[31]
GP[32]
GP[33]
GP[34]
GP[35]

B

GP[36]

GP[38]
GP[39]
GP[40]
GP[41]
GP[42]
GP[43]
GP[44]
GP[45]
GP[46]
GP[47]
GP[48]
GP[49]
GP
GP[51]

A

GP[52]
GP[53]
GP[54]
GP[55]

CR-4 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAG E4

8

[50]

WELL
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
RESUME
RESUME
RESUME
RESUME
RESUME
RESUME
RESUME
RESUME
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
RESUME
MAIN
RESUME
RESUME
RESUME
RESUME
RESUME
RESUME
MAIN
MAIN
MAI
MAIN
MAIN
MAINGP[37]
MAIN
MAIN
RESUM
RESUME
RESUME
RESUME
N/A
N/A
N/A
N/A
MAIN
V_CPU_IO
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN

8

TOL.

3.3V

3.3V
5V
5V
5V
5V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

N

3.3V

3.3V

3.3V

3.3V

E

3.3V

3.3V

3.3V

3.3V
N/A
N/A
N/A
N/A

3.3V
V_CPU_IO
5V

3.3V
5V

3.3V
5V

3.3V

PIN#
AG12
AJ8
F8
G11

2

F1
B3
AJ9
AH9
AE16
AG19
AJ24
AG22
AC19
AH21
AF22
AE20
AJ14
AG83.3V
AH12
AJ10
AE1
AJ12
AG10
E6
AJ27
AG18
AH27
AH25
AD16
AG17
AD12
AJ18
AH11
AE10
AG14
AG
AF113.3V
AG11
AF9
AJ11
AG
AG15
AE15
AF15
N/A
N/A
N/A
N/A
AD10
AG29
E18
C18
B19
F18
A11
C10

13

16

1

7

PLTRST

7

DEFAULT

IN

OUT

I/O
I/O

IN

NATIVE

OU

NATIVE

IN
IN
IN
I/O

OUT

IN
IN
IN
IN

OUT
IN

NATIVE

IN

NATIVE
IN
OUT

RIGHT SIDE
FROM DATASHEET

LEFT SID E
FROM SCHEMATIC

USAGE (NETNAME)

IN

BM_BUSY_N

IN

EC_EXTSMI_N
P_INTE_N

IN

P_INTF_N

IN
IN

P_INTG_N

IN

P_INTH_N

IN

HP_AMP_EN

IN

EC_RUNTIME_SCI_N

IN

EC_WAKE_SCI_N

IN

TP

IN

TP
SMB_ALERT_N

IN

GP12_MFG_MODE_N
ENERGY_DET_GPIO13

IN

TP

IN

PM_STPPCI_ICH_N
PM_DPRSLPVR_R

OUT

RF_KILL_N
FWH_TBL_N

IN

BOARD_ID0
PORT_REP_DETECT

OUT

IN

SATA0GP
FWH_WP_N
TP

OUT

TP
PM_STPCPU_ICH_N

T

TP

OUT

TP

OUT

TP
USB_OC5_N
USB_OC6_N
USB_OC7_N
PM_CLKRUN_N

OUT

TP
TP

OUT
OUT

CK_O
BOARD_ID1

IN

BOARD_ID4
TP

IN
IN

BOARD_ID2
USB_O
USB_OC2_N
USB_OC3_N

USB_OC4_N
N/A
N/A
N/A
N/A

IN

BOARD_ID3

H_PWRGD

P_REQ_N<1>

TP

P_REQ_N<2>

TP

P_REQ_N<3>

P_GNT_N<3>

6

E_SATA_N

C1_N

6

45

NOTES

FUNCTIONALITY NUXED WITH GPIO MY NOT BE USED FOR DESKTOP

DETECTS WHETHER PORT REPLICATOR IS CONNECTED

FUNCTIO

NALITY NUXED WITH GPIO MY NOT BE USED FOR DESKTOP

TRISTATED,UNABLE TO ACTIVELY DRIVING HIGH,NEED PULL UP

BPAGE DRAWING

tawas_b.sch_1.4

Wed Feb 07 17:18:04 2007

5

4 2

3

2

MODULE REV DETAILS

MODULE NAME

1

REV

DATE

D

C

B

A

[PAGE_TITLE=GPIO MAP]

PAGE

INTEL

CONFIDENTIAL

3

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

REV

4

2.0

1

CR-5 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE5

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

1

REV

DATE

D

USB PORT

USB_0

USB_1

C

B

USB_2

USB_3

USB_4

USB_5

USB_6

USB_7

SIGNAL NAME

USB_0_DN/DP

USB_1_DN/DP

USB_2_DN/DP

USB_3_DN/DP

USB_4_DN/DP

USB_5_DN/DP

USB_6_DN/DP

USB_7_DN/DP

GOING TO

USB JACK (CHASSIS DN SIG)

USB

USB JACK (CHASSIS UP SIG)

FINGER P (CHASSIS DN SIG)

REPLICATOR PORT

MINIPCIE FOR ROBSON

MINIPCIE FOR WLAN

EXPRESS CARD

JACK (CHASSIS UP SIG)

D

C

B

USB_8

A

8

USB_9

7

6

USB_8_DN/DP

USB_9_DN/DP

5

4 2

BLUETOOTH

CAMERA (INV CONN)

[

BPAGE DRAWING

tawas_b.sch_1.5

Wed Feb 07 17:18:04 2007

3

PAGE_TITLE=USB TABLE]

CONN

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

A

PAGE

REV

5

2.0

1

CR-6 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAG E6

8

D

C

H_STPCLK_N

29

B

IN

A

7

H_A_N<16..3>

10

BI

H_ADSTB0_N

10

BI

H_REQ_N<4..0>

10

BI

H_A_N<35..17>

10

BI

H_ADSTB1_N

10

BI

H_A20M_N

29

IN

H_FERR_N

29

OUT

H_IGNNE_N

29

R

2

R_STPCLK_N

HS_TAWAS

GND_1

GND_2

GND_3

IN

29

IN

29

IN

29

IN

HS20

1OF1

EMPTY

H_INTR
H_NMI

H_SMI_N

TP_CPU_RSVD01
TP_CPU_RSVD02
TP_CPU_RSVD03
TP_CPU_RSVD04
TP_CPU_RSVD05
TP_CPU_RSVD06
TP_CPU_RSVD07
TP_CPU_RSVD08
TP_CPU_RSVD09
TP_CPU_RSVD10

R14P

1

5%

0

CH

402

1

2

3

REV=1

6

U1PR

3
4
5
6
7
8
9
10
11
12
13
14
15
16

0
1
2
3
4

17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35

AA4
AB2
AA3

D22

A[3]#

L5

A[4]#

L4

A[5]#

K5

A[6]#

M3

A[7]#

N2

A[8]#

J1

A[9]#

N3

A[10]#

P5

A[11]#

P2

A[12]#

L2

A[13]#

P4

A[14]#

P1

A[15]#

R1

A[16]#

M1

ADSTB[0]#

K3

REQ[0]#

H2

REQ[1]#

K2

REQ[2]#

J3

REQ[3]#

L1

REQ[4]#

Y2

A[17]#

U5

A[18]#

R3

A[19]#

W6

A[20]#

U4

A[21]#

Y5

A[22]#

U1

A[23]#

R4

A[24]#

T5

A[25]#

T3

A[26]#

W2

A[27]#

W5

A[28]#

Y4

A[29]#

U2

A[30]#

V4

A[31]#

W3

A[32]#
A[33]#
A[34]#
A[35]#

V1

ADSTB[1]#

A6

A20M#

A5

F

ERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD[01]

N5

RSVD[02]

T2

RSVD[03]

V3

RSVD[04]

B2

RSVD[05]

C3

RSVD[06]

D2

RSVD[07]
RSVD[08]

D3

RSVD[09]

F6

RSVD[10]

ADDR GROUP 0

ADDR GROUP 1

PROCHOT#

THERMAL

TH

ERMTRIP#

ICH

HCLK

RESERVED

F4

1O

DEFER#

CONTROL

RESET#
RS[0]#
RS[1]#
RS[2]#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

XDP/ITP SIGNA LS

THERMDA
THERMDC

BCLK[0]
BCLK[1]

MEROM_SKT_NOHS

J4

REV=1

ADS#
BNR#

BPRI#

DRDY#
DBSY#

BR0#

IERR#
INIT#

LOCK#

TRDY#

HIT#

HITM#

PRDY#
PREQ#

TRST#

DBR#

TCK
TDI
TDO
TMS

IC

H1
E2
G5

H5
F21
E1

F1

D20
B3

H4

C1
F3
F4
G3
G2

G6
E4

AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C2

D21
A24
B25

C7

A22
A21

0

45

H_ADS_N
H_BNR_N
H_BPRI_N

H_DEFER_N
H_DRDY_N
H_DBSY_N

H_BREQ_N

H_IERR_N
H_INIT_N

H_LOCK_N

H_CPURST_N

H_RS_N<2..0>

0
1
2

H_TRDY_N

H_HIT_N
H_HITM_N

XDP_BPM_N<4..0>

0
1
2
3
4

XDP_BPM_N<5>
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST_N

XDP_DBRESET_N

H_PROCHOT_N

H_THERMDA
H_THERMDC

PM_THRMTRIP_N

CK_H_CPU_DP
CK_H_CPU_DN

BI
BI
BI

IN
BI
BI

BI

IN

BI
IN

IN

BI
BI

OUT

BI

BI

BI

BI

IN

OUT

OUT

IN
IN

6

50

6

50

IN

24
24

IN

IN

10
10
10

10

10
10

10

29

33

10

10

50

10

10

10
10

50

6

50

50

6

50

31

9
9

12

29

3

1

2

50

XDP_TCK

XDP_TRST_N

V_1P05_CPU

R1PR

56
5%

CH
402

R5PR

1

54.9
1%

CH

2

603

V_1P05_CPU

R11PR

1

68
5%

CH

2

603

R9PR

1

2

54.9

1%

CH

603

R10PR

2

1

649

1%

CH

603

IN

V_1P05_CPU

R4PR

1

54.9
1%

CH
603

678

50 79

2

MODULE REV DETAILS

NAME

MODULE

TAWAS_CORE

1

V

RE

1.02.01 2-05-07

E

DAT

D

678

50 79

IN

R2PR

1

54.9
1%

CH

22

603

C

50

OUT

50

IN

50

678

50 79

IN

77

BI

IN

B

A

BPAGE DRAWING

tawas_b.sch_1.6

Wed Feb 07 17:18:05 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

6

2.0

1

[PAGE_TITLE=CPU (1 OF 3)]

CR-7 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAG E7

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

TAWAS_CORE

1

REV

DATE

2-05-071. 02.01

D

U1PR

ROM_SKT_NOHS

BI

C

H_DSTBN_N<0>

10

BI

H_DSTBP_N<0>

10

BI

H_DINV_N<0>

10

BI

10

BI

B

H_DSTBN_N<1> H_DSTBN_N<3>

10

BI

H_DSTBP_N<1>

10

BI

H_DINV_N<1>

10

BI

H_GTLREF

7

IN

CPU_TEST1

7

IN

CPU_TEST2

7

IN

CPU_TEST4

7

IN

CPU_BSEL0

23

OUT

CPU_BSEL1

23

OUT

CPU_BSEL2

23

A

OUT

TP_CPU_TEST3

TP_CPU_TEST5
TP_CPU_TEST6

E22

0

F24

1

E26

2

G22

3

F23

4

G25

5

E25

6

E23

7

K24

8

G24

9

J24

10

J23

11

H22

12

F26

13

K22

14

H23

15

J26
H26
H25

N22

16

K25

17

P26

18

R23

19

L23

20

M24

21

L22

22

M23

23

P25

24

P23

25

P22

26

T24

27

R24

28

L25

29

T25

30

N25

31

L26
M26
N24

AD26

C23
D25
C24

AF26

AF1
A26

B22
B23
C21

ME

D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#

D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#

GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6

BSEL[0]
BSEL[1]
BSEL[2]

REV=1

DATA GRP 0

DATA GRP 2DATA GRP 3

DSTBN[2]#
DSTBP[2]#

DATA GRP 1

DSTBN[3]#
DSTBP[3]#

MISC

2OF4

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#

DINV[2]#

D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#

DINV[3]#

COMP[0]
COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

IC

SLP#
PSI#

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

R26
U26
AA1
Y1

E5
B5
D24
D6
D7
AE6

32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47

48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

H_D_N<47..32>H_D_N<15..0>

H_DSTBN_N<2>
H_DSTBP_N<2>
H_DINV_N<2>

H_D_N<63..48>H_D_N<31..16>

H_DSTBP_N<3>
H_DINV_N<3>

COMP0
COMP1
COMP2
COMP3

H_DPRSTP_N
H_DPSLP_N
H_DPWR_N
H_PWRGD
H_CPUSLP_N
H_PSI_N

OUT

1010

BI

10

BI

10

BI

10

BI

10

BI

10

BI

10

BI

10

BI

7

IN

7

IN

7

IN

7

IN

12

29

BI
BI
BI

IN

77
29
10

10

R8PR

77

1

1KCH5%

402

H_PWRGD_XDP

2

29

BI

50

BI

7

OUT

5079

7

IN

7

IN

7

IN

7

IN

7

IN

7

IN

CPU_TEST4

68

IN

COMP0

COMP1

COMP2

COMP3

CPU_TEST1

CPU_TEST2

V_1P05_CPU

C1PR

1

10%

.1UF

16V

EMPTY

603

2

1

R15PR

1K
1%

CH

2

603

R16PR

1

2K
1%

CH

2

603

R17PR

1

27.41%
603

R18PR

1

54.9CH1%
603

R19PR

1

27.4
603

R3PR

1

54.9
603

R6PR

1

1K

6031%EMPTY

1

R7PR

1K

EMPTY603

H_GTLREF

OUT

7

2

CH

2

2

1%
CH

2

1%
CH

2

2

1%

D

C

B

A

BPAGE DRAWING

tawas_b.sch_1.7

Wed Feb 07 17:18:07 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

7

2.0

1

[PAGE_TITLE=CPU (2 OF 3)]

CR-8 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAG E8

8

D

C

B

VCCP

8717879

IN IN

A10
A12
A13
A15
A17
A18
A20

B10
B12
B14
B15
B17
B18
B20

C10
C12
C13
C15
C17
C18

D10
D12
D14
D15
D17
D18

E10
E12
E13
E15
E17
E18
E20

F10
F12
F14
F15
F17
F18
F20
AA7

AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20

AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18

A7
A9

B7
B9

C9

D9

E7
E9

F7
F9

A

7

U1PR

MEROM_SKT_NOHS

VCC[001]

VCC[068]

VCC[002]

VCC[069]
VCC[070]

VCC[003]

VCC[071]

VCC[004]

VCC[072]

VCC[005]

VCC[073]

VCC[006]

VCC[074]

VCC[007]

VCC[075]

VCC[008]

VCC[076]

VCC[009]

VCC[077]

VCC[010]

VCC[078]

VCC[011]

VCC[079]

VCC[012]

VCC[080]

VCC[013]

VCC[081]

VCC[014]

VCC[082]

VCC[015]
VCC[016]

VCC[083]

VCC[017]

VCC[084]

VCC[018]

VCC[085]

VCC[019]

VCC[086]

VCC[020]

VCC[087]

VCC[021]

VCC[088]
VCC[089]

VCC[022]

VCC[090]

VCC[023]

VCC[091]

VCC[024]

VCC[092]

VCC[025]

VCC[093]

VCC[026]

VCC[094]

VCC[027]

VCC[095]

VCC[028]

VCC[096]

VCC[029]

VCC[097]

VCC[030]

VCC[098]

VCC[031]

VCC[099]

VCC[032]

VCC[100]

VCC[033]
VCC[034]
VCC[035]

VCCP[01]
VCCP[02]

VCC[036]

VCCP[03]

VCC[037]

VCCP[04]

VCC[038]

VCCP[05]

VCC[039]

VCCP[06]

VCC[040]

VCCP[07]

VCC[041]

VCCP[08]

VCC[042]

VCCP[09]

VCC[043]

VCCP[10]

VCC[044]

VCCP[11]

VCC[045]

VCCP[12]

VCC[046]

VCCP[13]

VCC[047]

VCCP[14]

VCC[048]

VCCP[15]

VCC[049]

VCCP[16]

VCC[050]
VCC[051]

VCCA[01]

VCC[052]

VCCA[02]

VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]

REV=1

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VCCSENSE

VSSSENSE

3OF4

6

62

H_

VID<6..0>

VCCP

2329

32

678

OUT

5079

1

C2PR

220U
20%

2.5V
TANT

2

SM

1

77 79

OU

T

2

1

2

8

16

1718

V_1P05_CPU

V_1P05_CPU

F

C3PR

.01UF
10%
25V

R

X7
402

R13PR

100
1%

EMPTY
402

78

71

79

1415

10
63

71

77

V_1P5_CORE

1

C4PR

10.0UF
20%

6.3V

2

X5R
1206

1

2

IN

R12PR

100
1%

EMPTY
402

V_1P05_CORE

68

IN

1832373940

16

IN

VCCP

VCC_SENSE

VSS_SENSE

FB1PR

1

1

7

FB2PR

N

UNK
330

1.5A
BROAD

2

FB

UNK
330

1.5A
BROAD

2

FB

50 79

IN

OUT

OUT

N

77

77

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6

0

AF5

1

AE5

2

AF4

3

AE3

4

AF3

5

AE2

6

AF7

AE7

IC

62 64

87178 79

45

71

3

U1

ME

ROM_SKT_NOHS

VSS[001]

VSS[082]
VSS[083]

VSS[002]

VSS[084]

VSS[003]

VSS[085]

VSS[004]
VSS[005]

VSS[086]

VSS[006]

VSS[087]
VSS[088]

VSS[007]
VSS[008]

VSS[089]

VSS[009]

VSS[090]

VSS[010]

VSS[091]

VSS[011]

VSS[092]
VSS[093]

VSS[012]
VSS[013]

VSS[094]

VSS[014]

VSS[095]

VSS[015]

VSS[096]
VSS[097]

VSS[016]

VSS[098]

VSS[017]

VSS[099]

VSS[018]
VSS[019]

VSS[100]
VSS[101]

VSS[020]

VSS[102]

VSS[021]

VSS[103]

VSS[022]

VSS[104]

VSS[023]

VSS[105]

VSS[024]

VSS[106]

VSS[025]

VSS[107]

VSS[026]

VSS[108]

VSS[027]

VSS[109]

VSS[028]

VSS[110]

VSS[029]

VSS[111]

VSS[030]

VSS[112]

VSS[031]

VSS[

VSS[032]

VSS[114]

VSS[033]

VSS[115]

VSS[034]

VSS[116]

VSS[035]

VSS[117]

VSS[036]

VSS[118]

VSS[037]

VSS[119]

VSS[038]

VSS[120]

VSS[039]

VSS[121]

VSS[040]

VSS[122]

VSS[041]
VSS[042]

VSS[123]

VSS[043]

VSS[124]
VSS[125]

VSS[044]

VSS[126]

VSS[045]

VSS[127]

VSS[046]

VSS[128]

VSS[047]

VSS[129]

VSS[048]

VSS[130]

VSS[049]

VSS[131]

VSS[050]

VSS[132]

VSS[051]

VSS[133]

VSS[052]

VSS[134]

VSS[053]

VSS[135]

VSS[054]

VSS[136]

VSS[055]

VSS[137]

VSS[056]

VSS[138]

VSS[057]

VSS[139]

VSS[058]

VSS[140]

VSS[059]

VSS[141]

VSS[060]

VSS[142]

VSS[061]

VSS[143]

VSS[062]

VSS[144]

VSS[063]

VSS[145]

VSS[064]

VSS[146]

VSS[065]

VSS[147]

VSS[066]
VSS[067]

VSS[148]
VSS[149]

VSS[068]

VSS[150]

VSS[069]

VSS[151]

VSS[070]

VSS[152]

VSS[071]

VSS[153]

VSS[072]

VSS[154]

VSS[073]
VSS[074]

VSS[155]

VSS[075]

VSS[156]

VSS[076]

VSS[157]

VSS[077]

VSS[158]

VSS[078]

VSS[159]

VSS[079]

VSS[160]

VSS[080]

VSS[161]

VSS[081] VSS[162]

VSS[163]

PR

113]

2

MODULE REV DETAILS

MODULE NAME

TAWAS_CORE

REV

CAD NOTE:

PLACE ON TOP SIDE IN

CPU CAVITY

V_1P05_CPU

C5PR

.1

UF
10%
16V
X7R
603

C7PR

.1UF
10%
16V
X7R
603

C9PR

.1UF
10%
16V
EMPTY
603

1

C6PR

.1UF
10%
16V

2

X7R
603

1

C8PR

.1UF
10%
16V

2

R

X7
603

1

C10PR

.1UF
10%
16V

2

EMPTY
603

1

2

1

2

1

2

CAD NOTE:

PLACE ON TOP SIDE SOUTH OF

CPU

1

DATE

2-05-071. 02.01

D

6

7

IN

8

50 79

C

B

A

4OF4

REV=1

IC

[PAGE_TITLE=CPU (3 OF 3)]

8

7

6

5

4 2

BPAGE DRAWING

tawas_b.sch_1.8

Thu Feb 08 10:56:06 2007

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

8

2.0

1

CR-9 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAG E9

8

7

6

45

3

VCC3

2

MODULE REV DETAILS

MODULE NAME

1

REV

DATE

VCC3

D

R25

10K

5%

R27

1

H_THERMDA

6

OUT

H_THERMDC

6

IN

499
603

R28

1

499CH1%
603

2

1%

CH

1

C6

1000P

F
10%
50V

2

X7R
603

2

CH
402

ADT_THERM_DXP

ADT_THERM_DXN

ADT_THM_N

U2

ADM1032

2

D+

3

D-

4

THERM*

5

GN

SCLK

SDATA

ALERT*

D

VDD

IC

1

8
7

THRM_ALERT_N

6

1

C5

0.

1UF
20%
16V

2

Y5V
402

1

R26

10K
5%

CH
402

2

1

R24

10K

5%
CH

402

2

SMB_THRM_CLK

SMB_THRM_DATA

1

2

R29

1A

0

EM

603

PTY

PM

_THRM_N

OUT

55

BI

55

BI

33

31

C

D

C

V_3P3_STBY\G

1

R45

10K
5%

2

CH
402

CPU_FAN_TACH

B

26

3233

45616265666869

707576777883

IN

V_5P0_STBY\G

R460BU

10K

5%
CH

402

1

1

C93

.1

UF
10%
10V

2

2

X5R
402

CPU_FAN_PWM_N

C94

4.7UF
10%

6.3V
EMPTY
603

1

C943

1UF

20%

16V

2

Y5V
805

OUT

A36295-007

J39

1X3HDR

1
2
3

HDR

IN

55

31

32 333740 44 50 52

22 26
54 55 56 65 67 68 69 72 75 77

B

3

Q100

D

A

CPU_FAN_PWM

55

IN

1

BSS138N

FET

S

G

2

A

[PAGE_TITLE=CPU THERMAL MONITORS AND FAN]

BPAGE DRAWING

tawas_b.sch_1.9

Thu Feb 08 17:24:51 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

9

2.0

1

CR-10 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE10

8

7

6

45

3

U1UB

H_D_N<63..0>

7

D

77

32

2329

15

16

17

18

6263

71

V_1P05_CORE

81014

IN

H_RCOMP

10

OUT

C

1

24.9
603

1

54.
402

1

54.
402

R34UB

R35UB

9

R36UB

9

2

1%
CH

1%
CH

2

1%

CH

H_SCOMP

2

H_SCOMP_N

OUT

OUT

10

10

BI

COMPS

V_1P05_CORE

161718

2329

32

B

A

8101415

IN

6263

7177

32

1

R32UB

221
1%

CH

2

603

1

R33UB

100
1%

2

CH
603

15

16

17

182329

71

77

H_SWING

1

C49UB

0.1UF
20%
16V

2

Y5V
402

V_1P05_CORE

8

1014

IN

6263

OUT

1

2

10

R37UB

1K
1%

CH
603

10
10

10
10

50

H_SWING

IN

H_RCOMP

IN

H_SCOMP

IN

H_SCOMP_N

IN

H_CPURST_N

6

OUT

H_CPUSLP_N

7

OUT

H_VREF

1

2

R38UB

2K

1%

CH
603

1

C53UB

.1UF
10%
10V

2

X5R
402

E2

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

AD12

32
33
34
35
36

AC14

37

AD11

38

AC11

39
40
41
42
43
44
45
46
47
48
49

AJ14

50
51

AE11

52

AH12

53
54
55
56
57
58
59
60
61
62

AH13

63

M10
N12

P13

W10

AE3
AD9
AC9
AC7

AB2
AD7
AB1

AC6
AE2
AC5
AG3
AJ9
AH8

AE9

AJ5
AH5
AJ6
AE7
AJ7
AJ2
AE5
AJ3
AH2

H_D#_0

G2

H_D#_1

G7

H_D#_2

M6

H_D#_3

H7

H_D#_4

H3

H_D#_5

G4

H_D#_6

F3

H_D#_7

N8

H_D#_8

H2

H_D#_9
H_D#_10
H_D#_11

N9

H_D#_12

H5

H_D#_13
H_D#_14

K9

H_D#_15

M2

H_D#_16
H_D#_17

Y8

H_D#_18

V4

H_D#_19

M3

H_D#_20

J1

H_D#_21

N5

H_D#_22

N3

H_D#_23

W6

H_D#_24

W9

H_D#_25

N2

H_D#_26

Y7

H_D#_27

Y9

H_D#_28

P4

H_D#_29

W3

H_D#_30

N1

H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42

Y3

H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63

B3

H_SWING

C2

H_RCOMP

W1

H_SCOMP

W2

H_SCOMP#

B6

H_CPURST#

E5

H_CPUSLP#

B9

H_AVREF

A9

H_DVREF

HOST

BPAGE DRAWING

Wed Feb 07 17:18:09 2007

CRESTLINE 1.0

8

7

6

5

4 2

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#

H_ADSTB#_0
H_ADSTB#_1

H_BNR#
H_BPRI#
H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#
H_DRDY#

H_HIT#
H_HITM#
H_LOCK#
H_TRDY#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DS

TBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

H_RS#_0
H_RS#_1
H_RS#_2

1OF10

tawas_b.sch_1.10

3

J13
B11
C11
M11
C15
F16
L13
G17

#_10

C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D1

7
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19

G12
H17
G20
C8
E8
F12
D6
C10
AM5
AM7
H8
K7
E4
C6
G10
B7

K5
L2
AD13
AE13

M7
K3
AD2
AH11

L7
K2
AC2
AJ10

M14
E13
A11
H13
B12

E12
D7
D8

IC

[PAGE_TITLE=GMCH (1 OF 8)]

2

H_A_N<35..3>

3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29

30

31

32

33

34

35

H_ADS_N

H_ADSTB0_N

H_ADSTB1_N

H_BNR_N
H_BPRI_N
H_BREQ_N
H_DEFER_N

H_DBSY_N
CK_H_MCH_DP
CK_H_MCH_DN

H_DPWR_N

H_DRDY_N

H_HIT_N

H_HITM_N

H_LOCK_N

H_TRDY_N

H_DINV_N<3..0>

0
1
2

3

H_DSTBN_N<3..0>

0
1
2

3

H_DSTBP_N<3..0>

0
1
2

3

H_REQ_N<4..0>

0
1
2

3

4

H_RS_N<2..0>

0
1
2

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

1

MODULE REV DETAILS

MODULE NAME

TAWAS_CORE

BI

BI
BI
BI
BI

OU

T

BI

OUT

BI
IN
IN

OUT

BI
BI
BI
IN

OUT

BI

BI

BI

BI

OUT

DOCUMENT_NUMBER

1.02.01 2-05-07

6

6
6
6
6
6
6
6
6

24
24
7

6

6

6

6
6

7

7

7

6

6

D89092

REV

PAGE

10

1

DATE

REV

2.0

D

C

B

A

D

C

B

A

28

28

CR-11 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE11

8

_BKLTCTL

L

26

OUT

L_BKLTEN

26

OUT

L_CTRL_CLK

1226

OUT

L_CTRL_DATA

1226

OUT

L_DDC_CLK

26

BI

L_DDC_DATA

26

BI

26

R41UB

1

R43UB

1

150
402

OUT
OUT
OUT

46UB

R

1

25
25

1%
CH

2

1%

CH

26
26
26
26

26
26
26

26
26
26

26
26
26

26
26
26

2

1%
CH

2

BI
BI

OUT

LVDS_IBG

BI
BI
BI
BI

BI
BI
BI

BI
BI
BI

BI
BI
BI

BI
BI
BI

27

OUT

27

OUT

27

OUT

R42UB

1

150
402

CRT_DDC_CLK
CRT_DDC_DATA

402

1.3KCH1%
603

402

CRT_BLUE
CRT_GREEN
CRT_RED

R48UB

1

39

R47UB

1

R49UB

1

39

R63UB

2

1

2.

1%

43K

CH

402

BOM NOTE:

MOD TO 2.37K OHM 1%
IPN A93548-283

150
402

28
28
28

R44UB

2

1

1%

150

CH

402

150

402

R45UB

2

1

1%

150

CH

402

CRT_HSYNC

OUT

CRT_VSYNC

OUT

8

R40UB

L_VDDEN

1

0
603

TP_LVDS_VBG

LA_CLK_DN
LA_CLK_DP
LB_CLK_DN
LB_CLK_DP

LA_DATA0_DN
LA_DATA1_DN
LA_DATA2_DN

LA_DATA0_DP
LA_DATA1_DP
LA_DATA2_DP

LB_DATA0_DN
LB_DATA1_DN
LB_DATA2_DN

LB_DATA0_DP
LB_DATA1_DP
LB_DATA2_DP

TVA_DAC
TVB_DAC
TVC_DAC

2

1%

CH

HSYNC

2

5%
CH

CRTIREF

2

VSYNC

2

5%
CH

2

1A
CH

7

L_VDD_EN_R

7

6

U1UB

CRESTLINE 1.0

J40

L_BKLT_CTRL

H39

L_BKLT_EN

E39

L_CTRL_CLK

E40

L_CTRL_DATA

C37

L_DDC_CLK

D35

L_DDC_DATA

K40

L_VDD_EN

L41

LVDS_IBG

L43

LVDS_VBG

N41

LVDS_VREFH

N40

LVDS_VREFL

D46

LVDSA_CLK#

C45

LVDSA_CLK

D44

LVDSB_CLK#

E42

LVDSB_CLK

G51

LVDSA_DATA#_0

E51

LVDSA_DATA#_1

F49

LVDSA_DATA#_2

G50

LVDSA_DATA_0

E50 L50

LVDSA_DATA_1

F48

LVDSA_DATA_2

G44

LVDSB_DATA#_0

7

B4

LVDSB_DATA#_1

B45

LVDSB_DATA#_2

E44

LVDSB_DATA_0

A47

LVDSB_DATA_1

A45

LV

DSB_DATA_2

E27

TVA_DAC

G27

TVB_DAC

K27

TVC_DAC

F27

TVA_RTN

J27

TVB_RTN

L27

TVC_RTN

M35

TP_TV_DCONSEL_0

TP_TV_DCONSEL_1

P33

H32
G32
K29
J29
F29
E29

K33
G3
F33
C32
E33

5

TV_DCONSEL_0
TV_DCONSEL_1

CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#

CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
CRT_VSYNC

LVDS

TV

VGA

PEG_COMPI
PEG_COMPO

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8

PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

PCI-EXPRESS GRAPHICS

PEG_RX_10

PEG_RX_11

PEG_RX_12

PEG_RX_13

PEG_RX_14

PEG_RX_15

PEG_TX#_0

PEG_TX#_1

PEG_TX#_2

PEG_TX#_3

PEG_TX#_4

PEG_TX#_5

PEG_TX#_6

PEG_TX#_7

PEG_TX#_8

PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

PEG_TX_10

PEG_TX_11

PEG_TX_12

PEG_TX_13

PEG_TX_14

PEG_TX_15

3OF10

6

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9

PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9

45

R39UB

2

VCC_PEG

16

17

IN

N43

PEG_COMP

M43

TP_PEG_RX_N<0>

J51

TP_PEG_RX_N<1>

L51

TP_PEG_RX_N<2>

N47

TP_PEG_RX_N<3>

T45

TP_PEG_RX_N<4>

T50

TP_PEG_RX_N<5>

U40

TP_PEG_RX_N<6>

Y44

TP_PEG_RX_N<7>

Y40

TP_PEG_RX_N<8>

AB51

TP_PEG_RX_N<9>

W49

TP_PEG_RX_N<10>

AD44

TP_PEG_RX_N<11>

AD40

TP_PEG_RX_N<12>

AG46

TP_PEG_RX_N<13>

AH49

TP_PEG_RX_N<14>

AG45

TP_PEG_RX_N<15>

AG41

TP_PEG_RX<0>

J50

TP_PEG_RX<1>
TP_PEG_RX<2>

M47

TP_PEG_RX<3>

U44

TP_PEG_RX<4>

T49

TP_PEG_RX<5>

T41

TP_PEG_RX<6>

W45

TP_PEG_RX<7>

W41

TP_PEG_RX<8>

AB50

TP_PEG_RX<9>

Y48

TP_PEG_RX<10>

AC45

TP_PEG_RX<11>

AC41

TP_PEG_RX<12>

AH47

TP_PEG_RX<13>

AG49

TP_PEG_RX<14>

AH45

TP_PEG_RX<15>

AG42

TP_P_TXN0

N45
U39

TP_P_TXN1
TP_P_TXN2

U47
N51

TP_P_TXN3

R50

TP_P_TXN4

T42

TP_P_TXN5

Y43

TP_P_TXN6

W46

TP_P_TXN7
TP_P_TXN8

W38

TP_P_TXN9

AD39
AC46

TP_P_TXN10
TP_P_TXN11

AC49

TP_P_TXN12

AC42

TP_P_TXN

AH39
AE49
AH44

M45
T38
T46
N50
R51
U43
W42
Y47
Y39
AC38
AD47
AC50
AD43
AG39
AE50
AH43

TP_P_TXN14
TP_P_TXN15

TP_P_TXP0
TP_P_TXP1
TP_P_TXP2
TP_P_TXP3
TP_P_TXP4
TP_P_TXP5
TP_P_TXP6
TP_P_TXP7
TP_P_TXP8
TP_P_TXP9
TP_P_TXP10
TP_P_TXP11
TP_P_TXP12
TP_P_TXP13
TP_P_TXP14
TP_P_TXP15

13

1

9

1%

24.
CH

603

61

71

IC

3

1

R52UB

1K
1%

CH
603

2

1

R54UB

3.

24K

1%
CH

603

2

1

R55UB

1K
1%

CH
603

2

V_SM SM_RCOMP

11

12

14

15

1617

1920

IN

SM_RCOMP_N

12

OUT

2

V_SM

BOM NOTE:

MOD TO 3.01K OHM 1%

IPN A93550-095

1

C57UB

.01UF
10%

25V

2

X7R
402

MODULE REV DETAILS

MODULE NAME

TAWAS_CORE

111214 151617

IN

SM_RCOMP_VOH

1

1

2

C54UB

.01UF

10%
25V
X7R
402

2

C55UB

2.2UF
10%

6.

X5R
603

SM_RCOMP_VOL

1

C58UB

2.2UF
10%

6.3V

2

X5R
603

1

2

R61UB

1%

20

CH

402

R62UB

1

2021%

402

CH

1

REV

1.02.01 2-05-07

12

OUT

3V

12

OUT

DATE

19 206171

12

OUT

D

C

B

A

[PAGE_TITLE=GMCH (2 OF 8)]

BPAGE DRAWING

tawas_b.sch_1.11

Wed Feb 07 17:18:10 2007

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

11

2.0

1

CR-12 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE12

8

11

14

ORE

ORE

15161719

19

20

61

11
11

11
11
20

21

19

21

20

21

19

21

20

21

19

21

20
20
19
19

20
20
19
19

1

R3UB

4.7K
5%

EMPTY

2

402

1

R4UB

4.
5%

2

EM
402

20

6171

D

C

71

V_1P25_C

12

1617

IN

18

32

68

CK_96M_DREF_DN

1224

IN

CK_96M_DREF_DP

1224

IN

B

71

V_1P25_C

12

16

17

IN

68

1832

1

2

CK_DREF_100M_SS_DN

12

24

IN

CK_DREF_100M_SS_DP

12

24

IN

1

VCC3

A

R67UB

10K
402

R68UB

10K
402

R69UB

10K
402

R70UB

10K
402

R71UB

10K
402

1

1

1

1

1

2

CK_

5%
CH

PM_EXTTS0_N

2

5%
CH

PM_EXTTS1_N

2

5%
CH

L_CTRL_CLK

2

5%
CH

2

L_CTRL_DATA

5%
CH

2

OE_MCH_N

8

V_SM

IN

DDR_REF

IN

IN
IN

IN
IN

BI
BI

BI
BI

BI
BI

M_CLK_DDR_DN<4>

OUT

M_CLK_DDR_DN<3>

OUT

M_CLK_DDR_DN<1>

OUT

M_CLK_DDR_DN<0>

OUT

M_CLK_DDR_DP<4>

OUT

M_CLK_DDR_DP<3>

OUT

M_CLK_DDR_DP<1>

OUT

M_CLK_DDR_DP<0>

OUT

7K

PTY

R6

UB

4.

7K

5%
EMPTY

402

R7UB

4.7K
5%

EMPTY
402

12

IN

121921

IN

12

IN

11

IN

11

IN

7

SM_RCOMP_VOL
SM_RCOMP_VOH

SM_RCOMP_N
SM_RCOMP
M_ODT<3..2>

M_ODT<1..0>

M_CS_N<3..2>

M_CS_N<1..0>

M_CKE<4..3>

M_CKE<1..0>

U1UB

24

20

21

26

26

7

CRESTLINE 1.0

6

R73UB

1

2

1K

1%

EMPTY

402

R74UB

1

2

1K1%

EMPTY

402

2

1

0

3

4

1

0

BD39

BG37

BG20

BK16

BG16

AV23

BA25

BB23

AV29

SM_CK_0

SM_CK_4

SM_CK_1

SM_CK_3

AY32

AW30

AW25

BA23

BE29

AW23

SM_CK#_4

SM_CK#_0

SM_CK#_1

SM_CK#_3

SM_CKE_0

SM_CKE_1

SM_CKE_3

SM_CKE_4

SM_CS#_0

SM_CS#_1

DDR

MUXING

R27UB

2

5%CH0

3

BE13

SM_CS#_2

SM_CS#_3

1

402

2

1

0

BJ14

BJ15

BH18

SM_ODT_0

SM_ODT_1

SM_ODT_2

SM_MCH_VREF

3

BK31

BL15

BE16

BK14

SM_ODT_3

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH

L31
B

SM_RCOMP_VOL

H48

K44

H47

C42

AW4

B42

AR49

PEG_CLK

SM_VREF_0

SM_VREF_1

PEG_CLK#

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

CLK

RSVD

RSVD1

RSVD2

RSVD3

RSVD4

P37

R35

N35

P36

TP_MCH_RSVD_1

TP_MCH_RSVD_2

TP_MCH_RSVD_4

TP_MCH_RSVD_3

RSVD11

RSVD10

RSVD12

RSVD5

RSVD6

AR13

AR12

TP_MCH_RSVD_6

TP_MCH_RSVD_5

RSVD13

RSVD7

RSVD8

RSVD9

RSVD14

37

J12

D20

AN13

AM12

AR37

AL36

AM36

AM

TP_MCH_RSVD_14

TP_MCH_RSVD_11

TP_MCH_RSVD_10

TP_MCH_RSVD_9

TP_MCH_RSVD_8

TP_MCH_RSVD_7

TP_MCH_RSVD_12

TP_MCH_RSVD_13

23

BI

23

BI

23

BI

RSVD21

RSVD20

H10

B51

TP_MCH_RSVD_21

TP_MCH_RSVD_20

MCH_BSEL0
MCH_BSEL1
MCH_BSEL2

RSVD22

RSVD23

RSVD24

RSVD25

RSVD26

RSVD27

RSVD28

BF23

BJ20

BF19

BJ18

BK18

BH20BK22

P_MCH_RSVD_26

P_MCH_RSVD_23

T

TP_MCH_RSVD_25

T

TP_MCH_RSVD_28

TP_MCH_RSVD_27

TP_MCH_RSVD_24

TP_MCH_RSVD_22

SVD35

RSVD31

RSVD30

RSVD32

RSVD33

RSVD29

RSVD34

BH39

BE24

BJ29

BG23

BC23

BD24

TP_MCH_RSVD_33

TP_MCH_RSVD_32

TP_MCH_RSVD_34

TP_MCH_RSVD_29

TP_MCH_RSVD_30

TP_MCH_RSVD_31

RSVD41

R

RSVD36

RSVD42

RSVD43

RSVD44

RSVD37

RSVD38

D47

C48

BK20

AW20

TP_MCH_RSVD_38

TP_MCH_RSVD_35

TP_MCH_RSVD_36

TP_MCH_RSVD_37

RSVD45

RSVD39

RSVD40

A35

B37

B34 K45

C44

B36

C34

B44

TP_MCH_RSVD_42

TP_MCH_RSVD_41

TP_MCH_RSVD_40

TP_MCH_RSVD_39

TP_MCH_RSVD_45

TP_MCH_RSVD_44

TP_MCH_RSVD_43

[PAGE_TITLE=GMCH (3 OF 8)]

6

5

45

CK_96M_DREF_DP

_96M_DREF_DN

CK
CK_DREF_100M_SS_DP
CK_DREF_100M_SS_DN
CK_PE_100M_3GPLL_DP
CK_PE_100M_3GPLL_DN

303030

30

OUT

OUT

OUT

OUT

DMI_IT_MR_0_DN

DMI_IT_MR_3_DN

DMI_IT_MR_2_DN

DMI_IT_MR_1_DN

AN47

AN46

AN42

AJ38

DMI_RXN_0

DMI_RXN_1

DMI_RXN_2

DMI_RXN_3

303030

30

OUT

OUT

OUT

OUT

DMI_IT_MR_3_DP

DMI_IT_MR_2_DP

DMI_IT_MR_1_DP

DMI_IT_MR_0_DP

AN41

AJ39

AN45

AM47

DMI_RXP_0

DMI_RXP_1

DMI_RXP_2

DMI_RXP_3

30

303030

OUT

OUT

OUT

OUT

DMI_MT_IR_1_DN

DMI_MT_IR_3_DN

DMI_MT_IR_2_DN

DMI_MT_IR_0_DN

AM40

AJ41

AM44

AJ46

DMI_TXN_0

DMI_TXN_1

DMI_TXN_2

DMI_TXN_3

303030

30

OUT

OUT

DMI_MT_IR_1_DP

DMI_MT_IR_2_DP

DMI_MT_IR_0_DP

AM39

AJ42

AJ47

DMI_TXP_0

DMI_TXP_1

DMI_TXP_2

DMI

CFG

CFG_1

CFG_3

CFG_4

CFG_2

CFG_0

C23

N27

P27

C21

N24

TP_MCH_CFG_4

TP_MCH_CFG_3

4 2

CFG_5

CFG_6

CFG_7

CFG_8

CFG_9

CFG_10

L23

C20

G23

F23

R24

J20

N23

TP_MCH_CFG_7

TP_MCH_CFG_6

TP_MCH_CFG_10

TP_MCH_CFG_11

TP_MCH_CFG_8

Wed Feb 07 17:18:11 2007

CFG_11

3

6870

12

24

IN

12

24

IN

12

24

IN

12

24

IN

24

IN

24

IN

OUT

OUT

DMI_MT_IR_3_DP

AM43

DMI_TXP_3

G

RAPHICS VID

CFG_12

CFG_13

E23

J23

BPAGE DRAWING

tawas_b.sch_1.12

CFG_20

CFG_14

CFG_15

CFG_16

CFG_17

CFG_18

CFG_19

K23

L35

L32

M20

M24

N33

E20

TP_MCH_CFG_14

TP_MCH_CFG_15

TP_MCH_CFG_17

TP_MCH_CFG_18

3

V_1P25_M

1617

IN

3

210

B39

A39

E36

C38

E35

GFX_VID_0

GFX_VID_1

GFX_VID_2

GFX_VID_3

GFX_VR_EN

PM NC

PM_EXT_TS#_0

PM_EXT_TS#_1

PWROK

RSTIN#

PM_DPRSTP#

THERMTRIP#

L39

L36

J36

DPRSLPVR

N20

G36

AV20

AW49

RST_IN_MCH+_N

100
402

PM_BM_BUSY#

G41

2

R51UB

1

1K
1%

CH

2

402

1

C56UB

.1UF
10%
16V

2

X7R
603

R9UB

1

0

402

CLPWROK_MCH_R

AM50

AM49

AN49

AK50

AT43

CL_CLK

CL_DATA

CL_RST#

CL_VREF

CL_PWROK

ME

NC_1

NC_2

NC_4

NC_5

NC_3

BL50

BK50

BL49

BJ51

BK51

TP_MCH_NC3

TP_MCH_NC5

TP_MCH_NC2

TP_MCH_NC1

TP_MCH_NC4

H_DPRSLPVR

PM_THRMTRIP_N

R50UB

PLTRST_N

2

1

DELAY_VR_PWRGOOD

5%

PM_EXTTS1_N

CH

PM_EXTTS0_N
H_DPRSTP_N
PM_BMBUSY_N
MCH_CFG_20
MCH_CFG_19

MCH_CFG_16

MCH_CFG_13
MCH_CFG_12
MCH_CFG_9
MCH_CFG_5

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

MODULE REV DETAILS

NAME

MODULE

TAWAS_CORE

MCH_CLVREF

1

R53UB

390
5%

BOM NOTE:

2

CH

REPLACE R53UB WIT H 392 OHM A93550-408

603

G_VID<3..0>

INT_GFX_ENABLE

CL_CLK0

CL_DATA0

CLPWROK

2

5%

CL_RST0_N

CH

MCH_CLVREF

H35K36

G39

G40

CLK_REQ#

ICH_SYNC#

SDVO_CTRL_CLK

SDVO_CTRL_DATA

MI

SC

NC_6

NC_7

NC_8

NC_9

NC_11

NC_10

NC_12

E1

BJ1A5C51

BK1

BL3

BL2

TP_MCH_NC11

TP_MCH_NC10

TP_MCH_NC8

TP_MCH_NC12

TP_MCH_NC6

TP_MCH_NC7

TP_MCH_NC9

IN

TP_SDVO_CTRLCLK

TP_SDVO_CTRLDATA

CK_OE_MCH_N

MCH_ICH_SYNC_N

MCH_TEST1_R

MCH_TEST2_R

A37

R32

1

2

IC

TEST_1

2OF10

NC_13

NC_14

NC_15

NC_16 TEST_2

BK2

B50

A50

A49

TP_MCH_NC13

TP_MCH_NC15

TP_MCH_NC14

TP_MCH_NC16

31

IN

6

OUT

34 37

IN

31

IN

122021

IN

121921

IN

7

IN

31

OUT

18

OUT

18

OUT

18

OUT

18

OUT

18

OUT

18

OUT

18

OUT

DOCUMENT_NUMBER

D89092

12

29

29 77

V

RE

OUT
OUT
OUT
OUT

OUT

OUT
OUT

R57UB

20K
5%

CH
402

77

52 59

55

1

E

DAT

2-05-071. 02.01

D

75

14

75

31

31

31

72

IN

31

12

IN

12

24

1

2

31

R56UB

0
5%

CH
402

C

B

A

PAGE

REV

12

2.0

1

CR-13 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE13

8

D

M_A_DQ<63..0>

19

BI

C

B

AR43

0

AW44

1

BA45

2

AY46

3

AR41

4

AR45

5

AT42

6

AW47

7

BB45

8

BF48

9

BG47

10

BJ45

11

BB47

12

BG50

13

BH49

14

BE45

15

AW43

16

BE44

17

BG42

18

BE40

19

BF44

20

BH45

21

BG40

22

BF40

23

AR40

24

AW40

25

AT39

26

AW36

27

AW41

28

AY41

29

AV38

30

AT38

31

AV13

32

AT13

33

AW11

34

AV11

35

AU15

36

AT11

37

BA13

38

BA11

39

BE10

40

BD10

41

BD8

42

AY9

43

BG10

44

AW9

45

BD7

46

BB9

47

BB5

48

AY7

49

AT5

50

AT7

51

AY6

52

BB7

53

AR5

54

AR8

55

AR9

56

AN3

57

AM8

58

AN10

59

AT9

60

AN9

61

AM9

62

AN11

63

A

7

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

U1UB

CRESTLINE 1.0

DDR SYSTEM MEMORY A

4OF10

SA_BS_0
SA_BS_1
SA_BS_2

SA_CAS#

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6

SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13

SA_RAS#

SA_RCVEN#

SA_WE#

6

M_B_DQ<63..0>

20

BI

M_A_DM<7..0>

0
1
2

3
4
5
6
7

M_A_DQS_DP<7..0>

0
1
2

3
4
5
6
7

M_A_DQS_DN<7..0>

0
1
2

3
4
5
6
7

M_A_A<13..0>

0
1
2

3
4
5
6
7
8
9
10
11
12
13

M_A_BS<0>
M_A_BS<1>
M_A_BS<2>

M_A_CAS_N

M_A_RAS_N

M_A_WE_N

OUT
OUT
OUT

OUT
OUT

OUT

OUT

19 21
19 21
19 21

19 21

19

19

BI

19

BI

21

19

BI

19 21

19 21

BB19
BK19
BF29

BL17

AT45
BD44
BD42
AW38
AW13
BG8
AY5
AN6

AT46
BE48
BB43
BC37
BB16
BH6
BB2
AP3
AT47
BD47
BC41
BA37
BA16
BH7
BC1
AP2

BJ19
BD20
BK27
BH28
BL24
BK28
BJ27
BJ25
BL28
BA28
BC19
BE28
BG30
BJ16

BE18
AY20

BA19

TP_SA_RCVEN_N

IC

45

AP49

0

AR51

1

AW50

2

AW51

3

AN51

4

AN50

5

AV50

6

AV49

7

BA50

8

BB50

9

BA49

10

BE50

11

BA51

12

AY49

13

BF50

14

BF49

15

BJ50

16

BJ44

17

BJ43

18

BL43

19

BK47

20

BK49

21

BK43

22

BK42

23

BJ41

24

BL41

25

BJ37

26

BJ36

27

BK41

28

BJ40

29

BL35

30

BK37

31

BK13

32

BE11

33

BK11

34

BC11

35

BC13

36

BE12

37

BC12

38

BG12

39

BJ10

40
41
42
43
44

BK10

45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

BL9
BK5
BL
BK9

BJ8
BJ6
BF4
BH5
BG1
BC2
BK3
BE4
BD3
BJ2
BA3
BB3
AR1
AT3
AY2
AY3
AU2
AT2

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42

5

SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

3

U1UB

CRESTLINE 1.0

SYSTEM MEMORY B

DDR

5OF10

SB_BS_0
SB_BS_1
SB_BS_2

SB_CAS#

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6

SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13

SB_RAS#

SB_RCVEN#

SB_WE#

IC

AY17
BG18
BG36

BE17

AR50
BD49
BK45
BL39
BH12
BJ7
BF3
AW2

AT50
BD50
BK46
BK39
BJ12
BL
BE2
AV2
AU50
BC50
BL45
BK38
BK12
BK7
BF2
AV3

BC18
BG28
BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13

AV16
AY18

BC17

7

2

0
1
2

3
4
5
6
7

0
1
2

3
4
5
6
7
0
1
2

3
4
5
6
7

0
1
2

3
4
5
6
7
8
9
10
11
12
13

TP_MB_RCVEN_N

1

MODULE REV DETAILS

MODULE NAME

TAWAS_CORE

M_B_BS<0>
M_B_BS<1>
M_B_BS<2>

M_B_CAS_N

M_B_DM<7..0>

M_B_DQS_DP<7..0>

M_B_DQS_DN<7..0>

M_B_A<13..0>

M_B_RAS_N

M_B_WE_N

REV

1.02.01 2-05-07

20

21

OUT

20

21

OUT

20

21

OUT

20

21

OUT

20

OUT

20

BI

20

BI

20

BI

20

21

OUT

20

21

OUT

DATE

D

C

21

B

A

BPAGE DRAWING

tawas_b.sch_1.13

Wed Feb 07 17:18:12 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

13

2.0

1

[PAGE_TITLE=GMCH (4 OF 8)]

CR-14 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE14

8

7

6

45

3

BOM NOTE:

REPLACE C63UB AND C64UB WITH

1823

D

62637177

IN

29

32

V_1P05_CORE

81015

16

17

C

BOM NOTE:

75

V_GFX

15

IN

71
76

REPLACE C68UB WITH 0.47UF IPN 602433-015

1

1

C67UB

C68UB

220UF

4700PF

20%

20%

2.5V

50V

2

PTY

EM

X7

2

7343

R

603

B

BOM NOTE:

REPLACE C73UB AND C74UB WITH

V_1P05_M

14

70

IN

A

0.22UF IPN 602433-021

1

72UB

C

22UF
20%

6.3V

2

X5R
805

0.22UF IPN 602433-021

1

C62UB

1

C59UB

220UF

22U

T

1U

F

3V

73UB

2

1

2

F

20%

6.3V
X5R
805

C70UB

10UF
20%

6.3V
X5R
805

1

2

C

2200PF
5%
25V
COG
603

20%

2.5V
TAN

2

SM

1

C69UB

20%

6.

2

X5R
603

1

C

2200PF
5%
25V

2

COG
603

74UB

U1UB

CRESTLINE 1.0

C63UB

2200P
5%
25V
COG
603

C60UB

22U

F

20%

6.3V
X5R
805

1

2

1

F

2

1

C71UB

.1

UF
10%
10V

2

X5R
402

5UB

C7

.1UF
10%
10V
X5R
402

1

2

1

2

C64UB

2200P
5%
25V
COG
603

1

2

1

2

F

C

.1UF
10%
10V
X5R
402

C61UB

.1
10%

10V
X5R
402

76UB

1

C65UB

.1

UF
10%
10V

2

X5R
402

UF

1

C77UB

.1UF
10%
10V

2

X5R
402

AB33
AB36
AB37
AC33
AC35
AC36
AD35
AD36
AF33
AF36
AH33
AH35
AH36
AH37
AJ33
AJ35
AK33
AK35
AK36
AK37
AD33
AJ36
AM35
AL33
AL35
AA33
AA35
AA36
AP35
AP36
AR35
AR36

AL24
AL26
AL28
AM26
AM28
AM29
AM31
AM32
AM33
AP29
AP31
AP32
AP33
AL29
AL31
AL32
AR31
AR32
AR33

Y32
Y33
Y35
Y36
Y37
T30
T34
T35
U29
U31
U32
U33
U35
U36
V32
V33
V36
V37

VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40

CC_NCTF_41

V
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44
VCC_NCTF_45
VCC_NCTF_46
VCC_NCTF_47
VCC_NCTF_48
VCC_NCTF_49
VCC_NCTF_50

VCC_AXM_NCTF_1
VCC_AXM_NCTF_2
VCC_AXM_NCTF_3
VCC_AXM_NCTF_4
VCC_AXM_NCTF_5
VCC_AXM_NCTF_6
VCC_AXM_NCTF_7
VCC_AXM_NCTF_8
VCC_AXM_NCTF_9
VCC_AXM_NCTF_10
VCC_AXM_NCTF_11
VCC_AXM_NCTF_12
VCC_AXM_NCTF_13
VCC_AXM_NCTF_14
VCC_AXM_NCTF_15
VCC_AXM_NCTF_16
VCC_AXM_NCTF_17
VCC_AXM_NCTF_18
VCC_AXM_NCTF_19

VCC NCTF

POWER

VCC AXM NCTF

VSS NCTF

VSS SCBVCC AXM

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8

VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_

NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21

VSS_SCB1
VSS_SCB2
VSS_SCB3
VSS_SCB4
VSS_SCB5
VSS_SCB6

VCC_AXM_1
VCC_AXM_2
VCC_AXM_3
VCC_AXM_4
VCC_AXM_5
VCC_AXM_6
VCC_AXM_7

T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28

A3
B2
C1
BL1
BL51
A51

AT33
AT31
AK29
AK24
AK23
AJ26
AJ23

BOM NOTE:

REPLACE C79UB WITH

IPN C71601-001

12

75

V_1P05_M

IN

IN

1

C79UB

F

330U
20%

6.3V
TANT

2

7343

G_VID<3..0>

14

70

1

2

C80UB

22UF
20%

6.

3V
X5R
805

2

MODULE REV DETAILS

MODULE NAME

TAWAS_CORE

V_SM

2

0

1

2

3

C81UB

22UF
20%

6.3V
X5R
805

R77UB

1

22K
402

R78UB

1

22K
402

R79UB

1

22K
402

R80UB

1

22K
4025%CH

IN

111215

11

2

2

5%
CH

2

5%
CH

2

5%
CH

2

C78UB

.1UF
10%
10V
X5R
402

1.02.01

16 17

1

REV

19 206171

VCC3

2-05-07

DATE

D

C

B

A

6OF10

IC

BPAGE DRAWING

tawas_b.sch_1.14

Wed Feb 07 17:18:14 2007

8

7

6

5

4 2

3

[PAGE_TITLE=GMCH (5 OF 8)]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

14

1

REV

2.0

CR-15 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE15

8

7

6

45

3

D

7576

IN

V_GFX

14

1571

7

AB19

AC16

Y28

U17

U19

U20

U23

U26

V16

V17

V19

T18

T19

T22

T23

T25

U15

T21

U16

T17

U21

V20

V23

V24

V21

Y23

Y15

Y16

Y17

Y19

Y20

Y24

Y26

Y21

AC17

Y29

AB16

AA16

AA1

AC19

AD15

AD16

AD17

AF16

AF19

AJ19

AH15

AH16

AH17

AJ16

AJ17

AL21

AL23

AM21

AM20

AP15

AP17

AP16

AM16

AM23

AM19

AM15

AL16

AK16

AK19

AL17

AL19

AL20

AR21

AP21

AP23

AP24

AP19

AP20

V28

AR23

AR24

AR26

AR20

V26

BC39

AW45

BD17

BD4

AW8

BE39

Y31

V29

C

VCC_SM_LF5

VCC_SM_LF4

VCC_SM_LF3

VCC_SM_LF2

VCC_SM_LF6

VCC_SM_LF1

U1UB

VCC_AXG_NCTF_1

VCC_AXG_NCTF_2

VCC_AXG_NCTF_9

VCC_AXG_NCTF_8

VCC_AXG_NCTF_7

VCC_AXG_NCTF_6

VCC_AXG_NCTF_5

VCC_AXG_NCTF_4

VCC_AXG_NCTF_3

VCC_AXG_NCTF_10

VCC_AXG_NCTF_17

VCC_AXG_NCTF_16

VCC_AXG_NCTF_15

VCC_AXG_NCTF_14

VCC_AXG_NCTF_13

VCC_AXG_NCTF_12

VCC_AXG_NCTF_11

VCC_AXG_NCTF_24

VCC_AXG_NCTF_23

VCC_AXG_NCTF_22

VCC_AXG_NCTF_21

VCC_AXG_NCTF_20

VCC_AXG_NCTF_19

VCC_AXG_NCTF_18

VCC_AXG_NCTF_31

VCC_AXG_NCTF_30

VCC_AXG_NCTF_29

VCC_AXG_NCTF_28

VCC_AXG_NCTF_27

VCC_AXG_NCTF_26

VCC_AXG_NCTF_25

VCC_AXG_NCTF_38

VCC_AXG_NCTF_37

VCC_AXG_NCTF_35

VCC_AXG_NCTF_32

VCC_AXG_NCTF_36

VCC_AXG_NCTF_34

VCC_AXG_NCTF_33

VCC_AXG_NCTF_45

VCC_AXG_NCTF_44

VCC_AXG_NCTF_43

VCC_AXG_NCTF_42

VCC_AXG_NCTF_41

VCC_AXG_NCTF_40

VCC_AXG_NCTF_39

VCC_AXG_NCTF_52

VCC_AXG_NCTF_51

VCC_AXG_NCTF_50

VCC_AXG_NCTF_49

VCC_AXG_NCTF_48

VCC_AXG_NCTF_47

VCC_AXG_NCTF_46

VCC_AXG_NCTF_59

VCC_AXG_NCTF_57

VCC_AXG_NCTF_56

VCC_AXG_NCTF_55

VCC_AXG_NCTF_54

VCC_AXG_NCTF_53

VCC_AXG_NCTF_61

VCC_AXG_NCTF_63

VCC_AXG_NCTF_64

VCC_AXG_NCTF_58

VCC_AXG_NCTF_65

VCC_AXG_NCTF_60

VCC_AXG_NCTF_62

VCC_AXG_NCTF_72

VCC_AXG_NCTF_70

VCC_AXG_NCTF_68

VCC_AXG_NCTF_66

VCC_AXG_NCTF_67

VCC_AXG_NCTF_69

VCC_AXG_NCTF_71

VCC_AXG_NCTF_73

VCC_AXG_NCTF_75

VCC_AXG_NCTF_77

VCC_AXG_NCTF_79

VCC_AXG_NCTF_80

VCC_AXG_NCTF_82

VCC_AXG_NCTF_83

VCC_AXG_NCTF_81

VCC_AXG_NCTF_78

VCC_AXG_NCTF_76

VCC_AXG_NCTF_74

VCC SM LF

VCC GFX NCTF

VCC_SM_LF1_C
VCC_SM_LF2_C
VCC_SM_LF3_C
VCC_SM_LF4_C
VCC_SM_LF5_C
VCC_SM_LF6_C
VCC_SM_LF7_C

AT6

VCC_SM_LF7

2

2

MODULE REV DETAILS

NAME

MODULE

TAWAS_CORE

BOM NOTE:

REPLACE C84UB AND C85UB
WITH 0.22UF IPN 602433-021

1

1

2

C83UB

.1UF
10%
10V
X5R
402

2

C84UB

2200PF
5%
25V
COG
603

1

2

C85UB

2200PF
5%
25V
COG
603

1

C82UB

.1UF
10%

10V
X5R
402

IC

F10

7O

RE

1.02.01 2-05-07

1

C86UB

.47UF
10%

6.3V

2

X5R
402

1

2

1

V

C87UB

1.00UF

20%

6.3V
X5R
402

1

2

C88UB

1.00UF
20%

6.3V
X5R
402

E

DAT

D

C

CRESTLINE 1.0

CORE

VCC

POWER

VCC SM

B

VCC_3

VCC_4

VCC_2

VCC_1

AT35

AT34

V_1P05_CORE

81014

161718

2329

32

62

IN

63

7177

VCC_9

VCC_8

VCC_7

VCC_6

VCC_5

AC32

AK32

AJ28

AH28

AJ31

AC31

AH32

VCC_10

AH31

VCC_11

AH29

VCC_12

AF32

VCC_13

R30

VCC_SM_1

VCC_SM_5

VCC_SM_4

VCC_SM_3

VCC_SM_2

VCC_SM_8

VCC_SM_7

VCC_SM_6

VCC_SM_15

VCC_SM_14

VCC_SM_13

VCC_SM_12

VCC_SM_11

VCC_SM_9

VCC_SM_10

VCC_SM_22

VCC_SM_21

VCC_SM_19

VCC_SM_18

VCC_SM_17

VCC_SM_16

VCC_SM_20

VCC_SM_29

VCC_SM_28

VCC_SM_27

VCC_SM_26

VCC_SM_25

VCC_SM_24

VCC_SM_23

5

BG35 AH19

BJ33

BJ32

BG32

BE35

BE32

BD35

BA3

AW35

AY35

BA32

BA33

BB33

BC32

AU33

AU35

AV33AW33

AU32

BC33

BF33

BC35

BD32

BE33

BF34

BG33

BH32

BH34

BH35

VCC_SM_36

VCC_SM_35

VCC_SM_34

VCC_SM_33

VCC_SM_32

VCC_SM_31

VCC_SM_30

BK32

BL33

BK35

BK34

BK33

BJ34

AU30

VCC_AXG_5

VCC_AXG_4

VCC_AXG_3

VCC_AXG_2

VCC_AXG_1

R20

T14

W13

W14

Y12

A

11

12

1416

17

19206171

14

1571

7576

V_SM

IN

V_GFX

IN

VCC GFX

VCC_AXG_12

VCC_AXG_11

VCC_AXG_9

VCC_AXG_8

VCC_AXG_7

VCC_AXG_6

VCC_AXG_10

VCC_AXG_14

AA20

AA23

AA26

AA28

AB24

AB29

AC20

AB21

AC21

VCC_AXG_21

VCC_AXG_17

VCC_AXG_15

VCC_AXG_16

AC23

AC26

AC28

AC24

VCC_AXG_25

VCC_AXG_20

AC29

AD20

AD23

AD24

AD28

AF26

AF21

AA31

VCC_AXG_26

VCC_AXG_24

VCC_AXG_23

VCC_AXG_22

VCC_AXG_19

VCC_AXG_18

VCC_AXG_13

VCC_AXG_33

VCC_AXG_31

VCC_AXG_27

VCC_AXG_32

VCC_AXG_34

VCC_AXG_30

VCC_AXG_29

VCC_AXG_28

AH20

AH23

AH24

AH26

AN14

AJ20

AH21

AD31

B

A

[PAGE_TITLE=GMCH (6 OF 8)]

BPAGE DRAWING

tawas_b.sch_1.15

Wed Feb 07 17:18:15 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

15

2.0

1

D

C

62
16
18

B

A

CR-16 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE16

8

71

16

OUT

16

V_3P3S_TVDAC

IN

656554-002

OUT

FB4UB

1SM2

FB

11

2

R23UB

2

1

1A

0

603

603

603

16

16

R24UB

1

0

R25UB

1

CH

2

1A
CH

2

1ACH0

V_3P3S_TVDACC

OUT

V_3P3S_TVDACB

OUT

2

2

2

1

1

1

C25UB

.1UF
10%
10V
X5R
402

C29UB

.1UF
10%
10V
X5R
402

C35UB

.1UF
10%
10V
X5R
402

1

2

1

2

1

2

C26UB

220PF

10%
50V
X7R
402

C30UB

220PF

10%
50V
X7
402

C36UB

220PF

10%
50V
X7R
402

8

7

BOM NOTE:

REPLACE C90UB WITH .022UF IPN A36096-073

V_3P3S_TVDAC

16

18

62

IN

V_1P25_CORE

12

68

16171832

IN

V_3P3S_TVDACA

VCCA_TVDAC

C24UB

F

10U
20%
16V
Y5V
1210

R

1

C39UB

C34UB

.1UF

220PF
10%

10%
10V

50V

2

2

X7R

X5R

402 402

BOM NOTE:

REPLACE C26UB, C30UB, C39UB
C

36UB, WITH .022UF IPN A36096- 073

32

37

39

406264

71

6171

7

6870

81618

1920

6

SM

FB1UB

2

1

FB

656554-002

L1U

B

10UH

2

1

IND

B

L2U

10UH

1

2

IND

BOM NOTE:

REPLACE C9UB, C101UB
WITH IPN TBD

17

6870

16

17

IN

15

17

V_1P25_M

12

IN

V_1P5_CORE

R72UB

1

0

1A

CH

2

603

1

R76UB

0
5%

EMPTY

2

402

11

12

14

IN

6

1

2

18

16

18

17

18

1

2

1

C9UB

470UF
20%
4V
TAN

2

7343

C101UB

470UF
20%
4V
TANT
7343

16

IN

12

IN

70
68
12
16

16

V_SM

1

C89UB

.1UF
10%
10V
X5R

2

402

1

T

2

1

2

VCC3

V_1P25_S_PEGPLL

V_1P25_M

1

2

R60UB

21A1

0

CH

603

V_1P5_CORE

IN

V_1P5S_QDAC

IN

V_1P25_M

IN

V_1P25_S_PEGPLL

IN

R75UB

1

0

603

VCC3

R17UB

1

C90UB

220PF

0

10%

5%

50V

EMPTY

2

R

X7

402

402

C98UB

UF

.1
10%
10V
X5R
402

C102UB

.1

UF
10%
10V
X5R
402

C11UB

1

C6UB

100UF

22UF

20%

20%

10V

6.3V

TANT

2

X5R

7343

805

VCCA_SM_CK

1

1

C18UB

1UF
20%

6.3V

2

2

X5R
603

C47UB

.1UF

10%
10V
X5R
402

DESIGN NOTE:

CHECK FOR CORRECT V ALUE

2

VCCD_LVDS

1A
CH

V_3P3S_CRTDAC

16

16

16

1617

1

C7UB

4.7UF
10%

6.

2

X5R
603

1

C19UB

1UF
20%

6.3V

2

X5R
603

1

1

2

2

C41UB

10UF

20%

6.3V
X5R
805

5

R59

UB

1

2

1A

0

CH

603

VCCA_TVDAC

IN

V_1P25_DPLLA

V_1P25_DPLLB

V_1P25M_HPLL

IN

V_1P25M_MPLL

IN

V_1P8_TXLVDS

IN

1

C2UB

1000P
10%
50V

2

X7R
402

1

C12UB

22UF
20%

3V

3V

6.

2

X5R
805

1

C20UB

22UF
20%

6.3V

2

X5R
805

V_3P3S_TVDACA

16

IN

V_3P3S_TVDACB

16

IN

V_3P3S_TVDACC

16

IN

V_1P5S_TVDAC_R

C52UB

220PF

10%

50V

C

31UB

X7R

.1UF

402

10%
10V
X5R
402

1

C40UB

1.00UF
20%

6.3V

2

X5R
402

C21UB

.1UF
10%
10V
X5R
402

C32UB

.1UF

1

2

V_3P3S_SYNC

R18UB

1

0
5%

2

EM

PTY

402

1

C3UB

.1

F

10%
10V

2

X5R
402

1

C8UB

1.00UF

20%

6.3V

2

X5R
402

1

10%
10V

2

X5R
402

1

2

45

1

C91UB

.1UF
10%
10V

2

X5R
402

J32

VCCSYNC

A33

VCCA_CRT_DAC_1

B33

VCCA_CRT_DAC_2

A30

VCCA_DAC_BG

B32

VSSA_DAC_BG

B49

V

CCA_DPLLA

H49

V

CCA_DPLLB

AL2

CCA_HPLL

V

AM2

VCCA_MPLL

A41

VCCA_LVDS

B41

UF

K50

K49

U51

AW18
AV19
AU19
AU18
AU17

AT22
AT21
AT19
AT18
AT17
AR17
AR16

BC29
BB29

C25
B25
C27
B27
B28
A28

M32
L29

N28

AN2

U48

J41
H42

LVDS

VSSA_

VCCA_PEG_BG

VSSA_PEG_BG

VCCA_PEG_PLL

VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5

VCCA_SM_7
VCCA_SM_8
VCCA_SM_9
VCCA_SM_10
VCCA_SM_11
V

CCA_SM_NCTF_1

VCCA_SM_NCTF_2

VCCA_SM_CK_1
VCCA_SM_CK_2

VCCA_TVA_DAC_1
VCCA_TVA_DAC_2
VCCA_TVB_DAC_1
VCCA_TVB_DAC_2
VCCA_TVC_DAC_1
VCCA_TVC_DAC_2

VCCD_CRT
VCCD_TVDAC

VCCD_QDAC

VCCD_HPLL

VCCD_PEG_PLL

VCCD_LVDS_1
VCCD_LVDS_2

3

U1UB

CRESTLINE 1.0

CRT

L
PL

VDS

AL

PEGASM
A

POWER

K

AC

TV

D TV/CRT

LVDS

AXD

AXF

SM CK

PEG

DMI

VCC_RXR_DMI_1
VCC_RXR_DMI_2

VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9

VTT_10

VTT

VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22

VCC_AXD_1
VCC_AXD_2
VCC_AXD_3
VCC_AXD_4
VCC_AXD_5
VCC_AXD_6

VCC_AXD_NCTF

VCC_AXF_1
VCC_AXF_2
VCC_AXF_3

VCC_DMI

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

VCC_TX_LVDS

HV

VCC_HV_1
VCC_HV_2

VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5

VTTLF

VTTLF1
VTTLF2
VTTLF3

8OF10

1

R29UB

0

1A

EMPTY

2

603

BPAGE DRAWING

Wed Feb 07 17:18:16 2007

4 2

[PAGE_TITLE=GMCH (7 OF 8)]

tawas_b.sch_1.16

3

2

U13
U12
U11
U9
U8
U7
U5
U3
U2
U1
T13
T11
T10
T9
T7
T6
T5
T3
T2
R3
R2
R1

AT23
AU28
AU24
AT29
AT25
AT30

AR29

B23
B21
A21

AJ50

BK24
BK23
BJ24
BJ23

A43

C40

0

B4

AD51
W50
W51
V49
V50

AH50
AH51

A7
F2
AH1

IC

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

MODULE REV DETAILS

NAME

MODULE

TAWAS_CORE

RE

1.02.01 2-05-07

V_1P25_M

V_1P05_CORE

1

V_1P25M_MPLL_R

V_1P25M_AXD

V_1P25S_AXF

1

CH

1

2

FB2UB

MULTI

603

CH

C10UB

FB3UB

MU

LTI

603

C17UB

22UF
20%

3V

6.
X5R

MOD R66UB TO 0.51 OHM 1%

805

IPN C49684-002

IN

IN

IN

2

22UF

20%

6.3V
X5R
805

2

V

_1P25M_MPLL

R66UB

1

0

603

BOM NOTE:

17

17

V_1P25_CORE

V_1P8_SM_CK

V_1P8_TXLVDS

V_3P3S_HV

17

IN

16 17

IN

18

IN

VCC_PEG

MCH_VTTLF1
MCH_VTTLF2
MCH_VTTLF3

1

1

2

DOCUMENT_NUMBER

C37UB

.47UF
10%

3V

6.
X5R
402

D89092

2

C38UB

.47UF
10%

6.3V
X5R
402

1

V

DAT

12 161768

IN

70

810141517 18
29

32

62 637177

V_1P25M_HPLL

1

1

C5UB

.1

UF
10%
10V

2

2

X5R
402

1

C14UB

UF

.1

2

10%
10V

1A

2

X5R

CH

402

IN

1

C4UB

.1UF
10%
10V

2

X5R
402

11

17

IN

1

C33UB

.47UF
10%

6.3V

2

X5R
402

PAGE

16

1

E

23

OUT

OUT

71
12 16
183268

REV

2.0

D

16

16

C

17

B

A

CR-17 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE17

8

A13
A15
A17

A24
AA21
AA24
AA29
AB20
AB23

D

C

B

A

AB26
AB28
AB31
AC10
AC13

AC3
AC39
AC43
AC47

AD1
AD21
AD26
AD29

AD3
AD4
AD45
AD49

AD5
AD50

AD8
AE10
AE14

AE6
AF20
AF23
AF24
AF31

AG2
AG38
AG43
AG47
AG50

AH3
AH40
AH41

AH7

AH9
AJ11
AJ13
AJ21
AJ24
AJ29
AJ32
AJ43
AJ45
AJ49
AK20
AK21
AK26
AK28
AK31
AK51

AL1
AM11
AM13

AM3

AM4
AM41
AM45

AN1
AN38
AN39
AN43

AN5

AN7

AP4
AP48
AP50
AR1

AR2
AR39
AR44
AR47

AR7
AT10
AT14
AT41
AT49

AU1
AU23
AU29

AU3
AU36
AU49
AU51
AV39
AV48

AW1
AW12
AW16

1

1

8

CRESTLINE 1.0

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

7

U1UB

VSS

9OF10

7

6

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197

IC

VSS_198

AW24
AW29
AW
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41

32

U1UB

C4
C50

D13
D24

D32
D39
D45
D49
E10
E16
E24
E28
E32
E47
F19
F36

F40
F50

G13
G16
G19
G24
G28
G29
G33
G42
G45
G48

H24
H28

H45
J11
J16

J24
J28
J33
J35
J39

K12
K47

L17
L20
L24
L28

L33
L49
M28
M42
M46
M49

M50

N11
N14
N17
N29
N32
N36
N39
N44
N49

P19

P23

P50
R4
T39
T43
T47
U41
U45
U50

6

C7

D3

F4

G1

G8

H4

J2

K8
L1

L3

M5

M9

N7

P2

P3

9

V2
V3

CRESTLINE 1.0

VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243

VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286

VSS

VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305

VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
V
VSS_313

10 FO 10

SS_312

IC

6

5

45

W11
W39
W43
W47
W5
W7
Y13
Y2
Y41
Y45
Y49
Y5
Y50
Y11
P29
T29
T31
T33
R28

AA32
AB32
AD32
AF28
AF29
AT27
AV25
H50

32

1

2

Wed Feb 07 17:18:17 2007

4 2

3

15

1617

182329

7177

BOM NOTE:

REPLACE L3UB
WITH 5.6NH

1

C99UB

1.00UF

20%

6.

3V

2

X5R
402

1

C103UB

1.00UF
20%

6.3V

2

X5R
402

1

C13UB

.1UF
10%
10V

2

X5R
402

R

30UB

2

2

1

1

C22UB

1000PF

10%
50V
X7R
402

C27UB

10UF
20%

6.3V
X5R
805

0
5%

EMPTY
402

[PAGE_TITLE=GMCH (8 OF 8)]

BPAGE DRAWING

tawas_b.sch_1.17

3

V_1P05_CORE

81014

OUT

6263

L3U

B

3.9NH
2

1

IND

1

C100UB

22.000UF
20%

6.3V

2

X5R
805

1

C1UB

10UF

20%

6.3V

2

X5R
805

1

C15UB

22.000UF
20%

3V

6.

2

X5R
805

L5UB

1UH

2

1

IND

1

C23UB

F

220U
20%

2.5V
TAN

T

2

SM

L6UB

90NH

2

1

IND

1

C28UB

220UF
20%

2.

5V

TANT

2

SM

2

1

C92UB

4.7UF
20%

6.

3V

2

X5R
805

V_1P25_M

V_1P25M_AXD

R64UB

1

MU

LTI

CH

1210

R65UB

1

5%

1

CH

402

V_SM

V_1P8_TXLVDS

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

MODULE REV DETAILS

MODULE NAME

TAWAS_CORE

1

1

2

C93UB

4.7UF
20%

6.3V
X5R
805

2

C94UB

1.0UF
10%

16V
X5R
805

BOM NOTE:

REPLACE C96UB WITH 0.47UF

IPN 602433-015

2

V_1P25_CORE

BOM NOTE:

REPLACE R64UB
WITH .1UH 1210

V_1P25S_AXF

L4UB

2

1

1UH

IND

2

V_1P8_SM

V_1P8_SMCK_RC

_CK

OUT

V_1P05_CORE

VCC_PEG

OUT

DOCUMENT_NUMBER

D89092

1

REV

1

C96UB

4700PF
20%
50V

2

X7

R

603

16 68 70

12

IN

16

OUT

12

16

IN

OUT

V_SM

IN

1

C16UB

10UF

20%

3V

6.

2

X5R
805

16

OUT

1112141516 17 19

IN

206171

16

8

10 1415161718

IN

23 29

32

11

16

1

DATE

2-05-071. 02.01

1

2

18 326871

16

61 71

111214
16

17 19

62 63

PAGE

17

C97UB

220UF
20%

2.5V
TANT
SM

15
20

71 77

REV

2.0

D

C

B

A

CR-18 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE18

8

12

MCH_CFG_5

D

7

12

1

R15UB

92K

3.
1%

EMPTY

2

603

6

MCH_CFG_9MCH_CFG_16

12

INININ

1

R16UB

92K

3.
1%

EMPTY

2

603

1

2

R21UB

3.92K
1%

EMPTY
603

45

NEED TABLES FOR EACH STRAPPING

12

INININ

MCH_CFG_12

1

2

R28UB

3.92K
1%

PTY

EM
603

406264

71

V

CC3

MCH_CFG_19

12

C

1

2

R22UB

3.92K
1%

PTY

EM
603

12

MCH_CFG_13

1

2

R26UB

3.92K
1%

PTY

EM
603

816323739

IN

3

VCC3

V_1P5_CORE

.002
1206

2

2

1

5%
CH

FB5UB

R1

R2UB

200MA
200
UNKN

UB

CH

1

FB

BOM NOTE:

V_1P05_CORE

C51UB

.1UF
10%

10V
X5R
402

CR2UB

1

30V

T23

SO
EM

PTY

0.2A

3

S

CHOTTKY

V_1P05_R_D

1

R8UB

10
5%

2

EMPTY
402

V_3P3S_TVDAC

1

R20UB

0

1A

2

EM

PTY

603

VCC

1

R10UB

10K
5%

2

1

C48UB

1UF
10%

25V

2

X5R
603

2

SHDN_TVDAC

1

2

CH
402

5

1

C95UB

1UF

20%

16V
EMPTY
805

U2UB

SC1563

IN

SHDN

GND

2

B

R13UB

D

S

2

3

1

100
402

Q1UB
BSS138N

T

FE

5%
CH

SHDN_TVDAC_R

A

75
69
37
26

IN

31
55
72

SLP_S3_N

1

G

BOM NOTE:

REPLACE R11UB WITH 17.8K 603

PN A93550-134

I

4

V_3P3S_TVDAC_R2

OUT

ADJ

SM

1

R11UB

18.2K

3

1%

2

CH
603

TVDAC_ADJ2

R12UB

1

10K
1%

2

CH
603

R58UB

2

1

1ACH0

805

1

C50UB

20%

4.0V
TANT

22

BOM NOTE:

REPLACE C50UB WITH 22UF

TANTLUM 202244-073

33UF

3528

1

8101415161718

OUT

63

71

16

OUT

77

62

23 29

32

62

12

IN

CHANGE C43UB TO 0.022UF

I

PN A36096-073

16

OUT

MCH_CFG_20

VCC3

V_1P25_S_PEGPLL

1

C44UB

.1UF
10%
10V

2

X5R
402

1

R14UB

3.92K
1%

2

EMPTY
603

2

MODULE REV DETAILS

MODULE NAME

TAWAS_CORE

CR1UB

30V

1

V_1P05_S_SD

10

402

2

1%

SCHOTTKY

1

3

V_1P05_CORE

T23

SO
DIO

0.2A

V_3P3S_HV

1

46UB

C

.1UF
10%
10V

2

X5R
402

V_1P5S_QDAC

1

C43UB

FB6UB

2

5%
CH

2A
220
UNK

1

FB

2

V_1P25_S_PEGPLL_RC

2

220PF

10%
50V
X7R
402

N

V_1P25_CORE

1

C42UB

.1UF
10%
10V

2

X5R
402

1

R5UB

1

402

R

1

19UB

0
5%

EMPTY

2

402

IN

1

C45UB

10UF
20%

3V

6.

2

X5R
805

1

REV

1.02.01 2-05-07

OUT

16

OUT

16

OUT

121617 326871

32

62 63
81014
17

18 23 29
77

DATE

71

15 16

D

C

B

A

[PAGE_TITLE=CRESTLINE STRAPPINGS]

BPAGE DRAWING

tawas_b.sch_1.18

Wed Feb 07 17:18:18 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

18

2.0

1

CR-19 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE19

8

OUT

IN
IN

IN

IN

13

IN

BI

PM_EXTTS0_N

M_ODT<1>

M_ODT<0>

M_A_DQS_DP<7..0>

M_A_DQS_DN<7..0>

M_A_DM<7..0>

63

6261605958

182

194

192

DQ<61>

DQ<62>

DQ<63>

1221

21

12

12

D

21

13

13

13

BOM NOTE:

M_A_DQ<63..0>

565755545351525049

191

181

189

179

176

180

<59>

DQ<60>

DQ<55>

DQ<58>

DQ<57>

DQ<56>A7DQ

174

7

484746

45

4443424140

151

157

154

152

140

142

153

159

173

175

158

160

<53>

DQ<52>

DQ<51>

DQ<50>

DQ<49>

DQ<54>

DQ<48>

DQ

143

DQ<45>

DQ<44>

DQ<47>

DQ<46>

DQ<41>

DQ<42>

DQ<43>

6

38

393736353334323130

141

136

134

124

126

135

137

12576123

DQ<38>

DQ<39>

DQ<40>

DQ<33>

DQ<37>

DQ<36>

DQ<35>

DQ<34>

DQ<32>

746275

DQ<31>

DQ<30>

29

64

DQ<29>

282726242523222120

73

6361584656

DQ<28>

DQ<24>

DQ<23>

DQ<22>

DQ<27>

DQ<26>

DQ<25>

DQ<21>

191817161514131210

36

44575545433822

DQ<18>

DQ<19>

DQ<20>

DQ<17>

DQ<14>

DQ<13>

DQ<16>

DQ<15>

11

9

37

203523

25

DQ<9>

DQ<10>

DQ<11>

DQ<12>

87654

16

14619417

DQ<6>

DQ<7>

DQ<8>

3

1

2

7

DQ<5>

DQ<1>

DQ<2>

DQ<3>

DQ<4>

45

5

147

DM5

4

130

DM4

3

67

DM3

7

185

DM7

6

170

DM6

0

5

DQ<0>

3

7

6

5

7

6

186

DQS*<7>

188

DQS<7>

167

DQS*<6>

169

DQS<6>

5

146

DQS*<5>

148

DQS<5>

1

2

0

TP_NC2_J8

120

10

52

26

NC

DM0

DM1

DM2

4

129

2

MODULE REV DETAILS

MODULE NAME

TAWAS_CORE

1

REV

DATE

2-05-071. 02.01

D

3

4

3

131

68

DQS<4>

DQS*<3>

DQS*<4>

1

2

0

1

2

0

31

13

70

DQS<3>

11

51

49

29

DQS<2>

DQS<0>

DQS<1>

DQS*<0>

DQS*<1>

DQS*<2>

TP_NC1_J8

83

NC

TP_NCTEST_J8

TP_NC4_J8

163

114

119

69

50

IO

NC

NC

ODT0

ODT1

NC/TEST

J1MY

C

13

21

IN

13

21

IN

13

21

IN

13

21

IN

13

21

BI

12

IN

12

IN

12

IN

12

IN

12

21

IN

12

21

IN

21

12

B

33
33

61

72

A

IN

12

21

IN

13

21

IN

13

21

IN

19

IN

19

50

IN

20

21

22

IN

21

22

20

IN

50

61

71

11

12

1415

IN

17

1920

16

DDR_REF

1220

IN

4869

71

20

31

3233

IN

3539

4647

83

6171

11

12

1415

IN

16

17

1920

8

SODIMM_202P

WE*

M_A_WE_N
M_A_RAS_N
M_A_CAS_N
M_A_BS<2>

109

M_A_A<13..0>

M_CLK_DDR_DP<0>
M_CLK_DDR_DN<0>
M_CLK_DDR_DP<1>
M_CLK_DDR_DN<1>
M_CS_N<0>
M_CS_N<1>

M_CKE<0>
M_CKE<1>
M_A_BS<0>
M_A_BS<1>
SA0_DIM0
SA1_DIM0
SMB_DATA_S
SMB_CLK_S

V_SM

R1MY

1

2

5%

0

1

CH

402

2

V_3P3_M

V_SM

1

C2MY

2.2UF
10%

6.3V

2

X5R
603

CAS*

RAS*

113

108

R14MY

1K
1%

EMPTY
402

BA2

85

1

R13M

1K
1%

2

EMPTY
402

1

A13

A12

A1

A14

A15

86

89909392949798

84

116

P_J23_M_A_A15

P_J23_M_A_A14

T

T

131210

11

Y

M_VREF_DIMM0

1

C1MY

.1UF
10%
16V

2

X7R
603

7

A10/AP

105

91

9

C4MY

2.2UF

846

10%

6.3V
X5R
603

CK0

A0A1A2A3A4A5A6A8A9

CK1

CK0*

CK1*

30

32

99

102

100

164

166

101

1

7

532

0

1

1

C3MY

.1UF
10%
16V

2

2

X7R
603

S0*

110

S1*

115

CKE1

CKE0

BA0

BA1

79

80

106

107

SA0

198

200

VDDSPD

VREF

SDA

SCL

SA1

1

195

197

199

VDD

VDD

VDD

VDD

VDD

88

103

104

112

111

VDD

VDD

VDD

VDD

VDD

VDD

VDD

96

95

82

81

87

118

117

61

14

71

GND

GND

202

201

1920

V_SM

11

12

IN

1617

15
71

15

1617

1920

61

VSS

VSS

VSS

VSS

VSS

184

187

190

193

196

1

2

1

C5MY

.1UF
10%

10V
X5R
402

C6MY

.1UF
10%
10V

2

X5R
402

V_SM

111214

IN

NOTE:

BOM

REPLACE C9MY WITH
IPN C71601-001

183

VSS

VSS

VSS

177

178

1

2

VSS

172

VSS

VSS

168

171

C7MY

.1UF
10%
10V
X5R
402

VSS

165

VSS

162

VSS

161

1

2

VSS

156

VSS

150

155

C8MY

.1UF
10%

10V
X5R
402

VSS

VSS

VSS

VSS

VSS

VSS

VSS

149

145

1

C9MY

330UF
20%

6.3V
TANT

2

7343

144

139

138

133

VSS

132

2

1

VSS

128

VSS

127

C10MY

2.2UF
10%

6.3V

X5R
603

122

VSS

VSS

VSS

VSS

VSS

VSS

VSS

787772

71

66

121

1

C11MY

2.2UF
10%

6.

3V

2

X5R
603

VSS

VSS

VSS

VSS

6560595453

1

2

VSS

VSS

VSS

4847424140

C12MY

2.2UF
10%

6.3V

X5R
603

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

393433

282724

1

C13MY

2.2UF
10%

6.3V

2

X5R
603

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

15

18

12

21

3

982

NC=203,204

B

1

C14MY

2.2UF
10%

6.3V

2

X5R
603

A

2

1

C

SA0_DIM0

19

OUT

SA1_DIM0

19

OUT

6

R4MY

1

10K
402

5

R3MY

5%

10K

CH

402

2

5%
CH

BPAGE DRAWING

Wed Feb 07 17:18:19 2007

4 2

[PAGE_TITLE=DDR DIMM 0]

tawas_b.sch_1.19

INTEL

CONFIDENTIAL

3

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

19

2.0

1

CR-20 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE20

8

12

21

1221

D

1221

13

13

13

C

13

21

IN

13

21

IN

13

21

IN

13

21

IN

1321

BI

12

IN

12

IN

12

IN

12

IN

12

21

IN

12

21

B

1920

61

IN

12

21

IN

21

12

IN

13

21

IN

13

21

IN

20

IN

20

50

IN

19

212233

IN

212233

19

IN

50

12

14

15

16

17

61

DDR_REF

1219

IN

A

71

474869

19203132

IN

333539

46

7283
6171

12

14

15

11

IN

1719

20

16

PM_EXTTS1_N

OUT

M_ODT<3>

IN

M_ODT<2>

IN

M_B_DQS_DP<7..0>

IN

M_B_DQS_DN<7..0>

IN

M_B_DM<7..0>

13

IN

BI

J2MY

SODIMM_202P

M_B_WE_N
M_B_RAS_N
M_B_CAS_N
M_B_BS<2>

M_B_A<13..0>

M_CLK_DDR_DP<3>
M_CLK_DDR_DN<3>
M_CLK_DDR_DP<4>
M_CLK_DDR_DN<4>
M_CS_N<2>
M_CS_N<3>

M_CKE<3>
M_CKE<4>
M_B_BS<0>
M_B_BS<1>
SA0_DIM1
SA1_DIM1
SMB_DATA_S
SMB_CLK_S

V_SM

11

IN

71

R2MY

2

1

0

5%
CH

402

V_3P3_M

SM

V_

C16MY

2.2UF
10%

6.3V

2

X5R
603

606162

63

182

180

194

192

DQ<60>

DQ<61>

DQ<62>

DQ<63>

WE*

CAS*

RAS*

113

108

109

1

2

1

R16MY

1K
1%

2

EMPTY
402

1

8

7

M_B_DQ<63..0>

5857555654

59

174

191

181

189

179

176

DQ<56>A7DQ<59>

DQ<54>

DQ<55>

DQ<58>

DQ<57>

1

A14

A15

A1

A13

A12

BA2

86

85

89909392949798

84

116

P_J9_M_A_A15

TP_J9_M_A_A14

T

13

R15MY

1K
1%

EMPTY
402

M_VREF_DIMM1

C18MY

1

C15MY

.1UF
10%
16V

2

X7R
603

7

5352505149

173

175

158

160

<53>
DQ

DQ<52>

DQ<51>

DQ<50>

A10/AP

91

105

101112

9

876

2.2UF
10%

6.3V
X5R
603

4847454644

157

154

159

DQ<49>

DQ<48>

DQ<47>

5

432

1

2

152

DQ<46>

99

142

DQ<45>

100

140

DQ<44>

101

1

2

6

434142

153

DQ<43>

A0A1A2A3A4A5A6A8A9

102

151

DQ<42>

143

DQ<41>

CK0

30

40

141

DQ<40>

CK0*

32

3938363735

136

134

124

126

DQ<38>

DQ<39>

DQ<37>

DQ<36>

CK1*

CK1

164

166

137

DQ<35>

333230

34

135

12576123

DQ<33>

DQ<34>

S1*

S0*

115

110

31

292826272524232122

746275

64

DQ<32>

DQ<31>

DQ<29>

DQ<30>

CKE1

CKE0

79

80

DQ<28>

BA0

107

DQ<27>

BA1

106

73

6361584656

DQ<26>

DQ<25>

SA0

198

DQ<24>

SA1

200

DQ<23>

DQ<22>

SDA

195

1817151614

19

20

44575545433822

DQ<18>

DQ<19>

DQ<20>

DQ<21>

DQ<17>

DQ<16>

VDDSPD

VREF

SCL

1

197

199

DQ<15>

VDD

88

36

DQ<14>

VDD

112

131112

DQ<13>

VDD

103

10

37

203523

DQ<10>

DQ<11>

DQ<12>

VDD

VDD

VDD

96

104

111

9

25

DQ<9>

VDD

95

8

DQ<8>

VDD

117

16

DQ<7>

VDD

87

3

675

4

14619417

DQ<6>

DQ<5>

DQ<3>

DQ<4>

VDD

VDD

VDD

82

81

118

7

DQ<1>

DQ<2>

0

71

6171

1

Y

C17M

.1UF
10%
16V
X7R
603

2

1

SA1_DIM1

20

OUT

SA0_DIM1

20

OUT

6

R5MY

10K

5%

402

CH

2

1

R6MY

5%

10K
402

CH

5

012

5

DQ<0>

61

45

5

147

5
DM

14

1214

VSS

196

12

11

4

130

DM4

VSS

193

11

VSS

190

187

IN

3

67

DM3

VSS

VSS

VSS

183

184

IN

7

6

170

185

DM7

DM6

GND

GND

202

201

15

1617

1920

15

161719

20

BOM NOTE:

REPLACE C28MY WITH
I

PN C71601-001

V_3P3_M

192031

IN

32 33 35 39

69

71

72 83

Wed Feb 07 17:18:20 2007

4 2

3

1

0

VSS

178

2

52

DM2

VSS

177

VSS

172

VSS

171

26

DM1

VSS

168

VSS

165

162

TP_NC2_J24

120

10

NC

DM0

VSS

VSS

VSS

VSS

VSS

156

149

150

155

161

V_SM

1

1

C19MY

.1

UF
10%
10V

2

2

X5R
402

V_SM

46 47 48

[PAGE_TITLE=DDR DIMM 1]

BPAGE DRAWING

tawas_b.sch_1.20

3

7

186

DQS*<7>

VSS

VSS

145

C20MY

.1UF
10%
10V
X5R
402

7

188

S<7>
DQ

VSS

144

1

C28MY

2

VSS

139

330UF
20%

6.3V
TANT
7343

6

167

DQS*<6>

VSS

138

169

133

6

DQS<6>

VSS

1

2

VSS

132

5

5

146

148

DQS<5>

DQS*<5>

VSS

VSS

128

127

C21MY

UF

.1
10%

10V
X5R
402

1

2

2

3

2

4

3

2

4

131

129

70

49

68

51

DQS<2>

DQS<3>

DQS<4>

DQS*<2>

DQS*<3>

DQS*<4>

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

787772

71

6560595453

66

122

121

1

C22MY

.1UF
10%
10V

2

X5R
402

1

C27MY

2.2UF

6.3V
X5R
603

CUSTOM TEXT BPAGE

C26MY

2.2UF

10%

10%

6.3V

2

X5R
603

INTEL

CONFIDENTIAL

MODULE REV DETAILS

MODULE NAME

TAWAS_CORE

1

0

1

0

31

11

13

29

DQS<0>

DQS<1>

DQS*<0>

DQS*<1>

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

393433

4847424140

1

C25MY

2.2UF
10%

6.3V

2

X5R
603

DOCUMENT_NUMBER

VSS

282724

1

2

D89092

VSS

VSS

C24MY

2.2UF
10%

6.3V

X5R
603

REV

TP_NC1_J24

TP_NC4_J24

114

83

69

NC

NC

ODT0

VSS

VSS

VSS

VSS

15

18

21

1

2

1

119

ODT1

VSS

VSS

982

12

C23MY

2.2UF
10%

6.3V

X5R
603

1

50

NC

VSS

TP_NCTEST_J24

163

NC/TEST

VSS

3

PAGE

20

DATE

2-05-071. 02.01

D

IO

C

VSS

NC=203,204

B

A

REV

2.0

CR-21 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE21

8

D

V_SM_VTT

2161

IN

71

C

31MY

2

.1UF

X5R
402

C

33MY

2

.1UF

X5R
402

C35MY

2

.1UF10%

C

B

A

2

.1UF

2

.1UF

2

.1

2

.1UF

2

.1UF

2

.1UF

2

.1UF

2

.1UF

2

.1UF

2

.1UF

X5R
402

C

37MY

X5R
402

C39MY

X5R
402

C41MY

UF

X5R
402

C43MY

X5R
402

C45MY

X5R
402

C47MY

X5R
402

C49MY

X5R
402

C51MY

X5R
402

C53MY

X5R
402

C55MY

X5R
402

C

32MY

1

2

1

10%

10V

10%

10V

10V

10%

10V

10%

10V

10%

10V

10%

10V

10%

10V

10%

10V

10%

10V

10%

10V

10%

10V

10%

10V

10%.1UF

10V
X5R
402

C34MY

1

1

1

1

1

1

1

1

1

1

1

1

2

10%.1UF

10V
X5R
402

C36MY

2

UF

10%.1

10V
X5R
402

C38MY

2

10%.1UF

10V
X5R
402

C40MY

2

.1UF 10%

10V
X5R
402

C42MY

2

UF

10%.1

10V
X5R
402

44MY

C

2

10%.1UF

10V
X5R
402

C46MY

2

10%.1UF

10V
X5R
402

C48MY

2

10%.1UF

10V
X5R
402

C50MY

2

.1UF 10%

10V
X5R
402

C52MY

2

10%.1UF

10V
X5R
402

C54MY

2

10%.1UF

10V
X5R
402

C56MY

2

10%.1UF

10V
X5R
402

1

1

1

1

1

1

1

1

1

1

Q1MY

MMBT3904
XSTR

1

1

1220

8

OUT

7

2161

71

3

1

2

PM_EXTTS1_N

7

V_SM_VTT

IN

DDR_THERM2

DDR_THERM1

1

0

402

R8MY

5%
CH

2

2

.063W

.063W

.063W

.

.063W

1

063W

C30MY

1000PF
10%
50V
X7R
603

5%

A93565-001

5% 56

A93565-001

A93565-001

5%

A93565-001

5%IC56

A93565-001

PM_EXTTSD1_N

6

RP1MY

8

1

M_A_BS<2>

7

2

M_A_A<7>

6

3

M_A_A<11>

45

M_CKE<1>

56

SM

IC

RP

5MY

8

1

M_A_A<9>

7

2

M_A_A<12>

3

6

M_A_A<6>

45

IC

IC

IC

M_CKE<0>

SM

RP6MY

8

1
2

3

1

2
3

1

2
3

45

RP7MY

RP8MY

565%

SM

56

SM

SM

7

6

54

8

7
6

54

8

7
6

M_A_A<3>

M_A_A<5>

M_A_A<4>

M_A_A<8>

M_A_A<2>

M_A_A<1>

M_A_A<0>

M_A_BS<1>

M_A_CAS_N

M_A_WE_N

M_A_BS<0>

M_A_A<10>

2

3

4

5

6

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

D+

D-

THERM*

GND

13

13

13

12

13

13

13

12

13

13

13

13

13

13

13

13

13

13

13

13

U1MY

ADM1032

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

SDATA

ALERT*

VDD

SCLK

IC

5

71

VCC3

1

8
7

PM_EXTTSD0_N

6

2161

IN

1

2

SMB_CLK_S
SMB_DATA_S

1

0

402

V_SM_VTT

C29MY

0.1UF
20%
16V
Y5V
402

R7MY

2

5%
CH

45

RP9MY

8

1

2

3

.063W

IC

A93565-001

RP10MY

1

2
3

45

063W

.

5%

IC

A93565-001

RP11MY

1

2

3

5%5456

.063W

IC

A93565-001

RP12MY

1

2
3

.

063W

IC

6

54

565%

SM

8

6

56

SM

8

6

SM

8

6

54

565%

SM

7

M_CS_N<1>

7

M_B_WE_N

7

M_B_BS<0>

7

M

M_ODT <0>

_A_RAS_N

M

M_ODT <1>

M_ODT <2>

M_B_A<13>

M_B_CAS_N

M_B_BS<1>

M_B_RAS_N

M_CS_N<2>

M_B_A<3>

M_B_A<0>

M_B_A<1>

_B_A<10>

A93565-001

RP2MY

1

8

M

_B_A<7>

7

.063W

19 20 22

IN

19 20 223350

BI

PM_EXTTS0_N

2

3

5%

IC

A93565-001

M_B_A<5>

6

M_B_A<2>

54

M_B_A<4>

56

SM

33

50

19

12

OUT

Wed Feb 07 17:18:21 2007

4 2

3

12 19

OUT

13 19

OUT

12 19

OUT

12 19

OUT

V_SM_VTT

216171

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

12 20

13 20

13 20

13 20

13 20

13 20

12 20

13 20

13 20

13 20

13 20

13 20

13 20

13 20

13 20

13 20

IN

[PAGE_TITLE=DDR TERMINATION AND THERMAL]

BPAGE DRAWING

tawas_b.sch_1.21

3

2

063W

5%

.

IC

A93565-

5%

.

063W

IC

1

56

402

1

56

402

1

56

402

1

56

402

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

MODULE REV DETAILS

MODULE NAME

TAWAS_CORE

RP

3MY

1

8

7

6

56

SM

001

RP4MY

8

7

6
54

56

SM

A93565-001

R9MY

2

5%
CH

R10MY

2

5%
CH

2

R11MY

5%
CH

2

R12MY

5%
CH

M_B_A<12>

M_B_A<8>

M_B_A<6>

M_CKE<3>

M_B_BS<2>

M_B_A<9>

M_A_A<13>

M_CS_N<0>

M_CS_N<3>

M_ODT <3>

2

3

45

1

2

3

DOCUMENT_NUMBER

M_B_A<11>

M_CKE<4>

D89092

OUT
OUT

OUT
OUT

OUT

OUT

OUT

OUT

OUT
OUT
OUT
OUT

REV

13 20

13 20

13 20

13 20

12

12

13

13

13

12

12 20

12 20

1

DATE

2-05-071. 02.01

D

20

20

20

20

19

19

C

B

A

PAGE

REV

21

2.0

1

CR-22 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE22

8

VCC3

37

D

C

40

22

67686972
445052

9

2226

31

323337
54555665
7577

SLP_M_N

IN

R300CK

1K

402

404450525455
77

IN

1

2

V_3P3_STBY\G

IN

5%
CH

IN

SLP_M

C112CK

1UF

20%

16V
EMPTY
805

1

R97CK

10K

5%
CH

2

402

1

SLP_M_CK_R

G

PFET_VDD_CLK_R

R301CK
10K
5%

CH
402

SLP_M

Q3

CK

MMBT3904
XSTR

56656768697275

V_3P3_STBY\G

9

2226

31

3233

B

19

20

2133

50

20

2133

50

19

A

2

S

D

3

202341-012

OUT

22

23

R105CK

1

0

EMPTY

603

R10CK

1

0

EM

603

Q2CK
PMOSFET

100CK

R

1

0

603

VDD_CLK

1

C8CK

7UF

4.
20%

10V

2

Y5V
805

22

IN

IN

BI

BI

7

2

1A

2

1A

PTY

2

1A

CH

CK_PWRGD_R

CK_BSEL1

SMB_DATA_S

SMB_CLK_S

R104CK

1

0

603

R18CK

1

0

402

202341-012

103CK

R

1

0

603

R101CK

1

0

603

R102CK

1

0

603

2

1A

CH

2

5%
CH

2

1A

CH

2

1A

CH

2

1A

CH

1

C10CK

.1UF
10%
16V

2

X7R
402

1

C13CK

4.7UF
20%

10V

2

Y5V
805

1

C2

.1UF
10%
16V

2

X7R
402

V

1

C4CK

.1UF
10%
16V

2

X7R
402

VDD_CK_VDD_REF

1

C1CK

.1UF
10%
16V

2

X7R
402

R12CK

1

1K

402

R61CK

1

0

402

R63CK

15%2

0

402

Y1CK

14.318MHZ

1

VDD_CK_VDD_PCI

VDD_CK_VDD_48

1

2

VDD_CK_VDD_SRC

1

CK

2

DD_CK_VDD_CPU

2

5%
CH

2

5%
CH

CH

2

XTAL

SM

6

C9CK
.1UF
10%
16V
X7R
402

C3

CK

.1UF
10%
16V
X7R
402

TESTMODE_FSB1_CK505

SMB_DATA_CK505

SMB_CLK_CK505

OSC_CK14M_XTALOUT

OSC_CK14M_XTALIN

BOM NOTE:

MOD U1CK TO
D31101-003

2

VDD_PCI

9

VDD_48

16

VDD_PLL3

39

VDD_SRC

55

VDD_CPU

61

VDD_REF

56

CKPWRGD/PWRDWN*

57

FSB/TESTMODE

63

SDA

64

SCL

59

XTAL_OUT

60

XTAL_IN

REV=1.01

31

IN

DESIGN NOTE:

U1CK

CK505_64PIN

REF/FSC/TESTSEL

R67CK

2

1

1K

5%
CH

402

MANUFACTURING TEST REQUIREMENT

45

PCIF5/ITP_EN
PCI4/SRC5_EN

PCI2/LTE
PCI1/CR_B*
PCI0/CR_A*

USB/FSA

VSS_PCI

VSS_48

VSS_REF

IO_VOUT

1of 2

CK_PWRGD_RCK_PWRGD

PCI3

OUT

CAD NOTE:

CLK PCI 2,4, 5: DO NOT STUB OFF MORE THAN 250 MILS

CLK PCI 2,4,5 (PULL-UP/PULL-DOWNS): OVERLAP PADS

62

7
6
5
4
3
1

10

8
11
58

48

IC

22

3

STRAP MODE STUFF UNSTUFF

SRC5_EN

23

IN

23

IN

40

DESI

R118CK.1 CHANGED FROM
V_1P05_CORE TO
V_3P3_STBY\G
CHANGE TO VDD_CLK FOR
FAB C

CK505_IO_VOUT_PIN48

LT ENABLED

LTE

LT DISABLED

SRC5 ENABLED

SC

ITP ENABLED ( SRC8 DISABLED)

ITP_EN

SRC8 ENABLED (ITP DISABLED)

CK_BSEL2

CK_BSEL0

676869727577
2226

31

323337

44505254555665

GN NOTE:

2

33

402

R5 DISABLED

1K

402

1K

402

9

IN

R2CK

1

5%
CH

DESIGN NOTE:

BSEL BIASING RES

2

C12CK

27PF
5%
50V

1

COG
603

8

7

2

C11CK

27PF
5%
50V

1

COG
603

6

5

4 2

ALWAYS STUFF

BPAGE DRAWING

tawas_b.sch_1.22

Wed Feb 07 17:18:22 2007

3

[PAGE_TITLE=CK505 PAGE [ 1 OF 3 ]]

2

VCC3

2

R11CK

1

2

5%
CH

2

CK_REF_R

CK_PCI5_R
CK_PCI4_R
CK_PCI3_R
CK_PCI2_R
CK_PCI1_R
CK_PCI0_R

CK_USB_R

R13CK

1

2

5%
CH

V_3P3_STBY\G

CK505_IO_VOUT_R

1

C26CK

100.0PF
5%
50V

2

COG
603

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

MODULE REV DETAILS

MODULE NAME

CK505_TAWAS 00.02.00 10-24-06

PCI2 PULLUP R65CK

PCI2 PULLDWN R66CK

P

CI4 PULLUP R4CK

I4 P ULLDWN R5CK

PC

PCI5 PULLDWN R24CK

1

1

R26CK

10K

5%
CH

402

R24CK

10K

5%
EMPTY

402

805

R118CK

1

0

OUT

OUT
OUT
OUT
OUT
OUT
OUT

OUT

1A

CH

1

1

2

1

2

R4CK

10K
5%

EMPTY
402

R5CK

10K
5%

CH
402

R120CK

47K
5%

2

EMPTY
402

R121CK

1

47K
5%

EMPTY

2

402

24

24
24
24
24
24
24

24

2

R3CK

1

15

5%
CH

2

805

VDD_CLK_R_INIT _IO

3

Q1CK

1

MMBT3904
XSTR

2

VDD_CLK_IO

DOCUMENT_NUMBER

D89092

1

REV

PCI2 PULLDWN R66CK

PCI2 PULLUP R65CK

PCI4 PULLDWN R5CK

PCI4 PULLUP R4CK

PCI5 PULLDWN R24CKPCI5 PULLUP R26CK

PCI5 PULLUP R26CK

2

2

1

1

R65CK

10K
5%

CH
402

R66CK

10K
5%

EMPTY
402

DATE

VCC3

1

R119CK

0
5%

2

EMPTY
402

R79CK

1

0

1A

EMPTY

2

603

23

OUT

PAGE

22

1

REV

2.0

D

C

B

A

CR-23 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE23

8

22

IN

D

DESIGN NOTE:

STUFF WITH 64 PIN PART

1

1

2

C

104CK

.1

UF
20%
50V
EMPTY
805

C

110CK

.1UF
20%
50V

2

EMPTY
805

C

VDD_CLK_IO

CAD NOTE:

1

C

105CK

.1

UF
20%
50V

2

X7R
805

7

CK505 VDD_*_ IO BULK DCPL: PLACE AROUND CK505

NOTE:

CAD

1

1

1

C102CK

10UF
20%

6.3V

2

2

X5R
805

CK505 VDD_*_IO DCPL: PLACE (1) PER PIN

1

1

C

106CK

.1

UF
20%
50V

2

2

X7R
805

CK_PE_SRC8_R_DN

24

OUT

CK_PE_SRC8_R_DP

24

OUT

CK_H_MCH_R_DN

24

OUT

CK_H_MCH_R_DP

24

OUT

CK_H_CPU_R_DN

24

OUT

CK_H_CPU_R_DP

24

OUT

C108CK

10UF
20%

6.

3V
X5R
805

C

103CK

.1UF
20%
50V
X7R
805

C109CK

10UF
20%

6.3V

2

X5R
805

1

C

100CK

.1UF
20%
50V

2

X7R
805

6

C111CK

10UF
20%

6.

3V
X5R
805

1

C21CK

.1UF
10%
16V

2

X7R
603

12
20
26
45
49
36

46
47

50
51

53
54

15
19
23
42
52
29

VDD_IO
VDD_PLL3_IO
VDD_SRC_IO
VDD_SRC_IO
VDD_CPU_IO
VDD_SRC_IO

SRC8-/ITP­SRC8+/ITP+

CPU1­CPU1+

CPU0­CPU0+

VSS_IO
VSS_PLL3
VSS_SRC
VSS_SRC
VSS_CPU
VSS_SRC

U1CK

CK505_64PIN

64 PIN
PART ONLY

CPU_STOP*/SRC5­PCI_STOP*/SRC5+

REV=1

45

SRC11-/CR_G*
SRC11+/CR_H*

SRC10­SRC10+

SRC9­SRC9+

SRC7-/CR_E*
SRC7+/CR_F*

S

RC6-

SRC6+

SRC4­SRC4+

SRC3-/CR_D*
SRC3+/CR_C*

SRC2-/SATA­SRC2+/SATA+

SRC1-/SE2
SRC1+/SE1

SRC0-/DOT96­SRC0+/DOT96+

2of 2

DESIGN NOTE:

SRC 9 THROUGH 11 ARE ONLY AVAILABLE
ON THE 64 PIN PART

32
33

35
34

31
30

43
44

40
41

37
38

28
27

25
24

22
21

18
17

14
13

IC

3

CK_PE_SRC11_R_DN
CK_PE_SRC11_R_DP

CK_PE_SRC10_R_DN
CK_PE_SRC10_R_DP

CK_PE_SRC9_R_DN
C

K_PE_SRC9_R_DP

CK_PE_SRC7_R_DN
CK_PE_SRC7_R_DP

CK_PE_SRC6_R_DN
CK_PE_SRC6_R_DP

PM_STPCPU_N
PM_STPPCI_N

CK_PE_SRC4_R_DN
CK_PE_SRC4_R_DP

CK_PE_SRC3_R_DN
CK_PE_SRC3_R_DP

CK_PE_SRC2_R_DN
CK_PE_SRC2_R_DP

CK_PE_SRC1_R_DN
CK_PE_SRC1_R_DP

CK_96M_DOT_R_DN
CK_96M_DOT_R_DP

2

MODULE REV DETAILS

MODULE NAME

CK505_TAWAS 00.02.00 10-24-06

24

OUT

24

OUT

24

OUT

24

OUT

24

OUT

24

OUT

24

OUT

24

OUT

24

OUT

24

OUT

31

OUT

31

OUT

24

OUT

24

OUT

24

OUT

24

OUT

24

OUT

24

OUT

24

OUT

24

OUT

24

OUT

24

OUT

1

REV

DATE

D

C

B

DESIGN NOTE:

ADD PLANE STI CHING CAPS HERE

32

62

15

1617

1829

63

71

77

A

V_1P05_CORE

81014

IN

R106CK

CPU_BSEL0

CPU_BSEL1

CPU_BSEL2

1

0

402

R107CK

1

0

402

R108CK

1

0

402

EMPTY

7

IN

7

IN

7

IN

2

5%
CH

2

5%

5%

EMPTY

R109CK

1

1K
1%

2

EMPTY
402

2

R115CK

1

0
5%

CH

2

402

1

2

1

2

R110CK

1K

5%
CH

402

R116CK

0
5%

EMPTY
402

1

2

1

2

R111CK

56
5%

EMPTY
402

R117CK

1K

5%
CH

603

R112CK

1

402

R113CK

1

1K

402

R114CK

1

1K

402

2

5%CH1K

2

5%
CH

2

5%
CH

MCH_BSEL0

CK_BSEL0

MCH_BSEL1

CK_BSEL1

MCH_BSEL2

CK_BSEL2

12

BI

22

IN

12

BI

22

IN

12

BI

22

IN

B

A

[PAGE_TITLE=CK505 PAGE [ 2 OF 3 ]]

BPAGE DRAWING

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Wed Feb 07 17:18:23 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

23

2.0

1

CR-24 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE24

8

DESIGN NOTE:

7

6

45

3

SRC CLOCK TERMINATION

1

2

R28CK

2

5%

2

5%

1

33

402

1

33

402

R15CK

2

1

225%

CH

402

R122CK

2

1

22

5%
CH

402

R16CK

15%2

22

CH

402

R23CK

1222

5%
CH

402

R20CK

2

1

225%

CH

402

CLOCK EMI CAPS: DEFAULT EMPTY

1

C7CK

C5CK

F

22P

10PF
5%

5%

50V

50V

2

EMPTY

EMPTY
402

402

1

33

402

R123CK

1

2

33

5%
CH

402

1

33

402

R124CK

1

2

5%

33

CH

402

R36CK

15%2

33

CH

402

R34CK

2

1

5%

33

CH

402

CK_PE_SRC11_R_DN

23

D

C

B

IN

CK_PE_SRC11_R_DP

23

IN

CK_PE_SRC10_R_DN

23

IN

CK_PE_SRC10_R_DP

23

IN

CK_PE_SRC9_R_DN

23

IN

CK_PE_SRC9_R_DP

23

IN

CK_PE_SRC7_R_DN

23

IN

CK_PE_SRC7_R_DP CK_OE_MINICARD1_N

23

IN

CK_PE_SRC6_R_DN

23

IN

CK_PE_SRC6_R_DP

23

IN

CK_PE_SRC4_R_DN

23

IN

CK_PE_SRC4_R_DP

23

IN

CK_PE_SRC3_R_DN

23

IN

CK_PE_SRC3_R_DP

23

IN

CK_PE_SRC2_R_DN

23

IN

CK_PE_SRC2_R_DP

23

IN

CK_PE_SRC1_R_DN

23

IN

CK_PE_SRC1_R_DP

23

IN

A

CK_96M_DOT_R_DN

23

IN

CK_96M_DOT_R_DP

23

IN

DESIGN NOTE:

96M DOT CLOCK SIGNALS: STUFF 33 OHM R39CK AND R40CK FOR MCH GRAPH IC SKU'S
EMPTY R39CK AND R40CK AND STUFF R93U B AND R98UB FOR MCH NON-GRAPHIC SKU'S

R90CK

2

5%
CH

R92CK

2

5%
CH

94CK

R

2

5%
CH

R125CK

1

470
402

R126CK

1

470
402

R4

2

5%
CH

R53CK

2

5%
CH

R52CK

2

5%
CH

R51CK

2

5%
CH

R41CK

2

5%
CH

R39CK

2

5%
CH

5CK

1

470
402

1

33

402

1

33

402

5%

EMPTY

5%
CH

1

402

1

402

1

402

1

402

1

402

1

402

CK_OE_EXPCARD_N

2

R91CK

2

5%
CH

R

2

5%
CH

R9

2

5%
CH

CK_OE_MCH_N

1

470
402

CK_PE_100M_3GPLL_DN

93CK

CK_PE_100M_3GPLL_DP

1

33

402

CK_PE_100M_EXPCARD_DN

5CK

1

CK_PE_100M_EXPCARD_DP

33

DESIGN NOTE:

402

SRC 9 THROUGH 11 ARE ONLY AVAILABLE
ON THE 64 PIN PART

TP_CK_OE_100M_EXT

2

33

R46CK

2

5%
CH

33

R48CK

2

5%
CH

33

R50CK

2

5%
CH

33

R38CK

2

5%
CH

33

R42CK

5%
CH

CK_PE_100M_EXT_DN

CK_PE_100M_EXT_DP

1

33

402

CK_PE_100M_MINICARD2_DN

CK_PE_100M_MINICARD2_DP

1

33

402

CK_PE_100M_ICH_DN

CK_PE_100M_ICH_DP

1

33

402

CK_PE_100M_SATA_DN

CK_PE_100M_SATA_DP

1

33

402

CK_DREF_100M_SS_DN

1332

CK_DREF_100M_SS_DP

402

CK_96M_DREF_DN

33

R40CK

2

5%
CH

1

33

402

CK_96M_DREF_DP

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

37

12

12

12

37

37

39

54

54

40

40

30

30

29

29

12

12

12

12

DESIGN NOTE:

HOST
TERMINATION

DESIGN NOTE:

SINGLE ENDED CLOCK
TERMINATION

31

24
24

31

24

34

2459
2452
24
2480
2455
2455

CLOCK

CK_14M_ICH

IN

CK_48M_USB_ICH

IN

CK_P_33M_ICH

IN

CK_P_33M_TPM

IN

CK_P_33M_LPC

IN

TP_CK_PCI2

IN

CK_P_33M_CRD

IN

CK_14M_EC

IN

CK_P_33M_KBC

IN

23

IN

23

IN

23

IN

23

IN

23

IN

23

IN

1

C15CK

22P
5%
50V

2

EM
402

CK_PE_SRC8_R_DN

CK_PE_SRC8_R_DP

CK_H_MCH_R_DN

CK_H_MCH_R_DP

CK_H_CPU_R_DN

CK_H_CPU_R_DP

22

22

22

22

22

22

22

PTY

F

IN

IN

IN

IN

IN

IN

IN

IN

1

2

CK_REF_R

CK_PCI5_R

CK_PCI3_R

CK

_PCI2_R

CK_PCI1_R

CK_PCI0_R

CK_USB_R

DESIGN NOTE:

C6CK

22PF
5%
50V

PTY

EM
402

EMPTY

R30CK

EMPTY

R35CK

2

5%
CH

R33CK

2

5%
CH

2

MODULE REV DETAILS

MODULE NAME

CK505_TAWAS 00.02.00 10-24-06

CK_14M_ICH

R14CK

15%2

CK_14M_EC

22

CH

402

R19CK

R21CK

R25CK

EMPTY

R17CK

R22CK

1

2

CK_P_33M_CRD

1

2

CK_P_33M_ICH

22

5%
CH

402

CK_P_33M_KBCCK_PCI4_R

2

CK_P_33M_TPM

1

5% 22
CH

402

CK_P_33M_LPC

T

1

2225%

402

CK_OE_MINICARD2_N

CK_OE_SATA_N

2

1

2

5% 2
CH

402

2

1

CK_48M_USB_ICH

5%

22

CH

402

1

C18CK

C17CK

10PF

10PF

5%

5%

50V

50V

2

EMPTY

EMPTY

402

402

P_CK_PCI2

1

2

CK_H_XDP_DN

CK_PE_100M_MINICARD1_DN

CK_H_XDP_DP

CK_PE_100M_MINICARD1_DP

CK_H_MCH_DN

CK_H_MCH_DP

CK_H_CPU_DN

CK_H_CPU_DP

C14CK

10PF
5%
50V
EMPTY
402

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

1

2

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

C16CK

10PF
5%
50V
EMPTY
402

24

24 55

24

24

24 5522

24 59

24 52

24

40

31

24

50

39

50

39

10

10

6

6

1

REV

DATE

31

D

80

34

33

31

1

C20CK

10PF
5%
50V

2

EMPTY
402

C

B

A

[PAGE_TITLE=CK505 PAGE [ 3 OF 3 ]]

BPAGE DRAWING

tawas_b.sch_1.24

Fri Feb 09 14:30:22 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

24

2.0

1

CR-25 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE25

8

7

6

45

3

VCC

D

1

2

C11GD

F

10P
5%
50V
COG
402

FB3GD

1

2

CRT_L1_RED

FB

1

2

D

28

OUT

RT_RED_CONN

C

1

R11GD

150
1%

CH

2

402

C1GD

22PF
5%
50V
COG
402

FB9G

MULTI

2

FB

1

C12GD

10PF
5%
50V

2

COG
402

1

F1GD

THRMSTR

1.10

1

2

2

V_5P0_S_VGA_D

1

MODULE REV DETAILS

MODULE NAME

TAWAS_CORE

GD

CR1
B

13013F

2

SM

D36654-001

1.02.01

1

V_5P0_S_VGA

DIO

REV

2-05-07

1

C4GD

.1UF
10%
10V

2

PTY

EM
402

DATE

OUT

D

25

FB2GD

2

1

CRT_GREEN_CONN

28

OUT

R10GD

1

1

150
1%

CH

2

402

C

CRT_BLUE_CONN

28

OUT

1

R9GD

150
1%

2

CH
402

C9GD

10PF
5%
50V

2

COG
402

FB1GD

1

1

C5GD

10PF
5%
50V

2

COG
402

CRT_L1_GREEN

FB

2

CRT_L1_BLUE

FB

2528

OUT

2528

OUT

CRT_HSYNC_CONN

CRT_

B

V_5P0_S_VGA

25

IN

VCC3

VCC3

3

D

Q2GD
BSS1

38N

1

FET

S

G

2

VCC3

3

Q1GD

D

BSS1

1

FET

S

G

2

A

1

2

C13GD

.1UF
10%

10V
X5R
402

2

1

C16GD

.1UF
10%

10V
X5R
402

VCC3

1

2

[PAGE_TITLE=CRT/VGA]

8

7

6

5

FB5GD

MULTI

FB4GD

2

FB

1

C10GD

F

10P
5%
50V

2

COG
402

2

1

FB

C6GD

10P

F
5%
50V

2

CO

G

402

CRT_L2_RED

CRT_L2_GREEN

CRT_L2_BLUE

CRT_DDC_CLK_CONN

2528

IN

V_5P0_S_VGA

OUT

TP_J10_PIN11
TP_J10_PIN4

1

1

C2GD

22PF
5%
50V

2

G

CO
402

1

MULTI

1

C3GD

22PF
5%
50V

2

COG
402

VSYNC_CONN

C15G

100PF
5%
50V
EMPTY
402

2

1

C14G

D

1

R7GD

2.2K
5%

CH
402

D

100PF
5%
50V

2

EM

PTY

402

R8GD

1

2.2K
5%

CH

2

402

1

2

CRT_DDC_CLK_ISO

CRT_DDC_DATA_ISO

38N

CRT_DDC_DATA

CRT_DDC_CLK

1

R6GD

R5GD

2.2K

2.2K
5%

5%

CH

CH

2

402

402

BPAGE DRAWING

Wed Feb 07 17:18:25 2007

4 2

2528

IN

tawas_b.sch_1.25

CRT_DDC_DATA_CONN

1

1

2

OUT

OUT

C7GD

100PF
5%
50V
EM
402

OUT

OUT

PTY

28

11

11

2528

2528

C8GD

100PF
5%
50V

2

EMPTY
402

CRT_L2_RED

IN

CRT_L2_GREEN

IN

CRT_VSYNC_CONN

IN

CRT_HSYNC_CONN

IN

3

CUSTOM TEXT BPAGE

U1
TVS6V

1

2

3

U2GD
TVS6V

1

2

3

INTEL

CONFIDENTIAL

J1

GD

16

1
9
2

10

3

11
4

12
5

13
6

14
7

15
8

17

6.0V

GD

6

5

4

EMPTY

6.0V

6

5

4

EMPTY

DOCUMENT_NUMBER

RCPT

CRT_L2_BLUE

TP_U62_PIN4

IN

CRT_DDC_DATA_CONN

TP_U63_PIN5

CRT_DDC_CLK_CONN

D89092

1

PAGE

25

VCC3

IN

IN

25
28

25
28

REV

2.0

C

B

A

CR-26 : @TAWAS_B_LIB.TAWAS_B(SCH_1):PAGE26

8

D

71

73

C

B

7

SLP_S3_N

18

3137

55697275

45

61

6265666869

77

7883

IN

INTERMEDIATE_BUS_POWER

61

62636566686970

IN

7475767778

L_BKLTEN

11

IN

V_5P0_STBY\G

9

3233

IN

707576

L_VDDEN

11

IN

6

VCC3

1

G

L_VDDEN_N

BSS138N

R15GD

1

100K

603

R14GD

1

1.

0M

5%

2

CH
603

3

INV_SRC_CTRL

D

S

2

Q4GD

FET

2

L

_VDDEN_N_R

5%
CH

GD

Q6
BSS138N

FET

VCC

3

D

S

2

1

C17GD

1000P
10%

50V

2

X7R
603

R19GD

INV_SRC_CTRL_DEL AY

2

1

5%

100K

CH

603

1

R18GD

1M
1%

2

CH
603

1

C30G

.1UF
10%
10V

2

X5R
402

1

G

1

2

1

R13GD

100K

5%

402

CH

525558

5255

58

D

4044505254

3

D

Q3GD
IRLML5103TR

1

F

FE

T

S

G

2

11

IN

11

IN

45

D

C22G

1000PF
10%
50V
X7R
603

R12GD

1

100 5%
402

2

33

BI

33

BI

5255

BI

555665676869727577
2231323337
9

IN

1

C33GD

0.1UF
20%

16V

2

Y5V
402

BOM NOTE:

REPLACE WITH 22UF
TANTLUM 202244-073

L_DDC_CLK
L_DDC_DATA

INV_SRC_FB

3

D

1

S

G

2

2

CH

SMB_BAT2_DATA

SMB_BAT2_CLK
EC_KEY_INT_N

V_3P3_STBY\G

1

1

2

C20GD

33UF

20%

4.0V
TANT

3528

C18GD

0.
20%
16V

212

Y5V
402

1

R16GD

2.2K
5%

2

CH
402

Q5GD
IRLML5103TR

FET

R4GD

1

2

0

5%

EMPTY

402

1

C32GD

0.1UF
20%
16V

2

Y5V
402

C21GD

1UF

1UF

0.
20%
16V
Y5V
402

1

R17GD

2.
5%

2

CH
402

A

BKLTEN

55
11
55

INV_SMB_INT_N

2K

3

FB10GD

2

1

FB

EC_LAMP_STAT

OUT

L_BKLTCTL

IN

DAC_BRIG

IN

0

402

VCC3

41
41

L_VDD_VDL

R2GD

1

30
30

5%

EMPTY

1

2

INV_SMB_DATA

2

R3GD

1

0

402

U

BI

USB_9_DP

BI

C31GD

.1UF
10%
10V
X5R

44

402

44

VCC3

INV_SRC

12

2

5%

EMPTY

SB_9_DN

OUT
IN

OUT
OUT

11

IN

11

IN

11

IN

11

IN

11

IN

11

IN

11

IN

11

IN

11

IN

11

IN

11

IN

11

IN

11

IN

11

IN

11

IN

11

IN

[PAGE_TITLE=LVDS\LCD PANEL]

2

1

C29GD

.1

UF
10%
10V

2

X5R
402

L_CTRL_DATA

BI

11

INV_SMB_CLK

L_CTRL_CLK

BI

DMIC_DATA

AUD_
AUD_DMIC_CLK

AUD_AMIC_R
AUD_AMIC_L

1

C19GD

0.1UF
20%
16V

2

Y5V
402

LA_DATA0_DN
LA_DATA0_DP

LA_DATA1_DN
LA_DATA1_DP

LA_DATA2_DN
LA_DATA2_DP

LA_CLK_DN
LA_CLK_DP

LB_DATA0_DN
LB_DATA0_DP

LB_DATA1_DN
LB_DATA1_DP

LB_DATA2_DN
LB_DATA2_DP

LB_CLK_DN
LB_CLK_DP

1

MODULE REV DETAILS

MODULE NAME

TAWAS_CORE

TP_PIN5

TP_PIN25

A_GND_LVDS

REV

1.02.01 2-05-07

J3GD

2X15HDR_6MTG

IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO

REQ 4813

1OF1

REV=1

CONN

1

4022CH

J2GD

2X15HDR_6MTG

IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO

REQ 4813

1OF1

IO
IO
IO
IO
IO
IO

0

CONNREV=1

R1GD

IO
IO
IO
IO
IO
IO

5%

DATE

D

C

B

A

BPAGE DRAWING

tawas_b.sch_1.26

Wed Feb 07 17:18:26 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

D89092

PAGE

REV

26

2.0

1