Intel Stratix 10 SX SoC Quick Start Guide

Intel® Stratix® 10 SX SoC

Development Kit User Guide

Subscribe	UG-20081 | 2020.09.08
Send Feedback	Latest document on the web: PDF | HTML

	Contents
Contents
1. Overview........................................................................................................................	4
1.1. General Development Kit Description........................................................................	4
1.2. Recommended Operating Conditions........................................................................	5
1.3. Handling the Development Kit.................................................................................	5
2. Getting Started...............................................................................................................	6
2.1. Installing Quartus Prime Software............................................................................	6
2.2. Installing the Intel FPGA Download Cable..................................................................	7
2.3. Installing the Intel SoC Embedded Development Suite (EDS).......................................	7
2.4. Installing the Intel Stratix 10 SX SoC Development Kit Package...................................	7
3. Development Kit Setup...................................................................................................	9
3.1. Inspect the Development Kit...................................................................................	9
3.2. Default Setup of the Development Kit.......................................................................	9
3.3. Intel MAX 10 System Controller Updates.................................................................	10
4. Development Kit Components.......................................................................................	12
4.1. Development Kit Feature Summary........................................................................	12
4.2. Board Components...............................................................................................	14
4.3. Intel Stratix 10 SoC Device Overview.....................................................................	17
4.4. Intel MAX 10 System Controller Overview...............................................................	22
4.5. FPGA Configuration..............................................................................................	24
4.6. General User Input/Output....................................................................................	24
4.7. Connectors and Interfaces....................................................................................	25
4.7.1. PCIe Slot................................................................................................	25
4.7.2. ZQSFP+..................................................................................................	28
4.7.3. SFP+......................................................................................................	29
4.7.4. HDMI.....................................................................................................	29
4.7.5. SDI Port.................................................................................................	30
4.7.6. MXP.......................................................................................................	30
4.7.7. Intel FPGA Download Cable Direct Port (Debug Port).....................................	31
4.7.8. FMC+ A/B Slot.........................................................................................	32
4.7.9. FMC+ A/B LVDS Interfaces (LPC Pins).........................................................	38
4.7.10. LMK05028 Jitter Attenuator.....................................................................	45
4.7.11. FPGA-IOMAX10 Interface........................................................................	46
4.8. Daughter Cards...................................................................................................	49
4.8.1. HPS IO-48 OOBE Daughter Card................................................................	49
4.8.2. HPS IO-48 NAND Flash Daughter Card........................................................	59
4.8.3. HPS Boot Flash Card.................................................................................	67
4.9. System Memory...................................................................................................	72
4.9.1. FPGA Memory (DDR4 SO-DIMM)................................................................	72
4.9.2. HPS Memory (External 4 GB HILO x72 DDR4 ).............................................	76
4.9.3. HPS I2C Interface.....................................................................................	81
4.10. System Power....................................................................................................	82
4.10.1. Power Supply Options.............................................................................	82
4.10.2. Power Sequence.....................................................................................	83
4.10.3. Power Distribution Network.....................................................................	84

Intel® Stratix® 10 SX SoC Development Kit User Guide	Send Feedback
2

Contents

5. Board Test System........................................................................................................	86
5.1. Preparing the Board.............................................................................................	87
5.2. Running the BTS..................................................................................................	87
5.3. Using the BTS.....................................................................................................	87
5.3.1. The Configure Menu.................................................................................	87
5.3.2. The GPIO Tab..........................................................................................	89
5.3.3. The QSFP/SFP Tab....................................................................................	90
5.3.4. The PCIE Tab...........................................................................................	93
5.3.5. The MXP Tab...........................................................................................	96
5.3.6. The FMCA Tab..........................................................................................	99
5.3.7. The FMCB Tab........................................................................................	105
5.3.8. The DDR4 Tab........................................................................................	110
5.3.9. Power Monitor........................................................................................	111
5.3.10. The Clock Control.................................................................................	113
A. Additional Information...............................................................................................	115
A.1. Modify the Intel Stratix 10 SX SoC Development Kit to use a battery for the BBRAM...	115
A.2. Modify the Intel Stratix 10 SX SoC Development Kit HPS DDR4 memory width and
ECC configuration using the Golden Hardware Reference Design project..................	116
A.3. Safety and Regulatory Information.......................................................................	117
A.3.1. Safety Warnings.....................................................................................	117
A.3.2. Safety Cautions.....................................................................................	119
A.4. Compliance Information......................................................................................	121
A.4.1. Compliance and Conformity Statements....................................................	121
B. Revision History..........................................................................................................	122
B.1. Revision History ................................................................................................	122

Send Feedback	Intel® Stratix® 10 SX SoC Development Kit User Guide
	3

UG-20081 | 2020.09.08

Send Feedback

1. Overview

This document describes the features of the Intel® Stratix® 10 SoC development kit, including detailed pin-out and component reference information required to create custom FPGA designs that interface with all components of the board.

This development board comes in two different versions as shown in the table below.

Table 1.		Development Kit Version Information
	Development Kit Version			Ordering Code	Device Part Number
	Intel Stratix 10		SX SoC L-Tile	DK-SOC-1SSX-L-A	1SX280LU2F50E1VG
				DK-SOC-1SSX-L-D
	Intel Stratix 10		SX SoC H-Tile	DK-SOC-1SSX-H-A	1SX280HU2F50E1VGAS

Figure 1. Development Kit Picture

1.1. General Development Kit Description

The Intel Stratix 10 SoC development board provides a hardware platform for developing and prototyping low-power, high-performance and logic-intensive designs using Intel Stratix 10 SoC. The board provides a wide range of peripherals and memory interfaces to facilitate the development of Intel Stratix 10 SoC designs.

	Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,
	Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or	ISO
	other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
		9001:2015
	accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
		Registered
	at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
	information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
	customers are advised to obtain the latest version of device specifications before relying on any published
	information and before placing orders for products or services.
	*Other names and brands may be claimed as the property of others.

1. Overview

UG-20081 | 2020.09.08

Figure 2. Intel Stratix 10 SoC Development Kit Block Diagram

				Intel® Enpirion® Power Solutions
					HPS Daughtercard
			Boot Flash	10/100/1000	USB 2.0	UART	Micro
				RGMII PHY	PHY
			DC			to USB	SD Port
				KSZ9031RNX	USB3320			SEEPROM/
								RTC/TEMP
			<![if ! IE]> <![endif]>SDMIBus	<![if ! IE]> <![endif]>RGMII	<![if ! IE]> <![endif]>USB2.0	<![if ! IE]> <![endif]>UART1TX/RX		LT_12C
								ClockI2C
								Ext I2C 1
FPGA Boot	SDMI Bus							Ext I2C 2
Flash DC		2F	SDM + JTAG + 05Cdk1		HPS_I/O		I2C 1	PMBUS_VID
(optional)

Intel® MAX 10

DDR4

2M

FPGA

HILO x72

2M

JTAG Switch

Signal Rank

3A

and Power

2L

Sequencer

HPS

Controller

Clock

Block

FPGA

SGMII

Intel FPGA

3I

<![if ! IE]> <![endif]>DDR3/DDR4

Download

MAC CORE

Cable II

2X

PHY

DDR4 Dual

3J

<![if ! IE]> <![endif]>Hardcore

SODIMM x72

Rank

3K

4E

x2

SGMII

88E1111

3L

4L

x4

x1

PCle® Gen3 x 16

PCle® Gen3 x 16

100G / 50G

4K

MXP

Hardcore CxP

2A

3C

FPGA

3A

2C

Hardcore

Hardcore

4M

/

/

/

/

SFP+

1C

1D

1E

1F

2B

3B

I/O

3L

2B

1K

1L

1M

1N

4C

4D

4E

4F

4N

4 Channels

HDMI

24 Channels

<![if ! IE]> <![endif]>Channels16

LVDS Bus

Avalon®-ST

x1

SDI/O

FMCA

FPGA_I/O

x2

16/32 Bus

<![if ! IE]> <![endif]>Channels24

<![if ! IE]> <![endif]>Bit-68Bus

ZQSFP

<![if ! IE]> <![endif]>DPIO

<![if ! IE]> <![endif]>I/OSDI

Gen3/Gen2/Gen1

FPGA

PCle EP

V57.4

Intel

PCle

MAX 10

Avalon-ST

x16 RC

Trace 16/32

(optional)

Intel MAX 10

FPGA_I/O

FMCA

HBA, HBB

V57.4

FPP

Flash

PCle EP

1.2.Recommended Operating Conditions

•Recommended ambient operating temperature range: 0 °C to 45 °C

•Maximum ICC load current: 190 A

•Maximum ICC load transient percentage: 30%

•FPGA maximum power supported by the supplied heatsink/fan: 300 W

1.3.Handling the Development Kit

When handling the board, it is important to observe static discharge precautions.

Caution: Without proper anti-static handling, the board can be damaged. Therefore, use antistatic handling precautions when touching the board.

Caution: You must not operate this development kit in a vibration environment.

Send Feedback	Intel® Stratix® 10 SX SoC Development Kit User Guide

5

UG-20081 | 2020.09.08

Send Feedback

2. Getting Started

2.1. Installing Quartus Prime Software

The Intel Quartus® Prime design software is a multiplatform design environment that easily adapts to your specific needs in all phases of FPGA, CPLD, and SoC designs. The Intel Quartus Prime software delivers the highest performance and productivity for Intel FPGAs, CPLDs, and SoCs.

Design software must enable dramatically increased design productivity in order to take advantage of devices with multi-million logic elements with increased capabilities that provide designers with an ideal platform to meet next-generation design opportunities.

The new Intel Quartus Prime Design Suite design software includes everything needed to design for Intel FPGAs, SoCs and CPLDs from design entry and synthesis to optimization, verification and simulation. The Intel Quartus Prime Design Suite software includes an additional Spectra-Q® engine that is optimized for Intel Stratix 10 and future devices. The Spectra-Q engine enables new levels of design productivity for next generation programmable devices with a set of faster and more scalable algorithms, a hierarchical database infrastructure and a unified compiler technology.

Intel Quartus Prime

The Intel Quartus Prime Design Suite software is available in three editions based on specific design requirements: Pro, Standard, and Lite Edition.

The Intel Quartus Prime Pro Edition is optimized to support the advanced features in Intel's next generation FPGAs and SoCs and requires a paid license.

Intel Quartus Prime Standard Edition includes the most extensive support for Altera's latest device families and requires paid license.

Intel Quartus Prime Lite Edition provides an ideal entry point to Intel's high-volume device families and is available as a free download with no license file required.

Included in the Intel Quartus Prime Pro Edition are the Intel Quartus Prime software, Nios® II EDS and the MegaCore IP Library.

To install Intel's development tools, download the Intel Quartus Prime Pro Edition software from the Quartus Prime Pro Edition page in the Download Center of Intel's website.

	Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,
	Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or	ISO
	other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
		9001:2015
	accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
		Registered
	at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
	information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
	customers are advised to obtain the latest version of device specifications before relying on any published
	information and before placing orders for products or services.
	*Other names and brands may be claimed as the property of others.

2. Getting Started

UG-20081 | 2020.09.08

2.2. Installing the Intel FPGA Download Cable

The Intel Stratix 10 SoC Development Kit includes embedded Intel FPGA Download Cable circuits for FPGA and Intel MAX® 10 programming. However, for the host computer and board to communicate, you must install the Intel FPGA Download Cable driver on the host computer.

Installation instructions for the Intel FPGA Download Cable driver for your operating system are available on the Intel website.

On the Intel website, navigate to the Cable and Adapter Drivers Information link to locate the table entry for your configuration and click the link to access the instructions.

2.3. Installing the Intel SoC Embedded Development Suite (EDS)

The Intel SoC EDS is a comprehensive software tool suite for embedded software development on Intel SoC devices. It contains development tools, utility programs, run-time software, and application examples to expedite firmware and application software of SoC embedded systems.

As a part of the Intel SoC EDS, the Arm* Development Studio (DS) Intel SoC FPGA Edition Toolkit provides a comprehensive set of embedded development tools for Intel's SoC FPGAs.

For more information and steps to install the SoC EDS Tool Suite refer to the links below.

Related Information

•Arm Development Studio (DS) Intel SoC FPGA Edition

•Intel SoC FPGA Embedded Development Suite User Guide

2.4.Installing the Intel Stratix 10 SX SoC Development Kit Package

The Intel Stratix 10 SX SoC Development Kit offers a quick and simple approach for developing custom Arm processor-based SoC designs. The Intel Stratix 10 SX SoCs offer full software compatibility with previous generation SoCs, a broad ecosystem of Arm software and tools, and the enhanced FPGA and digital signal processing (DSP) hardware design flow.

Intel Stratix 10 SX SoC Development Kit Package Installer is a single installation file contains that Intel Stratix 10 SX SoC Development Kit board design files, documents, and examples including the Board Test System (BTS) installation files.

Download and unzip Intel Stratix 10 SX SoC Development Kit Package Installer first. Install the Intel Stratix 10 SX SoC Board Test System.

Note: To view the the layout *.brd files in the board package, you can download the Cadence® Allegro®/OrCAD® Free Viewer from Cadence's website.

For additional information, refer to the Intel Stratix 10 SX SoC Development Kit webpage on Intel's website using the link provided at the end of this section.

Send Feedback	Intel® Stratix® 10 SX SoC Development Kit User Guide

7

2. Getting Started

UG-20081 | 2020.09.08

Related Information

•Intel Stratix 10 SX SoC Development Kit

•Cadence Allegro

Intel® Stratix® 10 SX SoC Development Kit User Guide	Send Feedback

8

UG-20081 | 2020.09.08

Send Feedback

3. Development Kit Setup

The instructions in this chapter explain how to setup the Intel Stratix 10 SoC Development Board.

3.1. Inspect the Development Kit

To inspect the board, perform the following steps:

1.Place the board on an anti-static surface and inspect it to ensure that it has not been damaged during shipment.

2.Verify that all components on the board appear in place and intact.

Caution:		Without proper anti-static handling, you could damage the board.
Table 2.		Stratix 10 SoC Development Kit Contents
		Item		Quantity
	Intel Stratix 10 SoC Development Board			1
	USB Cable			2
	USB Cable Micro			1
	Ethernet Cable			1
	HPS IO48 OOBE Daughter Card			1
	HPS IO48 NAND Daughter Card			1
	SODIMM Memory Card			1
	QSPI Flash			1
	SD Micro Flash			1

Related Information

•Thermal Management for FPGAs

•Intel Intel Enpirion® Digital Power Configurator Graphical User Interface (GUI)

3.2.Default Setup of the Development Kit

This development kit ships with its board switches preconfigured to support the design examples in the kit.

1.Power up the development board by using the included power supply.

2.When configuration is complete, the configuration done green LED (D22) illuminates, signaling that the Intel Stratix 10 device is configured successfully.

	Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,
	Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or	ISO
	other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
		9001:2015
	accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
		Registered
	at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
	information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
	customers are advised to obtain the latest version of device specifications before relying on any published
	information and before placing orders for products or services.
	*Other names and brands may be claimed as the property of others.

3. Development Kit Setup

UG-20081 | 2020.09.08

Caution: Use only the provided power supply. Power regulation circuits on the board can be damaged by power supplies with greater voltage and a lower-rated power supply may not be able to provide enough power for the board.

Table 3.		Default Setup
	Checkpoint		Name	Reference	Description
	1		Power Switch	SW7	Power is turn off at left position
	2		Power Adapter connector	J25, J55	Both connectors can be used to connect the
					power adapter
	3		Intel Intel Enpirion®	J29	You can install Intel Enpirion dongle to
					monitor the board power rails. Switch 8 is at
					off position.
	4		JTAG Dongle connector	J1	You can install Intel JTAG dongle to access
					FPGA
	5		JTAG Switch	SW1	Default Setup from bit 1 to bit 8 is “off, off,
					on, on, on, on, on, on”: Intel Stratix 10 SoC
					and Intel MAX 10 are on the JTAG chain
	6		USB JTAG Port	J57	You need connect Micro USB cable to access
					Intel Stratix 10 SoC
	7		12V Fan Connector	J16	You need use it to connect thermal Fan
	8		Boot Switch	SW4	Default set up from bit 1 to Bit 4 is “on, off,
					on, off”
					FPGA/HPS I2C is enabled. Daughter card
					power is on
	9		MSEL Switch	SW2	Default Setup is “on on on on”: JTAG mode

3.3. Intel MAX 10 System Controller Updates

The Intel MAX 10 System Controller manages several features on the Intel Stratix 10 SX SoC Development kit, including clocks, I2C, and some configuration signals. In certain situations, it may be necessary to ensure the Intel MAX 10 System Controller internal flash contains the latest available design. This may include the Intel Stratix 10 device failing to configure from OSC_CLK_1, or when other unexpected issues arise. The latest System Controller design is included in the Intel Stratix 10 SX Soc Development Kit Installer Package, in the “system_max10” folder inside the “examples” folder.

To update the internal flash, follow the steps outlined in the procedure below:

1.Power off the Intel Stratix 10 SX SoC Development Kit.

2.Ensure SW1 and SW2 are set to the default settings so the System Intel MAX 10 is on the JTAG chain and the Intel Stratix 10 device does not automatically configure itself.

3.Connect a micro USB cable to J57 for JTAG access and power on the board.

4.Open the Intel Quartus Prime Programmer and scan the device chain.

5.Right click on the Intel MAX 10 and select “Change File”. Navigate to the “system_max10” folder and select the .pof file, for example, “max10_system_rev13.pof”.

Intel® Stratix® 10 SX SoC Development Kit User Guide	Send Feedback

10

3. Development Kit Setup

UG-20081 | 2020.09.08

6.Check the Program/Verify box in the row with the .pof and the Intel MAX 10 Device. The Program/Verify boxes in the immediately following rows, CFM0 and UFM, will auto-check as well. Refer to the following screenshot:

7.Click Start and wait for the programming cycle to finish.

8.Power off the board and reset SW1 and SW2 to prior settings, if any.

Send Feedback	Intel® Stratix® 10 SX SoC Development Kit User Guide

11

UG-20081 | 2020.09.08

Send Feedback

4. Development Kit Components

This chapter introduces the major components on the Intel Stratix 10 Development Board. The board overview figure illustrates the component locations and the board components table provides a brief description of all component features of the board.

4.1. Development Kit Feature Summary

Table 4.		Intel Stratix 10 SoC Development Kit Feature Summary
		Feature	Description
	Programmable Logic		• Intel Stratix 10 SoC FPGA
			• 10M04SCU169C8G Intel MAX 10 CPLD as the Intel FPGA Download Cable
			and JTAG switch device
			• 10M16SAU169C8G Intel MAX 10 CPLD as the Power manager and
			sequencer device
			• 10M50DAF484I7G Intel MAX 10 CPLD as the IO level translator, IO MUX
			and Passive AVST-16 FPGA controller device
	HPS memory		1066 MHz 4 GB 72-bit HILO memory card
	HPS Boot Flash (Flash Card)		• Boot Codes for QSPI, SD Micro
			• QSPI Flash: 256 MB (MT25QU02GCBB8E12-0SIT)
			• SD Micro Flash Card: 16 GB (Kingston)
	HPS IO48 OOBE Daughter Card		• One HPS IO48 60-pin Samtec Connector
			• One RGMII 10/100/1000 Mbps Ethernet port: Standard RJ-45
			• One UART port: Standard USB Mini-B Receptacle
			• One Micro SD Card Connector: Standard Micro SD Card Socket
			• One USB 2.0 port: Standard USB Micro-AB Receptacle
			• One Mictor 38-pin connector (JTAG only without Trace signals)
			— Two JTAG targets selected by the resistors MUX: FPGA JTAG chain
			(optional) and HPS JTAG Port (default)
			• I2C: HPS I2C port
			• GPIO
			— 2 Push buttons
			— 3 LEDs
			— 1 Ethernet Interrupt from Ethernet PHY
			— 1 USB over-current indicator
			• HPS Clock: 25 MHz oscillator
	HPS IO48 NAND Flash Daughter Card		• One HPS IO48 60-pin Samtec connector
			• One RGMII 10/100/1000 Mbps Ethernet port: Standard RJ-45
			• One UART port: Standard USB Mini-B Receptacle
			• NAND Flash (x16): 8 Gb
			• eMMC (x8): 8 GB 5.0 compliant eMMC
			continued...

	Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,
	Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or	ISO
	other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
		9001:2015
	accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
		Registered
	at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
	information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
	customers are advised to obtain the latest version of device specifications before relying on any published
	information and before placing orders for products or services.
	*Other names and brands may be claimed as the property of others.

4. Development Kit Components

UG-20081 | 2020.09.08

Feature			Description
	• I2C: HPS I2C port
	•	GPIO
		—	2 Push Buttons
		— 3 LEDs
		— 1 Ethernet Interrupt from Ethernet PHY
	• HPS Clock: 25 MHz oscillator
FPGA memory	1200 MHz 16 GB DDR4 SO-DIMM MTA18ASF2G72HZ – 2G6
FPGA File Flash (Flash Card)	•	NAND Flash (x8): 1 GB
	• QSPI Flash: 256 MB
	• SD Micro Flash Card: 16 GB (Kingston)
Two V57.4 High Pin Count FMC+ Slots	•	28 Gbps signals: Insertion loss less than 5 dB, return loss less than 10 dB
	• FMC+ PCIe* Gen3 x16 cable (not included)
	• FMC to PCIe Gen3 x8 cable (not included)
	•	16/32 bit trace
	Note: FMC to PCIe cables are sold separately by Samtec. Please contact
			them directly regarding P/N HDR-201768-01-PCIEC
FPGA PCIe Gen 1/2/3 x16 RC Slot	•	75 W Power
	•	Meets PCIe specifications
FPGA Communication Ports	•	Two 28 Gbps ZQSFP+ Ports: 100/50 Gbps IP, Insertion loss less than 5
		dB, return loass less than 10 dB
	• One 10 Gbps SFP+ Port: 10 Gbps Ethernet IP
	• SMA Test Port: Up to four 28 Gbps channels, inseertion loss less than 5
		dB, return loss less than 10 dB, one external reference clock
	• One DB-9 RS-232 Port (MAX3221)
FPGA Debug Ports	Intel FPGA Download Cable Direct Port & JTAG
FPGA Reference Clocks	•	Clock Cleaner
		—	122.88 MHz (Network)
		—	644.5312 MHz (Network)
		— 297 MHz (SDI)
		— 245 MHz (SDI)
	•	Clock Generators
		—	LMH1983 (27 MHz, 148.5 MHz)
		—	Si5388 (133.33 MHz)
		—	PCIe (100 MHz)
		—	Si5338 (148 MHz, 100 MHz, 27 MHz, 100 MHz)
		—	Si5341 (155.52 MHz, 644.53125 MHz, 135 MHz, 156.25 MHz, 625
			MHz, 100 MHz, 125 MHz, 125 MHz)
I2C Devices	•	4 KB SEEPROM
	•	Real Time Clock
	• Silicon Labs™ Clock Generators
	•	FMC+ Slots
	•	PCIe Slots
	•	SFP+
	•	ZQSFP
	•	Clock Cleaner
	•	Power Supplies
Intel MAX 10 Controller I/O CPLD Features	•	System Reset Controller
	• FPGA PS AVST Configuration Controller
	•	I2C Master Controller
			continued...

Send Feedback	Intel® Stratix® 10 SX SoC Development Kit User Guide

13

			4. Development Kit Components
			UG-20081 | 2020.09.08
Feature			Description
	•	UART Level Shifter
	•	FPGA I/O MUX
	• SDI/HDMI/QSFP/SFP+ I/O level shift
Intel MAX 10 Power CPLD Sequencer	FPGA, PCIe, FMC+ slots power sequencer, Reset.
Intel MAX 10 CPLD Features	•	Intel FPGA Download Cable II
	•	JTAG Switch
		— Input JTAG Sources (Intel FPGA Download Cable II, 10-pin Program
			Header, FMCA+, FMCB+, Mictor JTAG)
		— Output JTAG Sources (Intel MAX 10 A JTAG, MAX10B JTAG, Intel
			Stratix 10 JTAG, FMCA+, FMCB+, PCIe)
		—	JTAG Program
		—	User I/O
User I/O	•	4 Push Buttons
	•	4-bit Dipswitch
	•	4 User LEDs
	•	2-pin I/O Header
	• System Intel MAX 10 LEDs and 4-bit switch
Power	•	Volgen KTPS200-12160, 12V, 24A
	•	ATX-Power
Mechanical	•	8.5" x 14.5" Rectangular Form Factor
	• Liquid cool thermal heat sink (300W @ 35C)
System Monitor	Power, Voltage, Current

4.2. Board Components

Figure 3. Board Picture (Top View)

Intel® Stratix® 10 SX SoC Development Kit User Guide	Send Feedback

14

4. Development Kit Components

UG-20081 | 2020.09.08

Figure 4. Board Picture (Bottom View)

		Board Components Table
Table 5.		Intel Stratix 10 SoC Board Components Table
	Board Reference		Type		Description
			Featured Device
	U15		FPGA		Intel Stratix 10 SoC FPGA
	U43		CPLD		Intel MAX 10 10M50DAF484I7G System Controller
	U46		CPLD		Intel MAX 10 10M16SAU169C8G Power Manager
					CPLD
			Configuration, Status and Setup Elements
	J1		JTAG chain header		Provides access to the JTAG chain and disables the
					on-board Intel FPGA Download Cable II when using
					an external JTAG debugger such as an Intel FPGA
					Download Cable II
	SW1		JTAG chain control DIP switch		Remove or include devices in the active JTAG chain
	SW2		MSEL DIP Switch		Controls the configuration scheme on the board.
					MSEL pin 0,1,2 connect to the DIP Switch
	J57		Micro-USB Header		USB interface to on-board Intel FPGA Download
					Cable II JTAG for programming and debugging
					HPS, FPGA orIntel MAX 10 CPLD through a type-B
					Micro-USB cable.
	SW4		Function DIP Switch		Selects I2C master, controls PCIe slot power and
					selects FPGA image source
	SW8		Power Switch		ON position: Power GUI
					continued...
	Send Feedback			Intel® Stratix® 10 SX SoC Development Kit User Guide

15

			4. Development Kit Components
			UG-20081 | 2020.09.08
	Board Reference	Type	Description
			OFF position: Intel Enpirion dongle
	S2	Program select push button	Toggles the program select LEDs which selects the
			program image that loads from flash memory to
			the FPGA
	S1	Configure push button	Load image from flash memory to the FPGA based
			on the settings of the program select LEDs
	D22	Configuration done LED	Illuminates when the FPGA is configured
	D20	Load LED	Illuminates when the Intel MAX 10 CPLD System
			Controller
	D19	Error LED	Illuminates when the FPGA configuration from flash
			memory fails
	D31	Power LED	Illuminates when 3.3V power is present
	D1, D2	JTAG TX/RX LEDs	Indicates the transmit or receive activity of the
			JTAG chain. The TX and RX LEDs flicker if the link
			is in use and active. The LEDs are either off when
			not in use or on when in use but idle
	D24, D26, D28	Program select LEDs	Illuminates to show which flash memory image
			loads to the FPGA when you press the program
			select push button
	D29, D30	FMC port present LEDs	Illuminates when a daughtercard is plugged into
			the FMC port
		Clock Circuits
	U26	Multi-output oscillator	Si5338A quad-output fixed oscillator with 148.5
			MHz, 100 MHz, 27 MHz and 100 MHz outputs
	U29	50-MHz oscillator	50 MHz crystal oscillator for general purpose logic
	U25	Multi-output oscillator	Two 100 MHz outputs for PCIe application
	J19, J20	Clock input SMA connector	External clock inputs for the transceiver test port
	U33	Multi-output oscillator	Si5341 ten-output fixed oscillator
	U31	Multi-output oscillator	Si5338A quad-output fixed oscillator with four
			133.33 MHz outputs
	U34	Multi-output clock cleaner	LMK05028 Clock Cleaner
		General User Input/Output
	D21, D23, D25, D27	User LEDs	Four user LEDs. Illuminate when driven high.
	SW3	User DIP Switch	User DIP switch. When the switch is ON, a logic 0
			is selected
	S3	FPGA Reset Push Button	Reset the FPGA logic
	S4, S5, S6, S7	General user push buttons	Four user push buttons. Driven low when pressed
	S20	HPS Reset Push Buttons	HPS cold/warm reset push buttons
		Memory Connectors
	J134	HPS HILO Memory Connector	HPS memory card include DDR3 HILO memory
			card and DDR4 HILO memory card
	J14	Boot Flash Connector	Boot flash card options include QSPI flash card, SD
			micro flash card
			continued...
Intel® Stratix® 10 SX SoC Development Kit User Guide			Send Feedback

16

4. Development Kit Components

UG-20081 | 2020.09.08

Board Reference	Type	Description
J28	SO-DIMM	16 GB SO-DIMM DDR4 Memory Card
U41	I2C EEPROM	32 Kb I2C serial EEPROM
	Communication Ports
J53	PCIe socket	Gen3 x16 Socket
J11, J12	FMC Port	J29 is a V57.4 compatible FMC connector. J19 is a
		FMC connector defined by Intel 16 transceivers
		specification
J7	SFP+ Port	One SFP+ Ports
J3	Gigabit Ethernet Port	SGMII Gigabit Ethernet port through FPGA
		transceiver
J4	Gigabit Ethernet Port	SGMII Gigabit Ethernet Port through FPGA
		transciever
J9-J10	QSFP28 Optical Transceiver Interface	17 Gbps/28 Gbps, 8 channels connected to QSFP28
		modules
J57, U2	USB-UART Port	Mini-B USB interface to USB-to-UART bridge for
		serial UART interface
J22	DB9 UART Port	DB9 RS-232 UART Port
U42	Real-time clock	DS1339 device with built-in power sense circuit
		that detects power failures and automatically
		switches to backup battery supply, maintaining
		time keeping even when the board is not powered
	Video and Display Ports
J8	HDMI Port	Display Port interface
J5, U13	SDI Video Output Port	HDBNC 75-Ohm SDI video TX interface
J6, U14	SDI Video Input Port	HDBNC 75-Ohm SDI video RX interface
J29	Power GUI Connector	Intel Enpirion Power GUI Connector
	Power Supply
J25, J55	DC input jack	Accepts 12 V DC power supply
SW7	Power Switch	Switch to power on or off the board when power is
		supplied from the DC input jack

4.3. Intel Stratix 10 SoC Device Overview

Intel's 14-nm Intel Stratix 10 SX SoCs deliver 2x core performance and up to 70% lower power over previous generation high-performance SoCs. Featuring several groundbreaking innovations, including the all new Intel Hyperflex™ core architecture, this device family enables you to meet the demand for ever-increasing bandwidth and processing performance in you most advanced applications, while meeting your power budget.

Featuring several groundbreaking innovations, including the all new HyperFlex™ core architecture, this device family enables you to meet the demand for ever-increasing bandwidth and processing performance in your most advanced applications, while meeting your power budget.

Send Feedback	Intel® Stratix® 10 SX SoC Development Kit User Guide

17

4. Development Kit Components

UG-20081 | 2020.09.08

With an embedded hard processor system (HPS) based on a quad-core 64-bit Arm Cortex*-A53, the Stratix 10 SoC devices deliver power efficient, application-class processing and allow designers to extend hardware virtualization into the FPGA fabric. Stratix 10 SoC devices demonstrate Intel's commitment to high-performance SoCs and extend Intel's leadership in programmable devices featuring an Arm-based processor system.

Important innovations in Stratix 10 FPGAs and SoCs include:

•All new HyperFlex core architecture delivering 2X the core performance compared to previous generation high-performance FPGAs

•Industry leading Intel 14-nm Tri-Gate (FinFET) technology

•Heterogeneous 3D System-in-Package (SiP) technology

•Monolithic core fabric with up to 5.5 million logic elements (LEs)

•Up to 96 full duplex transceiver channels on heterogeneous 3D SiP transceiver tiles

•Transceiver data rates up to 28.3 Gbps chip-to-chip/module and backplane performance

•Embedded eSRAM (45 Mbit) and M20K (20 kbit) internal SRAM memory blocks

•Fractional synthesis and ultra-low jitter LC tank based transmit phase locked loops (PLLs)

•Hard PCI Express® Gen3 x16 intellectual property (IP) blocks

•Hard 10GBASE-KR/40GBASE-KR4 Forward Error Correction (FEC) in every transceiver channel

•Hard memory controllers and PHY supporting DDR4 rates up to 2666 Mbps per pin

•Hard fixed-point and IEEE 754 compliant hard floating-point variable precision digital signal processing (DSP) blocks with up to 10 TFLOPS compute performance with a power efficiency of 80 GFLOPS per Watt

•Quad-core 64-bit Arm Cortex-A53 embedded processor running up to 1.5 GHz in SoC family variants

•Programmable clock tree synthesis for flexible, low power, low skew clock trees

•Dedicated secure device manager (SDM) for:

—Enhanced device configuration and security

—AES-256, SHA-256/384 and ECDSA-256/384 encrypt/decrypt accelerators and authentication

—Multi-factor authentication

—Physically Unclonable Function (PUF) service and software programmable device configuration capability

•Comprehensive set of advanced power saving features delivering up to 70% lower power compared to previous generation high-performance FPGAs

•Non-destructive register state readback and writeback, to support ASIC prototyping and other applications

Intel® Stratix® 10 SX SoC Development Kit User Guide	Send Feedback

18

4. Development Kit Components

UG-20081 | 2020.09.08

With these capabilities, Stratix 10 FPGAs and SoCs are ideally suited for the most demanding applications in diverse markets such as:

•Compute and Storage—for custom servers, cloud computing and data center acceleration

•Networking—for Terabit, 400G and multi-100G bridging, aggregation, packet processing and traffic management

•Optical Transport Networks—for OTU4, 2xOTU4, 4xOTU4

•Broadcast—for high-end studio distribution, headend encoding/decoding, edge quadrature amplitude modulation (QAM)

•Military—for radar, electronic warfare, and secure communications

•Medical—for diagnostic scanners and diagnostic imaging

•Test and Measurement—for protocol and application testers

•Wireless—for next-generation 5G networks

•ASIC Prototyping—for designs that require the largest monolithic FPGA fabric with the highest I/O count

Intel Stratix 10 SX SoC devices have a feature set that is identical to the Intel Stratix 10 FPGA devices, with the addition of an embedded quad-core 64-bit Arm Cortex A53 Hard Processor System.

Common to all Stratix 10 family variants is a high-performance fabric based on the new HyperFlex core architecture that includes additional Hyper-Registers throughout the interconnect routing and at the inputs of all functional blocks. The core fabric also contains an enhanced logic array utilizing Intel’s adaptive logic module (ALM) and a rich set of high performance building blocks including:

To clock these building blocks, Stratix 10 devices use programmable clock tree synthesis, which uses dedicated clock tree routing to synthesize only those branches of the clock trees required for the application. All devices support in-system, finegrained partial reconfiguration of the logic array, allowing logic to be added and subtracted from the system while it is operating.

All family variants also contain high speed serial transceivers, containing both the physical medium attachment (PMA) and the physical coding sublayer (PCS), which can be used to implement a variety of industry standard and proprietary protocols. In addition to the hard PCS, Stratix 10 devices contain multiple instantiations of PCI Express hard IP that supports Gen1/Gen2/Gen3 rates in x1/x2/x4/x8/x16 lane configurations, and hard 10GBASE-KR/40GBASE-KR4 FEC for every transceiver. The hard PCS, FEC, and PCI Express IP free up valuable core logic resources, save power, and increase your productivity.

Table 6. Stratix 10 FPGA and SoC Common Device Features

Feature	Description
Technology	• 14-nm Intel Tri-Gate (FinFET) process technology
	• SmartVoltage ID (VID) controlled standard VCC option
	• 0.8 V and 0.85 V optional VCC core voltage
Low power serial	• Up to 96 total transceivers available
transceivers	• Continuous operating range of 1 Gbps to 28.3 Gbps for Stratix 10 GX/SX devices
	• Backplane support up to 28.3 Gbps for Stratix 10 GX/SX devices
	continued...
Send Feedback	Intel® Stratix® 10 SX SoC Development Kit User Guide

19

4. Development Kit Components

UG-20081 | 2020.09.08

Feature		Description
	• Extended range down to 125 Mbps with oversampling
	• ATX transmit PLLs with user-configurable fractional synthesis capability
	• XFP, SFP+, QSFP/QSFP28, CFP/CFP2/CFP4 optical module support
	• Adaptive linear and decision feedback equalization
	• Transmit pre-emphasis and de-emphasis
	• Dynamic partial reconfiguration of individual transceiver channels
	• On-chip instrumentation (EyeQ non-intrusive data eye monitoring)
General purpose I/Os	•	Up to 1640 total GPIO available
	• 1.6 Gbps LVDS—every pair can be configured as an input or output
	• 1333 MHz/2666 Mbps DDR4 external memory interface
	• 1067 MHz/2133 Mbps DDR3 external memory interface
	• 1.2 V to 3.0 V single-ended LVCMOS/LVTTL interfacing
	• On-chip termination (OCT)
Embedded hard IP	•	PCIe Gen1/Gen2/Gen3 complete protocol stack, x1/x2/x4/x8/x16 end point and root
		port
	• DDR4/DDR3/LPDDR3 hard memory controller (RLDRAM3/QDR II+/QDR IV using soft
		memory controller)
	• Multiple hard IP instantiations in each device
	• Single Root I/O Virtualization (SR-IOV)
Transceiver hard IP	•	10GBASE-KR/40GBASE-KR4 Forward Error Correction (FEC)
	•	10G Ethernet PCS
	• PCI Express PIPE interface
	•	Interlaken PCS
	•	Gigabit Ethernet PCS
	• Deterministic latency support for Common Public Radio Interface (CPRI) PCS
	• Fast lock-time support for Gigabit Passive Optical Networking (GPON) PCS
	• 8B/10B, 64B/66B, 64B/67B encoders and decoders
	• Custom mode support for proprietary protocols
Power management	•	SmartVoltage ID controlled standard VCC option
	• Low static power device options
	• Intel Quartus Prime Pro Edition integrated power analysis
High performance monolithic	•	HyperFlex core architecture with Hyper-Registers throughout the interconnect routing
core fabric		and at the inputs of all functional blocks
	• Monolithic fabric minimizes compile times and increases logic utilization
	• Enhanced adaptive logic module (ALM)
	• Improved multi-track routing architecture reduces congestion and improves compile
		times
	• Hierarchical core clocking architecture with programmable clock tree synthesis
	• Fine-grained partial reconfiguration
Internal memory blocks	•	eSRAM - 45-Mbit with hard ECC support
	• M20K—20-Kbit with hard ECC support
	• MLAB—640-bit distributed LUTRAM
Variable precision DSP	•	IEEE 754-compliant hard single-precision floating point capability
blocks	•	Supports signal processing with precision ranging from 18x19 up to 54x54
	• Native 27x27 and 18x19 multiply modes
	• 64-bit accumulator and cascade for systolic FIRs
	• Internal coefficient memory banks
	• Pre-adder/subtractor improves efficiency
	• Additional pipeline register increases performance and reduces power
		continued...

Intel® Stratix® 10 SX SoC Development Kit User Guide	Send Feedback

20

4. Development Kit Components

UG-20081 | 2020.09.08

Feature		Description
Phase locked loops (PLL)	•	Fractional synthesis PLLs (fPLL) support both fractional and integer modes
	• Fractional mode with third-order delta-sigma modulation
	•	Precision frequency synthesis
	• Integer PLLs adjacent to general purpose I/Os, support external memory, and LVDS
		interfaces, clock delay compensation, zero delay buffering
Core clock networks	•	1 GHz fabric clocking
	• 667 MHz external memory interface clocking, supports 2666 Mbps DDR4 interface
	• 800 MHz LVDS interface clocking, supports 1600 Mbps LVDS interface
	• Programmable clock tree synthesis, backwards compatible with global, regional and
		peripheral clock networks
	• Clocks only synthesized where needed, to minimize dynamic power
Configuration	•	Dedicated Secure Device Manager
	• Software programmable device configuration
	• Serial and parallel flash interface
	• Configuration via protocol (CvP) using PCI Express Gen1/Gen2/Gen3
	• Fine-grained partial reconfiguration of core fabric
	• Dynamic reconfiguration of transceivers and PLLs
	• Comprehensive set of security features including AES-256, SHA-256/384, and
		ECDSA-256/384 accelerators, and multi-factor authentication
	• Physically Unclonable Function (PUF) service
Packaging	•	Intel Embedded Multi-die Interconnect Bridge (EMIB) packaging technology
	• Multiple devices with identical package footprints allows seamless migration across
		different device densities
	• 1.0 mm ball-pitch FBGA packaging
	• Lead and lead-free package options
Software and tools	•	Intel Quartus Prime Pro Edition design suite with new Spectra-Q engine and Hyper-
		Aware design flow
	• Fast Forward compiler to allow HyperFlex architecture performance exploration
	•	Transceiver toolkit
	• Qsys system integration tool
	• DSP Builder advanced blockset
	•	OpenCL™ support
	• SoC Embedded Design Suite (EDS)

Table 7.		Stratix 10 SoC Specific Device Features
	SoC Subsystem		Feature	Description
	Hard Processor		Multi-processor unit (MPU) core	• Quad-core Arm Cortex-A53 MPCore processor with Arm
	System			CoreSight debug and trace technology
				• Scalar floating-point unit supporting single and double
				precision
				• Arm NEON media processing engine for each processor
			System Controllers	• System Memory Management Unit (SMMU)
				• Cache Coherency Unit (CCU)
			Layer 1 Cache	• 32 KB L1 instruction cache with parity
				• 32 KB L1 data cache with ECC
			Layer 2 Cache	• 1 MB Shared L2 Cache with ECC
			On-Chip Memory	• 256 KB On-Chip RAM
			Direct memory access (DMA) controller	• 8-Channel DMA
				continued...

Send Feedback	Intel® Stratix® 10 SX SoC Development Kit User Guide

21

				4. Development Kit Components
				UG-20081 | 2020.09.08
SoC Subsystem	Feature			Description
	Ethernet media access controller	•	Three 10/100/1000 EMAC with integrated DMA
	(EMAC)
	USB On-The-Go controller (OTG)	•	2	USB OTG with integrated DMA
	UART controller	•	2	UART 16550 compatible
	Serial Peripheral Interface (SPI)	•	4	SPI
	controller
	I2C controller	•	5	I2C controllers
	SD/SDIO/MMC controller	•	1 eMMC version 4.5 with DMA and CE-ATA support
		• SD, including eSD, version 3.0
		• SDIO, including eSDIO, verion 3.0
		•	CE-ATA - version 1.1
	NAND flash controller	•	1	ONFI 1.0, 8- and 16-bit support
	General-purpose I/O (GPIO)	•	Maximum of 48 software programmable GPIO
	Timers	•	4 general-purpose timers
		•	4 watchdog timers
Secure Device	Security	•	Secure boot
Manager		•	Advanced Encryption Standard (AES) and authentication
			(SHA/ECDSA)
External	External Memory Interface	•	Hard Memory Controller with DDR4 and DDR3, and
Memory			LPDDR3
Interface

For further information , please refer to the Intel Stratix 10 GX/SX Device Overview available on the Intel website.

Related Information

Stratix 10 GX/SX Device Overview

4.4. Intel MAX 10 System Controller Overview

Intel MAX 10 devices are single-chip, non-volatile low-cost programmable logic devices (PLDs) to integrate the optimal set of system components.

Intel MAX 10 devices are the ideal solution for system management, I/O expansion, communication control planes, industrial, automotive, and consumer applications.

The highlights of the Intel MAX 10 devices include:

•Internally stored dual configuration flash

•User flash memory

•Instant on support

•Integrated analog-to-digital converters (ADCs)

•Single-chip Nios II soft core processor support

Intel® Stratix® 10 SX SoC Development Kit User Guide	Send Feedback

22

4. Development Kit Components

UG-20081 | 2020.09.08

Table 8.		Summary of Features for Intel MAX 10 Devices
		Feature		Description
	Technology		55 nm TSMC Embedded Flash (Flash + SRAM) process technology
	Packaging		•	Low cost, small form factor packages—support multiple packaging
				technologies and pin pitches
			• Multiple device densities with compatible package footprints for seamless
				migration between different device densities
			•	RoHS6-compliant
	Core architecture		•	4-input look-up table (LUT) and single register logic element (LE)
			• LEs arranged in logic array block (LAB)
			• Embedded RAM and user flash memory
			•	Clocks and PLLs
			•	Embedded multiplier blocks
			•	General purpose I/Os
	Internal memory blocks		•	M9K—9 kilobits (Kb) memory blocks
			• Cascadable blocks to create RAM, dual port, and FIFO functions
	User flash memory (UFM)		•	User accessible non-volatile storage
			• High speed operating frequency
			•	Large memory size
			•	High data retention
			•	Multiple interface option
	Embedded multiplier blocks		•	One 18 × 18 or two 9 × 9 multiplier modes
			• Cascadable blocks enabling creation of filters, arithmetic functions, and image
				processing pipelines
	ADC		•	12-bit successive approximation register (SAR) type
			• Up to 17 analog inputs
			• Cumulative speed up to 1 million samples per second ( MSPS)
			• Integrated temperature sensing capability
	Clock networks		•	Global clocks support
			• High speed frequency in clock network
	Internal oscillator		Built-in internal ring oscillator
	PLLs		•	Analog-based
			•	Low jitter
			• High precision clock synthesis
			•	Clock delay compensation
			•	Zero delay buffering
			•	Multiple output taps
	General-purpose I/Os (GPIOs)		•	Multiple I/O standards support
			• On-chip termination (OCT)
			• Up to 830 megabits per second (Mbps) LVDS receiver, 800 Mbps LVDS
				transmitter
	External memory interface (EMIF) (1)		Supports up to 600 Mbps external memory interfaces:
			• DDR3, DDR3L, DDR2, LPDDR2 (on 10M16, 10M25, 10M40 and 10M50)
			• SRAM (Hardware support only)
				continued...

(1)EMIF is only supported in selected MAX 10 device density and package combinations. Refer to the External Memory Interface User Guide for more information.

Send Feedback	Intel® Stratix® 10 SX SoC Development Kit User Guide

23

4. Development Kit Components

UG-20081 | 2020.09.08

Feature		Description
	Note: For 600 Mbps performance, –6 device speed grade is required.
		Performance varies according to device grade (commercial, industrial, or
		automotive) and device speed grade (–6 or –7). Refer to the MAX 10
		Device Data Sheet or External Memory Interface Spec Estimator for more
		details.
Configuration	•	Internal configuration
	•	JTAG
	• Advanced Encryption Standard (AES) 128-bit encryption and compression
		options
	• Flash memory data retention of 20 years at 85 °C
Flexible power supply schemes	•	Singleand dual-supply device options
	• Dynamically controlled input buffer power down
	• Sleep mode for dynamic power reduction

4.5. FPGA Configuration

This development kit supports the following FPGA configurations:

•QSPI Configuration

•SDMMC x4 Configuration

•JTAG Only

A 4-bit DIP Switch (SW2) is used to select the FPGA configuration mode.

Table 9.		DIP Switch Bits
		Switch Bit	Name
	1		MSEL0
	2		MSEL1
	3		MSEL2
	4		Not Used

Table 10.		DIP Switch Bit Description
		MSEL2	MSEL1	MSEL0	Mode
	OFF		OFF	ON	QSPI
	ON		OFF	OFF	SDMMC x4, SDMMC x8
	ON		ON	ON	JTAG

Note: The default setting is JTAG mode. The default bit position is "ON, ON, ON, ON"

4.6. General User Input/Output

Table 11. User I/O Pin Map

Pin Name	Schematic Signal Name	Description
PIN_A24	USER_LED_FPGA0	USER_LED0
PIN_B24	USER_LED_FPGA2	USER_LED1

continued...

Intel® Stratix® 10 SX SoC Development Kit User Guide	Send Feedback

24

4. Development Kit Components

UG-20081 | 2020.09.08

Pin Name	Schematic Signal Name	Description
PIN_F22	USER_LED_FPGA1	USER_LED2
PIN_E22	USER_LED_FPGA3	USER_LED3
PIN_A26	USER_PB_FPGA0	USER_PB0
PIN_A25	USER_PB_FPGA1	USER_PB1
PIN_D23	USER_PB_FPGA2	USER_PB2
PIN_D24	USER_PB_FPGA3	USER_PB3
PIN_B23	USER_DIPSW_FPGA0	USER_DPSW0
PIN_C23	USER_DIPSW_FPGA1	USER_DPSW1
PIN_E23	USER_DIPSW_FPGA2	USER_DPSW2
PIN_E24	USER_DIPSW_FPGA3	USER_DPSW3

4.7. Connectors and Interfaces

		The FPGA portion of this development kit includes 96 transceivers.
Table 12.		Channel Assignment for Transceiver Applications
		Applications	Channel (Bank, Number)
	FMC+ A		1C (1C, 0-5), 1D (1D, 0-5), 1E (1E, 0-3), 1F (PCIE EP x16)
	SFP+ Port		(4C, 0)
	PCIE RC x16		(4K, 0-5), (4L, 0-5), (4M, 0-3)
	SGMII Port 1 and Port 2		(4M, 4), (4M, 5)
	FMC+ B		1K (1K, 0-5), 1L (1L, 0-5), 1M (1M, 0-3), 1N (PCIE EPx16)
	MXP Test Ports		(4D, 0, 1, 3, 4)
	SDI Port		TX (4E,1), RX (4F, 0)
	HDMI		(4C, 2-5)
	ZQSFP+ B		(4F, (0,1,3,4))
	ZQSFP+ A		(4N, (0,1,3,4))

4.7.1. PCIe Slot

The PCIe root port is a PCIe Gen3 x16 port. This port is assigned to 4K, 4L and 4M Banks. The transceiver I/O bank power is connected to 1.8 V.

PCIE_PRSNT2n, PCIE_PERSTn and PCIE_WAKE_N 3V3 signals are mapped to the dedicated trasnceiver I/O bank (IO4) in the Intel MAX 10. The system performance of the PCIe root port should meet the PCIe 3.0 specifications.

Send Feedback	Intel® Stratix® 10 SX SoC Development Kit User Guide

25

					4. Development Kit Components
						UG-20081 | 2020.09.08
Table 13.		PCIE Root Port FPGA Pin Map
		Pin Name	Schematic Signal Name	Direction		Description
	PIN_V12		PCIE_REFCLK_QR0_P	Input		REFCLK_GXBR4K_CHTP
	PIN_V13		PCIE_REFCLK_QR0_N	Input		REFCLK_GXBR4K_CHTN
	PIN_L4		PCIE_TX_N15	Output		GXBR4M_TX_CH3N
	PIN_L3		PCIE_TX_P15	Output		GXBR4M_TX_CH3P
	PIN_H6		PCIE_RX_N15	Input		GXBR4M_RX_CH3N
	PIN_H5		PCIE_RX_P15	Input		GXBR4M_RX_CH3P
	PIN_K2		PCIE_TX_N14	Output		GXBR4M_TX_CH2N
	PIN_K1		PCIE_TX_P14	Output		GXBR4M_TX_CH2P
	PIN_L8		PCIE_RX_N14	Input		GXBR4M_RX_CH2N
	PIN_L7		PCIE_RX_P14	Input		GXBR4M_RX_CH2P
	PIN_N4		PCIE_TX_N13	Output		GXBR4M_TX_CH1N
	PIN_N3		PCIE_TX_P13	Output		GXBR4M_TX_CH1P
	PIN_K6		PCIE_RX_N13	Input		GXBR4M_RX_CH1N
	PIN_K5		PCIE_RX_P13	Input		GXBR4M_RX_CH1P
	PIN_M2		PCIE_TX_N12	Output		GXBR4M_TX_CH0N
	PIN_M1		PCIE_TX_P12	Output		GXBR4M_TX_CH0P
	PIN_N8		PCIE_RX_N12	Input		GXBR4M_RX_CH0N
	PIN_N7		PCIE_RX_P12	Input		GXBR4M_RX_CH0P
	PIN_R4		PCIE_TX_N11	Output		GXBR4L_TX_CH5N
	PIN_R3		PCIE_TX_P11	Output		GXBR4L_TX_CH5P
	PIN_M6		PCIE_RX_N11	Input		GXBR4L_RX_CH5N
	PIN_M5		PCIE_RX_P11	Input		GXBR4L_RX_CH5P
	PIN_P2		PCIE_TX_N10	Output		GXBR4L_TX_CH4N
	PIN_P1		PCIE_TX_P10	Output		GXBR4L_TX_CH4P
	PIN_R8		PCIE_RX_N10	Input		GXBR4L_RX_CH4N
	PIN_R7		PCIE_RX_P10	Input		GXBR4L_RX_CH4P
	PIN_T2		PCIE_TX_N9	Output		GXBR4L_TX_CH3N
	PIN_T1		PCIE_TX_P9	Output		GXBR4L_TX_CH3P
	PIN_P6		PCIE_RX_N9	Input		GXBR4L_RX_CH3N
	PIN_P5		PCIE_RX_P9	Input		GXBR4L_RX_CH3P
	PIN_U4		PCIE_TX_N8	Output		GXBR4L_TX_CH2N
	PIN_U3		PCIE_TX_P8	Output		GXBR4L_TX_CH2P
	PIN_T6		PCIE_RX_N8	Input		GXBR4L_RX_CH2N
						continued...

Intel® Stratix® 10 SX SoC Development Kit User Guide	Send Feedback

26

4. Development Kit Components

UG-20081 | 2020.09.08

Pin Name	Schematic Signal Name	Direction	Description
PIN_T5	PCIE_RX_P8	Input	GXBR4L_RX_CH2P
PIN_V2	PCIE_TX_N7	Output	GXBR4L_TX_CH1N
PIN_V1	PCIE_TX_P7	Output	GXBR4L_TX_CH1P
PIN_U8	PCIE_RX_N7	Input	GXBR4L_RX_CH1N
PIN_U7	PCIE_RX_P7	Input	GXBR4L_RX_CH1P
PIN_Y2	PCIE_TX_N6	Output	GXBR4L_TX_CH0N
PIN_Y1	PCIE_TX_P6	Output	GXBR4L_TX_CH0P
PIN_V6	PCIE_RX_N6	Input	GXBR4L_RX_CH0N
PIN_V5	PCIE_RX_P6	Input	GXBR4L_RX_CH0P
PIN_W4	PCIE_TX_N5	Output	GXBR4K_TX_CH5N
PIN_W3	PCIE_TX_P5	Output	GXBR4K_TX_CH5P
PIN_Y6	PCIE_RX_N5	Input	GXBR4K_RX_CH5N
PIN_Y5	PCIE_RX_P5	Input	GXBR4K_RX_CH5P
PIN_AB2	PCIE_TX_N4	Output	GXBR4K_TX_CH4N
PIN_AB1	PCIE_TX_P4	Output	GXBR4K_TX_CH4P
PIN_W8	PCIE_RX_N4	Input	GXBR4K_RX_CH4N
PIN_W7	PCIE_RX_P4	Input	GXBR4K_RX_CH4P
PIN_AA4	PCIE_TX_N3	Output	GXBR4K_TX_CH3N
PIN_AA3	PCIE_TX_P3	Output	GXBR4K_TX_CH3P
PIN_AB6	PCIE_RX_N3	Input	GXBR4K_RX_CH3N
PIN_AB5	PCIE_RX_P3	Input	GXBR4K_RX_CH3P
PIN_AD2	PCIE_TX_N2	Output	GXBR4K_TX_CH2N
PIN_AD1	PCIE_TX_P2	Output	GXBR4K_TX_CH2P
PIN_AA8	PCIE_RX_N2	Input	GXBR4K_RX_CH2N
PIN_AA7	PCIE_RX_P2	Input	GXBR4K_RX_CH2P
PIN_AC4	PCIE_TX_N1	Output	GXBR4K_TX_CH1N
PIN_AC3	PCIE_TX_P1	Output	GXBR4K_TX_CH1P
PIN_AD6	PCIE_RX_N1	Input	GXBR4K_RX_CH1N
PIN_AD5	PCIE_RX_P1	Input	GXBR4K_RX_CH1P
PIN_AE4	PCIE_TX_N0	Output	GXBR4K_TX_CH0N
PIN_AE3	PCIE_TX_P0	Output	GXBR4K_TX_CH0P
PIN_AC8	PCIE_RX_N0	Input	GXBR4K_RX_CH0N
PIN_AC7	PCIE_RX_P0	Input	GXBR4K_RX_CH0P

Send Feedback	Intel® Stratix® 10 SX SoC Development Kit User Guide

27

4. Development Kit Components

UG-20081 | 2020.09.08

4.7.2. ZQSFP+

The ZQSFP+ 0/1 ports meet SFF8665 and QSFP28 industrial standards. The connector part number is Molex 170432-001. The cage part number is TE 2227103-2. The PCB trace insertion loss is less than -5 dB and return loss is less than -10 dB. The ZQSFP+ signals (Modesl, RESETL, MOdPrsl, LPmode, int) are mapped to the dedicated I/O in System Intel MAX 10. The BC25, BC26 pins in 2F bank are I2C interface. The user needs this interface to access ZQSFP.

Table 14.		ZQSFP+ 0/1 Ports FPGA Pin Map
		Pin Name	Schematic Signal Name	Direction	Description
	PIN_P9		CLEARNER_XVR_644.53125 Input		REFCLK_GXBR4N_CHTP
			MHZ_P
	PIN_P10		CLEARNER_XVR_644.53125 Input		REFCLK_GXBR4N_CHTN
			MHZ_N
	PIN_C4		ZQSFP0_TXN3	Output	GXBR4N_TX_CH3N
	PIN_C3		ZQSFP0_TXP3	Output	GXBR4N_TX_CH3P
	PIN_A8		ZQSFP0_RXN3	Input	GXBR4N_RX_CH3N
	PIN_A7		ZQSFP0_RXP3	Input	GXBR4N_RX_CH3P
	PIN_E4		ZQSFP0_TXN2	Output	GXBR4N_TX_CH2N
	PIN_E3		ZQSFP0_TXP2	Output	GXBR4N_TX_CH2P
	PIN_C8		ZQSFP0_RXN2	Input	GXBR4N_RX_CH2N
	PIN_C7		ZQSFP0_RXP2	Input	GXBR4N_RX_CH2P
	PIN_G4		ZQSFP0_TXN1	Output	GXBR4N_TX_CH1N
	PIN_G3		ZQSFP0_TXP1	Output	GXBR4N_TX_CH1P
	PIN_D6		ZQSFP0_RXN1	Input	GXBR4N_RX_CH1N
	PIN_D5		ZQSFP0_RXP1	Input	GXBR4N_RX_CH1P
	PIN_F2		ZQSFP0_TXN0	Output	GXBR4N_TX_CH0N
	PIN_F1		ZQSFP0_TXP0	Output	GXBR4N_TX_CH0P
	PIN_G8		ZQSFP0_RXN0	Input	GXBR4N_RX_CH0N
	PIN_G7		ZQSFP0_RXP0	Input	GXBR4N_RX_CH0P
	PIN_T9		REFCLK0_P	Input	REFCLK_GXBR4N_CHBP
	PIN_T10		REFCLK0_N	Input	REFCLK_GXBR4N_CHBN
	PIN_AF2		ZQSFP1_TXN3	Output	GXBR4F_TX_CH3N
	PIN_AF1		ZQSFP1_TXP3	Output	GXBR4F_TX_CH3P
	PIN_AG8		ZQSFP1_RXN3	Input	GXBR4F_RX_CH3N
	PIN_AG7		ZQSFP1_RXP3	Input	GXBR4F_RX_CH3P
	PIN_AJ4		ZQSFP1_TXN2	Output	GXBR4F_TX_CH2N
	PIN_AJ3		ZQSFP1_TXP2	Output	GXBR4F_TX_CH2P

continued...

Intel® Stratix® 10 SX SoC Development Kit User Guide	Send Feedback

28

4. Development Kit Components

UG-20081 | 2020.09.08

Pin Name	Schematic Signal Name	Direction	Description
PIN_AF6	ZQSFP1_RXN2	Input	GXBR4F_RX_CH2N
PIN_AF5	ZQSFP1_RXP2	Input	GXBR4F_RX_CH2P
PIN_AL4	ZQSFP1_TXN1	Output	GXBR4F_TX_CH1N
PIN_AL3	ZQSFP1_TXP1	Output	GXBR4F_TX_CH1P
PIN_AH6	ZQSFP1_RXN1	Input	GXBR4F_RX_CH1N
PIN_AH5	ZQSFP1_RXP1	Input	GXBR4F_RX_CH1P
PIN_AK2	ZQSFP1_TXN0	Output	GXBR4F_TX_CH0N
PIN_AK1	ZQSFP1_TXP0	Output	GXBR4F_TX_CH0P
PIN_AL8	ZQSFP1_RXN0	Input	GXBR4F_RX_CH0N
PIN_AL7	ZQSFP1_RXP0	Input	GXBR4F_RX_CH0P
PIN_AM12	REFCLK_QSFP1_P	Input	REFCLK_GXBR4F_CHBP
PIN_AM13	REFCLK_QSFP1_N	Input	REFCLK_GXBR4F_CHBN

4.7.3. SFP+

The SFP+ Port meets SFF-8431 Industrial Standard. The connector part number is Samtec MECT-110-01-M-D-RA1. The cage part number is Molex 74754-0101. The PCB trace insertion loss is less than -5 dB and return loss less than -10 dB.

SFP+ signals (TX_disable, RS0/1, MOD_ABS, LOS, Fault) are mapped to the dedicated transceiver I/O in Intel MAX 10.

Table 15.		SFP+ Port FPGA Pin Map
	Pin Name		Schematic Signal Name	Direction	Description
	PIN_BJ5		SFPA_TX_N	Output	GXBR4C_TX_CH0N
	PIN_BJ4		SFPA_TX_P	Output	GXBR4C_TX_CH0P
	PIN_BH10		SFPA_RX_N	Input	GXBR4C_RX_CH0N
	PIN_BH9		SFPA_RX_P	Input	GXBR4C_RX_CH0P
	PIN_AT9		REFCLK_SFPA_P	Input	REFCLK_GXBR4C_CHBP
	PIN_AT10		REFCLK_SFPA_N	Input	REFCLK_GXBR4C_CHBN

4.7.4. HDMI

Table 16.		HDMI Port FPGA Pin Map
		Pin Name	Schematic Signal Name	Direction	Description
	PIN_AP9		HDMIREFCLK_P	Input	REFCLK_GXBR4C_CHTP
	PIN_AP10		HDMIREFCLK_N	Input	REFCLK_GXBR4C_CHTN
	PIN_BC4		HDMI_LANE_CLKN	Output	GXBR4C_TX_CH5N
	PIN_BC3		HDMI_LANE_CLKP	Output	GXBR4C_TX_CH5P

continued...

Send Feedback	Intel® Stratix® 10 SX SoC Development Kit User Guide

29

					4. Development Kit Components
						UG-20081 | 2020.09.08
	Pin Name		Schematic Signal Name	Direction		Description
	PIN_BF2		HDMI_LANE_N2	Output		GXBR4C_TX_CH4N
	PIN_BF1		HDMI_LANE_P2	Output		GXBR4C_TX_CH4P
	PIN_BE4		HDMI_LANE_N1	Output		GXBR4C_TX_CH3N
	PIN_BE3		HDMI_LANE_P1	Output		GXBR4C_TX_CH3P
	PIN_BG4		HDMI_LANE_N0	Output		GXBR4C_TX_CH2N
	PIN_BG3		HDMI_LANE_P0	Output		GXBR4C_TX_CH2P
4.7.5. SDI Port
Table 17.		SDI Port FPGA Pin Map
	Pin Name		Schematic Signal Name	Direction		Description
	PIN_AF9		CLEARNER_SDI_245MHZ_P	Input		REFCLK_GXBL4E_CHTP
	PIN_AF10		CLEARNER_SDI_245MHZ_N	Input		REFCLK_GXBL4E_CHTN
	PIN_AR4		SDI_TX_N	Output		GXBR4E_TX_CH1N
	PIN_AR3		SDI_TX_P	Output		GXBR4E_TX_CH1P
	PIN_AR8		SDI_RX_N	Input		GXBR4E_RX_CH0N
	PIN_AR7		SDI_RX_P	Input		GXBR4E_RX_CH0P
	PIN_AK12		CLEARNER_SDI_297MHZ_P	Input		REFCLK_GXBL4F_CHTP
	PIN_AK13		CLEARNER_SDI_297MHZ_N	Input		REFCLK_GXBL4F_CHTN

4.7.6. MXP

The MXP Test Port is a MXP Coaxial Print Connectors. The PCB trace insertion loss is less than -5 dB and return loss is less than -10 dB. You can use it for 100 Gbps applications.

Table 18.		MXP Port FPGA Pin Map
	Pin Name		Schematic Signal Name	Direction	Description
	PIN_AK9		REFCLK_SMA_P	Input	REFCLK_GXBR4D_CHTP
	PIN_AK10		REFCLK_SMA_N	Input	REFCLK_GXBR4D_CHTN
	PIN_AY2		MXP_TXN3	Output	GXBR4D_TX_CH3N
	PIN_AY1		MXP_TXP3	Output	GXBR4D_TX_CH3P
	PIN_AU8		MXP_RXN3	Input	GXBR4D_RX_CH3N
	PIN_AU7		MXP_RXP3	Input	GXBR4D_RX_CH3P
	PIN_AW4		MXP_TXN2	Output	GXBR4D_TX_CH2N
	PIN_AW3		MXP_TXP2	Output	GXBR4D_TX_CH2P
	PIN_AY6		MXP_RXN2	Input	GXBR4D_RX_CH2N
	PIN_AY5		MXP_RXP2	Input	GXBR4D_RX_CH2P

continued...

Intel® Stratix® 10 SX SoC Development Kit User Guide	Send Feedback

30