Intel Stratix 10 GX User Manual
Intel® Stratix® 10 GX Transceiver
Signal Integrity Development Kit
User Guide
UG-20047
2017.10.11
Subscribe
Send Feedback
Contents
Contents
1 Overview......................................................................................................................... 4
1.1 General Board Description....................................................................................... 4
1.2 Recommended Operating Conditions......................................................................... 4
1.3 Handling the Development Board..............................................................................4
2 Getting Started................................................................................................................ 5
2.1 Installing the Quartus Prime software........................................................................5
2.2 Installing the Development Board............................................................................. 5
2.3 Installing the Intel FPGA Download Cable Driver......................................................... 6
3 Development Board Setup............................................................................................... 7
3.1 Setting up the Development Board............................................................................7
3.2 Factory Default Switch and Jumper Settings...............................................................8
4 Board Components.........................................................................................................11
4.1 Board Overview.................................................................................................... 11
4.2 Stratix 10 GX FPGA............................................................................................... 14
4.3 MAX V CPLD System Controller............................................................................... 20
4.4 FPGA Configuration............................................................................................... 23
4.4.1 FPGA Programming over Embedded USB-Blaster........................................... 23
4.4.2 FPGA Programming from Flash Memory........................................................24
4.4.3 FPGA Programming over External USB-Blaster.............................................. 26
4.5 Status Elements................................................................................................... 27
4.6 Setup Elements.................................................................................................... 28
4.7 User Input-Output Components.............................................................................. 29
4.7.1 User-Defined Pushbuttons.......................................................................... 29
4.7.2 User-Defined DIP Switch............................................................................ 30
4.7.3 User-Defined LEDs.................................................................................... 30
4.7.4 Character LCD.......................................................................................... 31
4.8 Clock Circuits....................................................................................................... 31
4.8.1 Transceiver Dedicated Clocks......................................................................31
4.8.2 General-Purpose Clocks............................................................................. 32
4.8.3 Embedded USB-Blaster Clock..................................................................... 34
4.9 Transceiver Channels.............................................................................................34
4.10 Communication Ports...........................................................................................37
4.11 Flash Memory..................................................................................................... 38
5 System Power................................................................................................................ 42
5.1 Power Guidelines.................................................................................................. 42
5.2 Power Supply....................................................................................................... 42
5.3 Power Management...............................................................................................43
5.4 Power Distribution System..................................................................................... 44
5.5 Thermal Limitations and Protection Guidelines.......................................................... 46
6 Board Test System......................................................................................................... 47
6.1 Preparing the Board.............................................................................................. 48
6.2 Running the Board Test System.............................................................................. 48
6.3 Using the Board Test System.................................................................................. 49
6.3.1 The Configure Menu.................................................................................. 49
Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide
2
Contents
6.3.2 The System Info Tab................................................................................. 50
6.3.3 The GPIO Tab........................................................................................... 51
6.3.4 The Flash Tab........................................................................................... 52
6.3.5 The FMCA Tab...........................................................................................54
6.3.6 The FMCB Tab...........................................................................................60
6.3.7 The LPBK Tab........................................................................................... 65
6.3.8 The MXP Tab............................................................................................ 69
6.3.9 The SMA Tab............................................................................................ 72
6.3.10 The QSFP and SFP+ Tab...........................................................................75
6.3.11 The CFP4 Tab..........................................................................................78
6.3.12 Power Monitor.........................................................................................81
6.3.13 Clock Controller...................................................................................... 82
7 Board Update Portal.......................................................................................................85
7.1 Connecting to the Board Update Portal.....................................................................85
7.2 Using the Board Update Portal................................................................................ 86
A Additional Information.................................................................................................. 87
A.1 Safety and Regulatory Information..........................................................................87
A.1.1 Safety Warnings....................................................................................... 88
A.1.2 Safety Cautions........................................................................................ 89
A.2 Compliance and Conformity Information.................................................................. 91
B Revision History.............................................................................................................92
B.1 User Guide Revision History................................................................................... 92
Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide
3
1 Overview
1 Overview
1.1 General Board Description
The Intel® Intel Stratix® 10 GX Transceiver Signal Integrity Development Kit is a
complete design environment that includes both hardware and software you need to
develop Intel Stratix 10 GX FPGA designs.
The following list describes what you can accomplish with the kit:
• Evaluate transceiver performance up to 17.4 Gbps for L-Tile and 28.3 Gbps for HTile version.
• Generate and check pseudo-random binary sequence (PRBS) patterns
• Dynamically change differential output voltage (VOD) pre-emphasis and
equalization settings to optimize transceiver performance for your channel
• Perform jitter analysis
• Verify physical medium attachment (PMA) compliance to PCI Express* (PCIe*),
1G/10G/40G/100G Ethernet and other major standards.
Related Links
Stratix 10 Support
1.2 Recommended Operating Conditions
The recommended operating conditions for this development kit are:
• Recommended ambient operating temperature range: 0C to 45C
• Maximum ICC load current: 130 A
• Maximum ICC load transient percentage: 30%
• FPGA maximum power supported by the supplied heatsink/fan: 200 W
1.3 Handling the Development Board
When handling the board, it is important to observe static discharge precautions.
Caution: Without proper anti-static handling, the board can be damaged. Therefore, use anti-
static handling precautions when touching the board.
Caution: This development kit should not be operated in a Vibration Environment.
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2008
Registered
2 Getting Started
2 Getting Started
2.1 Installing the Quartus Prime software
The Intel Quartus® Prime design software is a multiplatform design environment that
easily adapts to your specific needs in all phases of FPGA, CPLD, and SoC designs. The
Intel Quartus Prime software delivers the highest performance and productivity for
Intel FPGAs, CPLDs, and SoCs.
Design software must enable dramatically increased design productivity in order to
take advantage of devices with multi-million logic elements with increased capabilities
that provide designers with an ideal platform to meet next-generation design
opportunities.
The new Intel Quartus Prime Design Suite® design software includes everything
needed to design for Intel FPGAs, SoCs and CPLDs from design entry and synthesis to
optimization, verification and simulation. The Intel Quartus Prime Design Suite
software includes an additional Spectra-Q® engine that is optimized for Intel Stratix
10 and future devices. The Spectra-Q engine enables new levels of design productivity
for next generation programmable devices with a set of faster and more scalable
algorithms, a hierarchical database infrastructure and a unified compiler technology.
Intel Quartus Prime Pro Edition
The Intel Quartus Prime Design Suite software is available in three editions based on
specific design requirements: Pro, Standard, and Lite Edition.
The Intel Quartus Prime Pro Edition is optimized to support the advanced features in
Intel's next generation FPGAs and SoCs and requires a paid license.
Included in the Intel Quartus Prime Pro Edition are the Intel Quartus Prime software,
Nios® II EDS and the MegaCore IP Library.
To install Intel's development tools, download the Intel Quartus Prime Pro Edition
software from the Quartus Prime Pro Edition page in the Download Center of Intel's
website.
2.2 Installing the Development Board
To install the Intel Stratix 10 GX Transceiver Signal Integrity Development Board,
perform the following steps:
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2008
Registered
1. Download the development kit installer from the Stratix 10 GX Transceiver Signal
documents
board_design_files
examples
factory_recovery
demos
<package rootdir>
Integrity Development Kit link on the Intel website.
2. Unzip the Intel Stratix 10 Transceiver Signal Integrity Development Kit installer
package.
3. The installer package creates the development kit directory structure shown in the
figure below.
Figure 1. Development Kit Directory Structure
The table below lists the file directory names and a description of their contents
2 Getting Started
Table 1. Installed Development Kit Directory Structure
File Directory Name Description of Directory Contents
board_design_files
demos
documents
examples
factory_recovery
Contains schematics, layout, assembly and bill of material
board design files. Use these files as a starting point for a
new prototype board design
Contains demonstration applications when available
Contains the development kit documentation
Contains the sample design files for the development kit
Contains the original data programmed onto the board
before shipment. Use this data to restore the board with its
original factory contents.
2.3 Installing the Intel FPGA Download Cable Driver
The Intel Stratix 10 GX Transceiver Signal Integrity Development Kit includes
embedded Intel FPGA Download Cable circuits for FPGA and MAX® V programming.
However, for the host computer and board to communicate, you must install the Intel
FPGA Download Cable driver on the host computer.
Installation instructions for the Intel FPGA Download Cable driver for your operating
system are available on the Intel website.
On the Intel website, navigate to the Cable and Adapter Drivers Information link to
locate the table entry for your configuration and click the link to access the
instructions.
Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide
6
3 Development Board Setup
3 Development Board Setup
The instructions in this chapter explain how to setup the Intel Stratix 10 GX
Transceiver Signal Integrity Development Board.
3.1 Setting up the Development Board
To prepare and apply power to the board, perform the following steps:
1. The Intel Stratix 10 GX transceiver signal integrity development kit ships with its
board switches preconfigured to support the design examples in the kit. If you
suspect your board might not be correctly configured with the default settings,
follow the instructions in the Factory Default Switch and Jumper Settings on page
8 to return the board to its factory settings before proceeding.
2. The development kit ships with design examples stored in the flash device. The
POWER-ON slide switch (SW7) is provided to turn the board ON or OFF.
Caution: When the power cord is plugged into connector J103 of the Intel Stratix
10 transceiver signal integrity development kit, 12V_IN and 3.3V_STBY
are present on to the board with switch SW7 in the 'OFF' position.
These voltages are restricted to a small area of the board. When switch
SW7 is placed to 'ON' position, all voltages planes have power at this
point.
3.
Set the POWER-ON switch SW7 to the ON position. When power is supplied to the
board, three green LEDs (D29, D31 and D32) illuminate and an amber LED
(D36) extinguishes indicating that the board has power. If the amber LED (D36)
illuminates, it indicates that one or more power supply is incorrect.
4.
RESET button (S12) is connected to the MAX V CPLD (MAX_RESETn pin) that is
used for AvST configuration. When this button is pressed, the MAX V CPLD
initiates a reloading of the stored image from the flash memory using AvST
configuration mode. The image loaded right after power cycle or MAX V reset
depends on FACTORY_LOAD settings.
• OFF(1) - factory load
• ON (0) - user defined load #1
Page selection can be changed by the PGMSEL button (S10) when the board is
powered on, and PGM_CONFIG (S11) is used to reconfigure FPGA with
corresponding page which is indicated by PGM_LED0, PGM_LED1 or PGM_LED2.
Caution: Use only the supplied power supply. Power regulation circuits on the
board can get damaged by power supplies with greater voltage.
The MAX V CPLD device on the board contains a parallel flash loader II (PFL II)
megafunction. After a POWER-ON or RESET (reconfiguration) event, the MAX V CPLD
configures the Intel Stratix 10 FPGA in AvST mode with either factory design or user
design depending on the setting of FACTORY_LOAD.
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2008
Registered
3 Development Board Setup
The development kit includes a MAX V CPLD design which contains the PFL II
megafunction. The design resides in the <package dir>\examples\max5 directory.
When configuration is complete, LED D25 (CONF_DONE) illumintes signaling that the
Intel Stratix 10 GX FPGA device is configured successfully. If the configuration fails,
the LED D23 (ERROR) illuminates.
3.2 Factory Default Switch and Jumper Settings
This section shows the factory switch settings for the Intel Stratix 10 GX transceiver
signal integrity development kit.
Table 2. Factory Default Switch Settings
Switch Board Label Default Position Function
SW10
MSEL2
MSEL1
SW11
SW3-1 Intel Stratix 10 OPEN/OFF Enable Intel Stratix 10 in
SW3-2
SW3-3
SW3-4
S15-1
S15-2
SW1-1
SW1-2
SW1-3
SW1-4
SW2-1
SW2-2
S1-1
S1-2
S14-1
S14-2
SW9-1
SW9-2
MSEL0
MAX V
FMC A
FMC B
OFF = OSC
ON = SMA
S0
S1
SS0
SS1
OFF=ISOLATE
ON=FULL CHAIN
OFF=ISOLATE
ON=FULL CHAIN
VCCT
VCCH
VCCRR
VCCRL
2-3 Closed MSEL setting=0
5-6 Closed MSEL setting=0
2-3 Closed MSEL setting=0
JTAG Chain
OPEN/OFF Enable MAX V in JTAG chain
CLOSE/ON Bypass FMC A in JTAG chain
CLOSE/ON Bypass FMC B in JTAG chain
OPEN/OFF Select Si570 clock source for
OPEN/OFF Select Si570 clock source for
OPEN/OFF Frequency Select
CLOSE/ON Frequency Select
OPEN/OFF Spread Spectrum Select
OPEN/OFF Spread Spectrum Select
CLOSE/ON U15 (LTC2987) is enabled in
CLOSE/ON U15 (LTC2987) is enabled in
CLOSE/ON U5 and U6 (Si5341) is
CLOSE/ON U5 and U6 (Si5341) is
OPEN/OFF
OPEN/OFF
OPEN/OFF
OPEN/OFF
U3
U4
I2C topology
I2C topology
enabled in I2C topology
enabled in I2C topology
Enable on-board VCCT
regulator
Enable on-board VCCH
regulator
Enable on-board VCCRR
regulator
Enable on-board VCCRL
regulator
continued...
Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide
8
3 Development Board Setup
Switch Board Label Default Position Function
SW9-3
SW9-4
SW8-1
SW8-2
SW8-3
SW8-4
SW6-1
SW6-2
SW6-3
SW6-4
SW4-1
SW4-2
SW4-3
SW4-4
SW5-1
SW5-2
SW5-3
SW5-4
SW7
VCCERAM
VCC
MAX10_DIPSWITCH
FAN_ON
PWR_MGMT_SEL
MAX10_BOOTSEL
FACTORY_LOAD
MAX5_SWITCH2
MAX5_SWITCH0
MAX5_SWITCH1
S10_UNLOCK
USER_DIP6
USER_DIP5
USER_DIP4
USER_DIP3
USER_DIP2
USER_DIP1
USER_DIP0
SW7
OPEN/OFF
OPEN/OFF
OPEN/OFF Power Intel MAX 10 user DIP
OPEN/OFF FAN is not full speed
OPEN/OFF Select Linear Tech PWR
OPEN/OFF Power Intel MAX 10 boot
OPEN/OFF Factory Load Control
OPEN/OFF MAX V user DIPSwitch
OPEN/OFF MAX V user DIPSwitch
OPEN/OFF MAX V user DIPSwitch
OPEN/OFF Stratix 10 User DIPSwitch
OPEN/OFF Stratix 10 User DIPSwitch
OPEN/OFF Stratix 10 User DIPSwitch
OPEN/OFF Stratix 10 User DIPSwitch
OPEN/OFF Stratix 10 User DIPSwitch
OPEN/OFF Stratix 10 User DIPSwitch
OPEN/OFF Stratix 10 User DIPSwitch
OPEN/OFF Stratix 10 User DIPSwitch
OFF On-board power switch
Enable on-board VCCERAM
regulator
Enable on-board VCC
regulator
Switch
MGMT solution
select
Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide
9
Figure 2. Default Switch Settings
Board size = 10" x11"
1 inch
S10GX
UF50
J28
QSFP 28 1
J27
QSFP 28 0
J30
SFP + 1
FMC+ A
J58
FMC+ B
J59
J14
CN1
J19
CFP4
J24
J29
SFP + 0
J92
J94
S15
S1
SW3
SW9
S14
SW8
VCCRR
SW6
ON
ON
ON
ON
ON
ON
ON
SW5
ON
SW4
ON
J89
J79 J91
VCCERAM
VCCT
VCCH
Bottom
Layer
J83
VCCRL
J86
SW2
Ethernet
Ext.
JTAG
USB
VCC
GND
ON
ON
SW7
MXP-0 J33
MXP-1 J44
MXP-2 J50
SW1
ON
SW10
0
1
SW11
0
1
3 Development Board Setup
Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide
10
ENET FPGA (SGMII)
Buttons, Switches,
LEDs, GPIOs
LCD
MXP Transceiver
2.4 mm Transceiver
SFP+ x2
QSFP28 x2
CFP4
EPCQ-L
32 bit CFI Flash
FMC-B x16FMC-A V57.1/V57.4
Intel Stratix 10 FPGA
ND5 F2397B Package
1SG280UF50
LVDS X80 Pairs
CLKIN X6 Pairs
REFCLK X2 Pairs
Transceiver X24 Ch
LVDS X34 Pairs
CLKIN X4 Pairs
Transceiver X16 Ch
MAX 10 FPGA
On-Board USB
Blaster II
and USB Interface
Side Bus
JTAG Chain
USB Type-B
LVDS X2 Pairs
X2
Transciever X12 Ch
Transciever X6 Ch
Transciever X2 Ch
Transciever X8 Ch
Transciever X4 Ch
AS X4
Transciever X6 Ch
MAX V
CPLD
PLLs
Programmable
Oscillators
SMA Clock
IN/OUT
CLK
CLKIN
CLKIN
Avalon-ST X32
X67
I2C
MAX 10 Power
Management
(Backup)
LT Power
Management
VCC
VCCERAM
VCCT
VCCR
VCCH
VCCIO
4 Board Components
4 Board Components
4.1 Board Overview
This section provides an overview of the Intel Stratix 10 GX transceiver signal integrity
development board including a block diagram of the board.
Figure 3. Stratix 10 GX Transceiver Signal Integrity Development Kit User Guide Block
Diagram
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2008
Registered
4 Board Components
Intel Stratix 10 GX Transceiver Signal Integrity Development Board
Components
Table 3. Board Components Table
Board Reference Type Description
Featured Devices
U43 FPGA Intel Stratix 10 GX 280 F2397 FPGA
U20 CPLD System MAX V CPLD (5M2210ZF256)
U97 FPGA USB Intel MAX 10 FPGA
U98 FPGA PWR Intel MAX 10 FPGA
General User Input and Output
D12-D19 User LEDs (Green) User LEDs (Green)
D20-D25 MAX V LEDs (Green) MAX V LEDs (Green)
S2-S13 User Push Buttons User Push Buttons
SW4-SW5 User DIP Switches User DIP
SW6 MAX V DIP Switch MAX V DIP Switch
J20 LCD Display Header Connector for 16 Character x2 line LCD
Configuration, Status and Setup Elements
J14 Intel FPGA Download Cable
Programming Header
D1-D2 Green LEDs JTAG Transmit-Receive Activity
D3-D4 Green LEDs System Console Transmit-Receive
D36 Amber LEDs System Power error indicator
D5-D6 Green LEDs FMC cards present indicator
D7-D11 Ethernet LEDs Ethernet LEDs (TX/RX/LINK)
Clock Circuits
X2
50-MHz Oscillator
X1 This 50-MHz oscillator provides clock to
SW1 Spread Spectrum/Frequency Selection
Switch
Y1
Transceiver Dedicated Reference Clock/
Programmable Oscillator
(10M04SCU169)
(10M16SAU169)
Header to interface external Intel FPGA
Download Cable direct to FPGA
(through USB Intel MAX 10)
Activity
This 50-MHz oscillator is the clock
source to clock buffer SL18860DC that
provides three 50 MHz outputs to the
FPGA and the MAX V CPLD
the PWR Intel MAX 10 FPGA
SW1 selects frequency and spread
spectrum percentages of clock buffer
outputs ICS557-03.
Feeds REFCLKs on left side of the Intel
Stratix 10 GX FPGA device and an
LVDS trigger output at board reference
J4/J5.
The external input is available at board
reference J2 and J3. The default
frequency is 644.53125 MHz.
continued...
Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide
12
4 Board Components
Board Reference Type Description
Y2
U3, U4, U5
Transceiver Dedicated Reference Clock/
U6
J61, J63 External core clock input
J62, J64 External core clock output SMA external output at
Programmable PLL
Feeds REFCLKs on right side of the
Intel Stratix 10 GX FPGA device and an
LVDS trigger output at board reference
J8/J9.
The external input is available at board
reference J6 and J7. The default
frequency is 706.25 MHz.
Feeds REFCLKs on left side of the Intel
Stratix 10 GX FPGA device and an
LVDS trigger output at board reference
J10/J11.
The default frequencies are 625 MHz,
614.4 MHz, 100 MHz.
Feeds REFCLKs on right side of the
Intel Stratix 10 GX FPGA device and an
LVDS trigger output at board reference
J12/J13.
The default frequencies are 625 MHz,
644.53125 MHz, 125 MHz.
SMA external input at CLKIN_3C0
PLL_3C_CLKOUT0
J65-J66
J67-J68 SMA external input bank at 1M
J69-J70 SMA external input bank at 4C
J71-J72 SMA external input bank at 4K
X4 100-MHz Oscillator This 100-MHz oscillator provides clock
J33, J44, J50 MXP connector 17 Gbps/28 Gbps, 4 channels MXP
J31-J32
J34-J43
J45-J49
J51-J57
J29-J30 SFP+ optical transceiver interface 17 Gbps/28 Gbps, 2 channels
J27-J28 QSFP28 optical transceiver interface 17 Gbps/28 Gbps, 8 channels
J24 CFP4 optical transceiver interface 17 Gbps/ 28 Gbps, 4 channels
J58-J59 FMC+ connector 17 Gbps/28 Gbps, 34 channels
U21-U22 Flash Memory Two 1-Gbit Micron PC28F00AP30BF CFI
External transceiver clock input
Transceiver Interfaces
2.4 mm RF connector 17 Gbps/ 28 Gbps, 6 channels 2.4 mm
Memory Devices
Communication Ports
SMA external input bank at 1C
to the MAX V CPLD
connectors
RF connectors
connected to SFP+ modules
connected to QSFP28 modules
connected to CFP4 module
connected to FMC+ connectors
Flash device
continued...
Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide
13
4 Board Components
Board Reference Type Description
J19 Gigabit Ethernet Port RJ-45 connector which provides a
CN1 USB Type-B connector Connects a type-B USB cable
Power Supply
U15 LTM2987 Linear Technology power monitor
U63-U64
U66-U67
U68 LTM4620
U69 LTM4620
U70 LTM4620
U71 LTM4620
U74 EN63A0
U78 EN63A0
U79 EN6337
U82 LTM4630A
LTM4677
3x LTM4650
10/100/1000 Ethernet connection
through a Marvell 88E1111 PHY
device
Power regulators for VCC rail
Power regulators for VCCERAM rail
Power regulators for VCCH rail
Power regulators for VCCRL rail
Power regulators for VCCRR rail
Power regulators for FMCA_VADJ rail
Power regulators for FMCB_VADJ rail
Power regulators for 2.5V rail
Power regulators for 3.3V rail
4.2 Stratix 10 GX FPGA
The development board features the Intel Stratix 10 GX FPGA (1SG280UF50).
Intel Stratix 10 GX FPGA I/O Usage Summary
Table 4. Stratix 10 GX FPGA Pin Table
Signal Name/Function I/O Count Description
S10_JTAG_TCK/TDO/TDI/TMS
FPGA_MSEL[2:0]
FPGA_CONF_DONE
FPGA_nSTATUS
FPGA_INIT_DONE
FPGAMSEL0
FPGA_nCONFIG
FPGA_OSC_CLK_1
FPGA_AS_CLK
CPU_RESETn
4 JTAG Configuration Pins
2 Configuration input pins to set
1 Configuration done pin
1 Configuration status pin
1 Configuration pin to signify user mode
1 Configuration input pins to set
1 Configuration input pin to reset FPGA
1 125 MHz Clock
1 Configuration Clock for AS
1 Global reset signal
Configuration
configuration scheme
configuration scheme and Chip select
pin to EPCQL device
configuration schemes
continued...
Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide
14
4 Board Components
Signal Name/Function I/O Count Description
FPGA_CONFIG_D[31:0]
FPGA_AS_DATA[3:0]
FPGA_AVST_READY
FPGA_AVST_VALID
FPGA_AVST_CLK
FPGA_PR_DONE
FPGA_PR_REQUEST
FPGA_PR_ERROR
NPERSTL, NPERSTR
FPGA_SDM10
FPGA_CvP_DONE
FPGA_SEU_ERR
VCC_SDA/VCC_SCL
VCC_ALERTn
SFP0_TX_DS
SFP0_RS[1:0]
SFP0_MOD_ABS
SFP0_RX_LOS
SFP0_TX_FLT
SFP0_SCL
SFP0_SDA
SFP1_TX_DIS
SFP1_RS[1:0]
SFP1_MOD_ABS
SFP1_RX_LOS
SFP1_TX_FLT
SFP1_SCL
SFP1_SDA
CFP4_MOD_LOPWR
CFP4_MOD_RSTn
CFP4_GLB_ALRMN
32 Configuration input pin that enables all
IOs
4 EPCQL data bus
1 SDM ready for AvST configuration
scheme
1 Data valid for AvST configuration
scheme
1 Configuration clock for AvST
configuration scheme
1 Partial reconfiguration done pin
1 Partial reconfiguration request pin
1 Partial reconfiguration error pin
4 Reset pin for PCIe HIP
1 SDM IO 10
1 CvP configuration done pin
1 SEU error indicate pin
2 SmartVID PMBus
1 SmartVID PMBus
Transceivers
1 SFP+ 0 TX disable control Pin
2 SFP+ 0 Rate Select Control Pin
1 SFP+ 0 Module Absent Status Pin
1 SFP+ 0
1 SFP+ 0 Transmitter Fault Status Pin
1 SFP+ 0 Management Data Clock
1 SFP+ 0 Management Data I/O Bi-
Directional Data
1 SFP+ 1 TX disable control pin
2 SFP+ 1 Rate Select Control Pin
1 SFP+ 1 Module Absent Status Pin
1 SFP+ 1
1 SFP+ 1 Transmitter Fault Status Pin
1 SFP+ 1 Management Data Clock
1 SFP+ 1 Management Data I/O Bi-
Directional Data
1 CFP4 Module Low Power Mode
1 CFP4 Module Reset
1 CFP4 Program Alarm bits
continued...
Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide
15
Signal Name/Function I/O Count Description
CFP4_PRTADR[2:0]
CFP4_TX_DIS
CFP4_RX_LOS
CFP4_MOD_ABS
CFP4_MDC
CFP4_MDIO
eQSFP_modselL0
eQSFP_resetL0
eQSFP_LPmode0
eQSFP_modprsL0
eQSFP_intl0
eQSFP_scl0
eQSFP_sda0
eQSFP_modselL1
eQSFP_resetL1
eQSFP_LPmode1
eQSFP_modprsL1
eQSFP_intl1
eQSFP_scl1
eQSFP_sda1
FALAp/n[33:0]
FAHAp/n[23:0]
FAHBp/n[21:0]
RZQ_2M
RZQ_3K
EXTA_SDA1V8
EXTA_SCL1V8
FAPRSNT1V8_N
FACLKBIR1V8
FBLAp/n[33:0]
EXTB_SDA1V8
EXTB_SCL1V8
FBPRSTN1V8_N
3 CFP4 MDIO Physical Port Address
1 CFP4 Transmitter Disable
1 CFP4 Receiver loss of signal
1 CFP4 Module Absent
1 CFP4 Management Data Clock
1 CFP4 Management Data I/O Bi-
Directional Data
1 QSFP28 0 model select
1 QSFP28 0 Module Reset
1 QSFP28 0 Module Low Power Mode
1 QSFP28 0 Module Present
1 QSFP28 0 Module Interrupt
1 QSFP28 0 Management Data Clock
1 QSFP28 0 Management Data I/O Bi-
Directional Data
1 QSFP28 1 model select
1 QSFP28 1 Module Reset
1 QSFP28 1 Module Low Power Mode
1 QSFP28 1 Module Present
1 QSFP28 1 Module Interrupt
1 QSFP28 1 Management Data Clock
1 QSFP28 1 Management Data I/O Bi-
Directional Data
68 FMC A LA bank GPIOs
48 FMC A HA bank GPIOs
44 FMC A HB bank GPIOs
1 RZQ pin for bank 2M
1 RZQ pin for bank 3K
1 FMC A I2C bus
1 FMC A I2C bus
1 FMC A present indicator
1 FMC A clock direction control
68 FMC B LA bank GPIOs
1 FMC B I2C bus
1 FMC I2C bus
1 FMC B present indicator
4 Board Components
continued...
Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide
16
4 Board Components
Signal Name/Function I/O Count Description
USB_FULL
USB_EMPTY
USB_RESETn
USB_OEn
USB_RDn
USB_WRn
USB_DATA[7:0]
USB_ADDR[1:0]
USB_SCL
USB_SDA
FM_D[31:0]
FM_A[26:1]
FLASH_WEn
FLASH_CEn0
FLASH_CEn1
FLASH_OEn
FLASH_RDYBSYn0
FLASH_RDYBSYn1
FLASH_RESETn
FLASH_CLK
FLASH_ADVn
MAX5_OEn
MAX5_CSn
MAX5_WEn
MAX5_CLK
MAX5_BEn[3:0]
USER_LED[7:0]
USER_PB[7:0]
USER_DIP[6:0]
USER_IO[9:0]
USB
1 USB FIFO is full
1 USB FIFO is empty
1 USB Reset
1 USB Output Enable
1 USB Read
1 USB Write
8 USB Data Bus
2 USB Address Bus
1 USB Serial Clock
1 USB Serial Data
Flash Memory
32 Flash Data Bus
26 Flash Address Bus
1 Flash Write Enable Strobe
1 Flash Chip Enable
1 Flash Chip Enable
1 Flash Output Enable
1 Flash ready or busy
1 Flash ready or busy
1 Flash reset
1 Flash clock
1 Flash address valid
MAX V CPLD
1 Output Enable
1 Chip Select
1 Write Enable
1 Clock
4 Byte Enable
Switches, Buttons, LED
8 Light Emitting Diodes
8 Push Buttons
7 DIP Switches
10 Input/Output
continued...
Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide
17
Signal Name/Function I/O Count Description
S10_UNLOCK
ENET_SGMII_TX_P/N
ENET_SGMII_RX_P/N
ENET_RSTn
ENET_INTn
ENET_MDIO
ENET_MDC
SPARE[20:1]
I2C_1V8_SCL
I2C_1V8_SDA
OVERTEMPn
TEMP_ALERTn
CLK_50M_S10
CLK_S10BOT_100M_p/n
CLKIN_SMA_3C_p/n
CLKOUT_SMA_3C_p/n
USB_FPGA_CLK
CLK_S10TOP_ADJ_p/n
CLK_S10TOP_125M_p/n
FACLKM2Cp/n0
FACLKM2Cp/n1
FBCLKM2Cp/n0
FBCLKM2Cp/n1
FACLKBIDIRp/n2
FACLKBIDIRp/n3
1 FPGA Unlock Switch
Ethernet
2 Ethernet SGMII Transmit Data
2 Ethernet SGMII Receive Data
1 Reset
1 Interrupt
1 Ethernet Management Data I/O
1 Ethernet Management Data Clock
Other Bus
20 Spare bus between Intel Stratix 10 and
MAX V
1 Intel Stratix 10 I2C bus
1 Intel Stratix 10 I2C bus
Temperature
1 Intel Stratix 10 over temperature
indicator
1 Intel Stratix 10 temperature alert
indicator
Global Clocks
1 50 MHz Global Clock Input
2 100 MHz differential core clock for
bottom banks
2 Global Clock input from SMA
2 Dedicated Clock output to SMA
1 USB FPGA Clock
2 Adjustable differential core clock for
top banks
2 125 MHz differential core clock for top
banks
2 FMC A clock input 0
2 FMC A clock input 1
2 FMC B clock input 0
2 FMC B clock input 1
2 FMC A bidirectional clock 2
2 FMC A bidirectional clock 3
Transceiver Clocks
4 Board Components
continued...
Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide
18
4 Board Components
Signal Name/Function I/O Count Description
CLK_CFP4_644_p/n
CLKIN_SMA_1C_p/n
CLK_QSFP0_644MT_p/n
CLK_QSFP0_644MB_p/n
CLK_GXBL1E_614MT_p/n
CLK_GXBL1E_614MB_p/n
CLK_GXBL1F_625M_p/n
CLK_SFP_644M_p/n
CLK_GXBL1K_614M_p/n
CLK_GXBK1L_625M_p/n
FBGBTCLKM2_Cp/n0
CLKIN_SMA_1M_p/n
CLK_FMCB_644M_p/n
FBGBTCLKM2_Cp/n1
CLK_SMA_706M_p/n
CLKIN_SMA_4C_p/n
CLK_MXP1_706M_p/n
CLK_GXBR4D_644M_p/n
CLK_MXP2_706M_p/n
CLK_GXBR4E_644M_p/n
CLK_MXP3_706M_p/n
CLK_GXB4F_644M_p/n
FAGBTCLKM2_Cp/n0
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Differential top REFCLK input to the
transceiver bank 1C
Differential bottom REFCLK input to
the transceiver bank 1C
Differential top REFCLK input to the
transceiver bank 1D
Differential bottomREFCLK input to the
transceiver bank 1D
Differential top REFCLK input to the
transceiver bank 1E
Differential bottom REFCLK input to
the transceiver bank 1E
Differential top REFCLK input to the
transceiver bank 1F
Differential top REFCLK input to the
transceiver bank 1K
Differential bottom REFCLK input to
the transceiver bank 1K
Differential top REFCLK input to the
transceiver bank 1L
Differential top REFCLK input to the
transceiver bank 1M
Differential bottomREFCLK input to the
transceiver bank 1M
Differential top REFCLK input to the
transceiver bank 1N
Differential bottom REFCLK input to
the transceiver bank 1N
Differential top REFCLK input to the
transceiver bank 4C
Differential bottomREFCLK input to the
transceiver bank 4C
Differential top REFCLK input to the
transceiver bank 4D
Differential bottom REFCLK input to
the transceiver bank 4D
Differential top REFCLK input to the
transceiver bank 4E
Differential bottom REFCLK input to
the transceiver bank 4E
Differential top REFCLK input to the
transceiver bank 4F
Differential bottomREFCLK input to the
transceiver bank 4F
Differential top REFCLK input to the
transceiver bank 4K
continued...
Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide
19
Signal Name/Function I/O Count Description
CLKIN_SMA_4K_p/n
FAGBTCLKM2_Cp/n1
CLK_GXBR4L_644M_p/n
FAGBTCLKM2_Cp/n2
CLK_GXBR4M_625M_p/n
FAGBTCLKM2_Cp/n3
CLK_FMCA_706M_p/n
2
2
2
2
2
2
2
4.3 MAX V CPLD System Controller
The Intel Stratix 10 GX transceiver signal integrity development kit consists of a MAX
V CPLD (5M2210Z-F256), 256-pin FineLine BGA package. MAX V CPLD devices provide
programmable solutions for applications such as FPGA reconfiguration from flash
memory, I2C chain to manage power consumption, core temperature, fan speed, clock
frequency and remote update system. MAX V devices feature on-chip flash storage,
internal oscillator and memory functionality. With up to 50% lower total power versus
other CPLDs and requiring as few as one power supply, MAX V CPLDs can help you
meet your low power design requirements.
4 Board Components
Differential bottom REFCLK input to
the transceiver bank 4K
Differential top REFCLK input to the
transceiver bank 4L
Differential bottom REFCLK input to
the transceiver bank 4L
Differential top REFCLK input to the
transceiver bank 4M
Differential bottomREFCLK input to the
transceiver bank 4M
Differential top REFCLK input to the
transceiver bank 4N
Differential bottomREFCLK input to the
transceiver bank 4N
The following list summarizes the features of MAX V CPLD devices:
• 2210 Logic Elements (LEs)
• 8192 bits of User Flash Memory
• 4 global clocks
• 1 internal oscillator
• 271 maximum user I/O pins
• Low-cost, low power and non-volatile CPLD architecture
• Fast propagation delays and clock-to-output times
• Single 1.8V external supply for device core
• Bus-friendly architecture including programmable slew rate, drive strength, bushold and programmable pull-up resistors
The table below lists the MAX V CPLD I/O signals.
Table 5. MAX V CPLD I/O Signals
Signal Name Description
FA_A[26:1]
FM_D[31:0]
Flash Address Bus
Flash Data Bus
continued...
Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide
20
4 Board Components
FLASH_CLK
FLASH_RESETn
FLASH_CEn[1:0]
FLASH_OEn
FLASH_WEn
FLASH_ADVn
FLASH_RDYBSYn[1:0]
FPGA_CONFIG_D[31:0]
FPGA_INIT_DONE
FPGA_nSTATUS
FPGA_CONF_DONE
FPGA_nCONFIG
FPGA_ASCLK
FPGA_SEU_ERR
FPGA_CvP_DONE
FPGA_SDM
FPGA_PR_REQUEST
FPGA_PR_DONE
FPGA_PR_ERROR
FPGA_MSEL[2:0]
FPGA_AVST_CLK
FPGA_AVST_VALID
FPGA_AVST_READY
I2C_1V8_SCL
I2C_1V8_SDA
FAPRSNT1V8_N
FBPRSNT1V8_N
SI5341_1_ENn
SI5341_1_INTn
SI5341_1_RSTn
SI5341_1_LOLn
SI5341_2_ENn
SI5341_2_INTn
SI5341_2_RSTn
Signal Name Description
Flash Clock
Flash Reset
Flash Chip Enable
Flash Output Enable
Flash Write Enable
Flash Address Valid
Flash Chip Ready/Busy
FPGA AvST configuration data bus
FPGA initialization complete
FPGA status
FPGA configuration complete
FPGA configuration control pin reset to FPGA
FPGA AS configuration clock
FPGA configuration SEU error
FPGA CvP configuration done
FPGA SDM IO10
FPGA partial reconfiguration request
FPGA partial reconfiguration done
FPGA partial reconfiguration error
FPGA configuration mode setting bits
FPGA AvST configuration clock
FPGA AvST configuration data valid
FPGA ready to receive data
MAX V I2C bus
MAX V I2C bus
FMC A present indicator
FMC B present indicator
SI5341 1 ENABLE
SI5341 1 interrupt indicators
SI5341 1 reset
SI5341 1 loss of clock indicators
SI5341 2 ENABLE
SI5341 2 interrupt indicators
SI5341 2 reset
continued...
Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide
21
SI5341_2_LOLn
EN_MASTER[1:0]
TEMP_ALERTn
OVERTEMPn
OVERTEMP
FAN_RPM
USB_CFG[14:0]
USB_MAX5_CLK
MAX_OSC_CLK_1
MAX5_JTAG_TCK
MAX5_JTAG_TMS
MAX5_JTAG_TDI
MAX5_JTAG_TDO
FACTORY_LOAD
MAX5_SWITCH [2:0]
PGM_SEL
PGM_CONFIG
MAX_RESETn
CPU_RESETn
PGM_LED[2:0]
MAXV_ERROR
MAXV_LOAD
MAXV_CONF_DONE
MAX5_BE_n[3:0]
MAX5_OEn
MAX5_CSn
MAX5_WEn
MAX5_CLK
SPARE[20:1]
CLK_50M_MAX5
FPGA_ASDATA[3:0]
CLK_CONFIG
4 Board Components
Signal Name Description
SI5341 2 loss of clock indicators
ENABLE specific I2C buffer
FPGA temperature alert input
FPGA over temperature input
Over temperature fan control
Fan speed control
Bus between USB Intel MAX 10 and MAX V
Clock from USB PHY chip
25MHz / 100 MHz / 125 MHz clock input
MAX V Test Clock
MAX V Test Mode Select
MAX V Test Data Input
MAX V Test Data Output
Factory image for configuration
System MAX V user DIP switch
Flash Memory program select pushbutton
Flash Memory program configuration pushbutton
System MAX V reset pushbutton
CPU reset pushbutton
Flash image program select indicators
Intel Stratix 10 configuration error indicator LED
Intel Stratix 10 configuration active indicator LED
Intel Stratix 10 configuration done indicator LED
Intel Stratix 10 and MAX V data path, byte enable
Intel Stratix 10 and MAX V data path, output enable
Intel Stratix 10 and MAX V data path, chip select
Intel Stratix 10 and MAX V data path, write enable
Intel Stratix 10 and MAX V data path, clock
Spare bus between MAX V and Intel Stratix 10
50 MHz clock input
Intel Stratix 10 AS configuration data
100 MHz clock input
Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide
22
Intel
Stratix 10
U43
MAX V
U20
MAX II USB
U97
USB-PHY
U9
I2C Buffer
U26
I2C Buffer
U28
I2C Buffer
U27
I2C Buffer
U29
Si5341
PLL
(1.8 V)
Si5341
PLL
(1.8 V)
add = 74h add = 76h
Si570 OSC
(2.5 V)
Si570 OSC
(2.5 V)
add = 66h add = 77h
(1.8 to 2.5 V)
(1.8 to 5 V)
(1.8 to 3.3 V)
(1.8 to 3.3 V)
Si570 OSC
(2.5 V)
add = 66h
MAX 10
FPGA
MAX 1619
add = 5Eh add = 18h
LTM2987
PM0/1
LTM4677
add = 5C/5Dh add = 4Fh
add = 31h/5Ah
add = 5Bh
J102 Silab
Debug Cable
J17 LT
Debug Cable
net name = VCC_SCL
net name = I2C_1V8_SCL
S1
net name = I2C_1V8_SCL_Si5341
net name = I2C_2V5_SCL
net name = I2C_5V_SCL
net name = I2C_3V3_SCL
SW2
net name =LT_SCL
4 Board Components
Figure 4. I2C Block Diagram
4.4 FPGA Configuration
This section describes the FPGA, flash memory and MAX V CPLD System Controller
device programming methods supported by the Intel Stratix 10 GX tranceiver signal
integrity development kit.
Three configuration methods except AS mode are mostly used on the Intel Stratix 10
transceiver signal integrity development kit.
• Embedded USB-Blaster is the default method for configuring the FPGA at any time
• MAX V configures the FPGA device via AvST mode using stored images from CFI
4.4.1 FPGA Programming over Embedded USB-Blaster
• JTAG external header for debugging. Intel recommends that you use lower JTAG
Embedded USB-Blaster is the default method for configuring the Intel Stratix 10 GX
FPGA using the Intel Quartus Prime Programmer in the JTAG mode with the supplied
USB cable.
using the Intel Quartus Prime Programmer in JTAG mode with the supplied USB
cable.
flash devices either at power-up or pressing the MAX_RESETn/PGM_CONFIG push
button.
clock frequency value such as 16 MHz.
Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide
23
The figure below shows the conceptual block diagram for the embedded USB-Blaster.
USB2 PHY
USB MAX 10
FMCA & FMCB
Stratix 10 GX
MAX V
*TCK
*TDI
*TDO
*TMS
TCK
TDI
TDO
TMS
EXT_JTAG_TCK
EXT_JTAG_TDI
EXT_JTAG_TDO
EXT_JTAG_TMS
BLASTER_DISn
JTAG
Header
IO[7:0]
IO[15:8]
IO[23:16]
RDn
WRn
FLAG-A
FLAG-B
FLAG-C
SDA
SCL
RESETn
PORTA_IO[7:0]
PORTB_IO[7:0]
PORTD_IO[7:0]
RDY0
RDY1
CTL0
CTL1
CTL2
SDA
SCL
RESETn
IFCLK
XTAL-IN
XTAL-OUT
WAKEUP
USB_D+
USB_B-
Oscillator
24 MHz
5V
P
N
USB Connector
Type B
CY7C68013A_QFN10M04SCU169
USB_CLK
Figure 5. USB-Blaster II Block Diagram
The embedded USB-Blaster core for USB-based configuration of the Intel Stratix 10
GX FPGA device is implemented using a Type-B USB connector, a CY7C68013A USB2
PHY device, and an Intel Intel MAX 10 10M04SCU169 FPGA. This will allow
configuration of the Intel Stratix 10 GX FPGA device using a USB cable directly
connected to a computer running Intel Quartus Prime software without requiring the
external USB-Blaster dongle. This design will convert USB data to interface with the
Intel Stratix 10 GX FPGA's dedicated JTAG port. Four LEDs are provided to indicate
USB Blaster activity. The embedded USB Blaster is automatically disabled when an
external USB Blaster dongle is connected to the JTAG header.
4 Board Components
4.4.2 FPGA Programming from Flash Memory
The figure below shows a detailed schematic block diagram for the MAX V + Flash
AvSTx32 mode configuration implementation.
Note: Typical JTAG clock frequency for CFI Flash programming via PFL II core is 16 MHz. You
may try it with a lower frequency such as 6 MHz if it fails with 16 MHz.
Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide
24
MAX V System Controller
Intel Stratix 10 GX
MSEL0
MSEL1
MSEL2
CPU_RESET
ERROR
nCONFIG
nSTATUS
CONF_DONE
INIT_DONE
AvST_READY
AvST_CLK
FPGA_DATA[31:0]
AvST_VALID
FA[26:1]
FCLK
FCEn
FOEn
FWEn
FWPn
FADVn
WAIT
FRSTn
FLASH_D[31:0]
nCONFIG
nSTATUS
CONF_DONE
INIT_DONE
AvST_READY
AvST_CLK
D[31:0]
AvST_VALID
FA[26:1]
FCLK
FCEn
FOEn
FWEn
FWPn
FADVn
WAIT
RESETn
FLASH_D[31:0]
OSC_CLK_1
U6
FPGA_OSC_CLK_1MAX_OSC_CLK_1
FA[26:1]
CLK
CEn
OEn
WEn
WPn
ADVn
WAIT
RESETn
FD[15:0]
PC28F00AP30BF
Flash (1G)
FA[26:1]
CLK
CEn
OEn
WEn
WPn
ADVn
WAIT
RESETn
FD[15:0]
PC28F00AP30BF
Flash (1G)
SW11
SW10
X4 100 MHz
CLK_CONFIG
U1 50 MHz
CLK_50M_MAX5
U9 48 MHz
USB_MAX5_CLK
Error
D23
LOAD
D24
CONF_DONE
D25
PGM0
D20
PGM1
D21
PGM2
D22
LOAD
CONF_DONE
PGM_LED0
PGM_LED1
PGM_LED2
SW6
Factory Load
MAX V Switch
MAX V Switch
MAX V Switch
MAX_RESETn
PGM_CONFIG
PGM_SEL
CPU_RESETn
S12
S11
S10
S13
5M2210ZF256
125 MHz
4 Board Components
Figure 6. MAX V + Flash AvSTx32 Configuration Block Diagram
Once the FPGA is successfully initialized and in user mode, the CPLD will tri-state its
Flash interface signals to avoid contention with the FPGA. The PGMSEL dipswitch (S10)
is provided to select between two POF files (FACTORY and USER) stored on the Flash.
The Parallel Flash Loader II (PFL II) Megafunction is used to implement the AvSTx32
configuration in the MAX V CPLD. The PFL II Megafunction reads data from the flash
and converts it to AvST format. This data is written into the Intel Stratix 10 GX FPGA
device through dedicated AvST CLK and FPGA Config Data [31:0] pins at
corresponding clock rate, such as 25 MHz, 50 MHz and 100 MHz.
Implementation will be done using an Intel MAX V 5M2210ZF256FBGA CPLD acting as
the AvST download controller and two 1G Flash devices. The Flash will be Numonyx
1.8V core, 1.8V I/O 1Gigabit CFI NOR-type device (P/N: PC28F00AP30BF). The MAX V
CPLD shares the CFI Flash interface with the Intel Stratix 10 GX FPGA. No arbitration
is needed between MAX V CPLD and Intel Stratix 10 GX FPGA to access the Flash as
the CPLD only has access prior to FPGA initialization.
Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide
25
4 Board Components
After a POWER-ON or RESET (reconfiguration) event, the MAX V device shall configure
the Intel Stratix 10 GX FPGA in the AvSTx32 mode with either the FACTORY POF or
an USER DEFINED POF depnding on the FACTORY_LOAD setting.
The MSEL[2:0] pins indicate which configuration scheme is chosen. The
manufacturing default condition is [000] for AvSTx32 scheme.
For different configuration modes, MSEL [2:0] signals must be set acccording to the
table below:
Table 6. Support Configuration Modes for Stratix 10 Transceiver Signal Integrity
Development Kit
Configuration Scheme
Avalon-ST (x32)
Avalon-ST (x16)
AS (Normal mode)
JTAG only
Not supported
000
101
011
111
Other Settings
4.4.3 FPGA Programming over External USB-Blaster
The JTAG chain allows programming of both the Intel Stratix 10 GX FPGA and MAX V
CPLD devices using an external USB-Blaster dongle or the on-board USB-II Blaster via
the USB Interface Connector.
During board bring-up, and as a back-up in case the on-board USB-Blaster II has a
problem, the external USB-Blaster dongle can be used to program both the Intel
Stratix 10 and MAX V CPLD via the external blaster 2x5 pin 0.1" programming header
(J14)
Another 2x5 pin 0.1" vertical non-shrouded header (J15) is provided on the board for
programming the Intel MAX 10_Blaster FPGA for configuring the on-board USB Blaster
circuitry. Once the on-board Blaster is configured and operational, the on-board
blaster can be used for subsequent programming of the Intel Stratix 10 GX FPGA and
MAX V CPLD.
The on-board blaster JTAG chain connects four JTAG nodes in the following order, with
the option to bypass the Intel Stratix 10, MAX V, FMC A or FMC B by a dip switch SW3
setting as follows:
• Switch closed/ON: Corresponding JTAG node is bypassed.
• Switch open/OFF: Corresponding JTAG node is enabled in the JTAG chain.
MSEL [2:0]
Pin 2 of the J14 Header is used to disable the embedded USB Blaster by connecting it
to the embedded Blaster's low active disable pin with a pull-up resistor. Since Pin 2
from the mating Blaster dongle is GND, when the dongle is connected into the JTAG
header, the embedded Blaster is disabled to avoid contention with the external USB
Blaster dongle.
Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide
26
Intel
Stratix 10
U43
MAX V
U20
USB-PHY
U9
USB_MAX_TCK
USB_MAX_TDO
USB_MAX_TMS
USB_MAX_TDI
S10_JTAG_TCK
S10_JTAG_TDO
S10_JTAG_TMS
S10_JTAG_TDI
M5_JTAG_TCK
M5_JTAG_TDO
M5_JTAG_TMS
M5_JTAG_TDI
FMC-A
J58
FATCK
FATDO
FATMS
FATDI
FMC-B
J59
FBTCK
FBTDO
FBTMS
FBTDI
External
JTAG
Header
J14
EXT_JTAG_TCK
EXT_JTAG_TDO
EXT_JTAG_TMS
EXT_JTAG_TDI
BLASTER_DISn
USB MAX 10 FPGA
U97
xxJTAG_BYPASSn
4 Board Components
Figure 7. JTAG Chain
4.5 Status Elements
The development board includes board-specific status LEDs and switches for enabling
and configuring various features on the board, as well as 16 character x 2 line LCD for
Table 7. Board Specific LEDs
D29 --- Green LED. Power 3.3V present.
D31 --- Green LED. Power 3.3V PRE present.
D32 --- Green LED. Power 12V present.
D5
D6
D36
D1
displaying board power and temperature measurements. This section describes these
status elements.
Board Reference Signal Name Description
FAPRSNT_N
FBPRSNT_N
ERR_LED_N
JTAG_RX
Green LED. FMC A daughter card
present.
Green LED. FMC B daughter card
present.
Amber LED. System Power error
indicator.
Green LED. JTAG receiver activity
indicator.
continued...
Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide
27
D2
D3
D4
D7
D8
D9
D10
D11
D27
4 Board Components
Board Reference Signal Name Description
JTAG_TX
SC_RX
SC_TX
ENET_LED_TX
ENET_LED_RX
ENET_LED_LINK1000
ENET_LED_LINK100
ENET_LED_LINK10
OVERTEMPn
Green LED. JTAG transmitter activity
indicator.
Green LED. System console receiver
activity indicator.
Green LED. System console
transmittter activity indicator.
Green LED. Blinks to indicate Ethernet
PHY transmit activity.
Green LED. Blinks to indicate Ethernet
PHY activity.
Green LED. Illuminates to indicate
Ethernet linked at 1000 Mbps
connection speed.
Green LED. Illuminates to indicate
Ethernet linked at 100 Mbps connection
speed.
Green LED. Illuminates to indicate
Ethernet linked at 10 Mbps connection
speed.
Amber LED. Intel Stratix 10 over
temperature indicator.
4.6 Setup Elements
This development board includes several different kinds of setup elements. This
section describes the following setup elements:
• JTAG Chain Device removal switch
• Program Select pushbutton
• MAX V Reset pushbutton
• CPU Reset pushbutton
JTAG Chain Device Removal Switch
The JTAG chain connects the Intel Stratix 10 GX FPGA, the MAX V CPLD, FMC A and
FMC B in a chain, with the option to selectively bypass each JTAG node by four dip
switch setting.
Program Select Pushbutton
After a POWER-ON or RESET (reconfiguration) event, the MAX V configures the Intel
Stratix 10 GX FPGA in the AvST mode with either the FACTORY POF or a USER-
DEFINED POF depending on FACTORY_LOAD setting. The setting of the PGMSEL bit is
selected by the PGMSEL pushbutton. Pressing this pushbutton and observing the
program LEDs (FACTORY or USER) dictates the program selection. Then, the
PGM_CONFIG pushbutton must be pressed to load the program.
Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide
28
Loading...