Intel S5721-xxx User Manual

CBI/CGI

CB BASIC

S5721-xxx

TECHNICAL REFERENCE

®

Intel

Pentium

or

®

Intel

Celeron

PROCESSOR-BASED

SBC

®

III

®

WARRANTY The product is warranted against material and manufacturing defects for two years from

date of delivery. Buyer agrees that if this product proves defective Chassis Plans is only
obligated to repair, replace or refund the purchase price of this product at Chassis Plans’
discretion. The warranty is void if the product has been subjected to alteration, neglect,
misuse or abuse; if any repairs have been attempted by anyone other than Chassis Plans;
or if failure is caused by accident, acts of God, or other causes beyond the control of
Chassis Plans. Chassis Plans reserves the right to make changes or improvements in any
product without incurring any obligation to similarly alter products previously
purchased.

In no event shall Chassis Plans be liable for any defect in hardware or software or loss or
inadequacy of data of any kind, or for any direct, indirect, incidental or consequential
damages arising out of or in connection with the performance or use of the product or
information provided. Chassis Plans’ liability shall in no event exceed the purchase
price of the product purchased hereunder. The foregoing limitation of liability shall be
equally applicable to any service provided by Chassis Plans

R

ETURN POLICY Products returned for repair must be accompanied by a Return Material Authorization

(RMA) number, obtained from Chassis Plans prior to return. Freight on all returned
items must be prepaid by the customer, and the customer is responsible for any loss or
damage caused by common carrier in transit. Items will be returned from Chassis Plans
via Ground, unless prior arrangements are made by the customer for an alternative
shipping method

To obtain an RMA number, call us at [phone]. We will need the following infor­mation:

Return company address and contact
Model name and model # from the label on the back of the board
Serial number from the label on the back of the board
Description of the failure

An RMA number will be issued. Mark the RMA number clearly on the outside of each
box, include a failure report for each board and return the product(s) to our San Diego,
CA facility:

Chassis Plans
8295 Aero Place, Suite 200
San Diego, CA 92123
Attn: Repair Department
858-571-4330

TRADEMARKS IBM, PC, VGA, EGA, OS/2 and PS/2 are trademarks or registered trademarks of

International Business Machines Corp.

AMI and AMIBIOS are trademarks or registered trademarks of American

Megatrends Inc.
Intel, Pentium, Celeron and AGP are registered trademarks of Intel Corporation.
MS-DOS and Microsoft are registered trademarks of Microsoft Corp.
PICMG and the PICMG logo are registered trademarks of the PCI Industrial Computer

Manufacturers Group.
SCSISelect is a trademark of Adaptec, Inc.
All other brand and product names may be trademarks or registered trademarks of their

respective companies.

L

IABILITY

D

ISCLAIMER

This manual is as complete and factual as possible at the time of printing; however, the
information in this manual may have been updated since that time. Chassis Plans
reserves the right to change the functions, features or specifications of their products at
any time, without notice.

Copyright

© 2003 by Chassis Plans All rights reserved.

E-mail: [e-mail]
Web: www.chassisplans.com

Chassis Plans, LLC
8295 Aero Place
Sales: [phone]

• Suite 200 • San Diego, California 92123

• Fax: [phone] • Web http://www.chassisplans.com

CBI/CGI Technical Reference

Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1

Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-3

SBC Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5

SBC Processor Board Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6

Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-7

Bus Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-7

Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-7

Bus Speed - ISA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-7

Bus Speed - PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-7

Bus Speed - System & Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-7

System & Memory Buses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-7

DMA Channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-7

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-7

BIOS (Flash). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-7

Cache Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-7

DRAM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-8

Memory Hole . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-9

Error Checking and Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-9

PCI Local Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-9

Universal Serial Bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-9

Concurrent PCI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-9

AGP VGA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-9

System Hardware Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-9

10/100Base-T Ethernet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . .1-10

PCI Ultra Wide SCSI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-10

PCI Enhanced IDE Ultra DMA/33 Interfaces (Dual) . . . . . . . . . . .1-11

Floppy Drive Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-11

Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-11

Enhanced Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-11

PS/2 Mouse Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-11

Keyboard Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-11

Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-11

Power Fail Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-11

Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-12

Power Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-12

Table of Contents

Chassis Plans i

CBI/CGI Technical Reference

Table of Contents

Specifications (continued)

Temperature/Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-12

Mean Time Between Failures (MTBF) . . . . . . . . . . . . . . . . . . . . . .1-12

UL Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-12

Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-13

Ethernet LEDs and Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-15

System BIOS Setup Utility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-15

Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-16

ISA/PCI Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1

ISA Bus Pin Numbering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1

ISA Bus Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2

ISA Bus Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3

I/O Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7

Interrupt Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7

PCI Local Bus Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8

PCI Local Bus Signal Definition . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9

PCI Local Bus Pin Numbering. . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10

PCI Local Bus Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . .2-11

PCI Local Bus Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . .2-14

PICMG Edge Connector Pin Assignments . . . . . . . . . . . . . . . . . . .2-18

System BIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1

BIOS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1

Password Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3

BIOS Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-4

Running AMIBIOS Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-5

AMIBIOS Setup Utility Main Menu . . . . . . . . . . . . . . . . . . . . . . . .3-6

AMIBIOS Setup Utility Options . . . . . . . . . . . . . . . . . . . . . . . . . . .3-6

Auto-Detect Hard Disks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-11

Change Password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-11

Change Supervisor Password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-11

Change User Password. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-12

Disabling the Password(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-13

Auto Configuration Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-13

Auto Configuration with Optimal Settings . . . . . . . . . . . . . . . . .3-13

Auto Configuration with Fail Safe Settings . . . . . . . . . . . . . . . .3-14

Chassis Plansii

CBI/CGI Technical Reference

System BIOS (continued)

Save Settings and Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-14

Exit Without Saving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-14

Key Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-15

Standard CMOS Setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1

Standard CMOS Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1

Boot Sector Virus Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-6

Advanced Setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1

Advanced CMOS Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1

Advanced Chipset Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-10

Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1

PCI/Plug and Play Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-1

Table of Contents

Peripheral Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1

Appendix A - BIOS Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-1

BIOS Beep Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-1

BIOS Error Messages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-2

ISA BIOS NMI Handler Messages . . . . . . . . . . . . . . . . . . . . . . . . .A-5

Port 80 Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-6

Additional Bus Checkpoints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-12

Appendix B - Adaptec, Inc. Software License . . . . . . . . . . . . . . . . . . .B-1

Appendix C - SCSISelect Configuration Utility. . . . . . . . . . . . . . . . . .C-1

Declaration of Conformity

Chassis Plans iii

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CBI/CGI Technical Reference

Copyright 2003 by Trenton Technology Inc. All rights reserved.

Chassis Plansiv

CBI/CGI Technical Reference

HANDLING
P

RECAUTIONS

S

OLDER-SIDE

C

OMPONENTS

_______________________________________________________________________

WA R NI N G : This product has components which may be damaged by electrostatic
discharge.
_______________________________________________________________________

To protect your single board computer (SBC) from electrostatic damage, be sure to
observe the following precautions when handling or storing the board:

• Keep the SBC in its static-shielded bag until you are ready to perform your

installation.

• Handle the SBC by its edges.

• Do not touch the I/O connector pins. Do not apply pressure or attach labels

to the SBC.

• Use a grounded wrist strap at your workstation or ground yourself

frequently by touching the metal chassis of the system before handling any
components. The system must be plugged into an outlet that is connected to
an earth ground.

• Use antistatic padding on all work surfaces.

• Avoid static-inducing carpeted areas.

This SBC has components on both sides of the PCB. It is important for you to observe
the following precautions when handling or storing the board to prevent solder-side
components from being damaged or broken off:

• Handle the board only by its edges.

• Store the board in padded shipping material or in an anti-static board rack.

• Do not place an unprotected board on a flat surface.

Chassis Plans v

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CBI/CGI Technical Reference

Copyright 2003 by Trenton Technology Inc. All rights reserved.

Chassis Plansvi

Chapter 1 Specifications

SpecificationsCBI/CGI Technical Reference

INTRODUCTION The CBI full-featured PCI/ISA processors are single board computers (SBCs) which

feature an Intel

®

Celeron® microprocessor or Intel® Pentium® III microprocessor, Intel
440BX AGPset, 66/100MHz system and memory buses, Intel Accelerated Graphics Port
(AGP) video interface, SDRAM, PCI Local Bus, cache, floppy controller, dual EIDE
(Ultra DMA/33) interface, PCI Ultra Wide SCSI controller, PCI 10/100Base-T Ethernet
controller, two serial ports, parallel port, speaker port, mouse port and keyboard port
on a single ISA-size card. These single-slot, high performance SBCs plug into PICMG
PCI/ISA passive backplanes and provide full PC compatibility for the system expansion
slots.

The CGI models of this SBC feature the Intel 440GX AGPset, supporting memory
configurations up to 1GB.

The CB BASIC model has all of the standard features of the CBI, but does not include
the Intel video interface, PCI Ultra Wide SCSI controller or PCI 10/100Base-T Ethernet
controller.

ODELS

M

Model # Model Name Speed

CBI - BX:

®

Intel

Pentium® III Processor - 100MHz FSB/256K cache:

S5721-110-xM
S5721-109-xM
S5721-108-xM
S5721-107-xM
S5721-106-xM
S5721-105-xM
S5721-104-xM
S5721-103-xM
S5721-102-xM
S5721-101-xM

CBI/1.0
CBI/900
CBI/850
CBI/800
CBI/750
CBI/700
CBI/650
CBI/600E
CBI/550E
CBI/500E

1.0GHz
900MHz
850MHz
800MHz
750MHz
700MHz
650MHz
600MHz
550MHz
500MHz

®

®

Intel

Celeron® Processor - 100MHz FSB/128K cache:

S5721-205-xM
S5721-204-xM

®

Intel

Celeron® Processor - 66MHz FSB/128K cache:

S5721-016-xM
S5721-015-xM
S5721-014-xM
S5721-013-xM
S5721-012-xM
S5721-011-xM
S5721-010-xM
S5721-009-xM
S5721-008-xM
S5721-007-xM
S5721-006-xM

CBI/900C
CBI/850C

CBI/800C
CBI/766
CBI/733
CBI/700C
CBI/667
CBI/633
CBI/600
CBI/566
CBI/533
CBI/500
CBI/466

900MHz
850MHz

800MHz
766MHz
733MHz
700MHz
667MHz
633MHz
600MHz
566MHz
533MHz
500MHz
466MHz

Chassis Plans 1-1

Specifications CBI/CGI Technical Reference

MODELS
(

CONTINUED)

Model #

CBI - BX: (continued)

®

Intel

Celeron® Processor - 66MHz FSB/128K cache: (cont’d)

S5721-005-xM
S5721-004-xM
S5721-003-xM
S5721-002-xM

CGI - GX:

®

Intel

Pentium® III Processor - 100MHz FSB/256K cache:

S5721-150-xM
S5721-149-xM
S5721-148-xM
S5721-147-xM
S5721-146-xM
S5721-145-xM
S5721-144-xM
S5721-143-xM
S5721-142-xM
S5721-141-xM

Model Name Speed

CBI/433
CBI/400
CBI/366
CBI/333

CGI/1.0
CGI/900
CGI/850
CGI/800
CGI/750
CGI/700
CGI/650
CGI/600E
CGI/550E
CGI/500E

433MHz
400MHz
366MHz
333MHz

1.0GHz
900MHz
850MHz
800MHz
750MHz
700MHz
650MHz
600MHz
550MHz
500MHz

®

Intel

Celeron® Processor - 100MHz FSB/128K cache:

S5721-245-xM
S5721-244-xM

®

Intel

Celeron® Processor - 66MHz FSB/128K cache:

S5721-056-xM
S5721-055-xM
S5721-054-xM
S5721-053-xM
S5721-052-xM
S5721-051-xM
S5721-050-xM
S5721-049-xM
S5721-048-xM
S5721-047-xM
S5721-046-xM
S5721-045-xM
S5721-044-xM
S5721-043-xM
S5721-042-xM

CGI/900C
CGI/850C

CGI/800C
CGI/766
CGI/733
CGI/700C
CGI/667
CGI/633
CGI/600
CGI/566
CGI/533
CGI/500
CGI/466
CGI/433
CGI/400
CGI/366
CGI/333

900MHz
850MHz

800MHz
766MHz
733MHz
700MHz
667MHz
633MHz
600MHz
566MHz
533MHz
500MHz
466MHz
433MHz
400MHz
366MHz
333MHz

CB BASIC - BX:

®

Intel

Pentium® III Processor - 100MHz FSB/256K cache:

S5721-130-xM
S5721-129-xM
S5721-128-xM

CBB/1.0
CBB/900
CBB/850

1.0GHz
900MHz
850MHz

Chassis Plans1-2

MODELS
(

CONTINUED)

Model #

Model Name Speed

CB BASIC - BX: (continued)

®

Intel

Pentium® III Processor - 100MHz FSB/256K: (cont’d)

S5721-127-xM
S5721-126-xM
S5721-125-xM
S5721-124-xM
S5721-123-xM
S5721-122-xM
S5721-121-xM

®

Intel

Celeron® Processor - 100MHz FSB/128K cache:

S5721-225-xM
S5721-224-xM

®

Intel

Celeron® Processor - 66MHz FSB/128K cache:

S5721-036-xM
S5721-035-xM
S5721-034-xM
S5721-033-xM
S5721-032-xM
S5721-031-xM
S5721-030-xM
S5721-029-xM
S5721-028-xM
S5721-027-xM
S5721-026-xM
S5721-025-xM
S5721-024-xM
S5721-023-xM
S5721-022-xM

CBB/800
CBB/750
CBB/700
CBB/650
CBB/600E
CBB/550E
CBB/500E

CBB/900C
CBB/850C

CBB/800C
CBB/766
CBB/733
CBB/700C
CBB/667
CBB/633
CBB/600
CBB/566
CBB/533
CBB/500
CBB/466
CBB/433
CBB/400
CBB/366
CBB/333

800MHz
750MHz
700MHz
650MHz
600MHz
550MHz
500MHz

900MHz
850MHz

800MHz
766MHz
733MHz
700MHz
667MHz
633MHz
600MHz
566MHz
533MHz
500MHz
466MHz
433MHz
400MHz
366MHz
333MHz

SpecificationsCBI/CGI Technical Reference

where xM indicates memory size (0M = 0MB memory,
8M =8MB memory, etc.)

F

EATURES • Intel

®

Pentium® III (FC-PGA) microprocessor

• 1.0GHz, 900MHz, 850MHz, 800MHz, 750MHz, 700MHz or 650MHz,

600EMHz, 550EMHz or 500EMHz with 256K cache and a 100MHz Front
Side Bus (FSB)

®

or Intel

Celeron® microprocessor

• 900MHz or 850MHz with 128K cache and a 100MHz FSB

• 800MHz, 766MHz, 733MHz, 700MHz, 667MHz, 633MHz, 600MHz,

566MHz, 533MHz, 500MHz, 466MHz, 433MHz, 400MHz, 366MHz or
333MHz with 128K cache and a 66MHz FSB

• Intel 440BX AGPset with 66/100MHz system and memory buses, and PCI

bandwidth greater than 100MB/second. 440GX AGPset also available.

Chassis Plans 1-3

Specifications CBI/CGI Technical Reference

FEATURES
(

CONTINUED)

• Intel Accelerated Graphics Port (AGP) VGA on-board video interface

• PCI Local Bus supports off-board PCI option cards, PCI 10/100Base-T Ethernet

controller and on-board PCI Ultra Wide SCSI controller - Adaptec AIC-7880

• DRAM error checking and correction (ECC) support

• Compatible with PCI Industrial Computer Manufacturers Group (PICMG) 1.0

Specification

• Supports up to 512MB of Synchronous DRAM (SDRAM) on board; 440GX

AGPset supports up to 1GB

• Floppy drive and dual PCI EIDE Ultra DMA/33 drive interface

• Two serial ports and one parallel port

• Automatic or manual peripheral configuration

• Watchdog timer

• System hardware monitor

• Supports 1M x 64 to 32M x 64 DIMMs for non-ECC configurations; supports

1M x 72 to 32M x 72 DIMMs for ECC configurations. 440GX configurations
support up to 64M x 72 DIMMs.

• Shadow RAM for System BIOS and peripherals increases system speed and

performance

• Full PC compatibility

Chassis Plans1-4

SBC BLOCK
D

IAGRAM

SpecificationsCBI/CGI Technical Reference

Chassis Plans 1-5

Specifications CBI/CGI Technical Reference

SBC PROCESSOR
B

OARD LAYOUT

Chassis Plans1-6

PROCESSORS • Intel® Pentium® III (FC-PGA) microprocessor

• 1.0GHz, 900MHz, 850MHz, 800MHz, 750MHz, 700MHz or 650MHz,

600EMHz, 550EMHz or 500EMHz with 256K cache and a 100MHz Front
Side Bus (FSB)

®

or Intel

Celeron® microprocessor

• 900MHz or 850MHz with 128K cache and a 100MHz FSB

• 800MHz, 766MHz, 733MHz, 700MHz, 667MHz, 633MHz, 600MHz,

566MHz, 533MHz, 500MHz, 466MHz, 433MHz, 400MHz, 366MHz or
333MHz with 128K cache and a 66MHz FSB

B

US INTERFACES ISA and PCI Local Bus compatible

D

ATA PATH DRAM/Memory - 64-bit

ISA Bus - 16-bit

PCI Bus - 32-bit

Video - 64-bit

SpecificationsCBI/CGI Technical Reference

B

US SPEED - ISA 8.33MHz

B

US SPEED - PCI 33MHz

B

US SPEED -

S

YSTEM &

M

EMORY

S

YSTEM &

M

EMORY BUSES

• Intel® Pentium® III - 100MHz

• Intel

®

Celeron® - 66MHz or 100MHz

The Intel 440BX/GX AGPset supports the system and memory buses at both 66MHz and
100MHz speeds. The 100MHz system and memory buses provide a higher bandwidth
path for transferring data between main memory/chip set and the processor.

DMA C

HANNELS The SBC is fully PC compatible with seven DMA channels, each supporting type F

transfers.

I

NTERRUPTS The SBC is fully PC compatible with interrupt steering for PCI plug and play compati-

bility.

BIOS (F

LASH) The BIOS is a Hi-Flex AMIBIOS with built-in advanced CMOS setup for system param-

eters, peripheral management for configuring on-board peripherals, PCI-to-PCI bridge
support and PCI interrupt steering. The BIOS chip is a boot block Flash device ­28F002BX-T120. The BIOS may be upgraded from floppy disk by pressing <Ctrl> +
<Home> immediately after reset or power-up with the floppy disk in drive A:. Custom
BIOSs are available.

C

ACHE MEMORY For Pentium III processors, the processor includes an integrated on-die, 256K 8-way set

associative level two (L2) cache. The L2 cache implements the Advanced Transfer
Cache architecture with a 256-bit wide bus. The processor also includes a 16K level one

Chassis Plans 1-7

Specifications CBI/CGI Technical Reference

(L1) instruction cache and 16K L1 data cache. These cache arrays run at the full speed
of the processor core.

For Celeron processors, a 128K unified, non-blocking second level (L2) cache improves
performance by reducing the average memory access time and providing fast access to
recently used instructions and data.

DRAM M

EMORY The DRAM interface consists of two dual in-line memory module (DIMM) sockets and

supports auto detection of memory up to 512MB of Synchronous DRAM (SDRAM) for
the 440BX or up to 1GB of SDRAM for the 440GX. Minimum memory size is 8MB.
The System BIOS automatically detects memory type, size and speed.

The SBC uses industry standard 64-bit or 72-bit wide gold finger DIMM SDRAM
modules in two 168-pin DIMM sockets.
______________________________________________________________________

NOTE: Memory can be installed in one or both DIMM sockets. If only one DIMM
module is used, it must be populated in the top DIMM socket (Bank 1 - BK1). If two
modules are used, they must be the same DIMM type, but may be different sizes (see
table below). EDO DIMMs are not supported. All DIMMs must have gold contacts.
______________________________________________________________________

The SBC supports DIMM memory modules which are PC-100 compliant and have the
following features:

• 168-pin DIMMs with gold-plated contacts

• 100MHz SDRAM

• Non-ECC (64-bit) or ECC (72-bit) memory

• 3.3 volt

• Single or double-sided DIMMs in the sizes listed below

• Buffered or Registered configuration

The following DIMM sizes are supported:

DIMM

Size

8MB
16MB
32MB
64MB

128MB
256MB
512MB

* CGI models only

All memory components and DIMMs used with the SBC must be PC-100 compliant,
which means that they comply with Intel's PC SDRAM specifications. These include the
PC SDRAM Specification (memory component specific), the PC Unbuffered DIMM

DIMM Type Non-ECC ECC

Unbuffered
Unbuffered
Unbuffered
Unbuffered
Unbuffered
Registered
Registered

1M x 64
2M x 64
4M x 64

8M x 64
16M x 64
32M x 64

64M x 64

1M x 72
2M x 72
4M x 72

8M x 72
16M x 72
32M x 72

64M x 72 *

Chassis Plans1-8

SpecificationsCBI/CGI Technical Reference

Specification, the PC Registered DIMM Specification and the PC Serial Presence Detect
Specification.

M

EMORY HOLE The SBC supports a 1MB memory hole option at 512KB-640KB or 15MB-16MB.

RROR CHECKING

E

AND CORRECTION

PCI L

OCAL BUS

I

NTERFACE

The memory interface supports ECC modes via BIOS setting for multiple-bit error
detection and correction of all errors confined to a single nibble.

The SBC is fully compliant with the PCI Local Bus 2.1 Specification. It has optimized
the PCI interface to allow the processor to sustain the highest possible bandwidth
(greater than 100MB/sec sustained) and low latency of the PCI Bus. It supports PCI-to­PCI bridge technology, a pipelined snoop ahead feature and improved PCI to DRAM
write-back policy. The PCI Local Bus interfaces to standard PCI option cards in the
backplane, and to the on-board PCI Ultra Wide SCSI controller and PCI 10/100Base-T
Ethernet controller. The PCI Local Bus interface to the backplane is compliant with the
PCI Industrial Computer Manufacturers Group (PICMG) 1.0 Specification.

U

NIVERSAL SERIAL

B

US (USB)

The SBC supports two USB 1.0 ports for serial transfers at 12 or 1.5Mbit/sec. The
Universal Serial Bus (USB) is an interface allowing for connectivity to many standard
PC peripherals via an external port.

C

ONCURRENT PCI Concurrent PCI maximizes system performance with simultaneous processor, PCI and

AGP Bus activities. It includes multitransaction timing, enhanced write performance, a
passive release mechanism and support for PCI 2.1 compliant delayed transactions.

AGP VGA
I

NTERFACE (NOT

AVAILABLE ON

BASIC

MODELS)

The 69000 HiQVideo video/graphic accelerator is an Accelerated Graphics Port (AGP)
device. AGP is designed to off-load the PCI Bus by allowing graphics data to move
directly from system memory. The 69000 integrates 2MB of high-speed SDRAM frame
buffer memory into the chip.

By embedding SDRAM and graphics controller logic on the same die, the 69000 delivers
uncompromising performance. The increase in the frame buffer bandwidth enables the
69000 to support high-color, high-resolution graphics modes and real-time video acceler­ation. The interface supports pixel resolutions up to 1600 x 1200 non-interlaced.

Software drivers for enhanced performance and resolution are available for most popular
operating systems.

S

YSTEM

H

ARDWARE

The system hardware monitoring system monitors system voltages, temperature and fan
speeds.

MONITOR

The circuitry is based on National Semiconductor's LM80. The LM80 monitors seven
system voltages, two fan speeds and the board ambient temperature. All of the voltages,
fan speeds and temperature measurements have associated programmable watchdog
limits. When any of these programmed limits are exceeded, the monitor software can be
used to notify the SBC. In addition, the externally available OS# signal can be used to
notify external hardware of any over-temperature condition.

Fan speed monitoring can be configured to monitor two system fans.

Chassis Plans 1-9

Specifications CBI/CGI Technical Reference

The LM80 also monitors an external chassis intrusion switch via the system hardware
monitor connector (P18).

A general purpose output (GPO) is also provided at the system hardware monitor
connector. This signal can be used to provide a user-defined function.

The following system voltages are monitored by the LM80:

• -12 volts

• 3.3 volts provided by the on-board voltage regulator for components on the

SBC

• 3.3 volts backplane power used by the option slots

• +5 volts

• +12 volts

• VCC_CORE, voltage provided by on-board VRM

• 1.5 volt, VTT voltage used by processor's GTL+ bus

10/100B
E

THERNET

I

NTERFACE (NOT

AVAILABLE ON

BASIC

PCI U
SCSI I

ASE-T

MODELS)

LTRA WIDE

NTERFACE

(NOT AVAILABLE

ON BASIC
MODELS)

The PCI Ethernet interface is implemented using an Intel 82559 and operates in
10Base-T and 100Base-TX Fast Ethernet modes. The interface is compliant with
IEEE 802.3 and PCI Local Bus 2.1 Specifications.

The main components of the interface are:

• Intel 82559 for 10/100-Mb/s media access control (MAC) with SYM, a

serial ROM port and a PCI Bus Master interface

• Serial ROM for storing the Ethernet address and the interface configuration

and control data

• Integrated RJ-45/Magnetics module connector on the SBC's I/O bracket for

direct connection to the network. The connector requires a category 5
(CAT5) unshielded twisted-pair (UTP) 2-pair cable for a 100-Mb/s network
connection or a category 3 (CAT3) or higher UTP 2-pair cable for a 10-Mb/s
network connection.

• Link status and activity LEDs on the I/O bracket for status indication (See

Ethernet LEDs and Connector later in this section.)

Software drivers are supplied for most popular operating systems.

The SCSI interface is a PCI Bus Master device which supports Ultra Wide SCSI data
transfer up to 40MB per second and bursts data to the host at full PCI speeds. Active
termination is provided with terminator voltage protected by self-resetting fuses. A
jumper is provided to disable the termination. The SCSI controller is an Adaptec
AIC-7880. Software drivers are available for most popular operating systems.

The Adaptec SCSISelect Configuration Utility allows you to view and/or change the
default configuration settings for the Ultra Wide SCSI adapter. This utility is described
in Appendix C - SCSISelect Configuration Utility.

Chassis Plans1-10

SpecificationsCBI/CGI Technical Reference

PCI ENHANCED
IDE U

LTRA

DMA/33
I

NTERFACE (DUAL)

F

LOPPY DRIVE

I

NTERFACE

ERIAL INTERFACE Two high-speed FIFO (16C550) serial ports with independently programmable baud

S

Dual high performance PCI Bus Master EIDE interfaces are capable of supporting two
IDE Type 4 disk drives each in a master/slave configuration. The interface supports
Ultra DMA/33 with synchronous DMA mode transfers up to 33MB per second.

The SBC supports two floppy disk drives. Drives can be 360K to 2.88MB, in any
combination.

rates are supported. The IRQ for each serial port has BIOS selectable addressing.

E

NHANCED

P

ARALLEL

I

NTERFACE

PS/2 M
I

NTERFACE

OUSE

The SBC provides a PC/AT compatible bidirectional parallel port and supports enhanced
parallel port (EPP) mode and extended capabilities port (ECP) mode. The ECP mode is
IEEE 1284 compliant. The IRQ for the parallel port has BIOS selectable addressing.

The SBC is compatible with a PS/2-type mouse. The mouse connection can be made by
using either the PS/2 mouse header or the bracket mounted PS/2 mouse mini DIN
connector. Mouse voltage is protected by a self-resetting fuse.

K

EYBOARD

I

NTERFACE

The SBC is compatible with an AT-type keyboard. The keyboard connection can be
made by using either the keyboard header or the bracket mounted keyboard mini DIN
connector. Keyboard voltage is protected by a self-resetting fuse.

W

ATCHDOG TIMER The watchdog timer is a hardware timer which resets the SBC if the timer is not

refreshed by software periodically. The timer is typically used to restart a system in
which an application becomes hung on an external event. When the application is hung,
it no longer refreshes the timer. The watchdog timer then times out and resets the SBC.

P

OWER FAIL

DETECTION

The watchdog timer has two levels of enable. First, the watchdog timer jumper must be
moved to the "enabled" position, which puts the watchdog timer under software control.

The second level involves software control of the watchdog's timer retriggering. Bit 6 of
the 82371EB GPOREG register at I/O address 437H must be set to a zero (0), which
blocks the triggering clock to the watchdog timer circuit, thus scheduling a hardware
reset in about 1.5 seconds.

To refresh the watchdog timer, the software in the application toggles bit 6 of the
GPOREG register. First the bit must be set to a one (1) to clear the watchdog timer
delay; then it must be set to a zero (0), which schedules a system reset in 1.5 seconds.
Toggling bit 6 of the GPOREG must occur within a period of less than 1.5 seconds to
insure that a system reset is not issued.

A set of watchdog timer software code and sample programs are available from
Technical Support.

A hardware reset is issued when on-board +5V voltage drops below 4.75 volts. In
addition, if the 3.3V Monitor jumper (JU15) is enabled, a reset is issued if 3.3V is below
tolerance. (See the Configuration Jumpers section later in this chapter.)

Chassis Plans 1-11

Specifications CBI/CGI Technical Reference

BATTERY A built-in lithium battery is provided, for ten years of data retention for CMOS memory.

______________________________________________________________________

CAUTION: There is a danger of explosion if the battery is incorrectly replaced.
Replace it only with the same or equivalent type recommended by the manufacturer.
Dispose of used batteries according to the manufacturer's instructions.
______________________________________________________________________

P

OWER

R

EQUIREMENTS

The following are typical values:

Processor

Speed

+5V * +12V -12V

Intel® Pentium® III -100MHz FSB:

T

EMPERATURE/

E

NVIRONMENT

850MHz
800MHz

®

Intel

733MHz
667MHz
633MHz

Operating Temperature: 0º C. to 60º C.

Storage Temperature: - 40

7.6 Amps

7.1 Amps

< 100 mAmps
< 100 mAmps

Celeron® - 66MHz FSB:

6.5 Amps

6.1 Amps

5.6 Amps

< 100 mAmps
< 100 mAmps
< 100 mAmps

0

º C. to 55º C. for 700MHz Intel

º C. to 70º C.

Humidity: 5% to 90% non-condensing

M

EAN TIME

B

ETWEEN

F

AILURES (MTBF)

CBI/CGI:

66,000 POH (Power-On Hours) at 40° C., per MIL-HDBK-217F

CB BASIC:

95,000 POH (Power-On Hours) at 40° C., per MIL-HDBK-217F

UL R

ECOGNITION This SBC is a UL recognized product listed in file #E208896.

< 100 mAmps
< 100 mAmps

< 100 mAmps
< 100 mAmps
< 100 mAmps

®

Pentium® III and above

This board was investigated and determined to be in compliance under the Bi-National
Standard for Information Technology Equipment. This included the Electrical Business
Equipment, UL 1950, Third Edition, and CAN/CSA C22.22 No. 950-95.

Chassis Plans1-12

SpecificationsCBI/CGI Technical Reference

CONFIGURATION
J

UMPERS

The setup of the configuration jumpers on the SBC is described below. * indicates the
default value of each jumper.
______________________________________________________________________

NOTE: For two-position jumpers (3-post), "RIGHT" is toward the bracket end of the
board; "LEFT" is toward the memory sockets.
______________________________________________________________________

Jumper

JU7 Combo I/O (P5A) Speaker Connect

JU8 Password Clear

JU9 CRT Type Select

Description

(Also refer to JU18 - Combo I/O Reset Connect.)

Install to connect speaker data signal to pin 8 of the Combo
I/O connector (P5A). *
Remove to disconnect.

Install for one power-up cycle to reset the password to the
default (null password).
Remove for normal operation. *

Install on the LEFT for a monochrome CRT.
Install on the RIGHT for a color CRT. *

JU10/JU11 System Flash ROM Operational Modes

The Flash ROM has two programmable sections: the Boot
Block for “flashing” in the BIOS and the Main Block for the
executable BIOS and PnP parameters. Normally only the
Main Block is updated when a new BIOS is flashed into the
system.

JU10

Program All (Boot and Main) Bottom Bottom
Normal PnP (Program Main Block) Bottom * Top *
Write Protect Top Top

JU12 CMOS Clear

Install to clear.
Remove to operate. *
__________________________________________________
NOTE: The CMOS Clear jumper works on power-up. To
clear the CMOS, power down the system, install the jumper,
then turn the power back on. CMOS is cleared during the
POST routines. Then power down the system again and
remove the jumper before the next power-up.
__________________________________________________

JU11

Chassis Plans 1-13

Specifications CBI/CGI Technical Reference

CONFIGURATION
J

UMPERS

(

CONTINUED)

Jumper

Description

JU13 SCSI Termination Enable (not available on BASIC models)

Install to disable on-board active termination for the SCSI
interface.
Remove to enable active termination. *

JU14 Fan Speed Monitor

This jumper must be removed (disabled).

JU15 3.3V Monitor Enable

Install to enable the 3.3V monitor.
Remove to disable the monitor. *

NOTE: On SBCs with revision L-07 and later, the position of
this jumper is horizontal; on earlier revisions it is vertical.
__________________________________________________

NOTE: JU15 enables the 3.3 volt monitor, which monitors
the 3.3V power plane of the backplane. This voltage is routed
to the SBC via the PICMG connector. The monitor generates
a RESET to the SBC if 3.3V is below tolerance. If your
system does not supply 3.3V to the backplane, this jumper
must be removed (disabled).
__________________________________________________

JU16 Watchdog Timer

Install on the LEFT for normal reset operation. *
Install on the RIGHT to enable watchdog timer operation.

JU18 Combo I/O (P5A) Reset Connect

(Also refer to JU7 - Combo I/O Speaker Connect.)

Install to connect reset data signal to pin 1 of the Combo I/O
connector (P5A). *
Remove to disconnect.

JU19 SCSI Activity LED Enable (not available on BASIC models)

Install to light the hard drive LED for SCSI drive activity. *
Remove if you do not have a SCSI drive (i.e., the SCSI
controller is not being used).

Chassis Plans1-14

SpecificationsCBI/CGI Technical Reference

ETHERNET LEDS

AND CONNECTOR

(

NOT AVAILABLE
ON BASIC
MODELS)

The Ethernet interface has two LEDs for status indication and an RJ-45 network
connector.

LED/Connector

Description

Link/Activity LED Green LED which indicates the link status

Off The Ethernet interface did not find a valid link on the

network connection. Transmit and receive are not
possible.

On (solid) The Ethernet interface has a valid link on the network

connection and is ready for normal operation. The Speed
LED identifies connection speed.

On (flashing) Indicates network transmit or receive activity.

Speed LED Amber LED which identifies the connection speed.

Off Indicates a 10Mb/s connection.

On Indicates a 100Mb/s connection.

RJ-45 Network
Connector

The RJ-45 network connector requires a category 5
(CAT5) unshielded twisted-pair (UTP) 2-pair cable for a
100-Mb/s network connection or a category 3 (CAT3) or
higher UTP 2-pair cable for a 10-Mb/s network
connection.

S

YSTEM BIOS

S

ETUP UTILITY

The System BIOS is a Hi-Flex AMIBIOS with a ROM-resident setup utility. The BIOS
Setup Utility allows you to select the following options:

• Standard CMOS Setup

• Advanced CMOS Setup

• Advanced Chipset Setup

• Power Management Setup

• PCI/Plug and Play Setup

• Peripheral Setup

• Auto-Detect Hard Disks

• Change User Password/Change Supervisor Password

• Auto Configuration with Optimal Settings

• Auto Configuration with Fail Safe Settings

• Save Settings and Exit

• Exit Without Saving

Chassis Plans 1-15

Specifications CBI/CGI Technical Reference

CONNECTORS ______________________________________________________________________

NOTE: Pin 1 on the connectors is indicated by the square pad on the PCB.
______________________________________________________________________

P2 - Keylock Connector

5 pin single row header, Amp #640456-5

Pin

Signal

1

LED Power

2

Key

3

Gnd

4

Keylock Data

5

Gnd

P3 - Floppy Drive Connector

34 pin dual row header, Robinson Nugent #IDH-34LP-S3-TR

Signal

Pin

1

Gnd

3

Gnd

5

Gnd

7

Gnd

9

Gnd

11

Gnd

13

Gnd

15

Gnd

17

Gnd

19

Gnd

21

Gnd

23

Gnd

25

Gnd

27

Gnd

29

Gnd

31

Gnd

33

Gnd

P4 - Keyboard Connector

6 pin mini DIN, Kycon #KMDG-6S-BS-PS

Pin

Signal

1

Kbd Data

2

Reserved

3

Gnd

4

Kbd Power (+5V fused) with self-resetting fuse

5

Kbd Clock

6

Reserved

Pin

2
4
6

8
10
12
14
16
18
20
22
24
26
28
30
32
34

Signal
N-RPM
NC
D-Rate0
P-Index
N-Motoron 1
N-Drive Sel2
N-Drive Sel1
N-Motoron 2
N-Dir
N-Stop Step
N-Write Data
N-Write Gate
P-Track 0
P-Write Protect
N-Read Data
N-Side Select
Disk Chng

Chassis Plans1-16

CONNECTORS
(

CONTINUED)

P4A - Keyboard Header

5 pin single row header, Amp #640456-5

Pin

Signal

1

Kbd Clock

2

Kbd Data

3

Key

4

Kbd Gnd

5

Kbd Power (+5V fused) with self-resetting fuse

P5 - Speaker Port Connector

4 pin single row header, Amp #640456-4

Signal

Pin

1

Speaker Data

2

Key

3

Gnd

4

+5V

P5A - Combo I/O Connector

8 pin single row header, Amp #640456-8

SpecificationsCBI/CGI Technical Reference

Signal

Pin

1

Reset (See JU18 in the Configuration Jumpers section.)

2

Gnd

3

NC

4

Kbd Clock

5

Kbd Data

6

Kbd Lock Data

7

Kbd Power (+5V fused) with self-resetting fuse

8

Speaker Data

P6 - Serial Port 1 Connector

10 pin dual row header, 3M #30310-6002HB

Pin

Signal

1

Carrier Detect

3

Receive Data-I

5

Transmit Data-O

7

Data Terminal Ready-O

9

Signal Gnd

P7 - Serial Port 2 Connector

10 pin dual row header, 3M #30310-6002HB

Pin

Signal

1

Carrier Detect

3

Receive Data-I

5

Transmit Data-O

Pin

Signal

2

Data Set Ready-I

4

Request to Send-O

6

Clear to Send-I

8

Ring Indicator-I

10

NC

Pin

Signal

2

Data Set Ready-I

4

Request to Send-O

6

Clear to Send-I

Chassis Plans 1-17

Specifications CBI/CGI Technical Reference

CONNECTORS
(

CONTINUED)

P7 - Serial Port 2 Connector (continued)

Signal

Pin

7

Data Terminal Ready-O

9

Signal Gnd

P8 - Parallel Port Connector

26 pin dual row header, 3M #30326-6002HB

Signal

Pin

1

Strobe

3

Data Bit 0

5

Data Bit 1

7

Data Bit 2

9

Data Bit 3

11

Data Bit 4

13

Data Bit 5

15

Data Bit 6

17

Data Bit 7

19

ACK

21

Busy

23

Paper End

25

Slct

P9 - PS/2 Mouse Connector

6 pin mini DIN, Kycon #KMDG-6S-BS-PS

Pin

Signal

8

Ring Indicator-I

10

NC

Pin

Signal

2

Auto Feed XT

4

Error

6

Init

8

Slct In

10

Gnd

12

Gnd

14

Gnd

16

Gnd

18

Gnd

20

Gnd

22

Gnd

24

Gnd

26

NC

Pin

Signal

1

Ms Data

2

Reserved

3

Gnd

4

Kbd Power (+5V fused) with self-resetting fuse

5

Ms Clock

6

Reserved

P9A - PS/2 Mouse Header

6 pin single row header, Amp #640456-6

Pin

Signal

1

Ms Data

2

Reserved

3

Kbd Gnd

4

Kbd Power (+5V fused) with self-resetting fuse

5

Ms Clock

6

Reserved

Chassis Plans1-18

CONNECTORS
(

CONTINUED)

P10 - External Reset Connector

2 pin header, Amp #640456-2

Pin

Signal

1

Negative External Reset

2

Gnd

P11 - Primary IDE Hard Drive Connector

40 pin dual row header, Robinson Nugent #IDH-40LP-S3-TR

SpecificationsCBI/CGI Technical Reference

Signal

Pin

1

Reset

3

Data 7

5

Data 6

7

Data 5

9

Data 4

11

Data 3

13

Data 2

15

Data 1

17

Data 0

19

Gnd

21

DRQ 0

23

IOW

25

IOR

27

IORDY

29

DACK 0

31

IRQ 14

33

Add 1

35

Add 0

37

CS 1P

39

IDEACTP

P11A - Secondary IDE Hard Drive Connector

40 pin dual row header, Robinson Nugent #IDH-40LP-S3-TR

Pin

2

4

6

8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

Signal
Gnd
Data 8
Data 9
Data 10
Data 11
Data 12
Data 13
Data 14
Data 15
NC
Gnd
Gnd
Gnd
+5V
Gnd
IOCS16
Gnd
Add 2
CS 3P
Gnd

Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27

Signal
Reset
Data 7
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
Data 0
Gnd
DRQ 1
IOW
IOR
IORDY

Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28

Signal
Gnd
Data 8
Data 9
Data 10
Data 11
Data 12
Data 13
Data 14
Data 15
NC
Gnd
Gnd
Gnd
+5V

Chassis Plans 1-19

Specifications CBI/CGI Technical Reference

CONNECTORS
(

CONTINUED)

P11A - Primary IDE Hard Drive Connector (continued)

Signal

Pin
29

DACK 1

31

MIRQ 0

33

Add 1

35

Add 0

37

CS 1S

39

IDEACTS

P12 - Hard Drive LED Connector

4 pin single row header, Amp #640456-4

(This connector is used for both IDE and SCSI drives. See
JU19 in the Configuration Jumpers section.)

Pin

Signal

1

+5V Pull-up

2

Light

3

Light

4

+5V Pull-up

P13 - PCI Ultra Wide SCSI Controller Connector

(not available on BASIC models)
50/68 pin high density connector, Amp #749069-7

Signal

Pin

1

Gnd

2

Gnd

3

Gnd

4

Gnd

5

Gnd

6

Gnd

7

Gnd

8

Gnd

9

Gnd

10

Gnd

11

Gnd

12

Gnd

13

Gnd

14

Gnd

15

Gnd

16

Gnd

17

TERMPWR

18

TERMPWR

19

NC

20

Gnd

21

Gnd

22

Gnd

Pin
30
32
34
36
38
40

Pin
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56

Signal
Gnd
IOCS16
Gnd
Add 2
CS 3S
Gnd

Signal
SCZDB12
SCZDB13
SCZDB14
SCZDB15
SCZDBPH
SCZDB0
SCZDB1
SCZDB2
SCZDB3
SCZDB4
SCZDB5
SCZDB6
SCZDB7
SCZDBP
Gnd
Gnd
TERMPWR
TERMPWR
NC
Gnd
SCZATN
Gnd

Chassis Plans1-20

CONNECTORS
(

CONTINUED)

SpecificationsCBI/CGI Technical Reference

P13 - PCI Ultra Wide SCSI Controller Connector (continued)

Signal

Pin
23

Gnd

24

Gnd

25

Gnd

26

Gnd

27

Gnd

28

Gnd

29

Gnd

30

Gnd

31

Gnd

32

Gnd

33

Gnd

34

WIDEPS

P15 - PCI SVGA Interface Connector

(not available on BASIC models)
15 pin VGA connector, Amp #748390-5

Pin

Signal

Pin Signal

6Gnd

1Red

7Gnd

2 Green

8Gnd

3Blue

9NC

4NC

10 Gnd

5Gnd

Pin
57
58
59
60
61
62
63
64
65
66
67
68

Pin

11

12

13

14

15

Signal
SCZBSY
SCZACK
ASCRST
SCZMSG
SCZSEL
SCZCD
SCZREQ
SCZIO
SCZDB8
SCZDB9
SCZDB10
SCZDB11

Signal

NC

EEDI

HSYNC

VSYNC

EECS

P16 - PCI 10/100Base-T Ethernet Connector

(not available on BASIC models)
8 pin shielded RJ-45 connector, Pulse #J0035D21B

Signal

Pin

1

TD+

2

TD-

3

RX+

4

NC

5

NC

6

RX-

7

NC

8

NC

Chassis Plans 1-21

Specifications CBI/CGI Technical Reference

CONNECTORS
(

CONTINUED)

P17 - Universal Serial Bus (USB) Connector

8 pin dual row header, Molex #702-46-0821
(+5V fused with self-resetting fuses)

Signal

Pin

1

+5V-USB0

3

USB0-

5

USB0+

7

Gnd-USB0

P18 - System Hardware Monitor Connector

6 pin single row header, Amp #640456-6

Signal

Pin

1

Gnd

2

GPO (General Purpose Output)

3

CI (Chassis Intrusion Input)

4

FAN1 (Fan 1 Tachometer Input)

5

FAN2 (Fan 2 Tachometer Input)

6

OS# (Temperature Sense Output)

P19 - CPU Fan

3 pin single row header, Molex #22-23-2031

Pin

Signal

1

Gnd

2

+12V

3

FanTach

Pin

2

4

6

8

Signal
+5V-USB1
USB1­USB1+
Gnd-USB1

Copyright 2003 by Trenton Technology Inc. All rights reserved.

Chassis Plans1-22

Chapter 2 ISA/PCI Reference

ISA BUS PIN
N

UMBERING

62-pin ISA Bus
Connector

ISA/PCI ReferenceCBI/CGI Technical Reference

Component Side
of Board

36-pin ISA Bus
Connector

Chassis Plans 2-1

ISA/PCI Reference CBI/CGI Technical Reference

ISA BUS PIN
A

SSIGNMENTS

The following tables summarize pin assignments for the Industry Standard Architecture
(ISA) Bus connectors.

I/O Pin Signal Name I/O I/O Pin Signal Name I/O

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31

IOCHK#
D7
D6
D5
D4
D3
D2
D1
D0
CHRDY
AEN
SA19
SA18
SA17
SA16
SA15
SA14
SA13
SA12
SA11
SA10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0

I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31

Gnd
RESDRV
+5V
IRQ9

-5V
DRQ2

-12V
NOWS#
+12V
Gnd
SMWTC#
SMRDC#
IOWC#
IORC#
DAK3#
DRQ3
DAK1#
DRQ1
REFRESH#
BCLK
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
DAK2#
T-C
BALE
+5V
OSC
Gnd

Ground
O
Power
I
Power
I
Power
I
Power
Ground
O
O
I/O
I/O
O
I
O
I
I/O
O
I
I
I
I
I
O
O
O
Power
O
Ground

I/O Pin Signal Name I/O I/O Pin Signal Name I/O

C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18

SBHE#
LA23
LA22
LA21
LA20
LA19
LA18
LA17
MRDC#
MWTC#
D8
D9
D10
D11
D12
D13
D14
D15

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18

M16#
IO16#
IRQ10
IRQ11
IRQ12
IRQ15
IRQ14
DAK0#
DRQ0
DAK5#
DRQ5
DAK6#
DRQ6
DAK7#
DRQ7
+5V
Master16#
Gnd

I
I
I
I
I
I
I
O
I
O
I
O
I
O
I
Power
I
Ground

Chassis Plans2-2

ISA/PCI ReferenceCBI/CGI Technical Reference

ISA BUS SIGNAL
D

ESCRIPTIONS

The following is a description of the ISA Bus signals. All signal lines are TTL­compatible.

AEN (O)

Address Enable (AEN) is used to degate the microprocessor and other devices from the I/O
channel to allow DMA transfers to take place. When this line is active, the DMA controller has
control of the address bus, the data-bus Read command lines (memory and I/O), and the Write
command lines (memory and I/O).

BALE (O) (Buffered)

Address Latch Enable (BALE) is provided by the bus controller and is used on the system board
to latch valid addresses and memory decodes from the microprocessor. It is available to the I/O
channel as an indicator of a valid microprocessor or DMA address (when used with AEN).
Microprocessor addresses SA[19::0] are latched with the falling edge of BALE. BALE is forced
high during DMA cycles.

BCLK (O)

BCLK is the system clock. The clock has a 50% duty cycle. This signal should only be used for
synchronization. It is not intended for uses requiring a fixed frequency.

CHRDY (I)

I/O Channel Ready (CHRDY) is pulled low (not ready) by a memory or I/O device to lengthen I/
O or memory cycles. Any slow device using this line should drive it low immediately upon
detecting its valid address and a Read or Write command. Machine cycles are extended by an
integral number of clock cycles. This signal should be held low for no more than 2.5 micro­seconds.

D[15::0] (I/O)

Data signals D[15::0] provide bus bits 15 through 0 for the microprocessor, memory, and I/O
devices. D15 is the most-significant bit and D0 is the least-significant bit. All 8-bit devices on
the I/O channel should use D[7::0] for communications to the microprocessor. The 16-bit
devices will use D[15::0]. To support 8-bit devices, the data on D[15::8] will be gated to D[7::0]
during 8-bit transfers to these devices. 16-bit microprocessor transfers to 8-bit devices will be
converted to two 8-bit transfers.

DAK[7::5]#, DAK[3::0]# (O)

DMA Acknowledge DAK[7::5]# and DAK[3::0]# are used to acknowledge DMA requests
DRQ[7::5] and DRQ[3::0]. They are active low.

DRQ[7::5], DRQ[3::0] (I)

DMA Requests DRQ[7::5] and DRQ[3::0] are asynchronous channel requests used by
peripheral devices and the I/O channel microprocessors to gain DMA service (or control of the
system). They are prioritized, with DRQ0 having the highest priority and DRQ7 having the
lowest. A request is generated by bringing a DRQ line to an active level. A DRQ line must be
held high until the corresponding DMA Request Acknowledge (DAK) line goes active.
DRQ[3::0] will perform 8-bit DMA transfers; DRQ[7::5] will perform 16-bit transfers.

Chassis Plans 2-3

ISA/PCI Reference CBI/CGI Technical Reference

IO16# (I)

I/O 16-bit Chip Select (IO16#) signals the system board that the present data transfer is a 16-bit,
1 wait-state, I/O cycle. It is derived from an address decode. IO16# is active low and should be
driven with an open collector or tri-state driver capable of sinking 20 mAmps.

IOCHK# (I)

I/O Channel Check (IOCHK#) provides the system board with parity (error) information about
memory or devices on the I/O channel. When this signal is active, it indicates an uncorrectable
system error.

IORC# (I/O)

I/O Read (IORC#) instructs an I/O device to drive its data onto the data bus. It may be driven by
the system microprocessor or DMA controller, or by a microprocessor or DMA controller
resident on the I/O channel. This signal is active low.

IOWC# (I/O)

I/O Write (IOWC#) instructs an I/O device to read the data on the data bus. It may be driven by
any microprocessor or DMA controller in the system. This signal is active low.

IRQ[15::14], IRQ[12::9], IRQ[7::3] (I)

Interrupt Requests IRQ[15::14], IRQ[12::9] and IRQ[7::3] are used to signal the microprocessor
that an I/O device needs attention. The interrupt requests are prioritized, with IRQ[15::14] and
IRQ[12::9] having the highest priority (IRQ9 is the highest) and IRQ[7::3] having the lowest
priority (IRQ7 is the lowest). An interrupt request is generated when an IRQ line is raised from
low to high. The line must be held high until the microprocessor acknowledges the interrupt
request (Interrupt Service routine).

LA[23::17] (I/O)

These signals (unlatched) are used to address memory and I/O devices within the system.
They give the system up to 16MB of addressability. These signals are valid when BALE is high.
LA[23::17] are not latched during microprocessor cycles and therefore do not stay valid for the
whole cycle. Their purpose is to generate memory decodes for 1 wait-state memory cycles.
These decodes should be latched by I/O adapters on the falling edge of BALE. These signals
also may be driven by other microprocessors or DMA controllers that reside on the I/O channel.

M16# (I)

M16# Chip Select signals the system board if the present data transfer is a 1<N>wait-state, 16­bit, memory cycle. It must be derived from the decode of LA[23::17]. M16# should be driven
with an open collector or tri-state driver capable of sinking 20 mAmps.

Master16# (I)

Master16# is used with a DRQ line to gain control of the system. A processor or DMA controller
on the I/O channel may issue a DRQ to a DMA channel in cascade mode and receive a DAK#.
Upon receiving the DAK#, an I/O microprocessor may pull Master16# low, which will allow it to
control the system address, data, and control lines (a condition known as tri-state). After
Master16# is low, the I/O microprocessor must wait one system clock period before driving the
address and data lines, and two clock periods before issuing a Read or Write command. If this
signal is held low for more than 15<N>microseconds, system memory may be lost because of a
lack of refresh.

Chassis Plans2-4

ISA/PCI ReferenceCBI/CGI Technical Reference

NOWS# (I)

The No Wait State (NOWS#) signal tells the microprocessor that it can complete the present bus
cycle without inserting any additional wait cycles. In order to run a memory cycle to a 16-bit
device without wait cycles, NOWS# is derived from an address decode gated with a Read or
Write command. In order to run a memory cycle to an 8-bit device with a minimum of two wait
states, NOWS# should be driven active on system clock after the Read or Write command is
active gated with the address decode for the device. Memory Read and Write commands to a
8-bit device are active on the falling edge of the system clock. NOWS# is active low and should
be driven with an open collector or tri-state driver capable of sinking 20 mAmps.

OSC (O)

Oscillator (OSC) is a high-speed clock with a 70-nanosecond period (14.31818 MHz). This
signal is not synchronous with the system clock. It has a 50% duty cycle.

REFRESH# (I/O)

The REFRESH# signal is used to indicate a refresh cycle and can be driven by a micropro­cessor on the I/O channel.

RESDRV (O)

Reset Drive (RESDRV) is used to reset or initialize system logic at power-up time or during a
low line-voltage outage. This signal is active high.

SA[19::0] (I/O)

Address bits SA[19::0] are used to address memory and I/O devices within the system. These
twenty address lines, in addition to LA[23::17], allow access of up to 16MB of memory.
SA[19::0] are gated on the system bus when BALE is high and are latched on the falling edge of
BALE. These signals are generated by the microprocessor or DMA Controller. They also may
be driven by other microprocessors or DMA controllers that reside on the I/O channel.

SBHE# (I/O)

System Bus High Enable (SBHE#) indicates a transfer of data on the upper byte of the data bus,
D[15::8]. 16-bit devices use SBHE# to condition data bus buffers tied to D[15::8].

SMRDC# (O), MRDC# (I/O)

These signals instruct the memory devices to drive data onto the data bus. SMRDC# is active
only when the memory decode is within the low 1MB of memory space. MRDC# is active on all
memory read cycles. MRDC# may be driven by any microprocessor or DMA controller in the
system. SMRDC is derived from MRDC# and the decode of the low 1MB of memory. When a
microprocessor on the I/O channel wishes to drive MRDC#, it must have the address lines valid
on the bus for one system clock period before driving MRDC# active. Both signals are active
low.

SMWTC# (O), MWTC# (I/O)

These signals instruct the memory devices to store the data present on the data bus. SMWTC#
is active only when the memory decode is within the low 1MB of the memory space. MWTC# is
active on all memory write cycles. MWTC# may be driven by any microprocessor or DMA
controller in the system. SMWTC# is derived from MWTC# and the decode of the low 1MB of
memory. When a microprocessor on the I/O channel wishes to drive MWTC#, it must have the
address lines valid on the bus for one system clock period before driving MWTC# active. Both
signals are active low.

Chassis Plans 2-5

ISA/PCI Reference CBI/CGI Technical Reference

T-C (O)

Terminal Count (T-C) provides a pulse when the terminal count for any DMA channel is reached.

Chassis Plans2-6

I/O ADDRESS MAP*

ISA/PCI ReferenceCBI/CGI Technical Reference

Hex Range Device

I

NTERRUPT

A

SSIGNMENTS*

000-01F
020-03F
040-05F
060-06F
070-07F
080-09F
0A0-0BF
0C0-0DF
0F0
0F1
0F8-0FF

1F0-1F8
200-207
278-27F
2F8-2FF
300-31F
360-36F
378-37F
380-38F
3A0-3AF
3B0-3BF
3C0-3CF
3D0-3DF
3F0-3F7
3F8-3FF

Interrupt Description

DMA Controller 1
Interrupt Controller 1, Master
Timer
8042 (Keyboard)
Real-time Clock, NMI (non-maskable interrupt) Mask
DMA Page Register
Interrupt Controller 2
DMA Controller 2
Clear Math Coprocessor Busy
Reset Math Coprocessor
Math Coprocessor

Fixed Disk
Game I/O
Parallel Printer Port 2
Serial Port 2
Prototype Card
Reserved
Parallel Printer Port 1
SDLC, Bisynchronous 2
Bisynchronous 1
Monochrome Display and Printer Adapter
Reserved
Color/Graphics Monitor Adapter
Diskette Controller
Serial Port 1

IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ8
IRQ9
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15

Timer Output 0
Keyboard (Output Buffer Full)
Interrupt 8 through 15
Serial Port 2
Serial Port 1
Parallel Port 2
Diskette Controller
Parallel Port 1
Real-time Clock Interrupt
Software Redirected to INT 0AH (IRQ2)
Unassigned
Unassigned
PS/2 Mouse
Coprocessor
Fixed Disk Controller
Unassigned (may be assigned by the system to the
secondary IDE)

* These are typical parameters, which may not reflect your current system.

Chassis Plans 2-7

ISA/PCI Reference CBI/CGI Technical Reference

PCI LOCAL BUS
O

VERVIEW

The PCI (Peripheral Component Interconnect) Local Bus is a high performance, 32-bit or
64-bit bus with multiplexed address and data lines. It is intended for use as an inter­connect mechanism between highly integrated peripheral controller components,
peripheral add-in boards and processor/memory systems.

The "local bus" moves peripheral functions with high bandwidth requirements closer to
the system’s processor bus and can produce substantial performance gains with graphical
user interfaces (GUIs) and other high bandwidth functions (i.e., full motion video, SCSI,
LANs, etc.).

The PCI Local Bus accommodates future system requirements and is applicable across
multiple platforms and architectures.

The PCI component and add-in card interface is processor independent, enabling an
efficient transition to future processor generations, by bridges or by direct integration,
and use with multiple processor architectures. Processor independence allows the PCI
Local Bus to be optimized for I/O functions, enables concurrent operation of the local
bus with the processor/memory subsystem, and accommodates multiple high perfor­mance peripherals in addition to graphics. Movement to enhanced video and multimedia
displays and other high bandwidth I/O will continue to increase local bus bandwidth
requirements. A transparent 64-bit extension of the 32-bit data and address buses is
defined, doubling the bus bandwidth and offering forward and backward compatibility of
32-bit (132MB/s peak) and 64-bit (264MB/s peak) PCI Local Bus peripherals.

Chassis Plans2-8

ISA/PCI ReferenceCBI/CGI Technical Reference

PCI LOCAL BUS
S

IGNAL DEFINITION

The PCI interface requires a minimum of 47 pins for a target-only device and 49 pins for
a master to handle data and addressing, interface control, arbitration and system
functions. The diagram below shows the pins in functional groups, with required pins on
the left side and optional pins on the right side.

Required Pins:

Address & Data:

AD[31::00]

C/BE[3::0]#

PAR

Interface Control:

FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
IDSEL

Error Reporting:

PERR#
SERR#

Arbitration
(masters only):

REQ#
GNT#

System:

CLK
RST#

PCI

COMPLIANT

DEVICE

Optional Pins:

64-bit Extension

AD[63::32]

C/BE[7::4]#

PAR 64
REQ64#
ACK64#

Interface Control:

LOCK#
INTA#
INTB#
INTC#
INTD#

Cache Support:

SBO#
SDONE

JTAG (IEEE 1149.1):

TDI
TDO
TCK
TMS
TRST#

PCI Pin List

Chassis Plans 2-9

ISA/PCI Reference CBI/CGI Technical Reference

PCI LOCAL BUS
P

IN NUMBERING

Component Side
of Board

5-volt/32-bit PCI Connector

Chassis Plans2-10

ISA/PCI ReferenceCBI/CGI Technical Reference

PCI LOCAL BUS
P

IN ASSIGNMENTS

The PCI Local Bus pin assignments shown below are for the PCI option slots on the
backplane.

The PCI Local Bus specifies both 5-volt and 3.3-volt signaling environments. The
following bus pin assignments are for the 5-volt connector. The 3.3-volt connector bus
pin assignments are the same with the following exceptions:

* The pins noted as +V (I/O) are +5 volts or +3.3 volts, depending on which

connector is being used.

† Pins B12, B13, A12 and A13 are Gnd (ground) on the 5-volt connector, but

are Connector Keys on the 3.3-volt connector.

†† Pin B49 is Gnd (ground) on the 5-volt connector, but is M66EN on the 3.3-

volt connector.

††† Pins B50, B51, A50 and A51 are Connectors Keys on the 5-volt connector,

but are Gnd (ground) on the 3.3-volt connector.

I/O Pin Signal Name I/O Pin Signal Name

B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35

-12V
TCK
Gnd
TDO
+5V
+5V
INTB#
INTD#
PRSNT1#
Reserved
PRSNT2#
Gnd

†

Gnd †
Reserved
Gnd
CLK
Gnd
REQ#
+V (I/O) *
AD31
AD29
Gnd
AD27
AD25
+3.3V
C/BE3#
AD23
Gnd
AD21
AD19
+3.3V
AD17
C/BE2#
Gnd
IRDY#

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35

TRST#
+12V
TMS
TDI
+5V
INTA#
INTC#
+5V
Reserved
+V (I/O) *
Reserved
Gnd

†

Gnd †
Reserved
RST#
+V (I/O) *
GNT#
Gnd
Reserved
AD30
+3.3V
AD28
AD26
Gnd
AD24
IDSEL
+3.3V
AD22
AD20
Gnd
AD18
AD16
+3.3V
FRAME#
Gnd

32-bit connector start

Chassis Plans 2-11

ISA/PCI Reference CBI/CGI Technical Reference

PCI LOCAL BUS
P

IN ASSIGNMENTS

(

CONTINUED)

I/O Pin Signal Name I/O Pin Signal Name

B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49

B50
B51

B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62

+3.3V
DEVSEL#
Gnd
LOCK#
PERR#
+3.3V
SERR#
+3.3V
C/BE1#
AD14
Gnd
AD12
AD10
Gnd

††

Connector Key
Connector Key †††

AD8
AD7
+3.3V
AD5
AD3
Gnd
AD1
+V (I/O) *
ACK64#
+5V
+5V

†††

A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49

A50
A51

A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62

TRDY#
Gnd
STOP#
+3.3V
SDONE
SBO#
Gnd
PAR
AD15
+3.3V
AD13
AD11
Gnd
AD9

Connector Key †††
Connector Key †††

C/BE0#
+3.3V
AD6
AD4
Gnd
AD2
AD0
+V (I/O) *
REQ64#
+5V
+5V 32-bit connector end

5-volt key
5-volt key

Chassis Plans2-12

ISA/PCI ReferenceCBI/CGI Technical Reference

PCI LOCAL BUS
P

IN ASSIGNMENTS

(

CONTINUED)

The following pin assignments apply only to backplanes with 64-bit PCI option slots.

I/O Pin Signal Name I/O Pin Signal Name

Connector Key
Connector Key

B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82
B83
B84
B85
B86
B87
B88
B89
B90
B91
B92
B93
B94

Reserved
Gnd
C/BE6#
C/BE4#
Gnd
AD63
AD61
+V (I/O) *
AD59
AD57
Gnd
AD55
AD53
Gnd
AD51
AD49
+V (I/O) *
AD47
AD45
Gnd
AD43
AD41
Gnd
AD39
AD37
+V (I/O) *
AD35
AD33
Gnd
Reserved
Reserved
Gnd

Connector Key
Connector Key

A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
A83
A84
A85
A86
A87
A88
A89
A90
A91
A92
A93
A94

Gnd
C/BE7#
C/BE5#
+V (I/O) *
PAR 64
AD62
Gnd
AD60
AD58
Gnd
AD56
AD54
+V (I/O) *
AD52
AD50
Gnd
AD48
AD46
Gnd
AD44
AD42
+V (I/O) *
AD40
AD38
Gnd
AD36
AD34
Gnd
AD32
Reserved
Gnd
Reserved

64-bit spacer
64-bit spacer

64-bit connector start

64-bit connector end

Chassis Plans 2-13

ISA/PCI Reference CBI/CGI Technical Reference

PCI LOCAL BUS
S

IGNAL

D

ESCRIPTIONS

The PCI Local Bus signals are described below and may be categorized into the
following functional groups:

• System Pins

• Address and Data Pins

• Interface Control Pins

• Arbitration Pins (Bus Masters Only)

• Error Reporting Pins

• Interrupt Pins (Optional)

• Cache Support Pins (Optional)

• 64-Bit Bus Extension Pins (Optional)

• JTAG/Boundary Scan Pins (Optional)

A # symbol at the end of a signal name indicates that the active state occurs when the
signal is at a low voltage. When the # symbol is absent, the signal is active at a high
voltage.

The following are descriptions of the PCI Local Bus signals.

ACK64# (optional)

Acknowledge 64-bit Transfer, when actively driven by the device that has positively decoded its
address as the target of the current access, indicates the target is willing to transfer data using
64bits. ACK64# has the same timing as DEVSEL#.

AD[31::00]

Address and Data are multiplexed on the same PCI pins. A bus transaction consists of an
address phase followed by one or more data phases. During the address phase, AD[31::00]
contain a physical address (32 bits). During data phases, AD[07::00] contain the least signif­icant byte (lsb) and AD[31::24] contain the most significant byte (msb).

AD[63::32] (optional)

Address and Data are multiplexed on the same pins and provide 32additional bits. During an
address phase (when using the DAC command and when REQ64# is asserted), the upper
32bits of a 64-bit address are transferred; otherwise, these bits are reserved but are stable and
indeterminate. During a data phase, an additional 32bits of data are transferred when REQ64#
and ACK64# are both asserted.

C/BE[3::0]#

Bus Command and Byte Enables are multiplexed on the same PCI pins. During the address
phase of a transaction, these pins define the bus command; during the data phase they are
used as byte enables. The byte enables are valid for the entire data phase and determine
which byte lanes carry meaningful data. C/BE0# applies to byte0 (lsb) and C/BE3# applies to
byte 3 (msb).

Chassis Plans2-14

ISA/PCI ReferenceCBI/CGI Technical Reference

C/BE[7::4]# (optional)

Bus Command and Byte Enables are multiplexed on the same pins. During an address phase
(when using the DAC command and when REQ64# is asserted), the actual bus command is
transferred on C/BE[7::4]#; otherwise, these bits are reserved and indeterminate. During a data
phase, C/BE[7::4]# are byte enables indicating which byte lanes carry meaningful data when
REQ64# and ACK64# are both asserted. C/BE4# applies to byte4 and C/BE7# applies to
byte7.

CLK

Clock provides timing for all transactions on PCI and is an input to every PCI device.

DEVSEL#

Device Select, when actively driven, indicates that the driving device has decoded its address
as the target of the current access. As an input, DEVSEL# indicates whether any device on the
bus has been selected.

FRAME#

Cycle Frame is an interface control pin which is driven by the current master to indicate the
beginning and duration of an access. When FRAME# is asserted, data transfers continue;
when it is deasserted, the transaction is in the final data phase.

GNT#

Grant indicates to the agent that access to the bus has been granted. This is a point to point
signal. Every master has its own GNT#.

IDSEL

Initialization Device Select is used as a chip select during configuration read and write transac­tions.

INTA#, INTB#, INTC#, INTD# (optional)

Interrupts on PCI are optional and defined as "level sensitive," asserted low (negative true),
using open drain output drivers. PCI defines one interrupt for a single function and up to four
interrupt lines for a multi-function device or connector.

Interrupt A is used to request an interrupt. For a single function device, only INTA# may be
used, while the other three interrupt lines have no meaning.

Interrupt B, Interrupt C and Interrupt D are used to request additional interrupts and only have
meaning on a multi-function device.

IRDY#

Initiator Ready indicates the initiating agent’s (bus master’s) ability to complete the current data
phase of the transaction. IRDY# is used in conjunction with TRDY#. During a write, IRDY#
indicates that valid data is present on AD[31::0]. During a read, it indicates that the master is
prepared to accept data.

LOCK#

Lock indicates an operation that may require multiple transactions to complete. When LOCK#
is asserted, non-exclusive transactions may proceed to an address that is not currently locked.

Chassis Plans 2-15

ISA/PCI Reference CBI/CGI Technical Reference

PAR

Parity is even parity across AD[31::00] and C/BE[3::0]#. Parity generation is required by all PCI
agents. The master drives PAR for address and write data phases; the target drives PAR for
read data phases.

PAR64 (optional)

Parity Upper DWORD is the even parity bit that protects AD[63::32] and C/BE[7::4]#. The
master drives PAR64 for address and write data phases; the target drives PAR64 for read data
phases.

PERR#

Parity Error is for the reporting of data parity errors during all PCI transactions except a Special
Cycle. There are no special conditions when a data parity error may be lost or when reporting
of an error may be delayed.

PRSNT1# and PRSNT2#

PRSNT1# and PRSNT2# are related to the connector only, not to other PCI components. They
are used for two purposes: indicating that a board is physically present in the slot and providing
information about the total power requirements of the board.

REQ#

Request indicates to the arbiter that this agent desires use of the bus. This is a point to point
signal. Every master has its own REQ#.

REQ64# (optional)

Request 64-bit Transfer, when actively driven by the current bus master, indicates it desires to
transfer data using 64 bits. REQ64# has the same timing as FRAME#. REQ64# has meaning
at the end of reset.

RST#

Reset is used to bring PCI-specific registers, sequencers and signals to a consistent state.

SBO# (optional)

Snoop Backoff is an optional cache support pin which indicates a hit to a modified line when
asserted. When SBO# is deasserted and SDONE is asserted, it indicates a "clean" snoop
result.

SDONE (optional)

Snoop Done is an optional cache support pin which indicates the status of the snoop for the
current access. When deasserted, it indicates the result of the snoop is still pending. When
asserted, it indicates the snoop is complete.

SERR#

System Error is for reporting address parity errors, data parity errors on the Special Cycle
command, or any other system error where the result will be catastrophic. If an agent does not
want a non-maskable interrupt (NMI) to be generated, a different reporting mechanism is
required.

Chassis Plans2-16

ISA/PCI ReferenceCBI/CGI Technical Reference

STOP#

Stop indicates that the current target is requesting the master to stop the current transaction.

TCK (optional)

Test Clock is used to clock state information and test data into and out of the device during
operation of the TAP (Test Access Port).

TDI (optional)

Test Data Input is used to serially shift test data and test instructions into the device during TAP
(Test Access Port) operation.

TDO (optional)

Test Data Output is used to serially shift test data and test instructions out of the device during
TAP (Test Access Port) operation.

TMS (optional)

Test Mode Select is used to control the state of the TAP (Test Access Port) controller in the
device.

TRDY#

Target Ready indicates the target agent’s (selected device’s) ability to complete the current data
phase of the transaction. TRDY# is used in conjunction with IRDY#. During a read, TRDY#
indicates that valid data is present on AD[31::00]. During a write, it indicates that the target is
prepared to accept data.

TRST# (optional)

Test Reset provides an asynchronous initialization of the TAP controller. This signal is optional
in the IEEE Standard Test Access Port and Boundary Scan Architecture.

Chassis Plans 2-17

ISA/PCI Reference CBI/CGI Technical Reference

PICMG EDGE
C

ONNECTOR PIN

A

SSIGNMENTS

The pin assignments shown below are for the PICMG portion of the edge connector on
the processor board. These pin assignments match those of the PICMG connector of the
processor slot on the backplane.

I/O Pin Signal Name I/O Pin Signal Name

B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49

-12V
NC
Gnd
NC
+5V
+5V
INTB#
INTD#
REQ3#
REQ1#
GNT3#
Gnd
Gnd
CLKS0
Gnd
CLKS1
Gnd
REQ0#
+5V
AD31
AD29
Gnd
AD27
AD25
BKPL3.3V
C/BE3#
AD23
Gnd
AD21
AD19
NC
AD17
C/BE2#
Gnd
IRDY#
NC
DEVSEL#
Gnd
LOCK#
PERR#
NC
SERR#
NC
C/BE1#
AD14
Gnd
AD12
AD10
M66EN

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49

NC
+12V
NC
NC
+5V
INTA#
INTC#
+5V
CLKS2
+5V
CLKS3
Gnd
Gnd
GNT1#
RST#
+5V
GNT0#
Gnd
REQ2#
AD30
NC
AD28
AD26
Gnd
AD24
GNT2#
NC
AD22
AD20
Gnd
AD18
AD16
NC
FRAME#
Gnd
TRDY#
Gnd
STOP#
NC
SDONE
SBO#
Gnd
PAR
AD15
NC
AD13
AD11
Gnd
AD9

32-bit connector start

Chassis Plans2-18

PICMG EDGE
C

ONNECTOR PIN

A

SSIGNMENTS

(

CONTINUED)

ISA/PCI ReferenceCBI/CGI Technical Reference

I/O Pin Signal Name I/O Pin Signal Name

B50
B51

B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62

Connector Key
Connector Key

AD8
AD7
NC
AD5
AD3
Gnd
AD1
+5V
ACK64#
+5V
+5V

A50
A51

A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62

Connector Key
Connector Key

C/BE0#
NC
AD6
AD4
Gnd
AD2
AD0
+5V
REQ64#
+5V
+5V 32-bit connector end

Chassis Plans 2-19

ISA/PCI Reference CBI/CGI Technical Reference

PICMG EDGE
C

ONNECTOR PIN

A

SSIGNMENTS

(

CONTINUED)

The following pin assignments apply only to SBCs with 64-bit PICMG connectors.

I/O Pin Signal Name I/O Pin Signal Name

Connector Key
Connector Key

B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82
B83
B84
B85
B86
B87
B88
B89
B90
B91
B92
B93
B94

NC
Gnd
C/BE6#
C/BE4#
Gnd
AD63
AD61
+5V
AD59
AD57
Gnd
AD55
AD53
Gnd
AD51
AD49
+5V
AD47
AD45
Gnd
AD43
AD41
Gnd
AD39
AD37
+5V
AD35
AD33
Gnd
NC
NC
Gnd

Connector Key
Connector Key

A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
A83
A84
A85
A86
A87
A88
A89
A90
A91
A92
A93
A94

Gnd
C/BE7#
C/BE5#
+5V
PAR 64
AD62
Gnd
AD60
AD58
Gnd
AD56
AD54
+5V
AD52
AD50
Gnd
AD48
AD46
Gnd
AD44
AD42
+5V
AD40
AD38
Gnd
AD36
AD34
Gnd
AD32
NC
Gnd
NC

64-bit spacer
64-bit spacer

64-bit connector start

64-bit connector end

Copyright 2003 by Trenton Technology Inc. All rights reserved.

Chassis Plans2-20

System BIOSCBI/CGI Technical Reference

Chapter 3 System BIOS

BIOS OPERATION Sections 3 through 8 of this manual describe the operation of the American Megatrends

AMIBIOS and the AMIBIOS Setup Utility. Refer to Running AMIBIOS Setup later in
this chapter for standard Setup screens, options and defaults. The available Setup
screens, options and defaults may vary if you have a custom BIOS.

When the system is powered on, AMIBIOS performs the Power-On Self Test (POST)
routines. These routines are divided into two phases:

1) System Test and Initialization. Test and initialize system boards for
normal operations.

2) System Configuration Verification. Compare defined configuration with
hardware actually installed.

If an error is encountered during the diagnostic tests, the error is reported in one of two
different ways. If the error occurs before the display device is initialized, a series of
beeps is transmitted. If the error occurs after the display device is initialized, the error
message is displayed on the screen. See BIOS Errors later in this section for more infor­mation on error handling.

The following are some of the Power-On Self Tests (POSTs) which are performed when
the system is powered on:

• CMOS Checksum Calculation

• Keyboard Controller Test

• CMOS Shutdown Register Test

• 8254 Timer Test

• Memory Refresh Test

• Display Memory Read/Write Test

• Display Type Verification

• Entering Protected Mode

• Memory Size Calculation

• Conventional and Extended Memory Test

• DMA Controller Tests

• Keyboard Test

• System Configuration Verification and Setup

_______________________________________________________________________

NOTE: When you perform a warm boot by pressing <Ctrl> + <Alt> + <Del>, all
memory tests are bypassed.
_______________________________________________________________________

AMIBIOS checks system and cache memory and reports them on both the initial
AMIBIOS screen and the AMIBIOS System Configuration screen which appears after
POST is completed. AMIBIOS attempts to initialize the peripheral devices by verifying

Chassis Plans 3-1

System BIOS CBI/CGI Technical Reference

the validity of the system setup information stored in the system CMOS RAM. (See
Running AMIBIOS Setup later in this chapter.) If AMIBIOS detects a fault, the screen
displays the error condition(s) which has/have been detected. If no errors are detected,
AMIBIOS attempts to load the system from any bootable device, such as a floppy disk or
hard disk.

Normally, the only POST routine visible on the screen is the memory test. The following
screen displays when the system is powered on:

AMIBIOS (C)1998 American Megatrends Inc.
TRENTON Technology Inc.

Hit DEL if you want to run SETUP

Initial Power-On Screen

You have two options:

• Press <Del> to access the AMIBIOS Setup Utility.

This option allows you to change various system parameters such as date
and time, disk drives, etc. The Running AMIBIOS Setup section of this
manual describes the options available.

You may be requested to enter a password before gaining access to the
AMIBIOS Setup Utility. (See Password Entry later in this section.)

If you enter the correct password or no password is required, the AMIBIOS
Setup Main Menu displays. (See Running AMIBIOS Setup later in this
section.)

• Allow the bootup process to continue without invoking the AMIBIOS Setup
Utility.

In this case, after AMIBIOS loads the system, you may be requested to enter
a password. (See Password Entry later in this section.)

Once the POST routines complete successfully, a screen displays showing the current
configuration of your system, including processor type, base and extended memory
amounts, floppy and hard drive types, display type and peripheral ports.

In systems with more than 1MB, AMIBIOS reports 384KB less RAM than it finds,
because it accounts for the address space between 640K and 1024K which is unavailable
to DOS. This space is used for video RAM, video BIOS, system BIOS and adapter
ROMs.

Chassis Plans3-2

System BIOSCBI/CGI Technical Reference

Password Entry

The system may be configured so that the user is required to enter a password each time
the system boots or whenever an attempt is made to enter AMIBIOS Setup. The
password function may also be disabled so that the password prompt does not appear
under any circumstances.

The Password Check option in the Advanced CMOS Setup program allows you to
specify when the password prompt displays: Always or only when Setup is attempted.
The supervisor and user passwords may be changed using the Change Supervisor
Password and Change User Password options on the AMIBIOS Setup Main Menu. If
the passwords are null, the password prompt does not display at any time. A more
detailed description of the password setup function may be found in the Running
AMIBIOS Setup section later in this chapter.

When password checking is enabled, the following password prompt displays:

Enter CURRENT Password:

Type the password and press <Enter>.
_______________________________________________________________________

NOTE: The null password is the system default and is in effect if a password has not
been assigned or if the CMOS has been corrupted. In this case, the password prompt
does not display. To set up passwords, you may use the Change Supervisor Password
and Change User Password options on the AMIBIOS Setup Main Menu. (See Running
AMIBIOS Setup later in this chapter.)
_______________________________________________________________________

If an incorrect password is entered, the following screen displays:

Enter CURRENT Password: X
Enter CURRENT Password:

Chassis Plans 3-3

System BIOS CBI/CGI Technical Reference

You may try again to enter the correct password. If you enter the password incorrectly
three times, the system responds in one of two different ways, depending on the value
specified in the Password Check option on the Advance CMOS Setup screen:

1) If the Password Check option is set to Setup, the system does not let you
enter Setup, but does continue the booting process. You must reboot the
system manually to retry entering the password.

2) If the Password Check option is set to Always, the system locks and you
must reboot. After rebooting, you will be requested to enter the password.

Once the password has been entered correctly, you are allowed to continue.

BIOS Errors

If an error is encountered during the diagnostic checks performed when the system is
powered on, the error is reported in one of two different ways:

1) If the error occurs before the display device is initialized, a series of beeps is
transmitted.

2) If the error occurs after the display device is initialized, the screen displays
the error message. In the case of a non-fatal error, a prompt to press the
<F1> key may also appear on the screen.

Explanations of the beep codes and BIOS error messages may be found in Appendix A -
BIOS Messages.

As the POST routines are performed, test codes are presented on Port 80H. These codes
may be helpful as a diagnostic tool and are listed in Appendix A - BIOS Messages.

If certain non-fatal error conditions occur, you are requested to run the AMIBIOS Setup
Utility. The error messages are followed by this screen:

AMIBIOS (C)1998 American Megatrends, Inc.
TRENTON Technology Inc.

RUN SETUP UTILITY
Press F1 to Resume

Press <F1>. You may be requested to enter a password before gaining access to the
AMIBIOS Setup Utility. (See Password Entry earlier in this section.)

If you enter the correct password or no password is required, the AMIBIOS Setup Utility
Main Menu displays.

Chassis Plans3-4

System BIOSCBI/CGI Technical Reference

RUNNING
AMIBIOS S

ETUP

AMIBIOS Setup keeps a record of system parameters, such as date and time, disk drives,
display type and other user-defined parameters. The Setup parameters reside in the Read
Only Memory Basic Input/Output System (ROM BIOS) so that they are available each
time the system is turned on. AMIBIOS Setup stores the information in the comple­mentary metal oxide semiconductor (CMOS) memory. When the system is turned off, a
backup battery retains system parameters in the CMOS memory.

Each time the system is powered on, it is configured with these values, unless the CMOS
has been corrupted or is faulty. The AMIBIOS Setup Utility is resident in the ROM
BIOS so that it is available each time the computer is turned on. If, for some reason, the
CMOS becomes corrupted, the system is configured with the default values stored in this
ROM file.

As soon as the system is turned on, the power-on diagnostic routines check memory,
attempt to prepare peripheral devices for action, and offer you the option of pressing
<Del> to run AMIBIOS Setup.

If certain non-fatal errors occur during the Power-On Self Test (POST) routines which
are run when the system is turned on, you may be prompted to run AMIBIOS Setup by
pressing <F1>.

Chassis Plans 3-5

System BIOS CBI/CGI Technical Reference

AMIBIOS SETUP
U

TILITY MAIN

M

ENU

When you press <F1> in response to an error message received during the POST
routines or when you press the <Del> key to enter the AMIBIOS Setup Utility, the
following screen displays:

AMIBIOS HIFLEX SETUP UTILITY - VERSION X.XX

(C)1998 American Megatrends, Inc. All Rights Reserved

Standard CMOS Setup

Advanced CMOS Setup
Advanced Chipset Setup
Power Management Setup

PCI / Plug and Play Setup

Peripheral Setup

Auto-Detect Hard Disks

Change User Password

Auto Configuration with Optimal Settings

Auto Configuration with Fail Safe Settings

Standard CMOS Setup for changing time, date, hard disk type, etc.

ESC:Exit

Change Supervisor Password

Save Settings and Exit

Exit Without Saving

↑↓:Sel F2/F3:Color F10:Save & Exit

AMIBIOS S
U

TILITY OPTIONS

ETUP

AMIBIOS Setup Main Menu

When the AMIBIOS Setup Main Menu screen displays, you may continue to subscreens
designed to change parameters for each of the AMIBIOS Setup areas. Use the Down
Arrow key to highlight the desired option and press <Enter> to proceed to the appro­priate subscreen.

The AMIBIOS Setup Utility allows you to change system parameters to tailor your
system to your requirements. Various options which may be changed are listed below.
Further explanations of these options and available values may be found in later chapters
of this manual, as noted below.
_______________________________________________________________________

NOTE: Do not change the values for any option unless you understand the impact on
system operation. Depending on your system configuration, selection of other values
may cause unreliable system operation.
_______________________________________________________________________

Use the Down Arrow key to select the desired option. The following Setup areas are
available for modification:

• Select Standard CMOS Setup to make changes to Standard CMOS Setup

parameters as described in the Standard CMOS Setup chapter of this
manual. The following options may be modified:

• Date/Time

• Floppy Drive A:/Floppy Drive B: Types

Chassis Plans3-6

System BIOSCBI/CGI Technical Reference

• Primary Master and Slave Disk Types

• Secondary Master and Slave Disk Types

• Logical Block Address (LBA) Mode

• Block Mode

• PIO Mode

• 32Bit Mode

• Boot Sector Virus Protection

• Select Advanced CMOS Setup to make changes to Advanced CMOS

Setup parameters as described in the Advanced Setup chapter of this manual.
The following options may be modified:

• Quick Boot

• ARMD Emulation for IDE Devices

• 1st Boot Device

• 2nd Boot Device

• 3rd Boot Device

• Try Other Boot Devices

• Initialize I2O Devices

• Display Mode at Add-On ROM Init

• Floppy Access Control

• Hard Disk Access Control

• S.M.A.R.T. for Hard Disks

• BootUp Num-Lock

• PS/2 Mouse Support

• System Keyboard

• Primary Display

• Password Check

• Parity Check

• Boot to OS/2

• Internal Cache

• External Cache

• System BIOS Cacheable

• Video and Adapter ROM Shadow

Chassis Plans 3-7

System BIOS CBI/CGI Technical Reference

• Select Advanced Chipset Setup to make changes to Advanced Chipset

Setup parameters as described in the Advanced Setup chapter of this manual.
The following options may be modified:

• USB Function

• USB KB/Mouse Legacy Support

• Port 64/60 Emulation

• System Error Signal (SERR#)

• Parity Error Signal (PERR#)

• USWC Write Post

• BX Master Latency Timer

• Multi-Transaction Timer

• PCI1 to PCI0 Access

• DRAM Integrity Mode

• DRAM Refresh Rate

• Memory Hole

• Graphics Aperture Size *

• AGP Multi-Transaction Timer *

• AGP Low-Priority Timer *

• AGP System Error Signal (SERR) *

• AGP Parity Error Response *

• 8bit and 16bit I/O Recovery Time

• PIIX4 System Error Signal (SERR#)

• USB Passive Release Enable

• PIIX4 Passive Release

• PIIX4 Delayed Transaction

• TypeF DMA Buffer Controls 1 and 2

• DMA-0, DMA-1, DMA-2, DMA-3, DMA-5, DMA-6 and

DMA-7 Types

* Not available on BASIC models

• Select Power Management Setup to make changes to Power Management

Setup parameters as described in the Power Management Setup chapter of
this manual. The following options may be modified:

• ACPI Aware O/S

• Power Management/APM

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System BIOSCBI/CGI Technical Reference

• Power Button Function

• Green PC Monitor Power State

• Video Power Down Mode

• Hard Disk Power Down Mode

• Hard Disk Time Out

• Power Saving Type

• Standby/Suspend Timer Unit

• Standby Time Out

• Suspend Time Out

• Slow Clock Ratio

• Display Activity

• Device 0 through Device 8 Monitor

• Select PCI/Plug and Play Setup to make changes to PCI/Plug and Play

Setup parameters as described in the PCI/Plug and Play Setup chapter of
this manual. The following options may be modified:

• On Board LAN *

• On Board Video *

• On Board SCSI *

• Plug and Play Aware O/S

• PCI Latency Timer

• PCI VGA Palette Snoop

• PCI IDE BusMaster

• OffBoard PCI IDE Card

• OffBoard PCI IDE Primary and Secondary IRQs

• DMA Channels 0, 1, 3, 5, 6 and 7

• IRQ5 /IRQ9/IRQ10/IRQ11/IRQ15

• Reserved Memory Size and Address

* Not available on BASIC models

• Select Peripheral Setup to make changes to Peripheral Setup parameters as

described in the Peripheral Setup chapter of this manual. The following
options may be modified:

• OnBoard FDC

• OnBoard Serial Port 1

• OnBoard Serial Port 2

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• OnBoard Parallel Port

• Parallel Port Mode

• EPP Version

• Parallel Port IRQ

• Parallel Port DMA Channel

• OnBoard IDE

• Select Auto-Detect Hard Disks to have AMIBIOS automatically detect the

type and parameters of each hard drive if you have IDE drive(s). This
option is described later in this chapter.

• Select Change User Password to establish or change the password for the

user. This function is described later in this chapter.

• Select Change Supervisor Password to establish or change the password

for the supervisor. This function is described later in this chapter.

• Select Auto Configuration with Optimal Settings to load the Optimal

default settings. These settings are best-case values which should provide
the best performance characteristics. This function is described later in this
chapter.

• Select Auto Configuration with Fail Safe Settings to load the Fail Safe

default settings. These settings are more likely to configure a workable
computer, but they may not provide optimal performance. This function is
described later in this chapter.

• Select Save Settings and Exit to store your changes in the CMOS. The

CMOS checksum is calculated and written to the CMOS. Control is then
passed back to AMIBIOS and the booting process continues, using the new
CMOS values. This function is described later in this chapter.

• Select Exit Without Saving to pass control back to the AMIBIOS without

writing any changes to the CMOS. AMIBIOS continues with the booting
process. This function is described later in this chapter.

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System BIOSCBI/CGI Technical Reference

AUTO-DETECT
H

ARD DISKS

The Auto-Detect Hard Disks option allows you to have AMIBIOS automatically detect
the type of hard disk drive(s) in your system. The automatic detection functions only if
you have IDE drives. The parameters are reported on the Standard CMOS Setup screen.

AMIBIOS searches first for the primary master and slave hard disk drives, then for the
secondary master and slave drives. If it can access a drive, it reads the disk parameters.
It then searches the AMIBIOS drive type table for matching parameters to determine the
disk type and displays both the type and parameters on the screen. If no matching
parameters are found in the table, AMIBIOS specifies the type as "User" and fills in the
parameter values it found on the drive. If it cannot access the drive or if it is not an IDE
drive, AMIBIOS times out and specifies that the disk drive is "Not Installed."
_______________________________________________________________________

NOTE: The auto detect feature displays disk parameter values as established by the
drive manufacturer. If the drive has been formatted using any other values, accepting the
auto detect values will cause erratic behavior. You must either reformat the drive to meet
the manufacturer's specifications or use Standard CMOS Setup to enter parameters which
match the current format of the drive.
_______________________________________________________________________

If you do not want to accept the hard disk type and its associated parameters as reported
by AMIBIOS or if the drive is "Not Installed," you may use Standard CMOS Setup to set
up the correct parameters for the drive.

Once the parameters are correct for all of the drives, you may exit from the Standard
CMOS Setup screen and save the settings in the CMOS.

C

HANGE

P

ASSWORD

C

HANGE

S

UPERVISOR

P

ASSWORD

AMIBIOS Setup has an optional password feature which can be configured so that a
password must be entered each time the system boots or just when a user attempts to
enter AMIBIOS Setup. (See the Advanced CMOS Setup section of this manual for infor­mation on how to enable the Password Check option.)

The Change Supervisor Password and Change User Password options on the
AMIBIOS Setup Main Menu allow you to establish passwords, change the current
passwords or disable the password prompts by entering null passwords. The passwords
are stored in CMOS RAM.

The Change User Password function is accessible only if the supervisor password has
been established previously. If you have signed on under the user password, you cannot
change the supervisor password.
_______________________________________________________________________

NOTE: The null password is the system default and is in effect if a password has not
been assigned or if the CMOS has been corrupted. In this case, the "Enter CURRENT
Password" prompt is bypassed when you boot the system, and you must establish a new
password.
_______________________________________________________________________

If you select the Change Supervisor Password option, the following window displays:

Enter new supervisor password: _

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This is the message which displays before you have established a password or if the last
password entered was the null password. If a password has already been established, you
are asked to enter the current password before being prompted to enter the new
password.

Type the new password and press <Enter>. The password cannot exceed six (6)
characters in length. The screen does not display the characters as you type them.

After you have entered the new password, the following window displays:

Retype new supervisor password: _

Re-key the new password as described above.

If the password confirmation is miskeyed, AMIBIOS Setup displays the following
message:

Incorrect password, press any key to continue

No retries are permitted; you must restart the procedure from the AMIBIOS Setup Main
Menu.

If the password confirmation is entered correctly, the following message displays:

New supervisor password installed, press any key to continue

When you press any key, the screen returns to the AMIBIOS Setup Main Menu screen,
which allows you to save the password change or exit from Setup without saving the new
password. To save the new password in CMOS memory, be sure to select Save Settings
and Exit.

If you save the changes when you exit AMIBIOS Setup, the password is stored in CMOS
RAM. The next time the system boots, you are prompted for the password if the
password function is present and is enabled. (See Advanced CMOS Setup later in this
manual for an explanation of how to enable password checking.)
_______________________________________________________________________

NOTE: Be sure to keep a record of the new password each time it is changed. If you
forget it, use the Password Clear jumper to reset it to the default (null password). See the
Specifications chapter of this manual for details.
_______________________________________________________________________

C

HANGE USER

P

ASSWORD

The Change User Password function is accessible only if the supervisor password has
been established previously.

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D

ISABLING THE

P

ASSWORD(S)

A

UTO

C

ONFIGURATION

O

PTIONS

System BIOSCBI/CGI Technical Reference

The Change User Password option is similar in functionality to the Change Supervisor
Password and displays the same messages, except that "user" replaces "supervisor." If
you have signed on under the user password, you cannot change the supervisor
password.

To disable password checking so that the password prompt does not appear under any
circumstances, you may create null passwords using the Change Supervisor Password
and Change User Password functions by pressing <Enter> without typing in a new
password. You will be asked to confirm the password. Select <Enter> again and the
following message displays:

Supervisor password disabled, press any key to continue

When you press any key, the screen returns to the AMIBIOS Setup Main Menu, which
allows you to save the password change or exit from Setup without saving the null
password. To save the null password(s) in CMOS memory, be sure to select Save
Settings and Exit.

Each AMIBIOS Setup option has two default settings (Optimal and Fail Safe). These
settings can be applied to all AMIBIOS Setup options when you select the appropriate
auto configuration option from the AMIBIOS Setup Main Menu.

You can use these auto configuration options to quickly set the system configuration
parameters which should provide the best performance characteristics, or you can select
a group of settings which have a better chance of working when the system is having
configuration-related problems.

Auto Configuration with Optimal Settings

This option allows you to load the Optimal default settings. These settings are best-case
values which should provide the best performance characteristics. If CMOS RAM is
corrupted, the Optimal settings are loaded automatically.

If you select the Auto Configuration with Optimal Settings option, the following
window displays:

Load high performance settings (Y/N) ? N

You have two options:

• Press 'N' and <Enter> to leave the current values in effect.

• Press 'Y' and <Enter> to load the Optimal default settings.

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Auto Configuration with Fail Safe Settings

This option allows you to load the Fail Safe default settings when you cannot boot your
computer successfully. These settings are more likely to configure a workable computer.
They may not provide optimal performance, but are the most stable settings. You may
use this option as a diagnostic aid if your system is behaving erratically. Select the Fail
Safe settings and then try to diagnose the problem after the computer boots.

If you select the Auto Configuration with Fail Safe Settings option, the following
window displays:

Load failsafe settings (Y/N) ? N

You have two options:

• Press 'N' and <Enter> to leave the current values in effect.

• Press 'Y' and <Enter> to load the Fail Safe default settings.

S

AVE SETTINGS

AND EXIT

The features selected and configured in the Setup screens are stored in the CMOS when
this option is selected. The CMOS checksum is calculated and written to the CMOS.
Control is then passed back to the AMIBIOS and the booting process continues, using
the new CMOS values.

E

XIT WITHOUT

SAVING

If you select the SAVE SETTINGS AND EXIT option, the following window displays:

Save current settings and exit (Y/N) ? Y

You have two options:

• Press 'N' and <Enter> to return to the AMIBIOS Setup Main Menu.

• Press 'Y' and <Enter> to save the system parameters and continue with the

booting process.

This option passes control back to AMIBIOS without writing any changes to the CMOS.

If you select the EXIT WITHOUT SAVING option, the following window displays:

Quit without saving the current settings (Y/N) ? N

You have two options:

• Press 'N' and <Enter> to return to the AMIBIOS Setup Main Menu.

• Press 'Y' and <Enter> to continue with the booting process without saving

any system parameters.

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KEY CONVENTIONS Listed below is an explanation of the keys you may use for navigation and selection in

the AMIBIOS Setup Utility:

Key Task

<Esc>

<Tab>

Arrow keys

<Enter>

<F2>/<F3>

<F10>

Plus key (+), <PgUp>

Minus key (-), <PgDn>

Close the current operation and return to
the previous level.

Move to the next field.

Move to the next field in the desired
direction.

Select the current item.

Change background and foreground colors.

Save all changes made to Setup and exit
from the AMIBIOS Setup Utility.

Increment a value.

Decrement a value.

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Chapter 4 Standard CMOS Setup

Standard CMOS SetupCBI/CGI Technical Reference

STANDARD CMOS
S

ETUP

When you select Standard CMOS Setup from the AMIBIOS Setup Utility Main Menu,
the following Setup screen displays:

(C)1998 American Megatrends, Inc. All Rights Reserved

Date (mm/dd/yyyy): Mon Jan 01, 1996 Base Memory: 640 KB
Time (hh/mm/ss): 12:30:00 Extd Memory: 14 MB

Floppy Drive A: 1.44 MB 3-1/2
Floppy Drive B: Not Installed

Pri Master : Auto Off
Pri Slave : Auto Off
Sec Master : Auto Off
Sec Slave : Auto Off

Boot Sector Virus Protection Disabled

Month: Jan - Dec ESC:Exit

Day: 01 - 31 PgUp/PgDn:Modify

Year: 1901 - 2099 F2/F3:Color

AMIBIOS SETUP - STANDARD CMOS SETUP

LBA Blk PIO 32Bit

Type Size Cyln Head WPcom Sec Mode Mode Mode Mode

↑↓:Sel

S

TANDARD CMOS

S

ETUP OPTIONS

Standard CMOS Setup Screen

When you display the Standard CMOS Setup screen, the format is similar to the sample
shown above. If values display for all parameters, the Setup parameters have been
defined previously. The available values for each option are displayed at the bottom of
the screen when you tab or arrow into the field.
_______________________________________________________________________

NOTE: The values on this screen do not necessarily reflect the values appropriate for
your SBC. Refer to the explanations below for specific instructions about entering
correct information.
_______________________________________________________________________

The descriptions for the system options listed below show the values as they appear if
you have not yet run Standard CMOS Setup. Once values have been defined, they
display each time Standard CMOS Setup is run.

Date

The Setup screen displays the system option:

Date (mm/dd/yyyy): Mon Jan 01, 1996

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The Help window displays allowable settings:

Month : Jan - Dec
Day : 01 - 31
Year : 1901 - 2099

There are three fields for entering the date. Use the left and right arrow keys or the tab
key to move from one field to another; use the plus and minus (or PgUp and PgDn) keys
to scroll through the allowable values for the field. As you scroll through the month, day
or year field, the day of the week changes automatically to reflect the new date.

Time

The Setup screen displays the system option:

Time (hh/mm/ss): 00:00:00

The Help window displays:

Time is 24 hour format:­Hour:00-23 Minute:00-59 Second:00-59
(1:30AM = 01:30:00, 1:30PM = 13:30:00)

There are three fields for entering the time. Use the left and right arrow keys or the tab
key to move from one field to another; use the plus and minus (or PgUp and PgDn) keys
to scroll through the allowable values for the field.

Floppy Drive A:/Floppy Drive B:

The floppy drive type(s) in your system can be configured using these options.

The Setup screen displays the system options:

Floppy Drive A: 1.44 MB 3-1/2
Floppy Drive B: Not Installed

Available options are:

Not Installed
360 KB 5-1/4

1.2 MB 5-1/4
720 KB 3-1/2

1.44 MB 3-1/2

2.88 MB 3-1/2

The Not Installed option can be used for diskless work stations.

Primary and Secondary Hard Disk Drives

The SBC supports up to four hard disk drives through a primary and secondary controller
in a master/slave configuration. The primary controller uses I/O port addresses 1F0H

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Standard CMOS SetupCBI/CGI Technical Reference

through 1F7H, 3F6H and IRQ14. The secondary controller uses I/O port addresses 170H
through 177H, 376H and IRQ15.

The AMIBIOS enhanced IDE (EIDE) interface can support IDE Type 4 disk drives.
This EIDE interface allows disk drives greater than 528MB to be used.

The hard disk drives can be detected automatically by AMIBIOS (if they are IDE drives)
or can be defined manually by the user, as described below.

The Setup screen displays the system options:

Pri Master: Auto
Pri Slave: Auto
Sec Master: Auto
Sec Slave: Auto

The Help window displays:

1-46: Predefined types
USER: Enter parameters manually
AUTO: Set parameters automatically on each boot
CD-ROM: Use for ATAPI CD-ROM drives
Or press ENTER to set all HDD parameters automatically

To set up the hard disk drive parameter(s), use the plus (+) key or PgDn key to scroll
through the drive types to locate the correct type of disk drive(s) in your computer.

As you scroll through the disk types, the drive Type displays, along with values for size,
cylinders, heads, write precompensation and sectors. Available predefined hard disk
drive types are listed at the end of this section. If the parameters supplied by the
manufacturer of your disk drive do not match any of these preprogrammed drive types,
you may have AMIBIOS detect the drive type automatically (if it is an IDE drive), or
you may select the User drive type to enter the parameters manually as described below.

Set the drive type to CD-ROM to boot from a CD-ROM drive.

Not Installed is available for use as an option. This option can be used for diskless work
stations.

Automatic Detection of Drive Type

If any of the hard disks are IDE drives, AMIBIOS can automatically configure the drive
type by detecting the IDE drive parameters and reporting them on the Standard CMOS
Setup screen.

You may invoke automatic detection of IDE drives in one of three ways:

• Press Enter when the cursor is in the Type field. AMIBIOS detects the

drive type and parameters as requested. If the drive type is not defined in
the drive type table, this option displays User as the drive type and displays
the parameters which were detected by AMIBIOS. The detected drive type
values may then be saved in the CMOS.

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• Set the drive type to Auto to have AMIBIOS detect the drive type and

parameters automatically each time the system is booted up. This option
does not display the drive type on the Standard CMOS Setup screen, but
does display it on the System Configuration screen shown after a successful
bootup.

• Select the Auto-Detect Hard Disks option on the AMIBIOS Setup Main

Menu to have AMIBIOS automatically detect the type and parameters of
each hard drive and place the information into the Standard CMOS Setup
screen. The detected drive type values may then be saved in the CMOS.
This option is described in the Running AMIBIOS Setup section of the
System BIOS chapter of this manual.

_______________________________________________________________________

NOTE: The auto detect feature displays disk parameter values as established by the
drive manufacturer. If the drive has been formatted using any other values, accepting the
auto detect values will cause erratic behavior. You must either reformat the drive to meet
the manufacturer's specifications or use the User type to enter parameters which match
the current format of the drive.
_______________________________________________________________________

User-Defined Drive Types

If the parameters supplied by the manufacturer of your disk drive do not match any of the
preprogrammed drive types provided by AMIBIOS, you may enter the parameters
manually.

The user-defined parameters for each of the four drives may be different, which effec­tively allows four different user-definable hard disk types.

Scroll to the end of the drive type list to the User type. You can manually enter the Cyln,
Head, WPcom and Sec parameters. The Size parameter is automatically calculated and
displayed by the system based on the other parameters entered.

Use the arrow keys or tab key to move between fields. Once you have placed the cursor
in a field, type in the correct value.

The following explains the drive parameters which you must enter for a drive type which
is not in the list:

Type is the numeric designation for a drive with certain identification param­eters.

Cylinders (Cyln) is the number of disk cylinders found in the specified drive
type.

Heads (Head) is the number of disk heads found in the specified drive type.

Write Precompensation (WPcom) is the read delay circuitry which takes into

account the timing differences between the inner and outer edges of the surface
of the disk. The size of the sector gets progressively smaller as the track
diameter diminishes. Yet each sector must still hold 512 bytes. Write precom­pensation circuitry on the hard disk compensates for the physical difference in

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Standard CMOS SetupCBI/CGI Technical Reference

sector size by boosting the write current for sectors on inner tracks. This
parameter designates the track (cylinder) number where write precompensation
begins.

Sectors (Sec) designates the number of disk sectors per track.

Size is the formatted capacity of the drive (in megabytes) based on the following

formula:

# of heads x # of cylinders x # of sects/cyln x 512 bytes/sect

IDE Drive Type Setup Options

For each of the four hard disk drives which is an IDE drive, the following options are
also available for the drive:

Logical Block Addressing (LBA) Mode

This option allows you to enable IDE LBA (Logical Block Addressing) Mode for the
specified primary or secondary IDE drive. Data is accessed by block addresses rather
than by the traditional cylinder-head-sector format. This allows you to use drives larger
than 528MB.

If LBA Mode is set to On and is supported by the hard disk drive, and if the drive is
formatted, AMIBIOS enables LBA mode and translates the physical parameters of the
drive to logical parameters. If a hard disk drive which supports LBA mode and has a
capacity greater than 528MB was formatted with LBA mode disabled, AMIBIOS does
not enable LBA mode even if the LBA Mode parameter is set to On in Standard CMOS
Setup.

If LBA Mode is set to Off, AMIBIOS uses the physical parameters of the hard disk and
does not translate parameters. The operating system which uses the parameter table then
sees only 528MB of hard disk space even if the drive contains more than 528MB.

Available options are:

Off
On

Block (Blk) Mode

This option supports transfer of multiple sectors to and from the specified primary or
secondary IDE drive.

Block mode boosts IDE drive performance by increasing the amount of data transferred
during an interrupt. Block mode allows transfers of up to 64KB per interrupt, whereas
only 512 bytes of data can be transferred per interrupt if block mode is not used.

If Block Mode is set to On and is supported by the IDE drive, AMIBIOS enables multi­sector transfers. AMIBIOS sets the number of sectors to be transferred per interrupt to
the value returned by the "identify drive" command.

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Available options are:

Off
On

Programmed I/O (PIO) Mode

IDE PIO mode programs timing cycles between the IDE drive and the programmable
IDE controller. As the PIO mode increases, the cycle time decreases.

Set the PIO Mode option to Auto to have AMIBIOS select the PIO mode used by the
IDE drive being configured. If you select a specific value for the PIO mode, you must
make absolutely certain that you are selecting the PIO mode supported by the IDE drive
being configured.

Available options are:

Auto
03
14
25

32Bit Mode

B

OOT SECTOR

V

IRUS PROTECTION

Hard disk drives connected to the SBC via the ISA Bus transfer data 16 bits at a time.
An IDE drive on the PCI Local Bus can use a 32-bit data path.

If the 32Bit Mode parameter is set to On, AMIBIOS enables 32-bit data transfers. If the
host controller does not support 32-bit transfer, this feature must be disabled.

Available options are:

Off
On

This option allows you to request AMIBIOS to issue a warning when any program or
virus issues a Disk Format command or attempts to write to the boot sector of the hard
disk drive.

The Setup screen displays the system option:

Boot Sector Virus Protection Disabled

Available options are:

Disabled
Enabled

If the Boot Sector Virus Protection option is set to Enabled, the following message
displays when a write is attempted to the boot sector.

Boot Sector Write!!! Possible VIRUS: Continue (Y/N)?

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Select ‘Y’ or ‘N’ as appropriate. You may have to select ‘N’ several times to prevent the
boot sector write.

The following message displays if any attempt is made to format any cylinder, head or
sector of any hard disk drive via the BIOS INT 13 Hard Disk Drive Service:

Format!!! Possible VIRUS: Continue (Y/N)?

Select ‘Y’ or ‘N’ as appropriate. If you select ‘Y’ to continue, formatting proceeds
normally. If you do not want to continue formatting, you may have to select ‘N’ several
times, depending on how many retries are performed by the upper-level software. For
example, DOS does at least five retries before the Format utility is actually terminated.
_______________________________________________________________________

NOTE: You should not enable boot sector virus protection when formatting a hard
drive.
_______________________________________________________________________

The DOS hard disk Format utility does not use INT 13H function AH=05H to format the
hard disk. It only verifies the hard disk using the INT 13H Verify function (AH=04H).
The virus warning message is not displayed during DOS hard disk drive formatting.

Saving and Exiting

When you have made all desired changes to Standard CMOS Setup, press <Esc> to
return to the AMIBIOS Setup Main Menu screen.

You may make changes to other Setup options before exiting from AMIBIOS Setup.
You may save the changes you have just made or you may exit from Setup without
saving your changes.

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Chapter 5 Advanced Setup

Advanced SetupCBI/CGI Technical Reference

ADVANCED CMOS
S

ETUP

When you select Advanced CMOS Setup from the AMIBIOS Setup Utility Main
Menu, the following Setup screen displays:

(C)1998 American Megatrends, Inc. All Rights Reserved

Quick Boot Disabled
Pri Master ARMD Emulated as Auto
Pri Slave ARMD Emulated as Auto
Sec Master ARMD Emulated as Auto
Sec Slave ARMD Emulated as Auto
1st Boot Device 1st IDE-HDD
2nd Boot Device Floppy
3rd Boot Device ATAPI CDROM
Try Other Boot Devices Yes
Initialize I2O Devices Yes
Display Mode at Add-On ROM Init Force BIOS
Floppy Access Control Read-Write
Hard Disk Access Control Read-Write
S.M.A.R.T. for Hard Disks Disabled
BootUp Num-Lock On
PS/2 Mouse Support Enabled
System Keyboard Present
Primary Display VGA/EGA
Password Check Setup
Parity Check Enabled
Boot To OS/2 No
Internal Cache WriteBack
External Cache WriteBack
System BIOS Cacheable Enabled
C000,16k, Shadow Cached
C400,16k, Shadow Cached
C800,16k, Shadow Disabled
CC00,16k, Shadow Disabled
D000,16k, Shadow Disabled
D400,16k, Shadow Disabled
D800,16k, Shadow Disabled
DC00,16k, Shadow Disabled

AMIBIOS SETUP - ADVANCED CMOS SETUP

Available Options:

Disabled
Enabled

ESC:Exit
PgUp/PgDn:Modify
F2/F3:Color

↑↓:Sel

Advanced CMOS Setup Screen

When you display the Advanced CMOS Setup screen, the format is similar to the sample
shown above, except the screen displays only twenty options at a time. If you need to
change other options, use the down arrow key to locate the appropriate option. The
available values for each option are displayed on the right side of the screen when you
tab or arrow into the field.
_______________________________________________________________________

NOTE: The values on this screen do not necessarily reflect the values appropriate for
your SBC. Refer to the explanations below for specific instructions about entering
correct information.
_______________________________________________________________________

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ADVANCED CMOS
S

ETUP OPTIONS

The descriptions for the system options listed below show the values as they appear if
you have not yet run Advanced CMOS Setup. Once values have been defined, they
display each time Advanced CMOS Setup is run.

Quick Boot

This option allows you to have the AMIBIOS boot quickly when the computer is
powered on or go through more complete testing.

When this option is set to Disabled, AMIBIOS tests all system memory. It waits up to
40 seconds for a READY signal from the IDE hard disk drive. It waits for .5 seconds
after sending a RESET signal to the IDE drive to allow the drive time to get ready again.
It also checks whether the user has pressed the <Del> key and runs the AMIBIOS Setup
program if the key has been pressed.

If the option is set to Enabled, AMIBIOS checks only the first 1MB of system memory.
It does not wait up to 40 seconds for a READY signal from the IDE hard disk drive. If a
READY signal is not received immediately, AMIBIOS does not configure the drive. It
does not wait for .5 seconds after sending a RESET signal to the IDE drive to allow the
IDE drive time to get ready again.

If you have set your system up for a quick boot, you cannot run AMIBIOS Setup at
system boot, because there is no delay for the "Hit DEL if you want to run SETUP"
message.

The Setup screen displays the system option:

Quick Boot Disabled

Available options are:

Disabled
Enabled

Primary/Secondary Master/Slave ARMD Emulation

These options specify the type of ARMD (ATAPI Removable Media Device) emulation
used for a non-disk device attached to the specified IDE device.

If the option is set to Auto, AMIBIOS automatically determines the proper emulation
type and will support particular storage devices with ATAPI interface. The default
emulation types are Floppy for LS120, Hard Disk for MO and Hard Disk for IOMEGA
Zip.

The Setup screen displays the system options:

Pri Master ARMD Emulated as Auto
Pri Slave ARMD Emulated as Auto
Sec Master ARMD Emulated as Auto
Sec Slave ARMD Emulated as Auto

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Available options are:

Auto
Floppy
Hard Disk

1st Boot Device

This option specifies the device type of the first boot drive from which AMIBIOS
attempts to boot after AMIBIOS post routines complete.

The Setup screen displays the system option:

1st Boot Device 1st IDE-HDD

Available options are:

Disabled Floppy SCSI
1st IDE-HDD ARMD-FDD NETWORK
2nd IDE-HDD ARMD-HDD I2O
3rd IDE-HDD ATAPI CDROM
4th IDE-HDD

2nd Boot Device/ 3rd Boot Device

These options specify the device types of the second and third boot drives from which
AMIBIOS attempts to boot if it cannot boot from the device specified in the 1st Boot
Device option.

The Setup screen displays the system options:

2nd Boot Device Floppy
3rd Boot Device ATAPI CDROM

Available options are:

Disabled Floppy
1st IDE-HDD ARMD-FDD
2nd IDE-HDD ARMD-HDD
3rd IDE-HDD ATAPI CDROM
4th IDE-HDD

Try Other Boot Devices

If AMIBIOS cannot find a boot drive among any of the drives specified in the 1st Boot
Device, 2nd Boot Device and 3rd Boot Device options, this option allows you to have

AMIBIOS attempt to boot from any other drive in the system. If set to No, AMIBIOS
will try to boot only from the boot devices specified in the previous three options.

Chassis Plans 5-3

Advanced Setup CBI/CGI Technical Reference

The Setup screen displays the system option:

Try Other Boot Devices Yes

Available options are:

No
Ye s

Initialize I2O Devices

If this option is set to Ye s , AMIBIOS initializes any attached I2O devices (processors or
storage devices).

The Setup screen displays the system option:

Initialize I2O Devices Yes

Available options are:

No
Ye s

Display Mode At Add-On ROM Init

This option specifies the system display mode which is set at the time the AMIBIOS post
routines initialize an optional option ROM.

The Setup screen displays the system option:

Display Mode at Add-On ROM Init Force BIOS

Two options are available:

• Select Force BIOS to use the display mode currently being used by

AMIBIOS.

• Select Keep Current to use the current display mode.

Floppy Access Control

This option specifies the read/write access which is set when booting from a floppy
drive. This option is effective only if the device is accessed through the BIOS.

The Setup screen displays the system option:

Floppy Access Control Read-Write

Available options are:

Read-Write
Read-Only

Chassis Plans5-4

Advanced SetupCBI/CGI Technical Reference

Hard Disk Access Control

This option specifies the read/write access which is set when booting from a hard disk
drive. This option is effective only if the device is accessed through the BIOS.

The Setup screen displays the system option:

Hard Disk Access Control Read-Write

Available options are:

Read-Write
Read-Only

S.M.A.R.T. For Hard Disks

This option allows AMIBIOS to use the SMART (Self-Monitoring Analysis and
Reporting Technology) protocol for reporting server system information over a network.

The Setup screen displays the system option:

S.M.A.R.T. for Hard Disks Disabled

Available options are:

Disabled
Enabled

BootUp Num-Lock

This option enables you to turn off the Num-Lock option on the enhanced keyboard
when the system is powered on. If Num-Lock is turned off, the arrow keys on the
numeric keypad can be used, as well as the other set of arrow keys on the enhanced
keyboard.

The Setup screen displays the system option:

BootUp Num-Lock On

Available options are:

Off
On

PS/2 Mouse Support

This option indicates whether or not a mouse is supported. If it is set to Enabled,
AMIBIOS supports a PS/2-type mouse.

Chassis Plans 5-5

Advanced Setup CBI/CGI Technical Reference

The Setup screen displays the system option:

PS/2 Mouse Support Enabled

Available options are:

Disabled
Enabled

System Keyboard

This option indicates whether or not a keyboard is attached to the computer.

The Setup screen displays the system option:

System Keyboard Present

Available options are:

Absent
Present

Primary Display

This option specifies the type of display monitor in the system. The Absent option can
be used for network file servers.

The Setup screen displays the system option:

Primary Display VGA/EGA

Available options are:

Absent
VGA/EGA
CGA 40 x 25
CGA 80 x 25
Mono (monochrome)

Password Check

This option determines when a password is required for access to the system.

The Setup screen displays the system option:

Password Check Setup

Chassis Plans5-6

Advanced SetupCBI/CGI Technical Reference

Two options are available:

• Select Setup to have the password prompt appear only when an attempt is

made to enter the AMIBIOS Setup program.

• Select Always to have the password prompt appear each time the system is

powered on.

_______________________________________________________________________

NOTE:To disable password checking, a null password should be entered in the Change
Supervisor Password or Change User Password function in the AMIBIOS Setup Main

Menu. (See the Running AMIBIOS Setup section of this manual.) The null password is
the system default and is in effect if a password has not been assigned or if the CMOS
has been corrupted.
_______________________________________________________________________

Parity Check

This option allows you to enable parity checking of all system memory.

The Setup screen displays the system option:

Parity Check Enabled

Available options are:

Disabled
Enabled

Boot To OS/2

This option should be set to Ye s if you are running the IBM OS/2 operating system and
using more than 64MB of system memory on the SBC.

The Setup screen displays the system option:

Boot To OS/2 No

Available options are:

No
Ye s

Internal Cache

This option specifies the caching algorithm used for L1 internal cache memory.

The Setup screen displays the system option:

Internal Cache WriteBack

Chassis Plans 5-7

Advanced Setup CBI/CGI Technical Reference

Three options are available:

• Select Disabled to disable both L1 internal cache memory on the SBC and

L2 secondary cache memory.

• Select WriteThru to use the write-through caching algorithm.

• Select WriteBack to use the write-back caching algorithm.

External Cache

This option specifies the caching algorithm used for L2 cache memory. If the Internal
Cache option described above is set to Disabled, this option is not available for modifi-

cation.

The Setup screen displays the system option:

External Cache WriteBack

Three options are available:

• Select Disabled to disable L2 cache memory.

• Select WriteThru to use the write-through caching algorithm.

• Select WriteBack to use the write-back caching algorithm.

System BIOS Cacheable

The System BIOS, which is in the F000H memory segment, is automatically shadowed
to RAM for faster execution. This option indicates that this memory segment can be
read from or written to cache memory.

The Setup screen displays the system option:

System BIOS Cacheable Enabled

Available options are:

Disabled
Enabled

Video or Adapter ROM Shadow

ROM shadow is a technique in which BIOS code is copied from slower ROM to faster
RAM. The BIOS is then executed from the RAM.

Each option allows for a segment of 16KB to be shadowed from ROM to RAM. If one
of these options is enabled and there is BIOS code present in that particular segment, the
BIOS is shadowed.

Video BIOS shadowing may be done in two 16KB segments at C000H and C400H.
Enabling shadowing can speed up the operation of a machine because RAM can be

Chassis Plans5-8

Advanced SetupCBI/CGI Technical Reference

accessed more rapidly than ROM and the data bus is wider to RAM. The default setting
for the video BIOS segments is Cached.

Other 16KB ROM segments may be shadowed in the memory area from C800H to
E000H, depending upon preferences and system requirements. The ROM area that is not
used by ISA adapter cards is allocated to PCI adapter cards.

The Setup screen displays the system option:

XXXX,16K Shadow Cached

where XXXX is the base address of the segment of memory to be shadowed.

Three options are available:

• Select Enabled to write the contents of the specified ROM area to the same

address in system memory (RAM) for faster execution.

• Select Cached to write the contents of the specified ROM area to the same

address in system memory (RAM), if an adapter ROM is using the ROM
area. This also indicates that the contents of the RAM area can be read from
and written to cache memory.

• Select Disabled if you do not want to copy the specified ROM area to

RAM. The contents of the video ROM cannot be read from or written to
cache memory.

Saving and Exiting

When you have made all desired changes to Advanced CMOS Setup, press <Esc> to
return to the AMIBIOS Setup Main Menu screen.

You may make changes to other Setup options before exiting from AMIBIOS Setup.
You may save the changes you have just made or you may exit from Setup without
saving your changes.

Chassis Plans 5-9

Advanced Setup CBI/CGI Technical Reference

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Chassis Plans5-10

Advanced SetupCBI/CGI Technical Reference

ADVANCED
C

HIPSET SETUP

When you select Advanced Chipset Setup from the AMIBIOS Setup Main Menu, the
following Setup screen displays:

(C)1998 American Megatrends, Inc. All Rights Reserved

USB Function Enabled
USB KB/Mouse Legacy Support Auto
Port 64/60 Emulation Disabled
SERR# Disabled
PERR# Disabled
USWC Write Post Enabled
BX Master Latency Timer (Clks) 64
Multi-Trans Timer (Clks) 32
PCI1 to PCI0 Access Enabled
DRAM Integrity Mode None
DRAM Refresh Rate 15.6 us
Memory Hole Disabled
Graphics Aperture Size 64MB
AGP Mlti-Trans Timer (AGP Clks) 32
AGP Low-Priority Timer (AGP Clks)16
AGP SERR Enabled
AGP Parity Error Response Enabled
8bit I/O Recovery Time Disabled
16bit I/O Recovery Time Disabled
PIIX4 SERR# Disabled
USB Passive Release Enabled
PIIX4 Passive Release Enabled
PIIX4 Delayed Transaction Enabled
TypeF DMA Buffer Control1 Disabled
TypeF DMA Buffer Control2 Disabled
DMA-0 Type Normal ISA
DMA-1 Type Normal ISA
DMA-2 Type Normal ISA
DMA-3 Type Normal ISA
DMA-5 Type Normal ISA
DMA-6 Type Normal ISA
DMA-7 Type Normal ISA

AMIBIOS SETUP - ADVANCED CHIPSET SETUP

Available Options:

Disabled
Enabled

ESC:Exit
PgUp/PgDn:Modify
F2/F3:Color

↑↓:Sel

Advanced Chipset Setup Screen

When you display the Advanced Chipset Setup screen, the format is similar to the
sample shown above, except the screen displays only twenty options at a time. If you
need to change other options, use the down arrow key to locate the appropriate option.
The available values for each option are displayed on the right side of the screen when
you tab or arrow into the field.
_______________________________________________________________________

NOTE: The values on this screen do not necessarily reflect the values appropriate for
your SBC. Refer to the explanations below for specific instructions about entering
correct information.
_______________________________________________________________________

Chassis Plans 5-11

Advanced Setup CBI/CGI Technical Reference

ADVANCED
C

HIPSET SETUP

O

PTIONS

The descriptions for the system options listed below show the values as they appear if
you have not run the Advanced Chipset Setup program yet. Once values have been
defined, they display each time Advanced Chipset Setup is run.
_______________________________________________________________________

NOTE:Do not change the values for the options on this screen unless you understand
the impact on system operation. Depending on your system configuration, selection of
other values may cause unreliable system operation.
_______________________________________________________________________

USB Function

This option allows you to enable the Universal Serial Bus (USB).

If this option is set to Disabled, the USB KB/Mouse Legacy Support and Port 64/60
Emulation options are not available for modification.

The Setup screen displays the system option:

USB Function Enabled

Available options are:

Disabled
Enabled

USB Keyboard/Mouse Legacy Support

This option allows you to enable support for older keyboards and mouse devices.

If the USB Function option is set to Disabled, this option is not available for modifi­cation.

The Setup screen displays the system option:

USB KB/Mouse Legacy Support Auto

Available options are:

Disabled
Keyboard
Auto
Keyb+Mouse

Port 64/60 Emulation

If the USB Function option is set to Disabled, this option is not available for modifi­cation.

The Setup screen displays the system option:

Port 64/60 Emulation Disabled

Chassis Plans5-12

Available options are:

Disabled
Enabled

SERR#

This option enables the System Error (SERR#) signal on the bus.

The Setup screen displays the system option:

SERR# Disabled

Available options are:

Disabled
Enabled

PERR#

This option enables the Parity Error (PERR#) signal on the bus.

Advanced SetupCBI/CGI Technical Reference

The Setup screen displays the system option:

PERR# Disabled

Available options are:

Disabled
Enabled

USWC Write Post

This option sets the status of Uncacheable, Speculatable, Write-Combined (USWC)
posted writes to I/O.

The Setup screen displays the system option:

USWC Write Post Enabled

Available options are:

Disabled
Enabled

BX Master Latency Timer (Clks)

This option specifies the master latency timings (in PCI clocks) for devices on the SBC.

Chassis Plans 5-13

Advanced Setup CBI/CGI Technical Reference

The Setup screen displays the system option:

BX Master Latency Timer (Clks) 64

Available options are:

Disabled 128
32 160
64 192
96 224

Multi-Transaction Timer (Clks)

This option specifies the multi-transaction latency timings (in PCI clocks) for devices on
the SBC.

The Setup screen displays the system option:

Multi-Trans Timer (Clks) 32

Available options are:

Disabled 128
32 160
64 192
96 224

PCI1 to PCI0 Access

This option enables access between two different PCI buses (PCI1 and PCI0).

The Setup screen displays the system option:

PCI1 to PCI0 Access Enabled

Available options are:

Disabled
Enabled

DRAM Integrity Mode

This option allows you to set the type of system memory checking used in your system.

The Setup screen displays the system option:

DRAM Integrity Mode None

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Advanced SetupCBI/CGI Technical Reference

Three options are available:

• None - No error checking or error reporting is done.

• EC - Multibit errors are detected and reported as parity errors. Single-bit

errors are corrected by the chipset. Corrected bits of data from memory are
not written back to DRAM system memory.

• ECC Hardware - Multibit errors are detected and reported as parity errors.

Single-bit errors are corrected by the chipset and are written back to DRAM
system memory.

If a soft (correctable) memory error occurs, writing the fixed data back to
DRAM system memory will resolve the problem. Most DRAM errors are
soft errors. If a hard (uncorrectable) error occurs, writing the fixed data
back to DRAM system memory does not solve the problem. In this case, the
second time the error occurs in the same location, a Parity Error is reported,
indicating an uncorrectable error.

DRAM Refresh Rate

This option specifies the interval between refresh signals to DRAM system memory.
Settings are in microseconds ("us").

The Setup screen displays the system option:

DRAM Refresh Rate 15.6 us

Available options are:

15.6 us

31.2 us

64.4 us

124.8 us

249.6 us

Memory Hole

This option may be used to specify an area in memory which cannot be addressed on the
ISA Bus.

The Setup screen displays the system option:

Memory Hole Disabled

Available options are:

Disabled
512KB-640KB
15MB-16MB

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Advanced Setup CBI/CGI Technical Reference

Graphics Aperture Size (not available on BASIC models)

This option specifies the amount of system memory which can be used by the Accel­erated Graphics Port (AGP).

The Setup screen displays the system option:

Graphics Aperture Size 64MB

Available options are:

4 MB 64MB
8 MB 128 MB
16MB 256 MB
32MB

AGP Multi-Transaction Timer (AGP Clks) (not available on BASIC models)

This option sets the AGP multi-transaction timer. The settings are in units of AGP
clocks.

The Setup screen displays the system option:

AGP Mlti-Trans Timer (AGP Clks) 32

Available options are:

Disabled 128
32 160
64 192
96 224

AGP Low-Priority Timer (AGP Clks) (not available on BASIC models)

The Setup screen displays the system option:

AGP Low-Priority Timer (AGP Clks) 16

Available options are:

Disabled 80 176
16 96 192
32 112 208
48 128 224
64 144 240

AGP SERR (not available on BASIC models)

This option allows you to use a System Error (SERR#) signal for the AGP Bus.

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Advanced SetupCBI/CGI Technical Reference

The Setup screen displays the system option:

AGP SERR Enabled

Available options are:

Disabled
Enabled

AGP Parity Error Response (not available on BASIC models)

This option enables the Accelerated Graphics Port (AGP) to respond to parity errors.

The Setup screen displays the system option:

AGP Parity Error Response Enabled

Available options are:

Disabled
Enabled

8 Bit I/O Recovery Time

This option specifies the length of the delay inserted between consecutive 8-bit I/O
operations.

The Setup screen displays the system option:

8bit I/O Recovery Time Disabled

Available options are:

Disabled
8 Sysclk 4 Sysclk
1 Sysclk 5 Sysclk
2 Sysclk 6 Sysclk
3 Sysclk 7 Sysclk

16 Bit I/O Recovery Time

This option specifies the length of the delay inserted between consecutive 16-bit I/O
operations.

The Setup screen displays the system option:

16bit I/O Recovery Time Disabled

Chassis Plans 5-17

Advanced Setup CBI/CGI Technical Reference

Available options are:

Disabled
3 Sysclk
1 Sysclk
2 Sysclk
4 Sysclk

PIIX4 SERR#

This option enables the System Error (SERR#) signal for the Intel PIIX4 chip.

The Setup screen displays the system option:

PIIX4 SERR# Disabled

Available options are:

Disabled
Enabled

USB Passive Release

This option enables passive release for the Universal Serial Bus (USB).

The Setup screen displays the system option:

USB Passive Release Enabled

Available options are:

Disabled
Enabled

PIIX4 Passive Release

This option enables passive release for the Intel PIIX4 chip.

The Setup screen displays the system option:

PIIX4 Passive Release Enabled

Available options are:

Disabled
Enabled

PIIX Delayed Transaction

This option enables delayed transactions for the Intel PIIX4 chip.

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Advanced SetupCBI/CGI Technical Reference

The Setup screen displays the system option:

PIIX4 Delayed Transaction Enabled

Available options are:

Disabled
Enabled

Type F DMA Buffer Control1/Type FDMA Buffer Control2

These options specify the DMA channels where Type F buffer control is implemented.

The Setup screen displays the system options:

Type F DMA Buffer Control1 Disabled
Type F DMA Buffer Control2 Disabled

Available options are:

Channel-0 Disabled
Channel-1 Channel-5
Channel-2 Channel-6
Channel-3 Channel-7

DMA-0 through DMA-7 Type

The DMA-# Type options specify the bus on which the specified DMA channel can be
used.

The Setup screen displays the system option:

DMA-# Type Normal ISA

where # is the DMA Channel number.

Available options are:

Normal ISA
PC/PCI
Distributed

Saving and Exiting

When you have made all desired changes to Advanced Chipset Setup, press <Esc> to
return to the AMIBIOS Setup Main Menu screen.

You may make changes to other Setup options before exiting from AMIBIOS Setup.
You may save the changes you have just made or you may exit from Setup without
saving your changes.

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Copyright 2003 by Trenton Technology Inc. All rights reserved.

Chassis Plans5-20

Chapter 6 Power Management Setup

Power Management SetupCBI/CGI Technical Reference

POWER
M

ANAGEMENT

S

ETUP

When you select Power Management Setup from the AMIBIOS Setup Utility Main
Menu, the following Setup screen displays:

(C)1998 American Megatrends, Inc. All Rights Reserved

ACPI Aware O/S No
Power Management/APM Disabled
Power Button Function On/Off
Green PC Monitor Power State Stand By
Video Power Down Mode Disabled
Hard Disk Power Down Mode Disabled
Hard Disk Time Out (Minute) Disabled
Power Saving Type POS
Standby/Suspend Timer Unit 4 Min
Standby Time Out Disabled
Suspend Time Out Disabled
Slow Clock Ratio 50%-62.5%
Display Activity Ignore
Device 6 (Serial port 1) Ignore
Device 7 (Serial port 1) Ignore
Device 8 (Parallel port) Ignore
Device 5 (Floppy disk) Ignore
Device 0 (Primary master IDE) Ignore
Device 1 (Primary slave IDE) Ignore
Device 2 (Secondary master IDE) Ignore
Device 3 (Secondary slave IDE) Ignore

AMIBIOS SETUP - POWER MANAGEMENT SETUP

Available Options:

No
Yes

ESC:Exit
PgUp/PgDn:Modify
F2/F3:Color

↑↓:Sel

P

OWER

M

ANAGEMENT

SETUP OPTIONS

Power Management Setup Screen

When you display the Power Management Setup screen, the format is similar to the
sample shown above, except the screen displays only twenty options at a time. If you
need to change other options, use the down arrow key to locate the appropriate option.
The available values for each option are displayed on the right side of the screen when
you tab or arrow into the field.
_______________________________________________________________________

NOTE: The values on this screen do not necessarily reflect the values appropriate for
your SBC. Refer to the explanations below for specific instructions about entering
correct information.
_______________________________________________________________________

The descriptions for the system options listed below show the values as they appear if
you have not yet run Power Management Setup. Once values have been defined, they
display each time Power Management Setup is run.

ACPI Aware O/S

This option indicates whether or not the operating system under which you are running
complies with Intel's Advanced Configuration and Power Interface (ACPI) specification.

Chassis Plans. 6-1

Power Management Setup CBI/CGI Technical Reference

The Setup screen displays the system option:

ACPI Aware O/S No

Available options are:

No
Ye s

Power Management/APM

This option allows you to enable Advanced Power Management (APM) on your system.
If this option is disabled, you cannot change any other options on the Power
Management Setup screen, except the ACPI Aware O/S.

The Setup screen displays the system option:

Power Management/APM Disabled

Available options are:

Disabled
Enabled

Power Button Function

This option specifies how the power button mounted externally on the computer chassis
is used.

The Setup screen displays the system option:

Power Button Function On/Off

Two options are available:

• Select Suspend to use the power button to place the computer into Suspend

mode or Full On power mode.

• Select On/Off to use the power button to turn the computer on or off.

Green PC Monitor Power State

This option specifies the power management state, if any, which the Green PC-compliant
video monitor enters after a specified period of display inactivity has expired. The
period of inactivity before a monitor enters Standby mode is specified in the Standby

Time Out option; the period of inactivity for Suspend mode is specified in the Suspend
Time Out option.

The Setup screen displays the system option:

Green PC Monitor Power State Stand By

Chassis Plans.6-2

Power Management SetupCBI/CGI Technical Reference

Available options are:

Stand By
Suspend
Off

Video Power Down Mode

If the video subsystem remains inactive for a specified period of time, AMIBIOS
conserves power by placing the subsystem into the power management state specified in
this option. The period of inactivity before the subsystem enters Standby mode is
specified in the Standby Time Out option; the period of inactivity for Suspend mode is
specified in the Suspend Time Out option.

The Setup screen displays the system option:

Video Power Down Mode Disabled

Available options are:

Disabled
Stand By
Suspend

Hard Disk Power Down Mode

If the hard disk drive remains inactive for a specified period of time, AMIBIOS
conserves power by placing the drive into the power management state specified in this
option. The period of inactivity before the drive is powered down is specified in the
Hard Disk Time Out option.

The Setup screen displays the system option:

Hard Disk Power Down Mode Disabled

Available options are:

Disabled
Stand By
Suspend

Hard Disk Time Out (Minute)

This option specifies the length of time AMIBIOS waits before turning off power to the
hard disk drive if the drive remains inactive. When this period expires, the hard disk
drive enters the power-conserving mode specified in the Hard Disk Power Down Mode
option described above.

The Setup screen displays the system option:

Hard Disk Time Out (Minute) Disabled

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Power Management Setup CBI/CGI Technical Reference

Available options are:

Disabled
1 through 15, in increments of 1 minute

Power Saving Type

The Setup screen displays the system option:

Power Saving Type POS

Available options are:

POS (Power On Suspend)
Sleep
Stop Clock
Deep Sleep

Standby/Suspend Timer Unit

This option specifies the unit of time used for the Standby and Suspend time-out periods.

The Setup screen displays the system option:

Standby/Suspend Timer Unit 4 Min

Available options are:

32 secs
4 msec
4 min
4 sec

Standby Time Out

This option specifies the length of the period of system inactivity when the computer is
in full power-on mode before it is placed in Standby mode. In Standby mode, some
power use is curtailed.

The default for this option depends on the value selected in the Standby/Suspend Timer
Unit option.

The Setup screen displays the system option:

Standby Time Out Disabled

Available options are:

Disabled
32 through 4064, in increments of 32 (if the Standby/Suspend
Timer Unit option is set to 32 secs)
4 through 508, in increments of 4 (if the Standby/Suspend
Timer Unit option is set to 4 msec, 4 min or 4 sec)

Chassis Plans.6-4