Revision History IntelP®P Server Board S3420GP TPS
Revision History
Date Revision
Number
Feb. 2009 0.3 Initial version
May 2009 0.5 Update
July. 2009 0.9 Update POST error code and diagram
Aug. 2009 1.0 Update MTBF
Modifications
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IntelP®P Server Board S3420GP TPS Disclaimers
Disclaimers
Information in this document is provided in connection with Intel® products. No license, express
or implied, by estoppel or otherwise, to any intellectual property rights is granted by this
document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel
assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular
purpose, merchantability, or infringement of any patent, copyright or other intellectual property
right. Intel products are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked
"reserved" or "undefined." Intel reserves these for future definition and shall have no
responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
This document contains information for a product that is still in development. Do not
finalize a design with this information. Information provided in this preliminary document may be
incomplete (as denoted by TBD) or may change. Revised information will be published in a later
release of this document and when the product is made available. Verify with your local sales
office that you have the latest datasheet before finalizing a design.
The Intel
®
Server Board S3420GP may contain design defects or errors known as errata which
may cause the product to deviate from published specifications. Current characterized errata
are available on request.
Intel Corporation server boards contain a number of high-density VLSI and power delivery
components that need adequate airflow to cool. Intel’s own chassis are designed and tested to
meet the intended thermal requirements of these components when the fully integrated system
is used together. It is the responsibility of the system integrator that chooses not to use Intel
developed server building blocks to consult vendor datasheets and operating parameters to
determine the amount of airflow required for their specific application and environmental
conditions. Intel Corporation cannot be held responsible if components fail or the server board
does not operate correctly when used outside any of their published operating or non-operating
limits.
Intel, Pentium, Itanium, and Xeon are trademarks or registered trademarks of Intel Corporation.
*Other brands and names may be claimed as the property of others.
Table 67. POST Progress Code LED Example ........................................................................109
Table 68. Diagnostic LED POST Code Decoder ...................................................................... 109
Table 69. POST Error Messages and Handling........................................................................ 113
Table 70. POST Error Beep Codes ..........................................................................................117
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IntelP®P Server Board S3420GP TPS List of Tables
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Introduction IntelP®P Server Board S3420GP TPS
1. Introduction
This Technical Product Specification (TPS) provides board specific information detailing the
features, functionality, and high-level architecture of the Intel
®
Server Board S3420GP.
In addition, you can obtain design-level information for specific subsystems by ordering the
External Product Specifications (EPS) or External Design Specifications (EDS) for a given
subsystem. EPS and EDS documents are not publicly available and must be ordered through
your local Intel representative.
1.1 Chapter Outline
This document is divided into the following chapters:
Chapter 8 – Intel
Chapter 9 – Design and Environmental Specifications
Chapter 10 – Regulatory and Certification Information
Appendix A – Integration and Usage Tips
Appendix B – Integrated BMC Sensor Tables
Appendix C – POST Code Diagnostic LED Decoder
Appendix D – POST Code Errors
Appendix E – Supported Intel
®
Light-Guided Diagnostics
®
Server Chassis
1.2 Server Board Use Disclaimer
Intel Corporation server boards contain a number of high-density VLSI and power delivery
components that need adequate airflow to cool. Intel ensures through its own chassis
development and testing that when Intel server building blocks are used together, the fully
integrated system meets the intended thermal requirements of these components. It is the
responsibility of the system integrator who chooses not to use Intel developed server building
blocks to consult vendor datasheets and operating parameters to determine the amount of
airflow required for their specific application and environmental conditions. Intel Corporation
cannot be held responsible if components fail or the server board does not operate correctly
when used outside any of their published operating or non-operating limits.
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IntelP®P Server Board S3420GP TPS Overview
2. Overview
The Intel® Server Board S3420GP is a monolithic printed circuit board (PCB) with features
designed to support entry-level severs. It has three board SKUs: S3420GPLX, S3420GPLC,
and S3420GPV.
2.1 Intel® Server Board S3420GP Feature Set
Table 1. Intel® Server Board S3420GP Feature Set
Feature Description
Processor Support for one Xeon® 3400 Series Processor in FC-LGA 1156 socket package.
2.5 GT/s point-to-point DMI interface to PCH
LGA 1156 pin socket
Memory Two memory channels with support for 1066/1333 MHz ECC Unbuffered (UDIMM) or
Chipset
ECC Registered (RDIMM) (Intel® Xeon® 3400 Series only) DDR3.
• Intel
• Intel® Server Board S3420GPV
• Intel® Server board S3420GPLX
• Intel® Server board S3420GPLC
®
Server Board S3420GPLX and S3420GPLC
Up to 2 UDIMMs or 3 RDIMM (Intel® Xeon® 3400 Series only) per channel
32 GB max with x8 ECC RDIMM (2 Gb DRAM) and 16 GB max with x8
ECC UDIMM (2 Gb DRAM)
Up to 2 UDIMMs per channel
16 GB max with x8 ECC UDIMM (2 Gb DRAM)
Support for Intel® 3420 Chipset Plaftorm Controller Hub (PCH)
ServerEngines* LLC Pilot II BMC controller (Integrated BMC)
PCI Express* switch
Support for Intel® 3420 Chipset Platform Controller Hub (PCH)
ServerEngines* LLC Pilot II BMC controller (Integrated BMC)
I/O
Revision 1.0
External connections:
DB-15 video connectors
DB-9 serial Port A connector
Four ports on two USB/LAN combo connectors at rear of board.
Internal connections:
Two USB 2x5 pin headers, each supporting two USB 2.0 ports
One 2x5 Serial Port B header
Six SATA II connectors
One Intel® SAS Entry RAID Module AXX4SASMOD connector
One SAS mezzanine slot supports for optional Intel® Remote Management
Module 3
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Overview IntelP®P Server Board S3420GP TPS
Feature Description
Add-in PCI Card, PCI
Express* Card
System Fan Support Five 4-pin fan headers supporting four system fans and one processor.
Video Onboard ServerEngines* LLC Pilot II BMC Controller
Onboard Hard Drive Support for six Serial ATA II hard drives through six onboard SATA II connectors with
LAN One Gigabit Ethernet device 82574L connect to PCI-E x1 interfaces on the PCH.
Server Management Onboard LLC Pilot II Controller (iBMC)
•Intel® Server Board S3420GPLX
Slot1: One 5V PCI 32 bit / 33 MHz connector.
Slot2: One PCI Express* Gen1 x4 (x1 throughput) connector.
Slot3: One PCI Express* Gen1 x8 (x4 throughput) connector.
Slot4: One PCI Express* Gen2 x8 (x4 throughput) connector.
Slot5: One PCI Express* Gen2 x8 (x8 throughput) connector.
Slot6: One PCI Express* Gen2 x16 (x8 throughput) connector.
• Intel® Server Board S3420GPLC/ S3420GPV
Slot1: One 5V PCI 32 bit / 33 MHz connector.
Slot3: One PCI Express* Gen1 x8 (x4 throughput) connector.
Slot5: One PCI Express* Gen2 x8 (x8 throughput) connector.
Slot6: One PCI Express* Gen2 x16 (x8 throughput) connector.
Integrated 2D Video Controller
64-MB DDR2 667 MHz Memory
SW RAID 0, 1, 5, and 10.
•Intel® Server Board S3420GPLX:
Up to four SAS hard drives through option Intel® SAS Entry RAID Module
AXX4SASMOD card
Intel® Server Board S3420GPLX/S3420GPLC:
One Gigabit Ethernet PHY 82578DM connected to PCH through PCI-E x1
The following figure shows the board layout of the server board. Each connector and major
component is identified by a number or letter, and 2 provides the description.
DD
CC
BB
A
ABCDEFGH
J
I
K
LM
N
O
P
Z
V
W
X
Y
U
T
R
S
Q
AF003290
®
Figure 2. Intel
Server Board S3420GP Layout
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Table 2. Major Board Components
A Slot 1, 32 Mbit/33 MHz PCI Q System FAN2 and System FAN 3
B Slot 2, PCI Express* Gen1 x1 (x4 connector)
(Intel Server Board S3420GPLX only)
C Intel RMM3 Connector(Intel Server Board S CPU Fan connector
S3420GPLX only)
D
Slot 3, PCI Express* Gen1 x4 (PCI Express* T USB SSD connector
Gen2 compliant)
E Slot 4, PCI Express* Gen2 x4 (x8 connector)
(x8 connector)( Intel
only)
F Slot 5. PCI Express* Gen2 x8 (x8 connector) V System FAN 1
G Slot 6, PCI Express* Gen2 x8 (x16 connector) W IPMB
H CMOS battery X SATA_SGPIO
I Ethernet and Dual USB COMBO Y HSBP
J Ethernet and Dual USB COMBO Z USB Floppy
K System FAN 4 AA Six SATA ports
L Video port BB Internal USB Connector
M External Serial port CCFront Panel Connector
N Main Power Connector DDInternal Serial Port
O CPU Power connector
P DIMM slots
Description Description
R CPU connector
®
Server Board
®
Server Board S3420GPLX
U SAS Module connector ( Intel
S3420GPLX only)
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Overview IntelP®P Server Board S3420GP TPS
2.2.2 Intel® Server Board S3420GP Mechanical Drawings
Figure 3. Intel® Server Board S3420GP – Key Connector and LED Indicator IDENTIFICATION
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IntelP®P Server Board S3420GP TPS Overview
Figure 4. Intel® Server Board S3420GP – Hole and Component Positions
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Overview IntelP®P Server Board S3420GP TPS
Figure 5. Intel
Revision 1.0
8
®
Server Board S3420GP – Major Connector Pin Location (1 of 2)
Intel order number E65697-003
IntelP®P Server Board S3420GP TPS Overview
Figure 6. Intel® Server Board S3420GP –Major Connector Pin Location (2 of 2)
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Overview IntelP®P Server Board S3420GP TPS
Figure 7. Intel® Server Board S3420GP – Primary Side Keepout Zone
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IntelP®P Server Board S3420GP TPS Overview
Figure 8. Intel® Server Board S3420GP – Secondary Side Keepout Zone
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Overview IntelP®P Server Board S3420GP TPS
2.2.3
The foligure shows the layou
lowing ft of the rear I/O components for the server board.
Server Board Rear I/O Layout
A Serial Port A CNIC Port 1 (1 Gb) and Dual USB Port
Connector
B Video DNIC port 2 (1 Gb) and Dual USB Port
Connector
Figure 9. Intel® Server Board S3420GP Rear I/O Layout
12
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Intel order number E65697-003
IntelP®P Server Board S3420GP TPS Functional Architecture
3nct. Fuional Architecture
The architecture and design of the Intel® Server Board S3420GP is based on the Intel
Chipset. The chipset is designed for systems based on the Intel
®
Xeon® processor in the FC-
®
3420
LGA 1156 socket package. The chipset contains two main components:
Intel 3420 Chipset
PCI Express* switch (Intel
®
®
Server Board S3420GPLX only).
This chapter provides a high-level description of the functionality associated with each chipset
component and the architectural blocks that make up the server board.
ATX - 12" x 9.6"
4 unbuffered
or
6 registered
DIMMs
SERIAL 2
SERIAL 1
(x16 connector)
(x8 connector)
(x8 connector)
(x8 connector)
(x4 connector)
Slot 6
Slot 5
Slot 4
Slot 3
Slot 2
Slot 1
SAS
PCI
FLASHFLASH
SATA-II
6 onboard
S3420GPLX Block Diagram
PCIe Gen2 x8
Intel® Xeon
PCIe Gen2 x8
PCIe Gen2 x4
PCIe Gen2 x4
PCIe
Gen1
PCIe
N/C
Gen1
PCI32
SPI
2
(FP
headers)
x4
x1
SATA
612
(User Bay
headers)
ICH
G2PS
ICH1
9/
0
Intel® 3420
PCH
1
2
USB
Floppy
Header
PCIe Gen2 x8
x4 DMI Gen1
PCIe
Gen1
PCIe
Gen1
LPC
USB
3400
Gen1 x1 )
( PCIe
x1
82574L
x1
IBMC
USB
1.1
RMII
Zoar
USB
2.0
RMII
RMM3
DDR3 (Ch B)
®
DDR3 (Ch A)
Ch ACh B
XDP0
82578DM
GbE
PHY
SPI
PORT 80
1
SPI
2
Z-U130
FLASHFLASH
DDR2
FLASH
USB2USB
GbE
GbE
BMC Boot
Flash
VIDEO
Notes:
1. Video integrated into BMC.
Figureagram For S3420GPLX 10. Intel® Server Board S3420GP Functional Block Di
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Intel order number E65697-003
ejd
13
Functional Architecture IntelP®P Server Board S3420GP TPS
(x16 ectoconn r)
(x8 to
(x8 connector)
Slot 6
Slot 5
Slot 3
Slot 1
PCI
FLASHFLASH
SATA-II
6 onboard
S3420GPLC Block Diagram
PCIe
Gen1
PCI32
SPI
headers)
x4
2
(FP
PCIe Gen2 x8connec r)
Intel® 3420
Chipset
612
SATA
2
(User Bay
headers)
PCIe Gen2 x8
Intel
3420
Chipset
1
USB
Floppy
Header
®
x4 DMI Gen1
PCIe
Gen1
PCIe
Gen1
LPC
USB
®®
Intel Xeon
3400
Processor
( PCIe Gen1 x1 )
x1
82574
x1
IBMC
Zoar
USB
USB
1.1
2.0
RMII
XDP0
RMII
SPI
Z-U130
82578DM
1
GbE
PHY
PORT 80
DDR3 (Ch B)
DDR3 (Ch A)
FLASHFLASH
DDR2
FLASH
2
USB2USB
Ch ACh B
GbE
GbE
BMC Boot SPI
Flash
VIDEO
Not
1. Video integrated into BMC.
SERIAL 1
es:
ATX - 12" x
4 unbuffered
or
6 registered
DIMMs
SERIAL 2
9.6"
ejd
®
Figure 11. I
ntel Server Board S3420GP Functional Block Diagram From S3420GPLC
<TBD>
Figure 12. Intel Server Board S3420GP Functional Block Diagram From S3420GPV
3.1
Processor Sub-System
Thet
In el® Server Board S3420GP supports the following processor:
®
Intel
The Intel
based
3.1.1
The Intel
Nehale
FC-
Xeon
®
Xrocessors processors are made up of multi-core processors
eon® 3400 Series p
on the 45 nm process technology.
Intel® Xeon® 3400 Processor
®
m-based processor cores.
®
Xeon 3400 Series processors highly integrated solution variant is composed of four
LGA 1156 socket package with 2.5 GT/s.
Up to 95 W Thermal Design Power (TDP); processors with higher TDP are not
®
®
3400 Processor series
supported.
14
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IntelP®P Server Board S3420GP TPS Functional Architecture
The server
3.1.2 Intel Turbo Boost Technology
Inte Boost certain processors in the Intel® Xeon® Processor
l® Turbo Technology is featured on
3400 Series. Intel
processor to run fa
board does not support previous generations of the Intel
®
®
Turbo Boost Technology opportunistically and automatically allows the
ster than the marked frequency if the processor is operating below power,
®
Xeon® processors.
temperature, and current limits. This results in increased performance for both multi-threaded
andn
si gle-threaded workloads.
®
Intel
Turbo Boost Technology operation:
t operates under Operating System control – It is only entered when the
Turbo Boos
operating system requests the highest (P0) performance state.
Turbo Boost operation can be enabled or disabled by BIOS.
Turbo Boost converts any available power and thermal headroom into higher frequency
on active cores. At nominal marked processor frequency, many applications consume
less than the rated processor power draw.
Turbo Boost availability
Maximum Turbo Boost frequency depends on the number of active cores and varies by
is independent of the number of active cores.
processor configuration.
The amount of time the system spends in Turbo Boost operation depends on workload,
o
perating environment, and platform design.
®
If tho
e pr cessor supports the Intel
an o
ption to enable or disable this feature. The default state is enabled.
Turbo Boost Technology feature, the BIO
S Setup provides
3.1. (SMT)
3 Simultaneous Multithreading
Mostts
t In el® Xeon® processors support Simultaneous Multithreading (SMT). The BIOS detec
processors that support this feature and enables the feature during POST.
If the processor supports this feature, the BIOS Setup provides an option to enab
this The d
feature.efault is enabled.
3.1.4 Enhanced In
®
Xeon® processors support the Geyserville3 feature of the Enhanced Intel SpeedStep®
Intel
chnology. This feature changes the processor operating ratio and voltage similar to the
te
tel SpeedStep® Technology
le or disable
Thermal Monitor 1 (TM1) feature. The BIOS implements the Geyserville3 feature in conjunction
with the TM1 feature.
The BIOS enables a combination of TM1 and TM2 according to the
processor BIOS writer's guide.
3.2 Memory Subsystem
The Intel® Xeon® 3400 series processor has an Integrated Memory Controller (IMC) in its
package. Each Intel
memory. Each DDR3 channel in the IMC supports up to three DDR3 RDIMM slots or up to two
UDIMM slots. The DDR3 RDIMM frequency can be 800/1066/1333 MHz. DDR3 UDIMM
®
Xeon® 3400 series processor produces up to two DDR3 channels of
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Functional Architecture IntelP®P Server Board S3420GP TPS
frequency can be 1066/1333 MHz. All RDIMMs and UDIMMs include ECC (Error Correction
Code) operation. Various speeds and memory technologies are supported.
RAS (Reliability, Availability, and Serviceability) is not supported on the Intel
®
Server Board
S3420GP.
3.2.1 Memory Sizing and Configuration
The Intel® Server Board S3420GP supports various memory module sizes and configurations.
These combinations of sizes and configurations are valid only for DDR3 DIMMs approved by
Intel Corporation.
S3420GP BIOS supports:
z DIMM sizes of 1 GB, 2 GB, 4 GB, and 8 GB.
z DIMMs composed of DRAM using 2 Gb technology.
z DRAMs organized as single rank, dual rank, or quad rank DIMMS.
z DIMM speeds of 800, 1066, or 1333 MT/s.
z Registered or Unregistered (unbuffered) DIMMs (RDIMMs or UDIMMs).
Note: UDIMMs should be ECC, and ma or may not have thermal sensors; RDIMMs must have y
ECC and must have thermal sensors.
S3420GP BIOS has the below limitations:
256 Mb technology, x4 DRAM on UDIMM, and quad rank UDIMM are NOT supported
x16 DRAM on UDIMM is not supported on combo routing
Memory suppliers not productizing native 800 ECC UDIMMs
Intel
256 Mb/512 Mb technology, x4 an
All channels in a system will run at
No mixing of registered and unbuffered DIMMs
®
Xeon® 3400 Series support all timings
d x16 DRAMs on RDIMM are NOT supported
the fastest common frequency
defined by JEDEC.
3.2.2 Post Error Codes
The range {0xE0 - 0xEF} of POST codes is used for memory errors in early POST. In late POST,
this range is used for reporting other system errors.
z0xE8 - No Us
Diagnostic LED
z0xE8 - Configuratio
the DIMM slot as if no
DIMM installed in the s
usable memo
z0xEB - Memory Test E
memory channe
the BIOS emits a beep code and displays POST Diagnostic LED code 0xEB
momentarily d
able Memory Error: If no memory is available, the system emits POST
code 0xE8 and halts the system.
n Error: If a DDR3 DIMM has no SPD information, the BIOS treats
DDR3 DIMM is present on it. Therefore, if this is the only DDR3
ystem, the BIOS halts with POST Diagnostic LED code 0xE8 (no
ry) and halts the system.
rror: If a DDR3 DIMM or a set of DDR3 DIMMs on the same
l (row) fails HW Memory BIST but usable memory remains available,
uring the beeping and then continues POST. If all of the memory fails HW
16
Revision 1.0
Intel order number E65697-003
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