Intel S3000PT - Server Board Motherboard Specification

Intel® Server Board S3000PT

Technical Product Specification

D69383-004

Revision 1.3

February 2007

Enterprise Platforms and Services Division

Revision History Intel® Server Board S3000PT TPS

ii Revision 1.3

Revision History

Date

Revision

Number

Modifications

September 2006

1.0

Initial Release
December , 2006

1.1

Updated
February, 2007

1.2

Updated calculated MTBF data
February, 2007

1.3

Inserted non-standard connector information matrix and table

Disclaimers

Information in this document is provided in connection with Intel® products. No license, express, imp lied,
by estoppel, or otherwise, to any intellectual property rights is granted by this document. Except as
provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever,
and Intel disclaims any express or implie d warranty, relating to sale and/or use of Intel products including
liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any
patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications. Intel may make changes to specifications and product descriptions
at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instruct ions marked reserved
or undefined. Intel reserves these for future definition and shall have no responsibility whatsoever for
conflicts or incompatibilities arising from future changes to them.

This document contains information on products in the design p hase of development. Do not finalize a
design with this information. Revised information will be published when the product is available. Verify
with your local sales office that you have the latest datasheet before finalizing a design.

The Intel® Server Board S3000PT may contain design defects or errors known as errata which may
cause the product to deviate from published specifications. Current characterized errata are available on
request.

Intel, Pentium®, Itanium, and Xeon are trademarks or registered trademarks of Intel Corporation.
*Other brands and names may be claimed as the property of others.
Copyright © Intel Corporation 2006.

Intel® Server Board S3000PT TPS Table of Contents

Revision 1.3

iii

Table of Contents

1. Introduction ................................ ................................ ................................ ........................ 1

1.1 Section Outline................................ ................................ .......................................1

1.2 Server Board Use Disclaimer ................................ ................................ .................1

2. Server Board Overview ................................ ................................ ................................ ......2

2.1 Intel® Server Board S3000PT Feature Set ................................ ............................ 2

3. Functional Architecture ................................ ................................ ................................ .....6

3.1 Processor Sub-System................................ ................................ ........................... 7

3.1.1 Processor Voltage Regulator Down (VRD) ................................ ............................. 7

3.1.2 Reset Configuration Logic ................................ ...................................................... 8

3.1.3 Processor Support ................................ ................................ ................................ .8

3.2 Intel®3000 Chipset................................ ................................ ................................ .9

3.2.1 Memory Controller Hub (MCH) ................................ ................................ ...............9

3.2.2 I/O Controller Hub ................................ ................................ ................................ 11

3.3 Memory Sub-System................................ ................................ ............................ 13

3.3.1 Memory DIMM Support ................................ ........................................................15

3.4 I/O Sub-System................................ ................................ ................................ ....15

3.4.1 PCI Subsystem ................................ ................................................................ ....15

3.4.2 Interrupt Routing ................................ ................................ ................................ ..16

3.5 PCI Error Handling ................................ ................................ ............................... 18

3.5.1 Video Support ................................ ................................ ................................ ......21

3.5.2 Network Interface Controller (NIC) ................................ ................................ .......21

3.5.3 Super I/O Chip ................................ ................................ ................................ .....22

3.5.4 BIOS Flash................................ ................................ ................................ ...........23

3.5.5 System Health Support ................................ ................................ ........................24

3.6 Replacing the Back-Up Battery ................................ ................................ ............24

4. System BIOS ................................ ................................ ................................ ..................... 25

4.1 BIOS Identification String ................................ ................................ .....................25

4.2 Logo / Diagnostic Window ................................ ................................ .................... 25

4.3 BIOS Setup Utility ................................ ................................ ................................ 26

4.3.1 Operation ................................ ................................ ................................ .............26

4.3.2 Server Platform Setup Screens ................................ ................................ ............28

Table of Contents Intel® Server Board S3000PT TPS

iv Revision 1.3

4.4 Loading BIOS Defaults ................................ ................................ ........................ 49

5. Platform Management Architecture ................................ ................................ ................50

5.1 Console Redirection ................................ ................................ ............................. 50

5.1.1 Serial Configuration Settings ................................ ................................ ................50

5.1.2 Keystroke Mappings ................................ ................................ ............................. 50

5.1.3 Limitations................................ ................................ ................................ ............51

5.2 Intel® Active Management Technology (AMT) ................................ ......................51

5.3 Wired For Management (WFM) ................................ ................................ ...........53

5.3.1 PXE BIOS Support ................................ ................................ ............................... 53

5.4 System Management BIOS (SMBIOS) ................................ ................................ .53

5.5 Security................................ ................................ ................................ ................53

5.5.1 Operating Model................................ ................................ ................................ ...53

5.5.2 Password Protection ................................ ................................ ............................ 54

5.5.3 Password Clear................................ ................................ ....................................54

6. Error Reporting and Handling ................................ ................................ ......................... 55

6.1 Error Handling and Logging ................................ ................................ .................55

6.1.1 Error Sources and Types ................................ ................................ .....................55

6.1.2 Error Logging via SMI Handler ................................ .............................................56

6.1.3 SMBIOS Type 15 ................................ ................................ ................................ .56

6.1.4 Logging Format Conventions ................................ ................................ ...............56

6.2 Error Messages and Error Codes ................................ ................................ .........58

6.2.1 Diagnostic LEDs................................ ................................ ................................ ...58

6.2.2 POST Code Checkpoints ................................ ................................ .....................60

6.2.3 POST Error Messages and Handling ................................ ................................ ...62

6.2.4 POST Error Beep Codes ................................ ................................ ...................... 63

6.2.5 POST Error Pause Option ................................ ................................ ....................63

7. Connectors and Jumper Blocks ................................ ................................ ......................64

7.1 Power Connectors................................ ................................ ................................ 64

7.2 SMBus Header................................ ................................ .....................................64

7.3 Front Panel Connector ................................ ................................ ......................... 65

7.4 I/O Connectors ................................ ................................ ................................ .....65

7.4.1 VGA Connector ................................ ................................ ....................................65

7.4.2 NIC Connectors................................ ................................ ................................ ....66

7.4.3 SATA Connectors ................................ ................................ ................................ 66

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7.4.4 Serial Port Connectors ................................ ................................ ......................... 67

7.4.5 USB Connector ................................ ................................ ................................ ....67

7.5 Fan Headers ................................ ................................ ................................ ........68

7.6 Miscellaneous Headers and Connectors .............................................................. 69

7.6.1 Back Panel I/O Connectors ................................ ................................ ..................69

7.6.2 Non-Standard Connector Information Matrix ................................ ........................ 69

7.6.3 POST Code LEDs ................................ ................................ ................................ 70

7.7 Jumper Blocks ................................ ................................ ................................ .....70

8. Absolute Maximum Ratings................................ ................................ ............................. 72

8.1 Mean Time Between Failures (MTBF) Test Results ................................ .............72

9. Design and Environmental Specifications ................................ ................................ .....73

9.1 Power Budget ................................ ................................ ................................ ......73

9.2 Product Regulatory Compliance ................................................................ ...........73

9.2.1 Product Safety Compliance ................................ ................................ ..................73

9.2.2 Product EMC Compliance – Class A Compliance ................................ ................74

9.2.3 Certifications / Registrations / Declarat ions................................ .......................... 74

9.2.4 Product Regulatory Compliance Markings ................................ ........................... 75

9.3 Electromagnetic Compatibility Notices ................................ ................................ .75

9.3.1 Industry Canada (ICES-003) ................................ ................................ ................75

9.3.2 Europe (CE Declaration of Conformity) ................................ ................................ 76

9.3.3 Australia / New Zealand ................................ ................................ .......................76

9.4 Restriction of Hazardous Substances (RoHS) ................................ ...................... 76

9.5 Calculated Mean Time Between Fa ilures (MTBF) ................................ ................76

9.6 Mechanical Specifications ................................ ................................ .................... 77

10. Hardware Monitoring ................................ ................................ ................................ .......78

10.1 Monitored Components ................................ ................................ ........................ 78

10.1.1 Fan Speed Control ................................ ................................ ............................... 79

Glossary ................................ ................................ ................................ ................................ ..80

References ................................ ................................ ................................ .............................. 83

List of Figures Intel® Server Board S3000PT TPS

vi Revision 1.3

List of Figures

Figure 1. Intel® Server Board S3000PT Layout ................................ ................................ ..........4

Figure 2. Intel® Server Board S3000PT Block Diagram ................................ .............................. 6

Figure 3. Memory Bank Label Definition ................................ ................................ ...................14

Figure 4. Interrupt Routing Diagram ................................ ................................ .......................... 19

Figure 5. Intel® ICH7R Controller Interrupt Routing Diagram ................................ ...................20

Figure 6. Setup Utility — Main Screen Display ................................ ................................ ..........29

Figure 7. Setup Utility — Advanced Screen Display ................................ ................................ ..30

Figure 8. Setup Utility — Processor Configuration Screen Dis play ................................ ...........31

Figure 9. Setup Utility — Memory Configuration Screen Display ...............................................32

Figure 10. Setup Utility — SATA Controller Configuration Screen Display ................................ 33

Figure 11. Setup Utility — Serial Port Configuration Screen Display ................................ .........35

Figure 12. Setup Utility — USB Controller Configuration Screen Display ................................ ..36

Figure 13. Setup Utility — PCI Configuration Screen Display ................................ ...................37

Figure 14. Setup Utility — Power Screen Display ................................ ................................ .....38

Figure 15. Setup Utility — Boot Configuration Screen Display ................................ ..................38

Figure 16. Setup Utility — Hardware Health Configuration Screen Display ............................... 39

Figure 17. Setup Utility — Hardware Monitor Screen Display ................................ ...................40

Figure 18. Setup Utility — Security Configuration Screen Display ................................ .............41

Figure 19. Setup Utility — Server Management Configuration Screen Display .........................42

Figure 20. Setup Utility — Console Redirection Screen Display ................................ ................44

Figure 21. Setup Utility — Server Management System Information Screen D isplay................45

Figure 22. Setup Utility — Boot Options Display ................................ ................................ .......46

Figure 23. Setup Utility — Boot Options Display ................................ ................................ .......46

Figure 24. Setup Utility — Error Manager Screen Displa y................................ ......................... 47

Figure 25. Setup Utility — Exit Screen Display................................ ................................ ..........48

Figure 26. Location of Diagnostic LEDs on Server Board ................................ ......................... 59

Figure 27. Back Panel I/O Connections (not to scale) ................................ ............................... 69

Figure 28. Intel® Server Board S3000PT Mechanical Drawing ................................ .................77

Figure 29. Fan Speed Control Block Diagram ................................ ................................ ...........79

Intel® Server Board S3000PT TPS List of Tables

Revision 1.3

vii

List of Tables

Table 1. Server Board Layout Reference ................................ ................................ ....................5

Table 2. Processor Support Matrix ................................ ................................ .............................. 8

Table 3. Segment E Connections ................................ ................................ ............................. 10

Table 4. Supported DDR 2 Modules ................................ ................................ .......................... 10

Table 5. Memory Bank Labels and DIMM Population Order ................................ ......................14

Table 6. Characteristics of Dual/Single Channel Configuration with or without Dynamic Mode .15

Table 7. Segment A Configuration IDs ................................ ................................ ......................16

Table 8. Segment A Arbitration Connections ................................ ............................................16

Table 9. PCI Interrupt Routing/Sharing ................................ ................................ .....................17

Table 10. Interrupt Definitions ................................ ................................................................ ...17

Table 11. Video Modes ................................ ................................ ................................ .............21

Table 12. Intel® 82573E Interface Connector (NIC1)................................ ................................ 22

Table 13. Intel® 82573V Interface Connector (NIC2) ................................ ................................ 22

Table 14. Serial A Header Pin -out................................ ................................ ............................. 23

Table 15. Serial B Header Pin-out................................ ................................ ............................. 23

Table 16. BIOS Setup Page Layout ................................ ................................ .......................... 26

Table 17. BIOS Setup: Keyboard Command Bar ................................ ......................................27

Table 18. Setup Utility — Main Screen Fields ................................ ................................ ...........29

Table 19. Setup Utility — Processor Configuration Screen Fields ................................ .............31

Table 20. Setup Utility — Memory Configuration Screen Fields ................................ ................33

Table 21. Setup Utility — ATA Controller Configuration Screen Fields ................................ .....34

Table 22. Setup Utility — Serial Ports Configuration Screen Fields ................................ ..........35

Table 23. Setup Utility — USB Controller Configuration Screen Fields ................................ .....36

Table 24. Setup Utility — PCI Configuration Screen Fields ................................ ....................... 37

Table 25. Setup Utility — Power Screen FieldsBoot Configuration ................................ ...........38

Table 26. Setup Utility — System Acoustic and Per formance Configuration Screen Fields ......39

Table 27. Setup Utility — Security Configuration Screen Fields ................................ ................41

Table 28. Setup Utility — Server Management Configuration Screen Fields ............................. 42

Table 29. Setup Utility — Console Redirection Configuration Fields ................................ .........44

Table 30. Setup Utility — Server Management System Information Fields ............................... 45

Table 31. Setup Utility — Error Manager Screen Fields ................................ ............................ 46

List of Tables Intel® Server Board S3000PT TPS

viii Revision 1.3

Table 32. Setup Utility — Error Manager Screen Fields ................................ ........................... 47

Table 33. Setup Utility — Error Manager Screen Fields ................................ ............................ 47

Table 34. Setup Utility — Exit Screen Fields................................ ................................ .............48

Table 35. Console Redirection Escape Sequences for Headless Operation ............................. 51

Table 36. Function List................................ ................................ ................................ ..............53

Table 37. Security Features Operating Model ................................ ................................ ...........54

Table 38. Event List ................................ ................................ ..................................................55

Table 39. SMBIOS Type 15 Event Record Format ................................ ................................ ....57

Table 40. Event Type Definition Table ................................ ...................................................... 57

Table 41. POST Progress Cod e LED Example ................................ ................................ .........59

Table 42. POST Code Checkpoints ................................ ................................ .......................... 60

Table 43. POST Error Messages and Handling ................................ ................................ ........63

Table 44. POST Error Beep Codes................................ ................................ ........................... 63

Table 45. Power Connector Pin -out (J3K2)................................................................ ...............64

Table 46. SMBus Header Pin-out (J1A1) ................................ ................................ ..................64

Table 47. Front Panel 14-pin Header Pin-out (J4K3) ................................ ................................ 65

Table 48. VGA Connector Pin -out (J4A1) ................................ ................................ .................65

Table 49. NIC1- Intel® 82573E (10/100/1000) Connector Pin -out (JA2A1)............................... 66

Table 50. NIC2- Intel® 82573V (10/100/1000) Connector Pin -out (JA2A2)............................... 66

Table 51. SATA Connector Pin -out (J1C2, J1C3)................................ ................................ .....66

Table 52. External DB9 Serial A Port Pin -out (J3A1) ................................ ................................ 67

Table 53. Internal 9-pin Serial B Port Pin-out (J2B1)................................ ................................ .67

Table 54. USB Connectors Pin-out (JA2A1) ................................ ................................ .............67

Table 55. Optional USB Connection Header Pin -out (J1C1)................................ .....................68

Table 56. 8-pin Fan Headers Pin-out (J3K1,J4K2,J4K1)................................ .......................... 68

Table 57. Non-Standard Connector Information ................................ ................................ ........70

Table 58. CMOS Clear Jumper Options (J1B1) ................................ ................................ ........70

Table 59. NIC1 Firmware Update Jumper Options (J1B2)................................ ........................ 71

Table 60. System Maintenance Mode Jumper Options (J1B3)................................ .................71

Table 61. Absolute Maximum Ratings ................................ .......................................................72

Table 62. The Board Power Budget ................................ ................................ .......................... 73

Table 63. Product Certification Markings ................................ ................................ ..................75

Table 64. Calculated MTBF Data ................................ ................................ .............................. 76

Table 65. Monitored Components ................................................................ ............................. 78

Intel® Server Board S3000PT TPS Introduction

Revision 1.3

1

1. Introduction

This Intel® Server Board S3000PT Technical Product Specification (TPS) provides a high -level
technical description for the Intel® Server Board S3000PT. It details the architecture and
feature set for all functional sub -systems that make up the server board.

1.1 Section Outline

This document is divided into the following chapters:

 Section 1 – Introduction
 Section 2 – Server Board Overview
 Section 3 – Functional Architecture
 Section 4 – System BIOS
 Section 5 – Platform Management Architecture
 Section 6 – Error Reporting and Handling
 Section 7 – Connectors and Jumper Blocks
 Section 8 – Absolute Maximum Ratings
 Section 9 – Design and Environmental Specifications
 Section 10 – Hardware Monitoring
 Glossary
 References

1.2 Server Board Use Disclaimer

Intel® server boards contain a number of high -density VLSI* and power delivery components
that need adequate airflow to cool. Intel’s own chassis are designed and tested to meet the
intended thermal requirements of these components when the fully integrated system is used
together. It is the responsibility of the system integrator that chooses not to use Intel developed
server building blocks to consult vendor datasheets and operating parameters to determine the
amount of airflow required for their specific application and environmental conditions. Intel
Corporation cannot be held responsible if components fail or the server board does not operate
correctly when used outside any of its published operating or non -operating limits.

Server Board Overview Intel® Server Board S3000 PT TPS

2 Revision 1.3

2. Server Board Overview

The Intel® Server Board S3000PT is a monolithic printed circuit board with features that
support the UP server market.

2.1 Intel® Server Board S3000PT Feature Set

The Intel® Server Board S3000PT supports the following feature set:

 Processor and Front Side Bus (FSB) support

- Supports Intel® Xeon® processor 3000 sequence, Intel® Core™2 Extreme Edition,
Intel® Core™2 Duo, Intel® Pentium® Processor Extreme Edition,Intel® Pentium® D
Processor,Intel® Pentium® 4 Processor, Intel® Celeron® D Processor in the Intel®
LGA775 package

- Supports Intel® Dual Core Architecture

- Supports Hyper-Threading Technology

- Supports Intel® Extended Memory System 64 Technology (Intel® EM64T)

 Intel® 3000 Chipset components

- Intel® 3000 MCH Memory Controller Hub

- Intel® ICH7R I/O Controller

- 12-deep In-order Queue

 Memory System

- Four DIMM sockets supporting DDR2 533/667MHz DIMMs

- Data bandwidth per channel of 4.2GB/s or 8.4GB/s in dual channel when using

DDR2 667MHz

- Support for up to two DDR2 channels for a total of four DIMMs (2 DIMMs / c hannel)

providing up to 8-GB max memory capacity.

- Support for 512-MB, 1-GB and 2-GB DRAM modules

 I/O Subsystem
 Board I/O Subsystem:

- Segment A: One embedded ATI* ES1000 video controller (Supports PCI

Specification, Rev 2.3).

- Segment B: One x1 PCI Express* resource implemented as an embedded Intel®

82573V 10/100/1000 gigabit Ethernet Controller

- Segment C: One x1 PCI Express* resource implemented as an embedded Intel®

82573E 10/100/1000 gigabit Ethernet Controller

- Segment D: One x8 PCI Express* resource implemented as a riser slot supporting

single x1/x4/x8 PCI Express* add -in cards through a riser

 Serial ATA host controller
 Two independent SATA ports suppo rt data transfer rates up to 3.0 Gb/s (300MB/s) per

port

 Universal Serial Bus 2.0 (USB)

Intel® Server Board S3000PT TPS Server Board Overview

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3

 Two external USB ports with an additional internal header providing two optional USB

ports for front panel support.

- Supports wake-up from sleeping states S1 -S4 (S3 not supported)

- Supports legacy keyboard/m ouse connections when using PS /2-USB dongle

 LPC (Low Pin Count) bus segment with one embedded device

- Super I/O controller chips providing all PC -compatible I/O (two serial COM ports)
and integrated hardware monitoring

- LC Super I/O = SMSC* SCH5027 or SMSC* SCH5017

 Customized 14-pin SSI front panel 2x9 power connectors
 Fan support

- Three customized 8-pin fan headers with PWM and Tach capability

- One 4-pin fan header without PWM and Tach capability

 Intel® Light-guided Diagnostic LEDs to display POST code indicato rs during boot

Server Board Overview Intel® Server Board S3000PT TPS

4 Revision 1.3

The following figure shows the board layout of the Intel® Server Board S3000PT. Each
connector and major component is identified by letter and is identified in Table 1.

Figure 1. Intel® Server Board S3000PT Layout

Intel® Server Board S3000PT TPS Server Board Overview

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5

Table 1. Server Board Layout Reference

Ref

Description

Ref

Description

A

Post LEDs

S

Battery
B

PCI-E x8 riser slot

T

USB 3 and 4 header
C

BIOS Flash(SPI)

U

SATA port 2
D

Intel® 82802 ICH7R

V

SATA port 1
E

Clock generator

W

Serial B header
F

SMSC* SCH5027 or SMSC* SCH5017
Super I/O (SIO)

X

Video Memory

G

Intel®3000 Memory Controller Hub
(MCH)

Y

Intel® 82573E LAN Controller

H

775-Land (LGA) CPU Socket

Z

Intel® AMT firmware (NIC1) update jumper
I

System Fan 1 (8-pin)

AA

Clear CMOS jumper
J

System Fan 2 (8-pin)

BB

NIC1 SPI Flash
K

System Fan 3 (8-pin)

CC

Intel® 82573V LAN Controller
L

2 x 7 Front Panel header

DD

SMBus Connector
M

2 x 9 Power connector

EE

NIC1 RJ-45 and USB 1 and 2 connector
N

Auxiliary Fan (4-pin)

FF

NIC2 RJ-45 connector
O

Memory Slot DIMM 2B

GG

NIC2 SPI EEPROM
P

Memory Slot DIMM 1B

HH

Serial A connector
Q

Memory Slot DIMM 2A

JJ

VGA connector
R

Memory Slot DIMM 1A

KK

ATI* ES1000 video controller

Functional Architecture Intel® Server Board S3000PT TPS

6 Revision 1.3

3. Functional Architecture

This section provides a high -level description of the functionality associated with the
architectural blocks that make up the Intel® Server Board S3000PT.

Figure 2. Intel® Server Board S3000PT Block Diagram

Intel® Server Board S3000PT TPS Functional Architecture

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3.1 Processor Sub-System

The Intel® Server Board S3000PT supports the following:

 Intel® Xeon® processor 3000 sequence
 Intel® Core™2 Extreme Edition
 Intel® Core™2 Duo
 Intel® Pentium® Processor Extreme Edition
 Intel® Pentium® D Processor
 Intel® Pentium® 4 Processor
 Intel® Celeron® D Processor

The processors, built on 90nm and 65nm process technology in the 775 -land package, utilize
Flip-Chip Land Grid Array (FC-LGA4) package technology and plug into a 775-land LGA socket
(which is referred to as the Intel®LGA775 socket).

The processors in the 775-land package, like their predecessors in the 478 -pin package, are
based on the same Pentium® 4 micro -architecture. They maintain compatibility with 32 -bit
software written for the IA -32 instruction set, while supporting 64 -bit native mode operation
when coupled with supported 64 -bit operating systems and applications.

The Celeron® Processor is not available with dual core, Hyper -Threading Technology or Intel®
EM64T.

3.1.1 Processor Voltage Regulator Down (VRD)

The Intel® Server Board S3000PT has a VRD (Voltage Regulator Down) to
support one processor. It is compliant with the VRD 11 DC-DC Converter Design
Guide Line and provides a maximum of 125A, which is capable of supporting the
requirements for the following processors:

 Intel® Xeon® processor 3000 sequence
 Intel® Core™2 Extreme Edition
 Intel® Core™2 Duo
 Intel® Pentium® Processor Extreme Edition
 Intel® Pentium® D Processor
 Intel® Pentium® 4 Processor
 Intel® Celeron® D Processor

The board hardware monitors the processor V TTEN (Output enable for VTT) pin before turning
on the VRD. If the VTTEN pin of the processors is not asserted, the Power ON Logic will not
turn on the VRD.

Functional Architecture Intel® Server Board S3000PT TPS

8 Revision 1.3

3.1.2 Reset Configuration Logic

The BIOS determines the processor stepping, cache size, etc., through the CPUID instruction.
The processor information is read at every system power -on.
Note: The processor speed is the processor power -on reset default value. No manual

processor speed setting options exist either in the form of a BIOS setup option or jumpers.

3.1.3 Processor Support

The Intel® Server Board S3000PT supports one processor in the Intel®LGA775 package. The
support circuitry on the server board consists of the following:

 One Intel® LGA775 processor socket supporting:

o Intel® Xeon® processor 3000 sequence
o Intel® Core™2 Extreme Edition processor
o Intel® Core™2 Duo processor
o Intel® Pentium® Processor Extreme Edition processor
o Intel® Pentium® D processor
o Intel® Pentium® 4 processor
o Intel® Celeron® D processor

 Processor host bus AGTL+ support circuitry.

Table 2. Processor Support Matrix

Processor Name

Socket

Core

Frequency

Cache size

FSB Frequency

Intel® Xeon® 3000
Processor

Intel® LGA775

4MB L2

800/1066MHz
Intel® Xeon® 3000

Processor

Intel® LGA775

2MB L2

800/1066MHz
Intel® Core™2 Extreme

Edition

Intel® LGA775

2.93GHz

4MB L2

1066MHz

Intel® Core™2 Duo

Intel® LGA775
Intel® Pentium® 4

Processor Extreme Edition

Intel® LGA775

3.2GHz

2 x 1MB L2

800MHz
Intel® Pentium® 4

Processor Extreme Edition

Intel® LGA775

3.73GHz

2MB L2

1066MHz

Intel® Pentium® D

Intel® LGA775

3.2 – 4.0GHz

2 x 1MB L2

800MHz
Intel® Pentium® 4

Intel® LGA775

3.2 – 4.0GHz

1MB or 2MB L2

800MHz
Intel® Celeron® D

Intel®LGA775

2.26 – 3.2 GHz

256K L2

533MHz

Intel® Server Board S3000PT TPS Functional Architecture

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Note: For a complete list of all supported processors, please visit the Intel® Server Board

S3000PT support site located at the following URL:

http://support.intel.com/support/motherboards/server/S3000PT/

In addition to the circuitry described above, the processor subsystem contains the following:

 Reset configuration logic

3.2 Intel®3000 Chipset

The Intel® Server Board S3000PT is designed around the Intel® 3000 chipset. The chipset
provides an integrated I/O bridg e and memory controller, and a flexible I/O subsystem core
(PCI Express*). The chipset consists of three primary components.

3.2.1 Memory Controller Hub (MCH)

3.2.1.1 Intel® 3000 Chipset MCH: Memory Control Hub

The MCH accepts access requests from the host (processor) b us and directs those accesses to
memory or to one of the PCI Express or PCI buses. The MCH monitors the host bus, examining
addresses for each request. Accesses may be directed to the following:

 A memory request queue for subsequent forwarding to the memor y subsystem
 An outbound request queue for subsequent forwarding to one of the PCI Express or PCI

buses

The MCH also accepts inbound requests from the Intel® ICH7R. The MCH is responsible for
generating the appropriate controls to control data transfer to a nd from memory.

The MCH is a 1202-ball FC-BGA device and uses the proven components of the following
previous generations:

 Pentium® Processor Extreme Edition , Pentium® D Processor , Pentium® 4 Processor,

Celeron® D Processor bus interface unit

 Hub interface unit
 PCI Express interface unit
 DDR2 memory interface unit

The MCH incorporates an integrated PCI Express* interface. The PCI Express* interface allows
the MCH to directly interface with the PCI Express* devices. The MCH also increases the main
memory interface bandwidth and maximum memory configuration with a 72-bit wide memory
interface.

The MCH integrates the following main functions:

 An integrated high performance main memory subsystem
 A PCI Express* bus which provides an interface to the PCI-Express devices( Fully

compliant to the PCI Express* Base Specification, Rev 1.0a )

 A DMI which provides an interface to the Intel® ICH7R

Functional Architecture Intel® Server Board S3000PT TPS

10 Revision 1.3

Other features provided by the MCH include the following:

 Full support of ECC on the DDR2 memory bus
 Twelve deep in-order queue, two deep defer queue
 Full support of un-buffered DDR2 ECC DIMMs
 Support for 256-MB, 512-MB, 1-GB and 2-GB DDR2 memory modules

3.2.1.2 Segment D PCI-Express x8

In this board, the MCH PCIe Lanes 0~7 are connected to an x8 PCI -E riser connector directly
through the MCH. It can support x1, x4, and x8 PCI-E add-in cards through a riser card.

Table 3. Segment E Connections

Lane

Device

Lane 0~7

Slot 1 (PCI Express* x8)

3.2.1.3 MCH Memory Sub-System Overview

The MCH supports a 72-bit wide memory sub-system that can support a maximum of 8 GB of
DDR2 memory using 2GB DIMMs. This configuration needs external registers for buffering the
memory address and control signals. The four chip selects are registered inside the MCH and
need no external registers fo r chip selects.

The memory interface runs at 533/667MT/s. The memory interface supports a 72 -bit wide
memory array. It uses seventeen address lines (BA [2:0] and MA [13:0]) and supports 256-MB,
512-MB, 1-GB, and 2-GB DRAM densities. The DDR DIMM interface supports single-bit error
correction, and multiple bit error detection .

3.2.1.3.1 DDR2 Configurations

The DDR2 interface supports up to 8 GB of main memory and supports single - and double­density DIMMs. The DDR2 can be any industry-standard DDR2. The following table shows the
DDR2 DIMM technology supported.

Table 4. Supported DDR2 Modules

DDR2-533/667 Un-buffered

SDRAM Module Matrix

DIMM

Capacity

DIMM

Organization

SDRAM

Density

SDRAM

Organization

# SDRAM

Devices/rows/Banks

# Address bits

rows/Banks/column

256MB

32M x 72

256Mbit

32M x 8

9 /1 / 4

13 / 2 / 10
512MB

64M x 72

256Mbit

32M x 8

18 / 2 / 4

13 / 2 / 10
512MB

64M x 72

512Mbit

64M x 8

9 / 1 / 4

14 / 2 / 10
1GB

128M x 72

512Mbit

64M x 8

18 / 2 / 4

14 / 2 / 10
1GB

128M x 72

1Gbit

128M x 8

9 / 1 / 8

14 / 4 / 10
2GB

256M x 72

1Gbit

128M x 8

18 / 2 / 8

14 / 8 / 10

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3.2.2 I/O Controller Hub

3.2.2.1 Intel® ICH7R: I/O Controller Hub 7R

The Intel® ICH7R controller has several components. It provides the interface for a
32-bit/33-MHz PCI bus. The Intel® ICH7R controller can be both a master and a target on that
PCI bus and includes a USB 2.0 controller and an IDE controller. The Intel® ICH7R controller is
also responsible for much of the power management functions, with ACPI control registers built
in. It also provides a number of GPIO pins and has the LPC bus to support low -speed Legacy
I/O.

The MCH and Intel® ICH7R chips provide the pathway between the processor and the I/O
systems. The MCH is responsible for accepting access requests from the host (pro cessor) bus,
and directing all I/O accesses to one of the PCI buses or Legacy I/O locations. If the cycle is
directed to one of the PCI Express* segments, the MCH communicates with the PCI Express*
devices (add-in card, on board devices) through the PCI Express* interface. If the cycle is
directed to the Intel® ICH7R controller, the cycle is output on the MCH’s DMI bus. All I/O for the
board, including PCI and PC -compatible I/O, is directed through the MCH and then through the
Intel® ICH7R provided PCI buses.

The Intel® ICH7R controller is a multi-function device, housed in a 652-pin mBGA device. It
provides the following:

 A DMI bus
 A PCI 32-bit/33-MHz interface
 An IDE interface
 An integrated serial ATA Host controller
 A USB controller
 A PCI Express* x4 inte rface
 Two PCI Express* x1 interface
 A power management controller

Each function within the Intel® ICH7R controller has its own set of configuration registers. Once
configured, each appears to the system as a distinct hardware controller sharing the same PC I
bus interface.

The primary role of the Intel® ICH7R controller is providing the gateway to all PC -compatible
I/O devices and features. The board uses the following Intel® ICH7R features:

 PCI 32-bit/33MHz interface to dedicated ATI* ES1000 video subsystem
 LPC bus interface
 x1 PCI Express* interface for Intel® 82573E Gigabit Ethernet Controller
 x1 PCI Express* interface for Intel® 82573 V Gigabit Ethernet Controller
 DMI (Direct Media Interface)
 Integrated dual-port Serial ATA Host controller
 Universal Serial Bus (USB) 2.0 interface
 PC-compatible timer/counter and DMA controllers
 APIC and 82C59 interrupt controller

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 Power management
 System RTC
 Supports the SMBus 2.0 Specification
 General-purpose I/O (GPIO)

The following are the descriptions of how each supporte d feature is used for the Intel® ICH7R
controller on the board.

3.2.2.1.1 SATA Controller

The Intel® ICH7R controller has an integrated SATA host controller that supports independent
DMA operation on four ports and supports data transfer rates of up to 3.0 Gb/s (300 MB/s).

3.2.2.2 Compatibility Modules (DMA Controller, Timer/Counters, Interrupt
Controller)

The DMA controller incorporates the logic of two Intel® 82C37 DMA controllers, with seven
independently programmable channels. Channels 0 –3 are hardwired to 8-bit, count-by-byte
transfers, and channels 5 –7 are hardwired to 16-bit, count-by-word transfers. Any two of the
seven DMA channels can be programmed to support fast Type -F transfers.

The timer/counter block contains three counters that are equivalent in function to t hose found in
one Intel® 82C54 programmable interval timer. These three counters are combined to provide
the system timer function, and speaker tone. The 14.31818 -MHz oscillator input provides the
clock source for these three counters.

The Intel® ICH7R controller provides an ISA-Compatible Programmable Interrupt Controller
(PIC) that incorporates the functionality of two, 82C59 interrupt controllers. The two interrupt
controllers are cascaded so that 14 external and two internal interrupts are possible. In addition,
the Intel® ICH7R controller supports a serial interrupt scheme.

All of the registers in these modules can be read and restored. This is required to save and
restore the system state after power has been removed and restored to the platform.

3.2.2.2.1 Advanced Programmable Interrupt Controller (APIC)

In addition to the standard ISA compatible Programmable Interrupt controller (PIC) described in
the previous section, the Intel® ICH7R incorporates the Advanced Programmable Interrupt
Controller (APIC).

3.2.2.2.2 Universal Serial Bus (USB) Controller

The Intel® ICH7R controller contains one EHCI* USB 2.0 controller and four USB ports. The
USB controller moves data between main memory and up to four USB connectors. All ports
function identically and with the same bandwidth . The Intel® Server Board S3000PT
implements four ports on the board.

Two external USB ports are provided on the back of the server board. The Universal Serial Bus
Specification, Revision 1.1, defines the external connectors.

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The third/fourth USB port is optional and can be accessed by cabling from an internal 9 -pin
connector located on the server board to an external USB port located either in front of or on
the rear of a given chassis.

3.2.2.2.3 Enhanced Power Management

The Intel® ICH7R controller’s power management functions include enhanced clock control and
various low-power (suspend) states (e.g., Suspend -to-RAM and Suspend-to-Disk). A hardware­based thermal management circuit permits a software-independent entrance to low -power
states. The Intel® ICH7R controller contains full support for the Advanced Configuration and
Power Interface (ACPI) Specification, Revision 3.0. The server board supports sleep states S1,
S4, and S5.

3.3 Memory Sub-System

The memory interface between the MCH and the DIMMs is a 72-bit (ECC) wide interface.
There are two banks of DIMMs, labeled 1 and 2. Bank 1 contains DIMM socket locations

DIMM_1A and DIMM_1B. Bank 2 contains DIMM socket locations DIMM _2A and DIMM_2B.
The sockets associated with each bank , or “channel,” are located next to each other, and the
DIMM socket identifiers are marked on the base board silkscreen, near the DIMM socket. When
only two DIMM modules are being used, the population order must be DIMM_1A, DIMM_1B to
ensure dual-channel operating mode.

In order to operate in dual-channel dynamic paging mode, the following conditions must be met:

 Two identical DIMMs are installed, one each in DIMM_1A and DIMM_1B
 Four identical DIMMs are installed (one in each socket location)

Note: Installing only three DIMMs is not supported . Do not use DIMMs that are not “matched”
(same type and speed). Use of identical memory parts is always the preferred method.

See Figure 3 for reference.
The system design is free to populate or not to populate any rank on either channel, including

either degenerate single channel case.

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DIMM and memory configurations must adhere to the following:

 DDR2 533/667, un-buffered, DDR2 DIMM modules
 DIMM organization: x72 ECC
 Pin count: 240
 DIMM capacity:512 MB, 1 GB and 2 GB DIMMs
 Serial PD: JEDEC Rev 2.0
 Voltage options: 1.8 V
 Interface: SSTL2

Table 5. Memory Bank Labels and DIMM Population Order

Location

DIMM Label

Channel

Population Order

J2D1

(DIMM_1A)

A

1
J1D2

(DIMM_2A)

A

3
J1D3

(DIMM_1B)

B

2
J1D1

(DIMM_2B)

B

4

Figure 3. Memory Bank Label Definition

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Table 6. Characteristics of Dual/Single Channel Configuration with or without Dynamic Mode

Throughput Level

Configuration

Characteristics

Highest

Dual channel with dynamic paging mode

All DIMMs matched
Dual channel without dynamic paging mode

DIMMs matched from Channel A to Channel B
DIMMs not matched within channels
Single channel with dynamic paging mode

Single DIMM or DIMMs matched within a
channel

Lowest

Single channel without dynamic paging
mode

DIMMs not matched

3.3.1 Memory DIMM Support

The board supports un-buffered (not registered) DDR2 533/667 ECC DIMMs operating at
533/667MT/s. Only DIMMs tested and qualified by Intel o r a designated memory test vendor are
supported on this board. A list of qualified DIMMs is available at

http://support.intel.com/support/motherboards/server/ .

Note: All DIMMs are supported by design, but only fully qualified DIMMs will be supported on
the board.

The minimum supported DIMM size is 256 MB. Therefore, the minimum main memory
configuration is 1 x 256 MB or 256 MB. The largest size DIMM supported is 2 GB and as such,
the maximum main memory configuration is 8 GB implemented by 4 x 2-GB DIMMs.

 Only un-buffered DDR2 533/667 compliant, ECC x8 or x16 memory DIMMs are

supported.

 ECC single-bit errors (SBE) will be corrected; multiple -bit error (MBE) will only be

detected.

 Intel® Server Board S3000PT supports Intel® x4 Single Device Data Correction with x4

DIMMs.

 The maximum memory capacity is 8 GB via four 2 -GB DIMM modules.
 The minimum memory capacity is 256 MB via a single 256-MB DIMM module.

3.4 I/O Sub-System

3.4.1 PCI Subsystem

There are three independent PCI bus segments directed from the Intel® ICH7R controller on
the Intel® Server Board S3000PT. PCI Segment A is a legacy PCI bus while PCI Segments B
and C are PCI Express*.

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3.4.1.1.1 Device IDs (IDSEL)

Each device under the PCI hub bridge has its IDSEL signal connected to one bit of AD (31:16),
which acts as a chip select on the PCI bus segment in configuration cycles. This determines a
unique PCI device ID value for use in configuration cycles. The following table shows the bit to
which each IDSEL signal is attached for Segment A devices and the corresponding device
description.

Table 7. Segment A Configuration IDs

IDSEL Value

Device

20

ATI* ES1000 video controller

3.4.1.1.2 Segment A Arbitration

PCI Segment A supports two PCI devices: the Intel® ICH7 R and one PCI bus master (NIC). All
PCI masters must arbitrate for PCI access, using resources supplied by the Intel® ICH7 R. The
host bridge PCI interface (ICH7 R) arbitration lines REQx* and GNTx* are a special case in that
they are internal to the host bridge. The following table defines the arbitration connections.

Table 8. Segment A Arbitration Connections

Server Board Signals

Device

PCI REQ_N4/GNT_N4

ATI* ES1000 video controller

3.4.2 Interrupt Routing

The board interrupt architecture accommodates both PC -compatible PIC mode and APIC mode
interrupts through use of the integrated I/O APICs in the Intel® ICH7R controller.

3.4.2.1 Legacy Interrupt Routing

For PC-compatible mode, the Intel® ICH7R controller provides two 82C59-compatible interrupt
controllers. The two controllers are cascaded with interrupt levels 8 -15 entering on level 2 of the
primary interrupt controller (standard PC configuration). A single interrupt signal is presented to
the processors, to which only one processor will respond for servicing. The Intel® ICH7R
contains configuration registers that define which interrupt source logically maps to I/O APIC
INTx pins.

The Intel® ICH7R controller handles both PCI and IRQ interrupts. The Intel® ICH7R translates
these to the APIC bus. The numbers in the following table indicate the Intel® ICH7R PCI
interrupt input pin to which the associated device interrupt (INTA, INTB, INTC, INTD, INT E,
INTF, INTG, INTH for PCI bus and PXIRQ0, PXIRQ1, PXIRQ2, PXIRQ3 for PCI-X bus) is
connected. The Intel® ICH7R I/O APIC exists on the I/O APIC bus with the processors.

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Table 9. PCI Interrupt Routing/Sharing

Interrupt

INT A

INT B

INT C

INT D

ATIES 1000

PIRQC

3.4.2.2 APIC Interrupt Routing

For APIC mode, the ser ver board interrupt architecture incorporates three Intel® I/O APIC
devices to manage and broadcast interrupts to local APICs in each processor. The Intel® I/O
APICs monitor each interrupt on each PCI device, including PCI slots in addition to the ISA
compatibility interrupts IRQ (0 -15).

When an interrupt occurs, a message corresponding to the interrupt is sent across a three -wire
serial interface to the local APICs. The APIC bus minimizes interrupt latency time for
compatibility interrupt sources. The I/O APICs can also supply greater than 16 interrupt levels to
the processor(s). This APIC bus consists of an APIC clock and two bi -directional data lines.

3.4.2.3 Legacy Interrupt Sources

The following table recommends the logical interrupt mapping of interrupt sourc es on the board.
The actual interrupt map is defined using configuration registers in the Intel® ICH7R controller.

Table 10. Interrupt Definitions

ISA Interrupt

Description

INTR

Processor interrupt
NMI

NMI to processor
IRQ0

System timer
IRQ1

Keyboard interrupt
IRQ2

Slave PIC
IRQ3

Serial port 1 interrupt from Super I/O* device, user-configurable
IRQ4

Serial port 1 interrupt from Super I/O* device, user-configurable
IRQ5

IRQ6

Floppy disk
IRQ7

Generic
IRQ8_L

Active low RTC interrupt
IRQ9

SCI*
IRQ10

Generic
IRQ11

Generic
IRQ12

Mouse interrupt
IRQ13

Floating point processor

IRQ14

Compatibility IDE interrupt from prim ary channel IDE devices 0 and 1
IRQ15

Secondary IDE cable
SMI*

System Management Interrupt. General -purpose indicator sourced by the Intel® ICH7R
Controller to the processors.

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3.4.2.4 Serialized IRQ Support

The Intel® Server Board S3000PT supports a serialized interrupt delivery mechanism.
Serialized Interrupt Requests (SERIRQ) consists of a start frame, a minimum o f 17 IRQ / data
channels, and a stop frame. Any slave device in the quiet mode may initiate the start frame.
While in the continuous mode, the start frame is initiated by the host controller.

3.5 PCI Error Handling

The PCI bus defines two error pins, PERR# and SERR#, for reporting PCI parity errors and
system errors, respectively. In the case of PERR#, the PCI bus master has the option to retry
the offending transaction, or to report it using SERR#. All other PCI -related errors are reported
by SERR#. SERR# is routed to the NMI if enabled by the BIOS.

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Figure 4. Interrupt Routing Diagram

IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ8
IRQ9
IRQ10
IRQ11
IRQ12

IRQ13

IRQ14
IRQ15
IRQ16
IRQ17
IRQ18
IRQ19
IRQ20
IRQ21
IRQ22
IRQ23

Intel® ICH7R

Controller IOAPIC 0

Intel®

ICH7R

Controller

MCH

Intel®

ICH7R

Controller

8259PIC

CPU

INTR

DMI INTERFACE

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20 Revision 1.3

Figure 5. Intel® ICH7R Controller Interrupt Routing Diagram

PIRQB#

PIRQD#

PIRQC#

PIRQE#

PIRQF#

PIRQG#

PIRQH#

PIRQA#

Super I/O

Timer

Keyboard

Serial Port2/ISA

Serial Port1/ISA

ISA

Floppy/ISA

ISA

RTC

SCI/ISA

ISA

ISA

Mouse/ISA

Coprocessor Error

P_IDE/ISA

Not Used

Cascade

Serialized IRQ Interface

SERIRQ

N/A

N/A

N/A

SERIRQ

Intel® ICH7R

Controller Interrupt

Routing

N/A

N/A

ATI ES1000

N/A

N/A