Intel order number G42278-002
Revision 1.0
February, 2012
Enterprise Platforms and Services Division – Marketing
Intel® Server Board S2600CO Family
Technical Product Specification
Revision History Intel® Server Board S2600CO Family TPS
ii
Date
Revision
Number
Modifications
February, 2012
1.0
Initial release.
Revision History
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Copyright © 2012 Intel Corporation
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Table of Contents
1. Introduction .......................................................................................................................... 1
1.1 Chapter Outline ........................................................................................................ 1
1.2 Server Board Use Disclaimer .................................................................................. 1
2. Product Overview ................................................................ ................................................. 3
2.1 Server Board Connector and Component Layout .................................................... 5
2.2 Server Board Dimensional Mechanical Drawings .................................................. 10
3. Functional Architecture Overview .................................................................................... 15
3.1 Processor Support ................................................................................................. 16
3.1.1 Processor Socket Assembly .................................................................................. 16
3.1.2 Processor Population Rules .................................................................................. 16
3.1.3 Processor Initializion Error Summary .................................................................... 17
3.2 Processor Function Overview ................................................................................ 19
3.2.1 Intel® QuickPath Interconnect ................................................................................ 20
3.2.2 Integrated Memory Controller (IMC) and Memory Subsystem .............................. 21
3.2.3 Processor Integrated I/O Module (IIO) ................................................................... 30
3.3 Intel® C600-A Chipset Functional Overview .......................................................... 34
3.3.1 Low Pin Count (LPC) Interface .............................................................................. 34
3.3.2 Universal Serial Bus (USB) Controller ................................................................... 35
3.3.3 On-board Serial Attached SCSI (SAS)/Serial ATA (SATA)/RAID Support and
Options 35
3.3.4 Manageability ......................................................................................................... 37
3.4 Integrated Baseboard Management Controller Overview ...................................... 38
3.4.1 Super I/O Controller ............................................................................................... 39
3.4.2 Graphics Controller and Video Support ................................................................. 40
3.4.3 Baseboard Management Controller ....................................................................... 41
4. Technology Support .......................................................................................................... 43
4.1 Intel® Trusted Execution Technology ..................................................................... 43
4.2 Intel® Virtualization Technology – Intel® VT-x/VT-d/VT-c ....................................... 43
4.3 Intel® Intelligent Power Node Manager .................................................................. 44
4.3.1 Hardware Requirements ........................................................................................ 45
5. System Security ................................................................................................................. 46
5.1 BIOS Password Protection .................................................................................... 46
5.2 Trusted Platform Module (TPM) Support ............................................................... 47
5.2.1 TPM security BIOS ................................................................................................ 47
5.2.2 Physical Presence ................................................................................................. 48
5.2.3 TPM Security Setup Options ................................................................................. 48
5.3 Intel® Trusted Execution Technology ..................................................................... 50
6. Platform Management Functional Overview .................................................................... 52
6.1 Baseboard Management Controller (BMC) Firmware Feature Support................. 52
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6.1.1 IPMI 2.0 Features .................................................................................................. 52
6.1.2 Non IPMI Features ................................................................................................. 53
6.1.3 New Manageability Features ................................................................................. 54
6.2 Advanced Configuration and Power Interface (ACPI) ........................................... 56
6.3 Power Control Sources .......................................................................................... 56
6.4 BMC Watchdog ...................................................................................................... 57
6.5 Fault Resilient Booting (FRB) ................................................................................ 57
6.6 Sensor Monitoring .................................................................................................. 58
6.7 Field Replaceable Unit (FRU) Inventory Device .................................................... 58
6.8 System Event Log (SEL) ....................................................................................... 59
6.9 System Fan Management ...................................................................................... 59
6.9.1 Thermal and Acoustic Management ...................................................................... 59
6.9.2 Fan Profiles ............................................................................................................ 60
6.9.3 Thermal Sensor Input to Fan Speed Control ......................................................... 60
6.9.4 Memory Thermal Throttling .................................................................................... 62
6.10 Messaging Interfaces ............................................................................................. 62
6.10.1 User Model ............................................................................................................ 63
6.10.2 IPMB Communication Interface ............................................................................. 63
6.10.3 LAN interface ......................................................................................................... 64
6.10.4 Address Resoluton Protocol (ARP) ....................................................................... 70
6.10.5 Internet Control Message Protocol (ICMP) ............................................................ 70
6.10.6 Virtual Local Area Network (VLAN) ....................................................................... 70
6.10.7 Secure Shell (SSH) ................................................................................................ 71
6.10.8 Serial-over-LAN (SOL 2.0) ..................................................................................... 71
6.10.9 Platform Event Filter .............................................................................................. 71
6.10.10 LAN Alterting .......................................................................................................... 72
6.10.11 Altert Policy Table .................................................................................................. 72
6.10.12 SM-CLP (SM-CLP Lite) ......................................................................................... 73
6.10.13 Embeded Web Server ........................................................................................... 73
6.10.14 Virtual Front Panel ................................................................................................. 75
6.10.15 Embedded Platform Debug ................................................................................... 75
6.10.16 Data Center Management Interface (DCMI) .......................................................... 78
6.10.17 Lightweight Directory Authentication Protocol (LDAP) .......................................... 78
7. Advanced Management Features Support (RMM4)......................................................... 79
7.1 Keyboard, Video, and Mouse (KVM) Redirection .................................................. 79
7.1.1 Remote Console .................................................................................................... 80
7.1.2 Performance .......................................................................................................... 80
7.1.3 Security .................................................................................................................. 81
7.1.4 Availability .............................................................................................................. 81
7.1.5 Usage .................................................................................................................... 81
7.1.6 Force-enter BIOS Setup ........................................................................................ 81
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7.2 Media Redirection .................................................................................................. 81
7.2.1 Availability .............................................................................................................. 82
7.2.2 Network Port Usage ............................................................................................... 82
8. On-board Connector/Header Overview ............................................................................ 83
8.1 Power Connectors ................................................................................................. 83
8.1.1 Main Power ............................................................................................................ 83
8.1.2 CPU Power Connectors ......................................................................................... 83
8.1.3 PCIe Card Power Connectors ............................................................................... 84
8.2 Front Panel Headers and Connectors ................................................................... 84
8.2.1 SSI Front Panel Header ......................................................................................... 84
8.2.2 Front Panel USB Connector .................................................................................. 88
8.2.3 Intel Local Control Panel Connector ...................................................................... 88
8.3 On-Board Storage Connectors .............................................................................. 88
8.3.1 SATA Only Connectors: 6 Gbps ............................................................................ 88
8.3.2 SATA/SAS Connectors .......................................................................................... 89
8.3.3 SAS SGPIO Connectors ........................................................................................ 89
8.3.4 Intel® RAID C600 Upgrade Key Connector ............................................................ 89
8.3.5 HSBP_I2C Header ................................................................................................. 89
8.3.6 HDD LED Header .................................................................................................. 90
8.3.7 Internal Type-A USB Connector ............................................................................ 90
8.3.8 Internal 2mm Low Profile eUSB SSD Connector ................................................... 90
8.4 Management and Security Connectors ................................................................. 90
8.4.1 RMM4_Lite Connector ........................................................................................... 90
8.4.2 RMM4_NIC connector ........................................................................................... 91
8.4.3 TPM Connector ...................................................................................................... 91
8.4.4 PMBUS Connector ................................................................................................ 91
8.4.5 Chassis Intrustion Header ..................................................................................... 91
8.4.6 IPMB Connector .................................................................................................... 92
8.5 Fan Connectors ..................................................................................................... 92
8.5.1 System FAN Connectors ....................................................................................... 92
8.5.2 CPU FAN Connector ............................................................................................. 93
8.6 Serial Port Connectors ........................................................................................... 93
8.6.1 Serial Port A connector (DB9) ............................................................................... 93
8.6.2 Serial Port B Connector ......................................................................................... 93
8.6.3 Video Connector .................................................................................................... 93
8.7 Other Connectors and Headers ............................................................................. 94
8.7.1 FAN BOARD_I2C Connector ................................................................................. 94
8.7.2 IEEE 1394b Connector .......................................................................................... 94
9. Reset and Recovery Jumpers ........................................................................................... 96
9.1 BIOS Default (a.k.a CMOS Clear) and Password Reset Usage Procedure .......... 97
9.1.1 Set BIOS to default (a.k.a Clearing the CMOS) ..................................................... 97
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9.1.2 Clearing the Password ........................................................................................... 97
9.2 Integrated BMC Force Update Procedure ............................................................. 98
9.3 ME Force Update Jumper ...................................................................................... 98
9.4 BIOS Recovery Jumper ......................................................................................... 99
10. Light Guided Diagnostics ................................................................................................ 100
10.1 5-volt Stand-by LED ............................................................................................. 100
10.2 Fan Fault LEDs .................................................................................................... 100
10.3 DIMM Fault LEDs ................................................................................................ 102
10.4 System ID LED, System Status LED and POST Code Diagnostic LEDs ............ 102
10.4.1 System ID LED .................................................................................................... 103
10.4.2 System Status LED .............................................................................................. 104
10.4.3 POST Code Diagnostic LEDs .............................................................................. 104
11. Environmental Limits Specification ............................................................................... 106
11.1 Processor Thermal Design Power (TDP) Support ............................................... 106
11.2 MTBF ................................................................................................................... 106
12. Power Supply Specification Guidelines ......................................................................... 108
12.1 Power Supply DC Output Specification ............................................................... 108
12.1.1 Output Power/Currents ........................................................................................ 108
12.1.2 Cross Loading ...................................................................................................... 108
12.1.3 Standby Output .................................................................................................... 109
Appendix A: Integration and Usage Tips .............................................................................. 114
Appendix B: Compatiable Intel® Server Chassis ................................................................. 115
Appendix C: Integrated BMC Sensor Tables ........................................................................ 122
Appendix D: Intel® Server Board S2600CO Family Specific Sensors ................................ 135
Product ID .......................................................................................................................... 135
ACPI S3 Sleep State Support ............................................................................................ 135
Processor Support for Intel® Server Board S2600CO ........................................................ 135
Supported Chassis ............................................................................................................. 135
Hot-plug fan support ........................................................................................................... 136
Fan redundancy support .................................................................................................... 136
HSC Availability .................................................................................................................. 138
Power unit support ............................................................................................................. 138
Redundant Fans only for Intel® Server Chassis ................................................................. 139
Fan Fault LED support ....................................................................................................... 139
Memory Throttling support ................................................................................................. 139
Appendix E: Management Engine Generated SEL Event Messages ................................. 140
Appendix F: POST Code Diagnostic LED Decoder.............................................................. 142
Appendix G: POST Code Errors ............................................................................................ 147
Glossary ................................................................................................................................... 154
Reference Documents ............................................................................................................ 157
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List of Figures
Figure 1. Major Board Components .............................................................................................. 6
Figure 2. Intel® Light Guided Diagnostic LED Identification .......................................................... 7
Figure 3. Jumper Block Identification ............................................................................................ 8
Figure 4. Rear I/O Layout ............................................................................................................. 9
Figure 5. Mounting Hole Locations (1 of 2) ................................................................................. 10
Figure 6. Mounting Hole Locations (2 of 2) ................................................................................. 11
Figure 7. Major Connector Pin-1 Locations ................................................................................ 12
Figure 8. Primary Side Keep-out ................................................................................................. 13
Figure 9. Secondary Side Keep-out ............................................................................................ 14
Figure 10. Intel® Server Board S2600CO Functional Block Diagram ......................................... 15
Figure 11. Processor Socket Assembly ...................................................................................... 16
Figure 12. Integrated Memory Controller Functional Block Diagram .......................................... 21
Figure 13. Intel® Server Board S2600CO DIMM Slot Layout ...................................................... 24
Figure 14. Functional Block Diagram of Processor IIO Sub-system ........................................... 31
Figure 15. Functional Block Diagram - Chipset Supported Features and Functions .................. 34
Figure 16. Intel® RAID C600 Upgrade Key Connector ................................................................ 35
Figure 17. Integrated BMC Functional Block Diagram ................................................................ 38
Figure 18. Integrated BMC Hardware ......................................................................................... 39
Figure 19. Setup Utility – TPM Configuration Screen ................................................................. 49
Figure 20. High Level Fan Speed Control Structure ................................................................... 61
Figure 21. Server Board Jumper Block Locations (J1E2, J1E3, J1E4, J1E6, J2J2) ................... 96
Figure 22. 5-volt Stand-by Status LED Location ....................................................................... 100
Figure 23. Fan Fault LED’s Location ........................................................................................ 101
Figure 24. DIMM Fault LED’s Location ..................................................................................... 102
Figure 25. Location of System Status, System ID and POST Code Diagnostic LEDs .............. 103
Figure 26. Differential Noise test setup ..................................................................................... 111
Figure 27. Output Voltage Timing ............................................................................................. 112
Figure 28. Turn On/Off Timing (Power Supply Signals) ............................................................ 113
Figure 29. Intel® Server Chassis P4308XXMFEN ..................................................................... 115
Figure 30. Intel® Server Chassis P4308XXMHGC .................................................................... 116
Figure 31. Chassis/System Product Code Naming Conventions .............................................. 117
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List of Tables
Table 1. Intel® Server Board S2600CO Family Feature Set ......................................................... 3
Table 2. Mixed Processor Configurations Error Summary .......................................................... 18
Table 3. UDIMM Support Guidelines .......................................................................................... 22
Table 4. RDIMM Support Guidelines .......................................................................................... 22
Table 5. LRDIMM Support Guidelines ........................................................................................ 23
Table 6. Intel® Server Board S2600CO DIMM Nomenclature ..................................................... 24
Table 7. Supported Intel® Integrated RAID Modules ................................................................... 32
Table 8. Supported Intel® Riser Card .......................................................................................... 33
Table 9. External RJ45 NIC Port LED Definition ......................................................................... 33
Table 10. Intel® RAID C600 Upgrade Key Options ..................................................................... 36
Table 11. Video Modes ............................................................................................................... 40
Table 12. Video mode ................................................................................................................. 41
Table 13. Data Center Problems ................................................................................................ 44
Table 14. Setup Utility – Security Configuration Screen Fields .................................................. 50
Table 15. ACPI Power States ..................................................................................................... 56
Table 16. Power Control Initiators ............................................................................................... 56
Table 17. Fan Profile Mapping .................................................................................................... 60
Table 18. Standard ID Channel Assignments ............................................................................. 63
Table 19. Factory Configured PEF Table Entries ....................................................................... 71
Table 20. Diagnostic Data. .......................................................................................................... 77
Table 21. Additional Diagnostics on Error. .................................................................................. 77
Table 22. Intel® RMM4 options kits ............................................................................................. 79
Table 23. Enabling Advanced Management Features ................................................................ 79
Table 24. Main Power Connector Pin-out (“MAIN PWR”) ........................................................... 83
Table 25. CPU Power Connector Pin-out (“CPU_1 PWR” and “CPU_2 PWR”) ......................... 83
Table 26. PCIe Card Power Connector Pin-out (“OPT_12V_PWR”) .......................................... 84
Table 27. SSI Front Panel Header Pin-out (“SSI Front Panel”) .................................................. 84
Table 28. Power/Sleep LED Functional States ........................................................................... 85
Table 29. NMI Signal Generation and Event Logging ................................................................. 86
Table 30. System Status LED State Definitions .......................................................................... 86
Table 31. Front Panel USB Connector Pin-out (USB5-6) ........................................................... 88
Table 32. Intel Local Control Pane Connector Pin-out (LCP) ..................................................... 88
Table 33. SATA Only Connector Pin-out (SATA_0 and SATA_1) .............................................. 88
Table 34. SATA/SAS Connector Pin-out (SATA/SAS_0 to SATA/SAS_7) ................................. 89
Table 35. SAS SGPIO Connector Pin-out (SAS_SPGIO_0 and SAS_SPGIO_1) ...................... 89
Table 36. Intel® RAID C600 Upgrade Key Connector Pin-out (STRO UPG KEY) ...................... 89
Table 37. HSBP_I2C Header Pin-out (HSBP_I2C) ..................................................................... 89
Table 38. Hard Drive Acitivity Header Pin-out (HDD_LED) ........................................................ 90
Table 39. Internal Type-A USB2.0 Connector Pin-out (USB_4) ................................................. 90
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Table 40. Internal eUSB Connector Pin-out (eUSB_SSD) ......................................................... 90
Table 41. RMM4_Lite Connector Pin-out (RMM4_Lite) .............................................................. 91
Table 42. RMM4_NIC Connector Pin-out (RMM4_NIC) ............................................................. 91
Table 43. TPM Connector Pin-out (TPM) ................................................................................... 91
Table 44. PMBUS Connector Pin-out (SMB_PMBUS) ............................................................... 91
Table 45. Chassis Intrusion Header Pin-out (CHAS INTR) ........................................................ 92
Table 46. Chassis Instrusion Header State Description ............................................................. 92
Table 47. IPMB Connector Pin-out (IPMB) ................................................................................. 92
Table 48. 6-pin System FAN Connector Pin-out (SYS_FAN_1 to SYS_FAN_6) ........................ 92
Table 49. 4-pin System FAN Connector Pin-out (SYS_FAN_7) ................................................. 92
Table 50. CPU Fan Connector Pin-out (CPU_1 FAN and CPU_2 FAN) .................................... 93
Table 51. Serial Port A Connector Pin-out (SERIAL_A) ............................................................. 93
Table 52. Serial-B Connector Pin-out (SERIAL_B) ..................................................................... 93
Table 53. Rear VGA Video Connector Pinout (VGA) .................................................................. 93
Table 54. HSBP 4-PIN I2C BUS Connector pin out(FAN BOARD_I2C) ..................................... 94
Table 55. IEEE 1394b Connector pin out ................................................................................... 95
Table 56. Server Board Jumpers (J1E2, J1E3, J1E4, J1E6, J1J2) ............................................ 96
Table 57. System Status LED ................................................................................................... 104
Table 58. POST Code Diagnostic LEDs ................................................................................... 105
Table 59. Server Board Design Specifications ......................................................................... 106
Table 60. MTBF Estimate ......................................................................................................... 107
Table 61. Over Voltage Protection Limits ................................................................................. 108
Table 62. Loading Conditions ................................................................................................... 108
Table 63. Voltage Regulation Limits ......................................................................................... 109
Table 64. Transient Load Requirements ................................................................................... 109
Table 65. Capacitive Loading Conditions ................................................................................. 110
Table 66. Ripples and Noise ..................................................................................................... 110
Table 67. Output Voltage Timing .............................................................................................. 111
Table 68. Turn On/Off Timing ................................................................................................... 112
Table 69. Intel® Server Chassis P4000M family Features ........................................................ 118
Table 70. BMC Core Sensors ................................................................................................... 124
Table 71. Chassis-specific Sensors .......................................................................................... 135
Table 72. Fan Domain Definition .............................................................................................. 136
Table 73. Power Supply Support .............................................................................................. 138
Table 74. Server Platform Services Firmware Health Event ..................................................... 140
Table 75. Node Manager Health Event ..................................................................................... 141
Table 76. POST Progress Code LED Example ........................................................................ 142
Table 77. Diagnostic LED POST Code Decoder ...................................................................... 143
Table 78. MRC Progress Codes ............................................................................................... 145
Table 79. MRC Fatal Error Codes ............................................................................................ 145
Table 80. POST Error Codes and Messages ........................................................................... 147
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Table 81. POST Error Beep Codes .......................................................................................... 152
Table 82. Integrated BMC Beep Codes .................................................................................... 153
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Intel® Server Board S2600CO Family TPS Introduction
1. Introduction
This Technical Product Specification (TPS) provides board-specific information detailing the
features, functionality, and high-level architecture of the Intel® Server Board S2600CO.
Design-level information related to specific server board components and subsystems can be
obtained by ordering External Product Specifications (EPS) or External Design Specifications
(EDS) related to this server generation. EPS and EDS documents are made available under
NDA with Intel and must be ordered through your local Intel® representative. See the Reference
Documents section for a list of available documents.
1.1 Chapter Outline
This document is divided into the following chapters:
Chapter 1 – Introduction
Chapter 2 – Product Overview
Chapter 3 – Functional Architecture Overview
Chapter 4 – Technology Support
Chapter 5 – System Security
Chapter 6 – Platform Management Functional Overview
Chapter 7 – Advanced Management Feature Support (RMM4)
Chapter 8 – On-board Connector/Header Overview
Chapter 9 – Reset and Recovery Jumpers
Chapter 10 – Light Guided Diagnostics
Chapter 11 – Environmental Limits Specifications
Chapter 12 – Power Supply Specification Guidelines
Appendix A: Integration and Usage Tips
Appendix B: Compatible Intel
Appendix C: Integrated BMC Sensor Tables
Appendix D: Intel
Appendix E: Management Engine Generated SEL Event Messages
Appendix F: POST Code Diagnostic LED Decoder
Appendix G: POST Code Errors
Glossary
Reference Documents
®
Server Board S2600CO Family Specific Sensors
®
Server Chassis
1.2 Server Board Use Disclaimer
Intel Corporation server boards support add-in peripherals and contain a number of high-density
VLSI (Very-large-scale integration) and power delivery components that need adequate airflow
to cool. Intel ensures through its own chassis development and testing that when Intel® server
building blocks are used together, the fully integrated system will meet the intended thermal
requirements of these components. It is the responsibility of the system integrator who chooses
not to use Intel developed server building blocks to consult vendor datasheets and operating
parameters to determine the amount of airflow required for their specific application and
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Introduction Intel® Server Board S2600CO Family TPS
environmental conditions. Intel Corporation cannot be held responsible if components fail or the
server board does not operate correctly when used outside any of the published operating or
non-operating limits.
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Intel® Server Board S2600CO Family TPS Product Overview
Feature
Description
Processor Support
Two LGA 2011 (Socket R) processor sockets
S2600CO4 - Support for one or two Intel® Xeon® Processor(s) E5-2600 product with
a Thermal Design Power (TDP) of up to 135W.
S2600COE - Support for one or two Intel® Xeon® Processor(s) E5-2600 product
family with a Thermal Design Power (TDP) of up to 150W with possible
configuration limits.
Memory
16 DIMM slots – 2 DIMM slots/channel – 4 memory channels per processor
Channels A, B, C, D, E, F, G and H
Support for Registered DDR3 Memory (RDIMM), LV-RDIMM, Unbuffered DDR3
memory ((UDIMM) with ECC and Load Reduced DDR3 memory (LR-DIMM)
Memory DDR3 data transfer rate of 800, 1066, and 1333 MT/s and1600 MT/s
DDR3 standard I/O voltage of 1.5V and DDR3 Low Voltage of 1.35V
Chipset
Intel® C600-A chipset with support for optional Storage Option Select keys
Rear I/O connections
One DB15 Video VGA connector
One DB9 Serial connector
Four USB2.0 connectors
Four RJ-45 Network Interface Connectors supporting 10/100/1000Mb
Internal I/O
connectors/headers
One 2x5 pin connector providing front panel support for two USB ports
One internal type A USB 2.0 connector
One internal low-profile 2mm USB port for USB Solid State Drive
One 2x15 pin SSI-EEB compliant front panel connector
One DH-10 Serial Port B connector
Two internal IEEE 1394b connectors (Intel® Server Board S2600COE only.)
Cooling Fan Support
Two 4-pin managed CPU fan headers
Six 6-pin managed system fan headers
One 4-pin managed rear system fan header
One 4-pin I2C header that is intended to be used for third party fan control circuits
using a Maxim 72408 controller. (Intel® Server Board S2600CO4 only.)
2. Product Overview
The Intel® Server Board S2600CO is a monolithic printed circuit board (PCB) assembly with
features designed to support the pedestal server markets. It has two board SKUs, namely
S2600CO4 and S2600COE. These server boards are designed to support the Intel® Xeon®
Processor E5-2600 product family. Previous generation Intel® Xeon® processors are not
supported. Many of the features and functions of these two SKUs are common. A board will be
identified by name when a described feature or function is unique to it.
Table 1. Intel® Server Board S2600CO Family Feature Set
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Product Overview Intel® Server Board S2600CO Family TPS
Feature
Description
Add-in Card Slots
Support up to six expansion slots
Slot 1: PCIe Gen II x4 electrical with x8 physical connector, routed from Intel® C600
Chipset, support half-length card
Slot 2: PCIe Gen III x16 electrical with x16 physical connector, routed from CPU1,
support full length card
Slot 3: PCIe Gen III x16 electrical with x16 physical connector, routed from CPU2,
support full length, double width card
Slot 4: PCIe Gen III x8 electrical with x8 connector, routed from CPU2, support full
length card; support Intel designed SAS RAID on Card (ROC) Module (PCIe slot
form factor)
Slot 5: PCIe Gen III x16 electrical with x16 connector, routed from CPU1, support
full length, double width card
Slot 6: PCIe Gen III x16 electrical with x16 connector, routed from CPU2, support
half-length card, Intel designed PCIe riser card
Storage
One low-profile eUSB 2x5 pin connector to support 2mm low-profile eUSB solid
state devices
Two AHCI SATA connectors capable of supporting up to 6Gb/sec
AHCI SATA 0 supports high profile, vertical SATA DOM with onboard power.
Eight SCU SAS/SATA connectors capable of supporting up to 3Gb/sec
Intel SAS ROC module support (Optional, PCIe slot form factor)
Intel® RAID C600 Upgrade Key support providing optional expanded SAS/SATA
RAID capabilities
RAID Support
Intel® RSTe SW RAID 0/1/10/5
LSI SW RAID 0/1/10
Video Support
Integrated Matrox G200 2D Video Graphics controller
LAN
Four Gigabit through Intel® I350-AM Quad 10/100/1000 integrated GbE MAC and PHY
controller
Security
Trusted Platform Module (Accessory Option)
Server Management
Integrated Baseboard Management Controller, IPMI 2.0 compliant
Support for Intel® Server Management Software
Intel® Remote Management Module 4 support (Accessory Option)
Intel® Remote Management Module 4 Lite support (Accessory Option)
Form Factor
SSI EEB (12”x13”)
Compatible Intel® Server
Chassis
Intel® Server Chassis P4000M family
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Callout
Description
Callout
Description
A
Chassis Intrusion
AH
System Fan 1 Connector
B
Slot1, PCI Express* Gen2
AI
LCP
C
RMM4 Lite
AJ
Optional 12V Power Connector
D
Slot 2, PCI Express* Gen3
AK
BIOS Default
E
Slot 3, PCI Express* Gen3
AL
SMB_PMBUS
2.1 Server Board Connector and Component Layout
The following illustrations provide a general overview of the server board, identifying key feature
and component locations. Each connector and major component is identified by a number or
letter, and the description is given below the figure.
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Product Overview Intel® Server Board S2600CO Family TPS
Callout
Description
Callout
Description
F
Battery
AM
Main Power
G
Slot 4, PCI Express* Gen3
AN
USB_4 (Internal Type A USB
Connector)
H
Slot 5, PCI Express* Gen3
AO
Storage Upgrade key connector
I
Slot 6, PCI Express* Gen3
AP*
FAN BOARD_I2C (Intel® Server
Board S2600CO4 only)
J
DIMM E1/E2/F1/F2
AQ
SATA_0 connector
K
Status LED
AR
SATA_1 Connector
L
ID LED
AS
SAS/SATA_7 Connector
M
Diagnostic LED
AT
SAS/SATA_6 Connector
N
NIC 3/4
AU
SAS/SATA_5 Connector
O
USB 0/1/2/3, NIC 1,2
AV
SAS/SATA_4 Connector
P
VGA
AW
SAS/SATA_3 Connector
Q
CPU 2 Power connector
AX
SAS/SATA_2 Connector
R
System Fan 7
AY
SAS/SATA_1 Connector
S
Serial Port A
AZ
SAS/SATA_0 Connector
T
CPU 2 Fan Connector
BA
SAS SGPIO 0
U
DIMM H1/H2/G1/G2
BB
SAS SGPIO 1
V
DIMM A1/A2/B1/B2
BC
IPMB
W
CPU 1 Power connector
BD
HSBP_I2C
X
CPU 1 Fan Connector
BE
USB 5-6 (front panel USB connector)
Y
DIMM C1/C2/D1/D2
BF
ME Force Update
Z
USB port to support SSD
BG
BMC Force Update
AA
HDD LED Header
BH**
IEEE_1394B_0 Connector (Intel®
Server Board S2600COE only)
AB
TPM Connector
BI
Password Clear
AC
System Fan 6 Connector
BJ
BIOS Recovery
AD
System Fan 5 Connector
BK**
IEEE_1394B_1 Connector (Intel®
Server Board S2600COE only)
AE
System Fan 4 Connector
BL
Serial B connector
AF
System Fan 3 Connector
BM
RMM4 NIC
AG
System Fan 2 Connector
BN
SSI Front Panel
6 Revision 1.0
Figure 1. Major Board Components
Intel order number G42278-002
Intel® Server Board S2600CO Family TPS Product Overview
Figure 2. Intel® Light Guided Diagnostic LED Identification
See Chapter 10 for additional details.
Revision 1.0 7
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Product Overview Intel® Server Board S2600CO Family TPS
Figure 3. Jumper Block Identification
See Chapter 9 for additional details.
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Intel® Server Board S2600CO Family TPS Product Overview
Callout
Description
Callout
Description
A
Serial Port A
E
NIC Port 3 and 4
B
Video
F
Diagnostics LED’s
C
NIC Port 1, USB Port 0 (top) and 1
(bottom)
G
ID LED
D
NIC Port 2, USB Port 2 (top) and 3
(bottom)
H
Status LED
Figure 4. Rear I/O Layout
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2.2 Server Board Dimensional Mechanical Drawings
Figure 5. Mounting Hole Locations (1 of 2)
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Figure 6. Mounting Hole Locations (2 of 2)
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Figure 7. Major Connector Pin-1 Locations
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Intel® Server Board S2600CO Family TPS Product Overview
Figure 8. Primary Side Keep-out
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Figure 9. Secondary Side Keep-out
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Intel® Server Board S2600CO Family TPS Functional Architecture Overview
Intel® C600
Series
Chipse
(w/ Dynamic SKU’ing)
HSBP
Integrated
BMC
LPC (33MHz)
USB 2.0 (480Mbs)
SMBUS PORTS
NC-SI PORT 1 (RMII) 100Mbps
NC-SI PORT 0 (RGMII)
VIDEO RGB
RMM4 Dedicated NIC
Module Conn
SERIAL PORT 1
2x5 HDR
USB 2.0
Zepher Conn
TPM Conn
SATA
SATA
3Gps
3Gps
3Gps
6Gps
4 USB 2.0 EXT
4 SATA 3G
Upgradable to
8 SATA/SAS 6G
ODD
Intel®
Ethernet
Controller
I350
Dual 1Gb LAN
Dual GbDual Gb
Dual 1Gb LAN
Dual GbDual Gb
SERIAL PORT 0
USB 2.0
2 USB 2.0 INT
PCIe Gen1 x1
DRAM
16MB iBMC
SPI Flash
DRAM
8MB BIOS
SPI Flash
DRAM
128MB
DDR3
SCU[7:4]
USB2.0
SCU[3:0] P[5:2] P[1:0]
LHSRHS
USB2.0
Type-A
INT
Conn
USB[7,6,5,1]
USB[13,11]
USB[0]
USB[2]
USB 1.1 (12Mbs)
USB[10]
USB[3]
SATA/SAS
SATA/SAS
SATA/SAS
SATA/SAS
SATA/SAS
SATA/SAS
SATA/SAS
SATA/SAS
Intel® Xeon®
E5-2600
CPU 1
DDR3 MEMORY
(1066/1333/1666Mhz)
CHANNEL 0
Intel® Xeon®
E5-2600
CPU 2
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
Slot 2: x16 Conn
Slot 1 x8 Conn
DDR3 MEMORY
(1066/1333/1666Mhz)
Slot 3: x16 Conn
Supports:
UDIMM/RDIMM QRx4 (1.5V)
LV-DIMMs (1.35V)
LR-DIMMs
Copper Pass Romley-EP Pedestal Server System
Architecture Diagram
DMI2 PCIe Gen2 x4 (4GB/s)
QPI Port 1 8.0GT/s
QPI Port 0 8.0GT/s
P2 P1P3P0
IOU0 IOU2IOU1
P1P3 P2P0
IOU2IOU1 IOU0
PCIe Gen3 x16 (32GB/s)
PCIe Gen3 x16 (32GB/s)
PCIe Gen3 x4 (8GB/s)
Slot 5: x16 Conn
Slot 4: x8 Conn
Slot 6 x16 Conn
PCIe Gen3 x4 (8GB/s)
PCIe Gen3 x4 (8GB/s)
PCIe Gen3 x16 (32GB/s)
PCIe Gen3 x16 (32GB/s)
PCIe Gen3 x8 (16GB/s)
PCIe Gen1 x1 1394b INT
1394b INT
LSI
FW643E-02
11x11
3port 1394b
PCIe Gen3 x4 (8GB/s)
PCIe Gen2 x4 (4GB/s)
3. Functional Architecture Overview
The architecture and design of the Intel® Server Board S2600CO is developed around the
integrated features and functions of the Intel® processor E5-2600 product family, the Intel®
C600-A chipset, the Intel® Ethernet Controller I350 Quad Port 1GbE chip and the Server
Engines* Pilot-III Server Management Controller.
The following diagram provides an overview of the server board architecture, showing the
features and interconnects of each of the major sub-system components.
Figure 10. Intel® Server Board S2600CO Functional Block Diagram
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3.1 Processor Support
The server board includes two Socket-R (LGA2011) processor sockets and can support one or
two of the following processors:
Intel
®
Xeon® processor E5-2600 product family, with a Thermal Design Power (TDP) of
up to 135W
Intel
®
Xeon® processor E5-2600 product family, with a Thermal Design Power (TDP) of
up to 150W with Intel® Server Board S2600COE with possible configuration limits.
Note: Previous generation Intel® Xeon® processors are not supported on the Intel server boards
described in this document.
Visit the Intel web site for a complete updated list of supported processors.
3.1.1 Processor Socket Assembly
Each processor socket of the server board is pre-assembled with an Independent Latching
Mechanism (ILM) and Back Plate which allow for secure placement of the processor and
processor heat to the server board.
The illustration below identifies each sub-assembly component.
Figure 11. Processor Socket Assembly
3.1.2 Processor Population Rules
Note: Although the server board does support dual-processor configurations consisting of
different processors that meet the defined criteria below, Intel® does not perform validation
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Intel® Server Board S2600CO Family TPS Functional Architecture Overview
testing of this configuration. For optimal system performance in dual-processor configurations,
Intel® recommends that identical processors be installed.
When using a single processor configuration, the processor must be installed into the processor
socket labeled “CPU_1”.
When two processors are installed, the following population rules apply:
Both processors must be of the same processor family.
Both processors must have the same number of cores.
Both processors must have the same cache sizes for all levels of processor cache
memory.
Processors with different core frequencies can be mixed in a system, given the prior
rules are met. If this condition is detected, all processor core frequencies are set to the
lowest common denominator (highest common speed) and an error is reported.
Processors which have different Intel QuickPath (QPI) Link Frequencies may operate
together if they are otherwise compatible and if a common link frequency can be
selected. The common link frequency would be the highest link frequency that all
installed processor can achieve.
Processor stepping within a common processor family can be mixed as long as it is
listed in the processor specification updates published by Intel Corporation.
3.1.3 Processor Initializion Error Summary
The following table describes mixed processor conditions and recommended actions for all
Intel® server boards and Intel® server systems designed around the Intel® Xeon® processor E52600 product family and Intel® C600 chipset product family architecture. The errors fall into one
of the following categories:
Fatal: If the system can boot, it pauses at a blank screen with the text “Unrecoverable
fatal error found. System will not boot until the error is resolved” and “Press <F2>
to enter setup”, regardless of whether the “Post Error Pause” setup option is enabled or
disabled.
When the operator presses the <F2> key on the keyboard and enter BIOS setup, the
error message is displayed on the Error Manager screen, and an error is logged to the
System Event Log (SEL) with the POST Error Code.
The system cannot boot unless the error is resolved. The user needs to replace the
faulty part and restart the system.
For Fatal Errors during processor initialization, the System Status LED will be set to a
steady Amber color, indicating an unrecoverable system failure condition
Major: If the “Post Error Pause” setup option is enabled, the system goes directly to the
Error Manager screen to display the error and log the error code to SEL. Operator
intervention is required to continue booting the system.
Otherwise, if “POST Error Pause” is disabled, the system continues to boot and no
prompt is given for the error, although the error code is logged to the Error Manager and
in a SEL message.
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Error
Severity
System Action
Processor family not
Identical
Fatal
The BIOS detects the error condition and responds as follows:
Logs the POST Error Code into the System Event Log (SEL).
Alerts the BMC to set the System Status LED to steady Amber.
Displays “0194: Processor family mismatch detected” message in the
Error Manager.
Takes Fatal Error action (see above) and will not boot until the fault
condition is remedied.
Processor model not
Identical
Fatal
The BIOS detects the error condition and responds as follows:
Logs the POST Error Code into the System Event Log (SEL).
Alerts the BMC to set the System Status LED to steady Amber.
Displays “0196: Processor model mismatch detected” message in the
Error Manager.
Takes Fatal Error action (see above) and will not boot until the fault
condition is remedied.
Processor
cores/threads not
identical
Fatal
The BIOS detects the error condition and responds as follows:
Logs the POST Error Code into the SEL.
Alerts the BMC to set the System Status LED to steady Amber.
Displays “0191: Processor core/thread count mismatch detected”
message in the Error Manager.
Takes Fatal Error action (see above) and will not boot until the fault
condition is remedied.
Processor cache not
identical
Fatal
The BIOS detects the error condition and responds as follows:
Logs the POST Error Code into the SEL.
Alerts the BMC to set the System Status LED to steady Amber.
Displays “0192: Processor cache size mismatch” detected message in
the Error Manager.
Takes Fatal Error action (see above) and will not boot until the fault
condition is remedied.
Processor frequency
(speed) not identical
Fatal
The BIOS detects the processor frequency difference, and responds as
follows:
Adjusts all processor frequencies to the highest common frequency.
No error is generated – this is not an error condition.
Continues to boot the system successfully.
If the frequencies for all processors cannot be adjusted to be the same,
then this is an error, and the BIOS responds as follows:
Logs the POST Error Code into the SEL.
Alerts the BMC to set the System Status LED to steady Amber.
Does not disable the processor.
Displays “0197: Processor speeds unable to synchronize” message in
the Error Manager.
Takes Fatal Error action (see above) and will not boot until the fault
condition is remedied.
Minor: The message is displayed on the screen or on the Error Manager screen, and
the POST Error Code is logged to the SEL. The system continues booting in a degraded
state. The user may want to replace the erroneous unit. The POST Error Pause option
setting in the BIOS setup does not have any effect on this error.
Table 2. Mixed Processor Configurations Error Summary
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Error
Severity
System Action
Processor Intel®
QuickPath
Interconnect link
frequencies not
identical
Fatal
The BIOS detects the QPI link frequencies and responds as follows:
Adjusts all QPI interconnect link frequencies to highest common
frequency.
No error is generated – this is not an error condition.
Continues to boot the system successfully.
If the link frequencies for all QPI links cannot be adjusted to be the same,
then this is an error, and the BIOS responds as follows:
Logs the POST Error Code into the SEL.
Alerts the BMC to set the System Status LED to steady Amber.
Displays “0195: PProcessor Intel(R) QPI link frequencies unable to
synchronize” message in the Error Manager.
Does not disable the processor.
Takes Fatal Error action (see above) and will not boot until the fault
condition is remedied.
Processor microcode
update missing
Minor
The BIOS detects the error condition and responds as follows:
Logs the POST Error Code into the SEL.
Displays “818x: Processor 0x microcode update not found” message in
the Error Manager or on the screen.
The system continues to boot in a degraded state, regardless of the
setting of POST Error Pause in the Setup.
Processor microcode
update failed
Major
The BIOS detects the error condition and responds as follows:
Logs the POST Error Code into the SEL.
Displays “816x: Processor 0x unable to apply microcode update”
message in the Error Manager or on the screen.
Takes Major Error action. The system may continue to boot in a degraded
state, depending on the setting of POST Error Pause in Setup, or may halt
with the POST Error Code in the Error Manager waiting for operator
intervention.
3.2 Processor Function Overview
With the release of the Intel® Xeon® processor E5-2600 product family, several key system
components, including the CPU, Integrated Memory Controller (IMC), and Integrated IO Module
(IIO), have been combined into a single processor package and feature per socket; two Intel®
QuickPath Interconnect point to point links capable of up to 8.0 GT/s, up to 40 lanes of Gen 3
PCI Express* links capable of 8.0 GT/s, and 4 lanes of DMI2/PCI Express* Gen 2 interface with
a peak transfer rate of 5.0 GT/s. The processor supports up to 46 bits of physical address space
and 48-bit of virtual address space.
The following sections will provide an overview of the key processor features and functions that
help to define the architecture, performance and supported functionality of the server board. For
more comprehensive processor specific information, refer to the Intel® Xeon® processor E52600 product family documents listed in the Reference Document list.
Revision 1.0 19
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Functional Architecture Overview Intel® Server Board S2600CO Family TPS
Processor Core Features:
Up to 8 execution cores
Each core supports two threads (Intel
®
Hyper-Threading Technology), up to 16 threads
per socket
46-bit physical addressing and 48-bit virtual addressing
1 GB large page support for server applications
A 32-KB instruction and 32-KB data first-level cache (L1) for each core
A 256-KB shared instruction/data mid-level (L2) cache for each core
Up to 20 MB last level cache (LLC): up to 2.5 MB per core instruction/data last level
cache (LLC), shared among all cores
Supported Technologies:
Intel
Intel
Intel
Intel
Intel
Intel
Intel
Intel
Intel
Execute Disable Bit
Intel
Intel
Enhanced Intel
®
Virtualization Technology (Intel® VT)
®
Virtualization Technology for Directed I/O (Intel® VT-d)
®
Virtualization Technology “Sandy Bridge” Processor Extensions
®
Trusted Execution Technology (Intel® TXT)
®
64 Architecture
®
Streaming SIMD Extensions 4.1 (Intel® SSE4.1)
®
Streaming SIMD Extensions 4.2 (Intel® SSE4.2)
®
Advanced Vector Extensions (Intel® AVX)
®
Hyper-Threading Technology
®
Turbo Boost Technology
®
Intelligent Power Technology
®
SpeedStep Technology
3.2.1 Intel
®
QuickPath Interconnect
The Intel® QuickPath Interconnect is a high speed, packetized, point-to-point interconnect used
in the processor. The narrow high-speed links stitch together processors in distributed shared
memory and integrated I/O platform architecture. It offers much higher bandwidth with low
latency. The Intel® QuickPath Interconnect has an
efficient architecture
allowing more
interconnect performance to be achieved in real systems. It has a snoop protocol optimized for
low latency and high scalability, as well as packet and lane structures enabling quick
completions of transactions. Reliability, availability, and serviceability features (RAS) are built into
the architecture.
The physical connectivity of each interconnect link is made up of twenty differential signal pairs
plus a differential forwarded clock. Each port supports a link pair consisting of two uni-directional
links to complete the connection between two components. This supports traffic in both
directions simultaneously. To facilitate flexibility and longevity, the interconnect is defined as
having five layers: Physical, Link, Routing, Transport, and Protocol.
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Intel® Xeon®
E5-2600
CPU 1
DDR3 MEMORY
2 DIMMs/channel
CHANNEL 0
Intel® Xeon®
E5-2600
CPU2
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
DDR3 MEMORY
2 DIMMs/channel
QPI
QPI
P2 P1P3P0
IOU0 IOU2IOU1
P1
P3
P2P0
IOU2
IOU1
IOU0
The Intel® QuickPath Interconnect includes a cache coherency protocol to keep the distributed
memory and caching structures coherent during system operation. It supports both low-latency
source snooping and a scalable home snoop behavior. The coherency protocol provides for
direct cache-to-cache transfers for optimal latency.
3.2.2 Integrated Memory Controller (IMC) and Memory Subsystem
Figure 12. Integrated Memory Controller Functional Block Diagram
Integrated into the processor is a memory controller. Each processor provides four DDR3
channels that support the following:
Unbuffered DDR3 and registered DDR3 DIMMs
LR DIMM (Load Reduced DIMM) for buffered memory solutions demanding higher
capacity memory subsystems
Independent channel mode or lockstep mode
Data burst length of eight cycles for all memory organization modes
Memory DDR3 data transfer rates of 800, 1066, 1333, and 1600 MT/s
64-bit wide channels plus 8-bits of ECC support for each channel
DDR3 standard I/O Voltage of 1.5 V and DDR3 Low Voltage of 1.35 V
1-Gb, 2-Gb, and 4-Gb DDR3 DRAM technologies supported for these devices:
o UDIMM DDR3 – SR x8 and x16 data widths, DR – x8 data width
o RDIMM DDR3 – SR,DR, and QR – x4 and x8 data widths
o LRDIMM DDR3 – QR – x4 and x8 data widths with direct map or with rank
multiplication
Up to 8 ranks supported per memory channel, 1, 2 or 4 ranks per DIMM
Open with adaptive idle page close timer or closed page policy
Per channel memory test and initialization engine can initialize DRAM to all logical zeros
with valid ECC (with or without data scrambler) or a predefined test pattern
Isochronous access support for Quality of Service (QoS)
Minimum memory configuration: independent channel support with 1 DIMM populated
Integrated dual SMBus master controllers
Command launch modes of 1n/2n
RAS Support:
o Rank Level Sparing and Device Tagging
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Ranks Per DIMM
and Data Width
Memory Capacity Per DIMM1
Speed (MT/s) and Voltage Validated by
Slot per Channel (SPC) and DIMM Per Channel (DPC)
2 Slots per Channel
1DPC
2DPC
1.35V
1.5V
1.35V
1.5V
SRx8 Non-ECC
1GB
2GB
4GB
n/a
1066, 1333
n/a
1066, 1333
DRx8 Non-ECC
2GB
4GB
8GB
n/a
1066, 1333
n/a
1066, 1333
SRx16 Non-ECC
512MB
1GB
2GB
n/a
1066, 1333
n/a
1066, 1333
SRx8 ECC
1GB
2GB
4GB
1066, 1333
1066, 1333
1066
1066, 1333
DRx8 ECC
2GB
4GB
8GB
1066, 1333
1066, 1333
1066
1066, 1333
Ranks Per DIMM
and Data Width
Memory Capacity Per
DIMM1
Speed (MT/s) and Voltage Validated by
Slot per Channel (SPC) and DIMM Per Channel (DPC)2
2 Slots per Channel
1DPC
2DPC
1.35V
1.5V
1.35V
1.5V
SRx8
1GB
2GB
4GB
1066, 1333
1066
1333
1600
1066,
1333
1066,
1333,
1600
DRx8
2GB
4GB
8GB
1066, 1333
1066
1333
1600
1066,
1333
1066,
1333,
1600
o Demand and Patrol Scrubbing
o DRAM Single Device Data Correction (SDDC) for any single x4 or x8 DRAM
device. Independent channel mode supports x4 SDDC. x8 SDDC requires
lockstep mode
o Lockstep mode where channels 0 and 1 and channels 2 and 3 are operated in
lockstep mode
o Data scrambling with address to ease detection of write errors to an incorrect
address.
o Error reporting by the Machine Check Architecture
o Read Retry during CRC error handling checks by IMC
o Channel mirroring within a socket
CPU1 Channel Mirror Pairs (A,B) and (C,D)
CPU2 Channel Mirror Pairs (E,F) and (G,H)
o Error Containment Recovery
Improved Thermal Throttling with dynamic Closed Loop Thermal Throttling (CLTT)
Memory thermal monitoring support for DIMM temperature
3.2.2.1 Supported Memory
Table 3. UDIMM Support Guidelines
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Table 4. RDIMM Support Guidelines
Intel order number G42278-002
Intel® Server Board S2600CO Family TPS Functional Architecture Overview
SRx4
2GB
4GB
8GB
1066, 1333
1066,
1333,
1600
1066,
1333
1066,
1333,
1600
DRx4
4GB
8GB
16GB
1066, 1333
1066,
1333,
1600
1066,
1333
1066,
1333,
1600
QRx4
8GB
16GB
32GB
800
1066
800
800
QRx8
4GB
8GB
16GB
800
1066
800
800
Ranks Per DIMM and Data Width1
Memory Capacity Per
DIMM2
Speed (MT/s) and Voltage Validated by
Slot per Channel (SPC) and DIMM Per
Channel (DPC)
3,4,5
2 Slots per Channel
1DPC and 2DPC
1.35V
1.5V
QRx4
(DDP)
16GB
32GB
1066
1066, 1333
QRx8
(P)
8GB
16GB
1066
1066, 1333
Table 5. LRDIMM Support Guidelines
3.2.2.2 Memory Slot Identification and Population Rules
Note: Although mixed DIMM configurations may be functional, Intel only performs platform
validation on systems that are configured with identical DIMMs installed.
Each installed processor provides four channels of memory. On the Intel® Server Board
S2600CO each memory channel support 2 memory slots, for a total possible 16 DIMMs
installed.
System memory is organized into physical slots on DDR3 memory channels that belong
to processor sockets.
The memory channels from processor socket 1 are identified as Channel A, B, C and D.
The memory channels from processor socket 2 are identified as Channel E, F, G, and H.
Each memory slot on the server board is identified by channel and slot number within
that channel. For example, DIMM_A1 is the first slot on Channel A on processor 1;
DIMM_E1 is the first DIMM socket on Channel E on processor 2.
The memory slots associated with a given processor are unavailable if the
corresponding processor socket is not populated.
A processor may be installed without populating the associated memory slots provided a
second processor is installed with associated memory. In this case, the memory is
shared by the processors. However, the platform suffers performance degradation and
latency due to the remote memory.
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Processor Socket 1
Processor Socket 2
(0)
Channel A
(1)
Channel B
(2)
Channel C
(3)
Channel D
(0)
Channel E
(1)
Channel F
(2)
Channel G
(3)
Channel H
A1
A2
B1
B2
C1
C2
D1
D2
E1
E2
F1
F2
G1
G2
H1
H2
Processor sockets are self-contained and autonomous. However, all memory subsystem
support (such as Memory RAS, Error Management,) in the BIOS setup is applied
commonly across processor sockets.
The BLUE memory slots on the server board identify the first memory slot for a given
memory channel.
DIMM population rules require that DIMMs within a channel be populated starting with the BLUE
DIMM slot or DIMM farthest from the processor in a “fill-farthest” approach. In addition, when
populating a Quad-rank DIMM with a Single- or Dual-rank DIMM in the same channel, the
Quad-rank DIMM must be populated farthest from the processor. Intel Memory Reference Code
(MRC) will check for correct DIMM placement.
On the Intel® Server Board S2600CO a total of 16 DIMM slots is provided (2 CPUs – 4
Channels/CPU, 2 DIMMs /Channel). The nomenclature for DIMM sockets is detailed in the
following table:
Table 6. Intel® Server Board S2600CO DIMM Nomenclature
Figure 13. Intel® Server Board S2600CO DIMM Slot Layout
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Intel® Server Board S2600CO Family TPS Functional Architecture Overview
The following are generic DIMM population requirements that generally apply to the Intel®
Server Board S2600CO.
All DIMMs must be DDR3 DIMMs
Unbuffered DIMMs can be ECC or non-ECC. However, Intel
®
only validates and
supports ECC memory for its server products.
Mixing of Registered and Unbuffered DIMMs is not allowed per platform.
Mixing of LRDIMM with any other DIMM type is not allowed per platform.
Mixing of DDR3 voltages is not validated within a socket or across sockets by Intel. If
1.35V (DDR3L) and 1.50V (DDR3) DIMMs are mixed, the DIMMs will run at 1.50V.
Mixing of DDR3 operating frequencies is not validated within a socket or across sockets
by Intel. If DIMMs with different frequencies are mixed, all DIMMs will run at the common
lowest frequency.
Quad rank RDIMMs are supported but not validated by Intel.
A maximum of 8 logical ranks (ranks seen by the host) per channel is allowed.
Mixing of ECC and non-ECC DIMMs is not allowed per platform.
DIMMs with different timing parameters can be installed on different slots within the
same channel, but only timings that support the slowest DIMM will be applied to all. As a
consequence, faster DIMMs will be operated at timings supported by the slowest DIMM
populated.
When one DIMM is used, it must be populated in the BLUE DIMM slot (farthest away
from the CPU) of a given channel.
When single, dual and quad rank DIMMs are populated for 2DPC, always populate the
higher number rank DIMM first (starting from the farthest slot), for example, first quad
rank, then dual rank, and last single rank DIMM.
Mixing of quad ranks DIMMs (RDIMM Raw Cards F and H) in one channel is not
validated.
3.2.2.3 Publishing System Memory
The BIOS displays the “Total Memory” of the system during POST if Display Logo is
disabled in the BIOS setup. This is the total size of memory discovered by the BIOS
during POST, and is the sum of the individual sizes of installed DDR3 DIMMs in the
system.
The BIOS displays the “Effective Memory” of the system in the BIOS setup. The term
Effective Memory refers to the total size of all DDR3 DIMMs that are active (not
disabled) and not used as redundant units.
The BIOS provides the total memory of the system in the main page of the BIOS setup.
This total is the same as the amount described by the first bullet above.
If Display Logo is disabled, the BIOS display the total system memory on the diagnostic
screen at the end of POST. This total is the same as the amount described by the first
bullet above.
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Note: Some server operating systems do not display the total physical memory installed. What
is displayed is the amount of physical memory minus the approximate memory space used by
system BIOS components. These BIOS components include, but are not limited to:
ACPI (may vary depending on the number of PCI devices detected in the system)
ACPI NVS table
Processor microcode
Memory Mapped I/O (MMIO)
Manageability Engine (ME)
BIOS flash(
3.2.2.4 Integrated Memory Controller Operating Modes
3.2.2.4.1 Independent Channel Mode
In non-ECC (Error Correction Code) and x4 Single Device Data Correction (SDDC)
configuration, each channel is running independently (nonlock-step), that is, each cache-line
from memory is provided by a channel. To deliver the 64-byte cache-line of data, each channel
is bursting eight 8-byte chunks, Back to back data transfer in the same direction and within the
same rank can be sent back-to-back without any dead-cycle. The independent channel mode is
the recommended method to deliver most efficient power and bandwidth as long as the x8
SDDC is not required.
3.2.2.4.2 Lockstep Channel Mode
In Lockstep Channel Mode the cache-line is split across channels. This is done to support
Single Device Data Correction (SDDC) for DRAM devices with 8-bit wide data ports. Also, the
same address is used on both channels, such that an address error on any channel is
detectable by bad ECC. The IMC module always accumulates 32-bytes before forwarding data
so there is no latency benefit for disabling ECC.
Lockstep channels must be populated identically. That is, each DIMM in one channel must have
a corresponding DIMM of identical organization (number ranks, number banks, number rows,
and number columns). DIMMs may be of different speed grades, but the IMC module will be
configured to operate all DIMMs according to the slowest parameters present by the Memory
Reference Code (MRC).
Channel 0 and channel 1 can be in lockstep. Channel 2 and channel 3 can be in lockstep.
Performance in lockstep mode cannot be as high as with independent channels. The burst
length for DDR3 DIMMs is eight which is shared between two channels that are in lockstep
mode. Each channel of the pair provides 32 bytes to produce the 64-byte cache-line. DRAMs on
independent channels are configured to deliver a burst length of eight. The maximum read
bandwidth for a given rank is half of peak. There is another drawback in using lockstep mode,
i.e. higher power consumption since the total activation power is about twice of the independent
channel operation if comparing to same type of DIMMs.
3.2.2.4.3 Mirror Mode
Memory mirroring mode is the mechanism by which a component of memory is mirrored. In
mirrored mode, when a write is performed to one copy, a write is generated to the target
location as well. This guarantees that the target is always updated with the latest data from the
main copy. The IMC module supports mirroring across the corresponding mirroring channel
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Intel® Server Board S2600CO Family TPS Functional Architecture Overview
within the processor socket but not across sockets. DIMM organization in each slot of one
channel must be identical to the DIMM in the corresponding slot of the other channel. This
allows a single decode for both channels. When mirroring mode is enabled, memory image in
Channel 0 is maintained the same as Channel 1 and Channel 2 is maintained the same as
Channel 3.
3.2.2.5 Memory RAS Support
The server board supports the following memory RAS modes:
Single Device Data Correction (SDDC)
Error Correction Code (ECC) Memory
Demand Scrubbing for ECC Memory
Patrol scrubbing for ECC Memory
Rank Sparing Mode
Mirrored Channel Mode
Lockstep Channel Mode
Regardless of RAS mode, the requirements for populating within a channel given in the section
3.2.2.2 must be met at all times. Note that support of RAS modes that require matching DIMM
population between channels (Mirrored and Lockstep) require that ECC DIMMs be populated.
Independent Channel Mode is the only mode that supports non-ECC DIMMs in addition to ECC
DIMMs.
For Lockstep Channel Mode and Mirroring Mode, processor channels are paired together as a
“Domain”.
CPU1 Mirroring/Lockstep Domain 1= Channel A + Channel B
CPU1 Mirroring/Lockstep Domain 2= Channel C + Channel D
CPU2 Mirroring/Lockstep Domain 1= Channel E + Channel F
CPU2 Mirroring/Lockstep Domain 2= Channel G + Channel H
For RAS modes that require matching populations, the same slot positions across channels
must hold the same DIMM type with regards to size and organization. DIMM timings do not
have to match but timings will be set to support all DIMMs populated (i.e., DIMMs with slower
timings will force faster DIMMs to the slower common timing modes).
3.2.2.5.1 Singel Device Data Correction (SDDC)
SDDC – Single Device Data Correction is a technique by which data can be replaced by the
IMC from an entire x4 DRAM device which is failing, using a combination of CRC plus parity.
This is an automatic IMC driven hardware. It can be extended to x8 DRAM technology by
placing the system in Channel Lockstep Mode.
3.2.2.5.2 Error Correction Code (ECC) Memory
ECC uses “extra bits” -64-bit data in a 72-bit DRAM array – to add an 8-bit calculated “Hamming
Code” to each 64 bits of data. This additional encoding enables the memory controller to detect
and report single or multiple bit errors when data is read, and to correct single-bit errors.
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3.2.2.5.2.1 Correctable Memory ECC Error Handling
A “Correctable ECC Error” is one in which a single-bit error in memory contents is detected and
corrected by use of the ECC Hamming Code included in the memory data. For a correctable
error, data integrity is preserved, but it may be a warning sign of a true failure to come. Note that
some correctable errors are expected to occur.
The system BIOS has logic to copy with the random factor in correctable ECC errors. Rather
than reporting every correctable error that occurs, the BIOS have a threshold and only logs a
correctable error when a threshold value is reached. Additional correctable errors that occur
after the threshold has been reached are disregarded. In addition, on the expectation the server
system may have extremely long operational runs without being rebooted, there is a “Leaky
Bucket” algorithm incorporated into the correctable error counting and comparing mechanism.
The “Leaky Bucket” algorithm reduces the correctable error count as a function of time – as the
system remains running for a certain amount of time, the correctable error count will “leak out”
of the counting registers. This prevents correctable error counts from building up over an
extended runtime.
The correctable memory error threshold value is a configurable option in the <F2> BIOS Setup
Utility, where you can configure it for 20/10/5/ALL/None.
Once a correctable memory error threshold is reached, the event is logged to the System Event
Log (SEL) and the appropriate memory slot fault LED is lit to indicate on which DIMM the
correctable error threshold crossing occurred.
3.2.2.5.2.2 Uncorrectable Memory ECC Error Handling
All multi-bit “detectable but not correctable” memory errors are classified as Uncorrectable
Memory ECC Errors. This is generally a fatal error.
However, before returning control to the OS drivers from the Machine Check Exception (MCE)
or Non-Maskable Interrupt (NMI), the Uncorrectable Memory ECC error is logged to the SEL,
the appropriate memory slot fault LED is lit, and the System Status LED state is changed to a
solid Amber.
3.2.2.5.3 Demand Scrubbing for ECC Memory
Demand scrubbing is the ability to write corrected data back to the memory once a correctable
error is detected on a read transaction. This allows for correction of data in memory at detect,
and decrease the chances of a second error on the same address accumulating to cause a
multi-bit error (MBE) condition.
Demand Scrubbing is enabled/disabled (default is enabled) in the Memory Configuration screen
in Setup.
3.2.2.5.4 Patrol Scrubbing for ECC Memory
Patrol scrubs are intended to ensure that data with a correctable error does not remain in DRAM
long enough to stand a significant chance of further corruption to an uncorrectable stage.
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Intel® Server Board S2600CO Family TPS Functional Architecture Overview
3.2.2.5.5 Rank Sparing Mode
Rank Sparing Mode enhances the system’s RAS capability by “swapping out” failing ranks of
DIMMs. Rank Sparing is strictly channel and rank oriented. Each memory channel is a Sparing
Domain.
For Rank Sparing to be available as a RAS option, there must be 2 or more single rank or dual
rank DIMMs, or at least one quad rank DIMM installed on each memory channel.
Rank Sparing Mode is enabled/disabled in the Memory RAS and Performance Configuration
screen in the <F2> BIOS Setup Utility.
When Sparing Mode is operational, for each channel, the largest size memory rank is reserved
as a “spare” and is not used during normal operation. The impact on Effective Memory Size is to
subtract the sum of the reserved ranks from the total amount of installed memory.
Hardware registers count the number of Correctable ECC Errors for each rank of memory on
each channel during operations and compare the count against a Correctable Error Threshold.
When the correctable error count for a given rank hits the threshold value, that rank is deemed
to be “failing”, and it triggers a Sparing Fail Over (SFO) event for the channel in which that rank
resides. The data in the failing rank is copied to the Spare Rank for that channel, and the Spare
Rank replaces the failing rank in the IMC’s address translation registers.
An SFO Event is logged to the BMC SEL. The failing rank is then disabled, and any further
Correctable Errors on that now non-redundant channel will be disregarded.
The correctable error that triggered the SFO may be logged to the BMC SEL, if it was the first
one to occur in the system. That first correctable error event will be the only one logged for the
system. However, since each channel is a Sparing Domain, the correctable error counting
continues for other channels which are still in a redundant state. There can be as many SFO
Events as there are memory channels with DIMMs installed.
3.2.2.5.6 Mirrored Channel Mode
Channel Mirroring Mode gives the best memory RAS capability by maintaining two copies of the
data in main memory. If there is an Uncorrectable ECC error, the channel with the error is
disabled and the system continues with the “good” channel, but in a non-redundant
configuration.
For Mirroring mode to be available as a RAS option, the DIMM population must be identical
between each pair of memory channels that participate. Not all channel pairs need to have
memory installed, but for each pair, the configuration must match. If the configuration is not
matched up properly, the memory operating mode falls back to Independent Channel Mode.
Mirroring Mode is enabled/disabled in the Memory RAS and Performance Configuration screen
in the <F2> BIOS Setup Utility.
When Mirroring Mode is operational, each channel in a pair is “mirrored” by the other channel.
The impact on Effective Memory size is to reduce by half the total amount of installed memory
available for use. When Mirroring Mode is operational, the system treats Correctable Errors the
same way as it would in Independent channel mode. There is a correctable error threshold.
Correctable error counts accumulate by rank, and the first event is logged.
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What Mirroring primarily protects against is the possibility of an Uncorrectable ECC Error
occurring with critical data “in process”. Without Mirroring, the system would be expected to
“Blue Screen” and halt, possibly with serious impact to operation. But with Mirroring Mode in
operation, an Uncorrectable ECC Error from one channel becomes a Mirroring Fail Over (MFO)
event instead, in which the IMC retrieves the correct data from the “mirror image” channel and
disables the failed channel. Since the ECC Error was corrected in the process of the MFO Event,
the ECC Error is demoted to a Correctable ECC Error. The channel pair becomes a single nonredundant channel, but without impacting operations, and the Mirroring Fail Over Event is
logged to SEL to alert the user that there is memory hardware that has failed and needs to be
replaced.
3.2.3 Processor Integrated I/O Module (IIO)
The processor’s integrated I/O module provides features traditionally supported through chipset
components. The integrated I/O module provides the following features:
PCI Express Interfaces: The integrated I/O module incorporates the PCI Express
interface and supports up to 40 lanes of PCI Express. Following are key attributes of the
PCI Express interface:
o Gen3 speeds up to 8 GT/s
o X16 interface bifurcated down to two x8 or four x4 (or combinations)
o X8 interface bifurcated down to two x4
DMI2 Interface to the PCH: The platform requires an interface to the legacy
Southbridge (PCH) which provides basic, legacy functions required for the server
platform and operating systems. Since only one PCH is required and allowed for the
system, any sockets which do not connect to PCH would use this port as a standard x4
PCI Express 2.0 interface.
Integrated IOAPIC: Provides support for PCI Express devices implementing legacy
interrupt messages without interrupt sharing
Non Transparent Bridge: PCI Express non-transparent bridge (NTB) acts as a gateway
that enables high performance, low overhead communication between two intelligent
subsystems; the local and the remote subsystems. The NTB allows a local processor to
independently configure and control the local subsystem, provides isolation of the local
host memory domain from the remote host memory domain while enabling status and
data exchange between the two domains.
Intel
®
QuickData Technology: Used for efficient, high bandwidth data movement
between two locations in memory or from memory to I/O.
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Intel® Server Board S2600CO Family TPS Functional Architecture Overview
Intel® C600
Series Chipset
Intel®
Ethernet
Controller
I350
Dual 1Gb LAN
Dual GbDual Gb
Dual 1Gb LAN
Dual GbDual Gb
Intel® Xeon®
E5-2600
CPU 1
Intel® Xeon®
E5-2600
CPU2
Slot 2: x16 Conn
Slot 1 x8 Conn
Slot 3: x16 Conn
DMI2 PCIe Gen2 x4 (4GB/s)
QPI
QPI
P2 P1P3P0
IOU0 IOU2IOU1
P1P3 P2P0
IOU2
IOU1
IOU0
PCIe Gen
3
x
16
(32
GB
/s
)
PCIe Gen3 x16(32GB/s)
Slot 5: x16 Conn
Slot 4: x8 Conn
Slot 6 x16 Conn
PCIe Gen3 x4 (8GB/s)
PCIe Gen3 x4 (8GB/s)
PCIe Gen3 x16
(32GB/s)
PCIe Gen3 x16 (32GB/s)
PCIe Gen
3
x
8
(
16
GB
/
s
)
PCIe Gen3 x4 (8GB/s)
PCIe Gen
2
x
4
(
4
GB
/
s
)
Figure 14. Functional Block Diagram of Processor IIO Sub-system
The following sub-sections will describe the server board features that are directly supported by
the processor IIO module. These include the PCI Card Slots, Network Interface, and connectors
for the optional SAS Module. Features and functions of the Intel® C600 Series chipset will be
described in its own dedicated section.
3.2.3.1 PCI Card Support
The server board provides six PCI card slots identified by PCIe Slot 1 to PCIe Slot 6. The PCIe
slot 1 is routed from Intel® C600 Series Chipset, The PCIe slot 2 and 5 are routed from CPU 1.
The PCIe slot 3, 4, 6 are routed from CPU 2.
Slot 1: PCIe Gen II x4 electrical with x8 physical connector, routed from Intel
Chipset, support half-length card
Slot 2: PCIe Gen III x16 electrical with x16 physical connector, routed from CPU1,
support full length card
Slot 3: PCIe Gen III x16 electrical with x16 physical connector, routed from CPU2,
®
C600
support full length, double width card
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External Name
Description
Product Code
Intel® Integrated RAID Module
RMS25KB080
8 Port SAS, PCIe Slot
RAID Levels 0,1,1E and 10
RMS25KB080
Intel® Integrated RAID Module
RMS25KB040
4 Port SAS, PCIe Slot
RAID Levels 0,1,1E and10
RMS25KB040
Intel® Integrated RAID Module
RMS25PB080
8 Port SAS/SATA, PCIe Slot
RAID Levels 0,1,10, 5, 50, 6, 60
RMS25PB080
Intel® Integrated RAID Module
RMS25PB040
4 Port SAS/SATA, PCIe Slot
RAID Levels 0,1,10, 5, 50, 6, 60
RMS25PB040
Intel® Integrated RAID Module
RMT3PB080
8 Port SATA, PCIe Slot
RAID Levels 0,1,10, 5, 50, 6, 60
RMT3PB080
Slot 4: PCIe Gen III x8 electrical with x8 connector, routed from CPU2, support full
length card; support Intel designed SAS RAID on Card (ROC) Module (PCIe slot form
factor)
Slot 5: PCIe Gen III x16 electrical with x16 connector, routed from CPU1, support full
length, double width card
Slot 6: PCIe Gen III x16 electrical with x16 connector, routed from CPU2, support half-
length card, Intel PCIe riser card
Note: PCIe Slot 3, 4, 6 can only be used in dual processor configurations.
3.2.3.2 Intel
®
Integrated RAID Option
The server board provides support for Intel® Integrated RAID modules with PCIe form factor.
These optional modules attach to PCIe slot4 on the server board and are supported by x8 PCIe
Gen3 signals from the IIO module of the CPU 2 processor. Features of this option include:
SKU options to support full or entry level hardware RAID
Dual-core 6Gb SAS ROC
4 or 8 port and SAS/SATA or SATASKU options to support 512MB or 1GB embedded
memory
Intel designed flash + optional support for super-cap backup (Maintenance Free Back
Up) or improved Lithium Polymer battery
Table 7. Supported Intel® Integrated RAID Modules
For additional product information, please refer the following Intel documents:
1. Intel® Integrated RAID Module RMS25PB080, RMS25PB040, RMS25CB080, and
RMS25CB040 Hardware/Installation User Guide
2. Intel Integrated RAID Module RMS25KB040, RMS25KB080, RMS25JB040,
RMS25JB080 –Hardware/Installation User Guide
3. Intel Integrated RAID Module RMT3PB080 and RMT3CB080 –Hardware/Installation
User Guide
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Product Code
Description
AXX2UPCIEX16
2U PCIe x16 riser, 1 slot
x16 electrical/x16 mechanical
AXX2UPCIEX8X4
2U PCIe x16 riser, 3 slots
one x8 electrical/x16 mechanical
Two x4 electrical/x8 mechanical
AXX1UPCIEX16
1U PCIe x16 riser, 1 slot
x16 electrical/x16 mechanical
LED
Color
LED State
NIC State
Left
Green
Off
LAN link not established
On
LAN link is established
Blinking
LAN activity is occurring
Right
N/A
Off
10 Mb/sec data rate
Amber
On
100 Mb/sec data rate
Green
On
1000 Mb /sec data rate
3.2.3.3 Intel Riser Card Option
The server board provides support for Intel® Riser Card. These optional modules attach to PCIe
slot6 on the server board and are supported by x16 PCIe Gen3 signals from the IIO module of
the CPU 2 processor.
Table 8. Supported Intel® Riser Card
3.2.3.4 Network Interface
Network connectivity is provided by means of an onboard Intel® Ethernet Controller 1350-AM4
providing up to four 10/100/1000 Mb Ethernet ports. The NIC chip is supported by implementing
x4 PCIe Gen3 signals from the IIO module of the CPU 1 processor.
On the Intel® Server Board S2600CO, four external 10/100/1000 Mb RJ45 Ethernet ports are
provided. Each Ethernet port drives two LEDs located on each network interface connector. The
LED at the right of the connector is the link/activity LED and indicates network connection when
on, and transmit/receive activity when blinking. The LED at the left of the connector indicates
link speed as defined in the following table.
Table 9. External RJ45 NIC Port LED Definition
The server board has seven MAC addresses programmed at the factory. MAC addresses are
assigned as follows:
NIC 1 MAC address (for OS usage)
NIC 2 MAC address = NIC 1 MAC address + 1 (for OS usage)
NIC 3 MAC address = NIC 1 MAC address + 2 (for OS usage)
NIC 4 MAC address = NIC 1 MAC address + 3 (for OS usage)
BMC LAN channel 1 MAC address = NIC1 MAC address + 4
BMC LAN channel 2 MAC address = NIC1 MAC address + 5
BMC LAN channel 3 (RMM) MAC address = NIC1 MAC address + 6
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Intel® C600
Series Chipset
Integrated
BMC
LPC (33MHz)
USB 2.0 (480Mbs)
SMBUS PORTS
USB 2.0
Zepher
Connector
TPM
Connector
SATA
4 USB 2.0 EXT
SCU SATA/SAS
(3GB/s)
USB 2.0
2 USB 2.0 INT
PCIe Gen1 x1
DRAM
DRAM
8MB BIOS
SPI Flash
SCU[7:4]
USB2.0
SCU[3:0] P[5:2] P[1:0]
LHSRHS
USB2.0
Type-A
Internal
Connector
USB[7,6,5,1]
USB[13,11]
USB[0]
USB[2]
USB 1.1 (12Mbs)
USB[10]
USB[3]
SATA/SAS
Slot 1 x8 Conn
PCIe Gen1 x1
1394b INT
1394b INT
LSI
FW643E-02
11x11
3port 1394b
PCIe Gen2 x4 (4GB/s)
SATA
SATA/SAS
AHCI SATA
(6GB/s)
SATA/SAS
SATA/SAS
SATA/SAS
SATA/SAS
SATA/SAS
SATA/SAS
4 SATA 3G
Upgradable to
8 SATA/SAS 3G
3.3 Intel
®
C600-A Chipset Functional Overview
The following sub-sections will provide an overview of the key features and functions of the
Intel® C600-A chipset used on the server board. For more comprehensive chipset specific
information, refer to the Intel® C600 Series chipset documents listed in the Reference Document
list.
Figure 15. Functional Block Diagram - Chipset Supported Features and Functions
On the Intel® Server Boards S2600CO, the chipset provides support for the following on-board
functions:
Low Pin Count (LPC) interface
Serial Peripheral Interface (SPI)
Universal Serial Bus (USB) Controller
Serial Attached SCSI (SAS)/Serial ATA (SATA) Support
Manageability Features
3.3.1 Low Pin Count (LPC) Interface
The chipset implements an LPC Interface as described in the LPC 1.1Specification and
provides support for up to two Master/DMI devices. On the server board, the LPC interface is
utilized as an interconnect between the chipset and the Integrated Base Board Management
Controller (IBMC) as well as providing support for the optional Trusted Platform Module (TMP).
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3.3.2 Universal Serial Bus (USB) Controller
The chipset has two Enhanced Host Controller Interface (EHCI) host controllers that support
USB high-speed signaling. High-speed USB 2.0 allows data transfers up to 480 Mb/s which is
40 times faster than full-speed USB. The server board utilizes ten USB 2.0 ports from the
chipset. All ports are high-speed, full- speed, and low-speed capable.
Four external USB ports are provided in a stacked housing located on the rear I/O
section of the server board.
Two USB ports are routed to an internal 10-pin connector that can be cabled for front
panel support.
One internal Type ‘A’ USB port.
One eUSB connector intended for use with an optional eUSB SSD device.
Two USB ports are routed to the IBMC.
3.3.2.1 eUSB SSD Support
The server board provides support for a low profile eUSB SSD storage device. A 2mm 2x5-pin
connector labeled “eUSB SSD” is used to plug this small flash storage device into.
3.3.3 On-board Serial Attached SCSI (SAS)/Serial ATA (SATA)/RAID Support and
Options
The Intel® C600-A chipset provides storage support by two integrated controllers: Advanced
Host Controller Interface (AHCI) and SCU. By default the server board will support up to 6
SATA ports: Two single 6Gb/sec SATA ports routed from the AHCI controller to the two white
SATA connectors labeled “SATA_0” and “SATA_1”, and four 3Gb/sec SATA ports routed from
the SCU to the blue SATA/SAS port connectors labeled “SATA/SAS_0”, “SATA/SAS_1”,
“SATA/SAS_2”, “SATA/SAS_3”.
AHCI SATA_0 port also supports high profile, vertical SATA DOM header with onboard power.
Note: The connectors labeled “SATA/SAS_4” to “SATA/SAT_7” is NOT functional by default
and is only enabled with the addition of an Intel® RAID C600 Upgrade Key option supporting 8
SATA/SAS ports.
The server board is capable of supporting additional chipset embedded SAS, SATA, and RAID
options from the SCU controller when configured with one of several available Intel® RAID C600
Upgrade Keys. Upgrade keys install onto a 4-pin connector on the server board labeled
“STRO_UPG_KEY”.
Figure 16. Intel® RAID C600 Upgrade Key Connector
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Intel® RAID C600 Upgrade Key Options
Key Color
Description
Default – No option key installed
N/A
4 Port SATA with Intel® ESRT RAID 0,1,10 and
Intel® RSTe RAID 0,1,5,10
RKSATA4R5
Black
4 Port SATA with Intel® ESRT2 RAID 0,1, 5, 10
and Intel® RSTe RAID 0,1,5,10
RKSATA8
Blue
8 Port SATA with Intel® ESRT2 RAID 0,1, 10
and Intel® RSTe RAID 0,1,5,10
RKSATA8R5
White
8 Port SATA with Intel® ESRT2 RAID 0,1, 5, 10
and Intel® RSTe RAID 0,1,5,10
RKSAS4
Green
4 Port SAS with Intel® ESRT2 RAID 0,1, 10 and
Intel® RSTe RAID 0,1,10
RKSAS4R5
Yellow
4 Port SAS with Intel® ESRT2 RAID 0,1, 5, 10
and Intel® RSTe RAID 0,1,10
RKSAS8
Orange
8 Port SAS with Intel® ESRT2 RAID 0,1, 10 and
Intel® RSTe RAID 0,1,10
RKSAS8R5
Purple
8 Port SAS with Intel® ESRT2 RAID 0,1, 5, 10
and Intel® RSTe RAID 0,1,10
The following table identifies available upgrade key options and their supported features.
Table 10. Intel® RAID C600 Upgrade Key Options
Additional information for the on-board RAID features and functionality can be found in the Intel®
RAID Software User’s Guide.
The system includes support for two embedded software RAID options:
Intel
®
Embedded Server RAID Technology 2 (ESRT2) based on LSI* MegaRAID SW
RAID technology
Intel
®
Rapid Storage Technology (RSTe)
Using the <F2> BIOS Setup Utility, accessed during system POST, options are available to
enable/disable SW RAID, and select which embedded software RAID option to use.
3.3.3.1 Intel
®
Embedded Server RAID Technology 2 (ESRT2)
Features of the embedded software RAID option Intel® Embedded Server RAID Technology 2
(ESRT2) include the following:
Based on LSI* MegaRAID Software Stack
Software RAID with system providing memory and CPU utilization
Supported RAID Levels – 0,1,5,10
o 4 & 8 Port SATA RAID 5 support provided with appropriate Intel® RAID C600
Upgrade Key
o 4 & 8 Port SAS RAID 5 support provided with appropriate Intel® RAID C600
Upgrade Key
Maximum drive support = 8 (with or without SAS expander option installed)
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Open Source Compliance = Binary Driver (includes Partial Source files) or Open Source
using MDRAID layer in Linux.
OS Support = Windows 7*, Windows 2008*, Windows 2003*, RHEL*, SLES, other Linux*
variants using partial source builds.
Utilities = Windows* GUI and CLI, Linux GUI and CLI, DOS CLI, and EFI CLI
3.3.3.2 Intel
Features of the embedded software RAID option Intel® Rapid Storage Technology (RSTe)
include the following:
Software RAID with system providing memory and CPU utilization
Supported RAID Levels – 0,1,5,10
o 4 Port SATA RAID 5 available standard (no option key required)
o 8 Port SATA RAID 5 support provided with appropriate Intel® RAID C600
o No SAS RAID 5 support
Maximum drive support = 32 (in arrays with 8 port SAS), 16 (in arrays with 4 port SAS),
128 (JBOD)
Open Source Compliance = Yes (uses MDRAID)
OS Support = Windows 7*, Windows 2008*, Windows 2003*, RHEL* 6.2 and later,
SLES* 11 w/SP2 and later, VMWare 5.x.
Utilities = Windows* GUI and CLI, Linux CLI, DOS CLI, and EFI CLI
Uses Matrix Storage Manager for Windows
MDRAID supported in Linux (Does not require a driver)
Note: No boot drive support to targets attached through SAS expander card
®
Rapid Storage Technology (RSTe)
Upgrade Key
3.3.4 Manageability
The chipset integrates several functions designed to manage the system and lower the total
cost of ownership (TCO) of the system. These system management functions are designed to
report errors, diagnose the system, and recover from system lockups without the aid of an
external microcontroller.
TCO Timer. The chipset’s integrated programmable TCO timer is used to detect system
locks. The first expiration of the timer generates an SMI# that the system can use to
recover from a software lock. The second expiration of the timer causes a system reset
to recover from a hardware lock.
Processor Present Indicator. The chipset looks for the processor to fetch the first
instruction after reset. If the processor does not fetch the first instruction, the chipset will
reboot the system.
ECC Error Reporting. When detecting an ECC error, the host controller has the ability
to send one of several messages to the chipset. The host controller can instruct the
chipset to generate an SMI#, NMI, SERR#, or TCO interrupt.
Function Disable. The chipset provides the ability to disable the following integrated
functions: LAN, USB, LPC, SATA, PCI Express or SMBus. Once disabled, these
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Intel® C600
Series Chipset
Integrated
BMC
LPC (33MHz)
USB 2.0 (480Mbs)
SMBUS PORTS
NC-SI PORT 0 (RGMII)
VIDEO RGB
RMM4 Dedicated NIC
Module Connector
SERIAL PORT 1
2x5 HDR
TPM
Connector
SERIAL PORT 0
PCIe Gen1 x1
DRAM
16MB
iBMC SPI
Flash
DRAM
128MB
DDR3
USB 1.1 (12Mbs)
USB[10]
USB[3]
functions no longer decode I/O, memory, or PCI configuration space. Also, no interrupts
or power management events are generated from the disabled functions.
3.4 Integrated Baseboard Management Controller Overview
The server board utilizes the I/O controller, Graphics Controller, and Baseboard Management
features of the Server Engines* Pilot-III Server Management Controller. The following is an
overview of the features as implemented on the server board from each embedded controller.
Figure 17. Integrated BMC Functional Block Diagram
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Figure 18. Integrated BMC Hardware
3.4.1 Super I/O Controller
The integrated super I/O controller provides support for the following features as implemented
on the server board:
Two Fully Functional Serial Ports, compatible with the 16C550
Serial IRQ Support
Up to 16 Shared direct GPIO’s
Serial GPIO support for 80 general purpose inputs and 80 general purpose outputs
available for host processor
Programmable Wake-up Event Support
Plug and Play Register Set
Power Supply Control
Host SPI bridge for system BIOS support
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2D Mode
2D Video Mode Support
8 bpp
16 bpp
24 bpp
32 bpp
640x480
Supported
Supported
Supported
Supported
800x600
Supported
Supported
Supported
Supported
1024x768
Supported
Supported
Supported
Supported
1152x864
Supported
Supported
Supported
Supported
1280x1024
Supported
Supported
Supported
Supported
1600x1200**
Supported
Supported
3.4.1.1 Keyboard and Mouse Support
The server board does not support PS/2 interface keyboards and mice. However, the system
BIOS recognizes USB specification-compliant keyboard and mice.
3.4.1.2 Wake-up Control
The super I/O contains functionality that allows various events to power on and power off the
system.
3.4.2 Graphics Controller and Video Support
The integrated graphics controller provides support for the following features as implemented on
the server board:
Integrated Graphics Core with 2D Hardware accelerator
DDR-3 memory interface with 16MB of memory allocated and reported for graphics
memory
High speed Integrated 24-bit RAMDAC
Single lane PCI-Express host interface running at Gen 1 speed
The integrated video controller supports all standard IBM VGA modes. The following table
shows the 2D modes supported for both CRT and LCD:
Table 11. Video Modes
** Video resolutions at 1600x1200 and higher are only supported through the
external video connector located on the rear I/O section of the server board.
Utilizing the optional front panel video connector may result in lower video
resolutions.
The server board provides one video interfaces. The video interface is accessed using a
standard 15-pin VGA connector found on the back edge of the server board.
The BIOS supports dual-video mode when an add-in video card is installed.
In the single mode (dual monitor video = disabled), the on-board video controller is disabled
when an add-in video card is detected.
In the dual mode (on-board video = enabled, dual monitor video = enabled), the on-board video
controller is enabled and is the primary video device. The add-in video card is allocated
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On-board Video
Enabled
Disabled
Dual Monitor Video
Enabled
Disabled
Shaded if on-board video is set to "Disabled"
resources and is considered the secondary video device. The BIOS Setup utility provides
options to configure the feature as follows:
Table 12. Video mode
3.4.3 Baseboard Management Controller
The server board utilizes the following features of the embedded baseboard management
controller.
IPMI 2.0 Compliant
400MHz 32-bit ARM9 processor with memory management unit (MMU)
Two independent10/100/1000 Ethernet Controllers with Reduced Media Independent
Interface (RMII)/ Reduced Gigabit Media Independent Interface (RGMII) support
DDR2/3 16-bit interface with up to 800 MHz operation
16 10-bit ADCs
Sixteen fan tachometers
Eight Pulse Width Modulators (PWM)
Chassis intrusion logic
JTAG Master
Eight I2C interfaces with master-slave and SMBus timeout support. All interfaces are
SMBus 2.0 compliant.
Parallel general-purpose I/O Ports (16 direct, 32 shared)
Serial general-purpose I/O Ports (80 in and 80 out)
Three UARTs
Platform Environmental Control Interface (PECI)
Six general-purpose timers
Interrupt controller
Multiple Serial Peripheral Interface (SPI) flash interfaces
NAND/Memory interface
Sixteen mailbox registers for communication between the BMC and host
LPC ROM interface
BMC watchdog timer capability
SD/MMC card controller with DMA support
LED support with programmable blink rate controls on GPIOs
Port 80h snooping capability
Secondary Service Processor (SSP), which provides the HW capability of offloading time
critical processing tasks from the main ARM core.
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3.4.3.1 Remote Keyboard, Video, Mourse, and Storage (KVMS) Support
USB 2.0 interface for Keyboard, Mouse and Remote storage such as CD/DVD ROM and
floppy
USB 1.1/USB 2.0 interface for PS2 to USB bridging, remote Keyboard and Mouse
Hardware Based Video Compression and Redirection Logic
Supports both text and Graphics redirection
Hardware assisted Video redirection using the Frame Processing Engine
Direct interface to the Integrated Graphics Controller registers and Frame buffer
Hardware-based encryption engine
3.4.3.2 Integrated BMC Embedded LAN Channel
The Integrated BMC hardware includes two dedicated 10/100 network interfaces. These
interfaces are not shared with the host system. At any time, only one dedicated interface may
be enabled for management traffic. The default active interface is the NIC 1 port.
For these channels, support can be enabled for IPMI-over-LAN and DHCP. For security
reasons, embedded LAN channels have the following default settings:
IP Address: Static.
All users disabled.
For a functional overview of the baseboard management features, refer to Chapter 6.
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4. Technology Support
4.1 Intel
The Intel® Xeon® Processor E5 4600/2600/2400/1600 Product Families support Intel® Trusted
Execution Technology (Intel® TXT), which is a robust security environment designed to help
protect against software-based attacks. Intel® Trusted Execution Technology integrates new
security features and capabilities into the processor, chipset and other platform components.
When used in conjunction with Intel® Virtualization Technology and Intel® VT for Directed IO,
with an active TPM, Intel® Trusted Execution Technology provides hardware-rooted trust for
your virtual applications.
4.2 Intel
Intel® Virtualization Technology consists of three components which are integrated and
interrelated, but which address different areas of Virtualization.
Intel® Virtualization Technology (VT-x) is processor-related and provides capabilities
Intel® Virtualization Technology for Directed I/O (VT-d) is primarily concerned with
Intel® Virtualization Technology for Connectivity (VT-c) is primarily concerned I/O
Intel ®VT-x is designed to support multiple software environments sharing same hardware
resources. Each software environment may consist of OS and applications. The Intel®
Virtualization Technology features can be enabled or disabled in the BIOS setup. The default
behavior is disabled.
Intel® VT-d is supported jointly by the Intel® Xeon® Processor E5 4600/2600/2400/1600 Product
Families and the C600 chipset. Both support DMA remapping from inbound PCI Express*
memory Guest Physical Address (GPA) to Host Physical Address (HPA). PCI devices are
directly assigned to a virtual machine leading to a robust and efficient virtualization.
The Intel® S4600/S2600/S2400/S1600/S1400 Server Board Family BIOS publishes the DMAR
table in the ACPI Tables. For each DMA Remapping Engine in the platform, one exact entry of
DRHD (DMA Remapping Hardware Unit Definition) structure is added to the DMAR. The DRHD
structure in turn contains a Device Scope structure that describes the PCI endpoints and/or subhierarchies handled by the particular DMA Remapping Engine.
Similarly, there are reserved memory regions typically allocated by the BIOS at boot time. The
BIOS marks these regions as either reserved or unavailable in the system address memory
map reported to the OS. Some of these regions can be a target of DMA requests from one or
more devices in the system, while the OS or executive is active. The BIOS reports each such
memory region using exactly one RMRR (Reserved Memory Region Reporting) structure in the
DMAR. Each RMRR has a Device Scope listing the devices in the system that can cause a
DMA request to the region.
For more information on the DMAR table and the DRHD entry format, refer to the Intel®
Virtualization Technology for Directed I/O Architecture Specification. For more general
®
Trusted Execution Technology
®
Virtualization Technology – Intel® VT-x/VT-d/VT-c
needed to provide a hardware assist to a Virtual Machine Monitor (VMM).
virtualizing I/O efficiently in a VMM environment. This would generally be a chipset I/O
feature, but in the Second Generation Intel® Core™ Processor Family there is an
Integrated I/O unit embedded in the processor, and the IIO is also enabled for VT-d.
hardware assist features, complementary to but independent of VT-d.
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IT Challenge
Requirement
Over-allocation of power
Ability to monitor actual power consumption
•Control capability that can maintain a power budget to
enable dynamic power allocation to each server
Under-population of rack space
Control capability that can maintain a power budget to
enable increased rack population.
High energy costs
Control capability that can maintain a power budget to
ensure that a set energy cost can be achieved
Capacity planning
Ability to monitor actual power consumption to enable
power usage modeling over time and a given planning
period
•Ability to understand cooling demand from a
temperature and airflow perspective
Detection and correction of hot spots
Control capability that reduces platform power
consumption to protect a server in a hot-spot.
Ability to monitor server inlet temperatures to enable
greater rack utilization in areas with adequate cooling.
information about VT-x, VT-d, and VT-c, a good reference is Enabling Intel® Virtualization
Technology Features and Benefits White Paper.
4.3 Intel
®
Intelligent Power Node Manager
Data centers are faced with power and cooling challenges that are driven by increasing
numbers of servers deployed and server density in the face of several data center power and
cooling constraints. In this type of environment, Information Technology (IT) needs the ability to
monitor actual platform power consumption and control power allocation to servers and racks in
order to solve specific data center problems including the following issues:
Table 13. Data Center Problems
The requirements listed above are those that are addressed by the C600 chipset Management
Engine (ME) and Intel® Intelligent Power Node Manager (NM) technology. The ME/NM
combination is a power and thermal control capability on the platform, which exposes external
interfaces that allow IT (through external management software) to query the ME about platform
power capability and consumption, thermal characteristics, and specify policy directives (for
example, set a platform power budget).
Node Manager (NM) is a platform resident technology that enforces power capping and thermaltriggered power capping policies for the platform. These policies are applied by exploiting
subsystem knobs (such as processor P and T states) that can be used to control power
consumption. NM enables data center power management by exposing an external interface to
management software through which platform policies can be specified. It also implements
specific data center power management usage models such as power limiting, and thermal
monitoring.
The NM feature is implemented by a complementary architecture utilizing the ME, BMC, BIOS,
and an ACPI-compliant OS. The ME provides the NM policy engine and power control/limiting
functions (referred to as Node Manager or NM) while the BMC provides the external LAN link by
which external management software can interact with the feature. The BIOS provides system
power information utilized by the NM algorithms and also exports ACPI Source Language (ASL)
code used by OS-Directed Power Management (OSPM) for negotiating processor P and T state
changes for power limiting. PMBus-compliant power supplies provide the capability to
monitoring input power consumption, which is necessary to support NM.
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Following are the some of the applications of Intel® Intelligent Power Node Manager technology.
Platform Power Monitoring and Limiting: The ME/NM monitors platform power
consumption and hold average power over duration. It can be queried to return actual
power at any given instance. The power limiting capability is to allow external
management software to address key IT issues by setting a power budget for each
server. For example, if there is a physical limit on the power available in a room, then IT
can decide to allocate power to different servers based on their usage – servers running
critical systems can be allowed more power than servers that are running less critical
workload.
Inlet Air Temperature Monitoring: The ME/NM monitors server inlet air temperatures
periodically. If there is an alert threshold in effect, then ME/NM issues an alert when the
inlet (room) temperature exceeds the specified value. The threshold value can be set by
policy.
Memory Subsystem Power Limiting: The ME/NM monitors memory power
consumption. Memory power consumption is estimated using average bandwidth
utilization information
Processor Power monitoring and limiting: The ME/NM monitors processor or socket
power consumption and holds average power over duration. It can be queried to return
actual power at any given instant. The monitoring process of the ME will be used to limit
the processor power consumption through processor P-states and dynamic core
allocation
Core allocation at boot time: Restrict the number of cores for OS/VMM use by limiting
how many cores are active at boot time. After the cores are turned off, the CPU will limit
how many working cores are visible to BIOS and OS/VMM. The cores that are turned off
cannot be turned on dynamically after the OS has started. It can be changed only at the
next system reboot.
Core allocation at run-time: This particular use case provides a higher level processor
power control mechanism to a user at run-time, after booting. An external agent can
dynamically use or not use cores in the processor subsystem by requesting ME/NM to
control them, specifying the number of cores to use or not use.
4.3.1 Hardware Requirements
NM is supported only on platforms that have the NM FW functionality loaded and enabled on
the Management Engine (ME) in the SSB and that have a BMC present to support the external
LAN interface to the ME. NM power limiting features requires a means for the ME to monitor
input power consumption for the platform. This capability is generally provided by means of
PMBus-compliant power supplies although an alternative model using a simpler SMBus power
monitoring device is possible (there is potential loss in accuracy and responsiveness using nonPMBus devices). The NM SmaRT/CLST feature does specifically require PMBus-compliant
power supplies as well as additional hardware on the baseboard.
.
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5. System Security
5.1 BIOS Password Protection
The BIOS uses passwords to prevent unauthorized tampering with the server setup. Passwords
can restrict entry to the BIOS Setup, restrict use of the Boot Popup menu, and suppress
automatic USB device reordering.
There is also an option to require a Power On password entry in order to boot the system. If the
Power On Password function is enabled in Setup, the BIOS will halt early in POST to request a
password before continuing POST.
Both Administrator and User passwords are supported by the BIOS. An Administrator password
must be installed in order to set the User password. The maximum length of a password is
14 characters. A password can have alphanumeric (a-z, A-Z, 0-9) characters and it is case
sensitive. Certain special characters are also allowed, from the following set:
! @ # $ % ^ & * ( ) - _ + = ?
The Administrator and User passwords must be different from each other. An error message will
be displayed if there is an attempt to enter the same password for one as for the other.
The use of “Strong Passwords” is encouraged, but not required. In order to meet the criteria for
a “Strong Password”, the password entered must be at least 8 characters in length, and must
include at least one each of alphabetic, numeric, and special characters. If a “weak” password is
entered, a popup warning message will be displayed, although the weak password will be
accepted.
Once set, a password can be cleared by changing it to a null string. This requires the
Administrator password, and must be done through BIOS Setup or other explicit means of
changing the passwords. Clearing the Administrator password will also clear the User
password.
Alternatively, the passwords can be cleared by using the Password Clear jumper if necessary.
Resetting the BIOS configuration settings to default values (by any method) has no effect on the
Administrator and User passwords.
Entering the User password allows the user to modify only the System Time and System Date in
the Setup Main screen. Other setup fields can be modified only if the Administrator password
has been entered. If any password is set, a password is required to enter the BIOS setup.
The Administrator has control over all fields in the BIOS setup, including the ability to clear the
User password and the Administrator password.
It is strongly recommended that at least an Administrator Password be set, since not having set
a password gives everyone who boots the system the equivalent of Administrative access.
Unless an Administrator password is installed, any User can go into Setup and change BIOS
settings at will.
In addition to restricting access to most Setup fields to viewing only when a User password is
entered, defining a User password imposes restrictions on booting the system. In order to
simply boot in the defined boot order, no password is required. However, the F6 Boot popup
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prompts for a password, and can only be used with the Administrator password. Also, when a
User password is defined, it suppresses the USB Reordering that occurs, if enabled, when a
new USB boot device is attached to the system. A User is restricted from booting in anything
other than the Boot Order defined in the Setup by an Administrator.
As a security measure, if a User or Administrator enters an incorrect password three times in a
row during the boot sequence, the system is placed into a halt state. A system reset is required
to exit out of the halt state. This feature makes it more difficult to guess or break a password.
In addition, on the next successful reboot, the Error Manager displays a Major Error code 0048,
which also logs a SEL event to alert the authorized user or administrator that a password
access failure has occurred
5.2 Trusted Platform Module (TPM) Support
The Trusted Platform Module (TPM) option is a hardware-based security device that addresses
the growing concern on boot process integrity and offers better data protection. TPM protects
the system start-up process by ensuring it is tamper-free before releasing system control to the
operating system. A TPM device provides secured storage to store data, such as security keys
and passwords. In addition, a TPM device has encryption and hash functions. The server board
implements TPM as per TPM PC Client specifications revision 1.2 by the Trusted Computing
Group (TCG).
A TPM device is optionally installed onto a high density 14-pin connector labeled “TPM” on the
server board, and is secured from external software attacks and physical theft. A pre-boot
environment, such as the BIOS and operating system loader, uses the TPM to collect and store
unique measurements from multiple factors within the boot process to create a system
fingerprint. This unique fingerprint remains the same unless the pre-boot environment is
tampered with. Therefore, it is used to compare to future measurements to verify the integrity of
the boot process.
After the system BIOS completes the measurement of its boot process, it hands off control to
the operating system loader and in turn to the operating system. If the operating system is TPMenabled, it compares the BIOS TPM measurements to those of previous boots to make sure the
system was not tampered with before continuing the operating system boot process. Once the
operating system is in operation, it optionally uses TPM to provide additional system and data
security (for example, Microsoft Vista* supports Bitlocker drive encryption).
5.2.1 TPM security BIOS
The BIOS TPM support conforms to the TPM PC Client Implementation Specification for
Conventional BIOS and to the TPM Interface Specification, and the Microsoft Windows
BitLocker* Requirements. The role of the BIOS for TPM security includes the following:
Measures and stores the boot process in the TPM microcontroller to allow a TPM
enabled operating system to verify system boot integrity.
Produces EFI and legacy interfaces to a TPM-enabled operating system for using TPM.
Produces ACPI TPM device and methods to allow a TPM-enabled operating system to
send TPM administrative command requests to the BIOS.
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Verifies operator physical presence. Confirms and executes operating system TPM
administrative command requests.
Provides BIOS Setup options to change TPM security states and to clear TPM
ownership.
For additional details, refer to the TCG PC Client Specific Implementation Specification, the
TCG PC Client Specific Physical Presence Interface Specification, and the Microsoft BitLocker*
Requirement documents.
5.2.2 Physical Presence
Administrative operations to the TPM require TPM ownership or physical presence indication by
the operator to confirm the execution of administrative operations. The BIOS implements the
operator presence indication by verifying the setup Administrator password.
A TPM administrative sequence invoked from the operating system proceeds as follows:
1. User makes a TPM administrative request through the operating system’s security software.
2. The operating system requests the BIOS to execute the TPM administrative command
through TPM ACPI methods and then resets the system.
3. The BIOS verifies the physical presence and confirms the command with the operator.
4. The BIOS executes TPM administrative command(s), inhibits BIOS Setup entry and boots
directly to the operating system which requested the TPM command(s).
5.2.3 TPM Security Setup Options
The BIOS TPM Setup allows the operator to view the current TPM state and to carry out
rudimentary TPM administrative operations. Performing TPM administrative options through the
BIOS setup requires TPM physical presence verification.
Using BIOS TPM Setup, the operator can turn ON or OFF TPM functionality and clear the TPM
ownership contents. After the requested TPM BIOS Setup operation is carried out, the option
reverts to No Operation.
The BIOS TPM Setup also displays the current state of the TPM, whether TPM is enabled or
disabled and activated or deactivated. Note that while using TPM, a TPM-enabled operating
system or application may change the TPM state independent of the BIOS setup. When an
operating system modifies the TPM state, the BIOS Setup displays the updated TPM state.
The BIOS Setup TPM Clear option allows the operator to clear the TPM ownership key and
allows the operator to take control of the system with TPM. You use this option to clear security
settings for a newly initialized system or to clear a system for which the TPM ownership security
key was lost.
5.2.3.1 Security Screen
To enter the BIOS Setup, press the F2 function key during boot time when the OEM or Intel logo
displays. The following message displays on the diagnostics screen and under the Quiet Boot
logo screen:
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Main
Advanced
Security
Server Management
Boot Options
Boot Manager
Administrator Password Status
<Installed/Not Installed>
User Password Status
<Installed/Not Installed>
Set Administrator Password
[1234aBcD]
Set User Password
[1234aBcD]
Front Panel Lockout
Enabled/Disabled
TPM State
<Enabled & Activated/Enabled & Deactivated/Disabled &
Activated/Disabled & Deactivated>
TPM Administrative Control
No Operation/Turn On/Turn Off/Clear Ownership
Press <F2> to enter setup
When the Setup is entered, the Main screen displays. The BIOS Setup utility provides the
Security screen to enable and set the user and administrative passwords and to lock out the
front panel buttons so they cannot be used. The Intel® Server Board S5520URT provides TPM
settings through the security screen.
To access this screen from the Main screen, select the Security option.
Figure 19. Setup Utility – TPM Configuration Screen
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Setup Item
Options
Help Text
Comments
TPM State*
Enabled and
Activated
Enabled and
Deactivated
Disabled and
Activated
Disabled and
Deactivated
Information only.
Shows the current TPM device
state.
A disabled TPM device will not
execute commands that use TPM
functions and TPM security
operations will not be available.
An enabled and deactivated TPM
is in the same state as a disabled
TPM except setting of TPM
ownership is allowed if not
present already.
An enabled and activated TPM
executes all commands that use
TPM functions and TPM security
operations will be available.
TPM
Administrative
Control**
No Operation
Turn On
Turn Off
Clear Ownership
[No Operation] - No changes to
current state.
[Turn On] - Enables and activates
TPM.
[Turn Off] - Disables and deactivates
TPM.
[Clear Ownership] - Removes the
TPM ownership authentication and
returns the TPM to a factory default
state.
Note: The BIOS setting returns to
[No Operation] on every boot cycle
by default.
Table 14. Setup Utility – Security Configuration Screen Fields
5.3 Intel
®
Trusted Execution Technology
The Intel® Xeon® Processor E5-4600/2600/2400/1600 Product Families support Intel® Trusted
Execution Technology (Intel® TXT), which is a robust security environment. Designed to help
protect against software-based attacks, Intel® Trusted Execution Technology integrates new
security features and capabilities into the processor, chipset and other platform components.
When used in conjunction with Intel® Virtualization Technology, Intel® Trusted Execution
Technology provides hardware-rooted trust for your virtual applications.
This hardware-rooted security provides a general-purpose, safer computing environment
capable of running a wide variety of operating systems and applications to increase the
confidentiality and integrity of sensitive information without compromising the usability of the
platform.
Intel® Trusted Execution Technology requires a computer system with Intel® Virtualization
Technology enabled (both VT-x and VT-d), an Intel® Trusted Execution Technology-enabled
processor, chipset and BIOS, Authenticated Code Modules, and an Intel® Trusted Execution
Technology compatible measured launched environment (MLE). The MLE could consist of a
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virtual machine monitor, an OS or an application. In addition, Intel® Trusted Execution
Technology requires the system to include a TPM v1.2, as defined by the Trusted Computing
Group TPM PC Client Specifications, Revision 1.2.
When available, Intel Trusted Execution Technology can be enabled or disabled in the
processor from a BIOS Setup option.
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6. Platform Management Functional Overview
Platform management functionality is supported by several hardware and software components
integrated on the server board that work together to control system functions, monitor and report
system health, and control various thermal and performance features in order to maintain (when
possible) server functionality in the event of component failure and/or environmentally stressed
conditions.
This chapter provides a high level overview of the platform management features and
functionality implemented on the server board. For more in depth and design level Platform
Management information, please reference the BMC Core Firmware External Product
Specification (EPS) and BIOS Core External Product Specification (EPS) for Intel® Server
products based on the Intel® Xeon® processor E5-4600,2600,1600 product families.
6.1 Baseboard Management Controller (BMC) Firmware Feature Support
The following sections outline features that the integrated BMC firmware can support. Support
and utilization for some features is dependent on the server platform in which the server board
is integrated and any additional system level components and options that may be installed.
6.1.1 IPMI 2.0 Features
Baseboard management controller (BMC)
IPMI Watchdog timer
Messaging support, including command bridging and user/session support
Chassis device functionality, including power/reset control and BIOS boot flags support
Event receiver device: The BMC receives and processes events from other platform
subsystems.
Field Replaceable Unit (FRU) inventory device functionality: The BMC supports access
to system FRU devices using IPMI FRU commands.
System Event Log (SEL) device functionality: The BMC supports and provides access to
a SEL.
Sensor Data Record (SDR) repository device functionality: The BMC supports storage
and access of system SDRs.
Sensor device and sensor scanning/monitoring: The BMC provides IPMI management of
sensors. It polls sensors to monitor and report system health.
IPMI interfaces
o Host interfaces include system management software (SMS) with receive
message queue support, and server management mode (SMM)
o IPMB interface
o LAN interface that supports the IPMI-over-LAN protocol (RMCP, RMCP+)
Serial-over-LAN (SOL)
ACPI state synchronization: The BMC tracks ACPI state changes that are provided by
the BIOS.
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BMC self-test: The BMC performs initialization and run-time self-tests and makes results
available to external entities.
See also the Intelligent Platform Management Interface Specification Second Generation
v2.0.
6.1.2 Non IPMI Features
The BMC supports the following non-IPMI features.
In-circuit BMC firmware update
Fault resilient booting (FRB): FRB2 is supported by the watchdog timer functionality.
Chassis intrusion detection (dependent on platform support)
Basic fan control using Control version 2 SDRs
Fan redundancy monitoring and support
Power supply redundancy monitoring and support
Hot-swap fan support
Acoustic management: Support for multiple fan profiles
Signal testing support: The BMC provides test commands for setting and getting
platform signal states.
The BMC generates diagnostic beep codes for fault conditions.
System GUID storage and retrieval
Front panel management: The BMC controls the system status LED and chassis ID
LED. It supports secure lockout of certain front panel functionality and monitors button
presses. The chassis ID LED is turned on using a front panel button or a command.
Power state retention
Power fault analysis
Intel® Light-Guided Diagnostics
Power unit management: Support for power unit sensor. The BMC handles power-good
dropout conditions.
DIMM temperature monitoring: New sensors and improved acoustic management using
closed-loop fan control algorithm taking into account DIMM temperature readings.
Address Resolution Protocol (ARP): The BMC sends and responds to ARPs (supported
on embedded NICs).
Dynamic Host Configuration Protocol (DHCP): The BMC performs DHCP (supported on
embedded NICs).
Platform environment control interface (PECI) thermal management support
E-mail alerting
Embedded web server
Integrated KVM
Integrated Remote Media Redirection
Lightweight Directory Access Protocol (LDAP) support
Intel® Intelligent Power Node Manager support
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6.1.3 New Manageability Features
Intel® S2600CO Server Platforms offer a number of changes and additions to the manageability
features that are supported on the previous generation of servers. The following is a list of the
more significant changes that are common to this generation Integrated BMC based on Intel®
Xeon® Processors E5 2600 Families:
Sensor and SEL logging additions/enhancements (for example, additional thermal
monitoring capability)
SEL Severity Tracking and the Extended SEL
Embedded platform debug feature which allows capture of detailed data for later
analysis.
Provisioning and inventory enhancements:
o Inventory data/system information export (partial SMBIOS table)
Enhancements to fan speed control.
DCMI 1.1 compliance (product-specific).
Support for embedded web server UI in Basic Manageability feature set.
Enhancements to embedded web server
o Human-readable SEL
o Additional system configurability
o Additional system monitoring capability
o Enhanced on-line help
Enhancements to KVM redirection
o Support for higher resolution
Support for EU Lot6 compliance
Management support for PMBus rev1.2 compliant power supplies
BMC Data Repository (Managed Data Region Feature)
Local Control Display Panel
System Airflow Monitoring
Exit Air Temperature Monitoring
Ethernet Controller Thermal Monitoring
Global Aggregate Temperature Margin Sensor
Memory Thermal Management
Power Supply Fan Sensors
Energy Star Server Support
Smart Ride Through (SmaRT)/Closed Loop System Throttling (CLST)
Power Supply Cold Redundancy
Power Supply FW Update
Power Supply Compatibility Check
BMC FW reliability enhancements:
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o Redundant BMC boot blocks to avoid possibility of a corrupted boot block resulting
in a scenario that prevents a user from updating the BMC.
o BMC System Management Health Monitoring
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State
Supported
Description
S0
Yes
Working.
The front panel power LED is on (not controlled by the BMC).
The fans spin at the normal speed, as determined by sensor inputs.
Front panel buttons work normally.
S1
Yes
Sleeping. Hardware context is maintained; equates to processor and chipset clocks being
stopped.
The front panel power LED blinks at a rate of 1 Hz with a 50% duty cycle (not controlled
by the BMC).
The watchdog timer is stopped.
The power, reset, front panel NMI, and ID buttons are unprotected.
Fan speed control is determined by available SDRs. Fans may be set to a fixed state, or
basic fan management can be applied.
The BMC detects that the system has exited the ACPI S1 sleep state when the BIOS SMI
handler notifies it.
S2
No
Not supported.
S3
No
Not supported.
S4
No
Not supported.
S5
Yes
Soft off.
The front panel buttons are not locked.
The fans are stopped.
The power-up process goes through the normal boot process.
The power, reset, front panel NMI, and ID buttons are unlocked.
Source
External Signal Name or Internal
Subsystem
Capabilities
Power Button
Front Panel power button
Turns power on or off
BMC watchdog timer
Internal BMC timer
Turns power off, or power cycle
Command
Routed through command processor
Turns power on or off, or power cycle
Power state retention
Implemented by means of BMC
internal logic
Turns power on when AC power returns
Chipset
Sleep S4/S5 signal (same as
POWER_ON)
Turns power on or off
CPU Thermal
CPU Thermtrip
Turns power off
6.2 Advanced Configuration and Power Interface (ACPI)
The server board has support for the following ACPI states:
Table 15. ACPI Power States
6.3 Power Control Sources
The server board supports several power control sources which can initiate a power-up or
power-down activity.
Table 16. Power Control Initiators
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Source
External Signal Name or Internal
Subsystem
Capabilities
WOL (Wake On LAN)
LAN
Turn power on
6.4 BMC Watchdog
The BMC FW is increasingly called upon to perform system functions that are time-critical in
that failure to provide these functions in a timely manner can result in system or component
damage. Intel® S1400/S1600/S2400/S2600/S4600 Server Platforms introduce a BMC watchdog
feature to provide a safe-guard against this scenario by providing an automatic recovery
mechanism. It also can provide automatic recovery of functionality that has failed due to a fatal
FW defect triggered by a rare sequence of events or a BMC hang due to some type of HW
glitch (for example, power).
This feature is comprised of a set of capabilities whose purpose is to detect misbehaving
subsections of BMC firmware, the BMC CPU itself, or HW subsystems of the BMC component,
and to take appropriate action to restore proper operation. The action taken is dependent on
the nature of the detected failure and may result in a restart of the BMC CPU, one or more BMC
HW subsystems, or a restart of malfunctioning FW subsystems.
The BMC watchdog feature will only allow up to three resets of the BMC CPU (such as HW
reset) or entire FW stack (such as a SW reset) before giving up and remaining in the uBOOT
code. This count is cleared upon cycling of power to the BMC or upon continuous operation of
the BMC without a watchdog-generated reset occurring for a period of > 30 minutes. The BMC
FW logs a SEL event indicating that a watchdog-generated BMC reset (either soft or hard reset)
has occurred. This event may be logged after the actual reset has occurred. Refer sensor
section for details for the related sensor definition. The BMC will also indicate a degraded
system status on the Front Panel Status LED after an BMC HW reset or FW stack reset. This
state (which follows the state of the associated sensor) will be cleared upon system reset or (AC
or DC) power cycle.
Note: There will no SEL event and front panel LED status change for BMC reset due to Linux
“kernel panic”.
A reset of the BMC may result in the following system degradations that will require a system
reset or power cycle to correct:
1. Timeout value for the rotation period can be set using this parameterPotentially incorrect
ACPI Power State reported by the BMC.
2. Reversion of temporary test modes for the BMC back to normal operational modes.
3. FP status LED and DIMM fault LEDs may not reflect BIOS detected errors.
6.5 Fault Resilient Booting (FRB)
Fault resilient booting (FRB) is a set of BIOS and BMC algorithms and hardware support that
allow a multiprocessor system to boot even if the bootstrap processor (BSP) fails. Only FRB2 is
supported using watchdog timer commands.
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FSB2 refers to the FRB algorithm that detects system failures during POST. The BIOS uses the
BMC watchdog timer to back up its operation during POST. The BIOS configures the watchdog
timer to indicate that the BIOS is using the timer for the FRB2 phase of the boot operation. After
the BIOS has identified and saved the BSP information, it sets the FRB2 timer use bit and loads
the watchdog timer with the new timeout internal.
If the watchdog timer expires while the watchdog use bit is set to FRB2, the BMC (if so
configured) logs a watchdog expiration event showing the FRB2 timeout in the event data bytes.
The BMC then hard resets the system, assuming the BIOS-selected reset as the watchdog
timeout action.
The BIOS is responsible for disabling the FRB2 timeout before initiating the option ROM scan
and before displaying a request for a boot password. If the processor fails and causes an FRB2
timeout, the BMC resets the system.
The BIOS gets the watchdog expiration status from the BMC. If the status shows an expired
FRB2 timer, the BIOS enters the failure in the system event log (SEL). In the OEM bytes entry
in the SEL, the last POST code generated during the previous boot attempt is written. FRB2
failure is not reflected in the processor status sensor value.
The FRB2 failure does not affect the front panel LEDs.
6.6 Sensor Monitoring
The BMC monitors system hardware and reports system health. Some of the sensors includes
those for monitoring.
Component, board, and platform temperatures
Board and platform voltages
System fan presence and tach
Chassis intrusion
Front Panel NMI
Front Panel Power and System Reset Buttons
SMI timeout
Processor errors
The information gathered from physical sensors is translated into IPMI sensors as part of the
“IPMI Sensor Model”. The BMC also reports various system state changes by maintaining
virtual sensors that are not specifically tied to physical hardware.
See Appendix C – Integrated BMC Sensor Tables for additional sensor information.
6.7 Field Replaceable Unit (FRU) Inventory Device
The BMC implements the interface for logical FRU inventory devices as specified in the
Intelligent Platform Management Interface Specification, Version 2.0. This functionality provides
commands used for accessing and managing the FRU inventory information. These commands
can be delivered through all interfaces.
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The BMC provides FRU device command access to its own FRU device and to the FRU
devices throughout the server. The FRU device ID mapping is defined in the Platform Specific
Information. The BMC controls the mapping of the FRU device ID to the physical device
6.8 System Event Log (SEL)
The BMC implements the system event log as specified in the Intelligent Platform Management
Interface Specification, Version 2.0. The SEL is accessible regardless of the system power state
through the BMC's in-band and out-of-band interfaces..
The BMC allocates 65,502 bytes (approximately 64 KB) of non-volatile storage space to store
system events. The SEL timestamps may not be in order. Up to 3,639 SEL records can be
stored at a time. Any command that results in an overflow of the SEL beyond the allocated
space is rejected with an “Out of Space” IPMI completion code (C4h).
Events logged to the SEL can be viewed using Intel’s SELVIEW utility, Embedded Web Server,
and Active System Console.
6.9 System Fan Management
The BMC controls and monitors the system fans. Each fan is associated with a fan speed
sensor that detects fan failure and may also be associated with a fan presence sensor for hotswap support. For redundant fan configurations, the fan failure and presence status determines
the fan redundancy sensor state.
The system fans are divided into fan domains, each of which has a separate fan speed control
signal and a separate configurable fan control policy. A fan domain can have a set of
temperature and fan sensors associated with it. These are used to determine the current fan
domain state.
A fan domain has three states: sleep, nominal, and boost. The sleep and boost states have
fixed (but configurable through OEM SDRs) fan speeds associated with them. The nominal
state has a variable speed determined by the fan domain policy. An OEM SDR record is used to
configure the fan domain policy.
System fan speeds are controlled through pulse width modulation (PWM) signals, which are
driven separately for each domain by integrated PWM hardware. Fan speed is changed by
adjusting the duty cycle, which is the percentage of the time the signal is driven high in each
pulse.
6.9.1 Thermal and Acoustic Management
This feature refers to enhanced fan management to keep the system optimally cooled while
reducing the amount of noise generated by the system fans. Aggressive acoustics standards
might require a trade-off between fan speed and system performance parameters that
contribute to the cooling requirements, primarily memory bandwidth. The BIOS, BMC, and
SDRs work together to provide control over how this trade-off is determined.
This capability requires the BMC to access temperature sensors on the individual memory
DIMMs. Additionally, closed-loop thermal throttling is only supported with buffered DIMMs.
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Type
Profile
Details
OLTT
0
Acoustic, 300M altitude
OLTT
1
Performance, 300M altitude
OLTT
2
Acoustic, 900M altitude
OLTT
3
Performance, 900M altitude
OLTT
4
Acoustic, 1500M altitude
OLTT
5
Performance, 1500M altitude
OLTT
6
Acoustic, 3000M altitude
OLTT
7
Performance, 3000M altitude
CLTT
0
Acoustic, 300M altitude
CLTT
1
Performance, 300M altitude
CLTT
2
Acoustic, 900M altitude
CLTT
3
Performance, 900M altitude
CLTT
4
Acoustic, 1500M altitude
CLTT
5
Performance, 1500M altitude
CLTT
6
Acoustic, 3000M altitude
CLTT
7
Performance, 3000M altitude
6.9.2 Fan Profiles
The server system supports multiple fan control profiles to support acoustic targets and
American Society of Heating, Refrigerating and Air Conditioning Engineers (ASHRAE)
compliance. The BIOS Setup utility can be used to choose between meeting the target acoustic
level or enhanced system performance. This is accomplished through fan profiles.
The BMC supports eight fan profiles, numbered from 0 to 7.
Table 17. Fan Profile Mapping
Each group of profiles allows for varying fan control policies based on the altitude. For a given
altitude, the Tcontrol SDRs associated with an acoustics-optimized profile generates less noise
than the equivalent performance-optimized profile by driving lower fan speeds, and the BIOS
reduces thermal management requirements by configuring more aggressive memory throttling.
The BMC only supports enabling a fan profile through the command if that profile is supported
on all fan domains defined for the given system. It is important to configure platform Sensor
Data Records (SDRs) so that all desired fan profiles are supported on each fan domain. If
no single profile is supported across all domains, the BMC, by default, uses profile 0 and does
not allow it to be changed.
6.9.3 Thermal Sensor Input to Fan Speed Control
The BMC uses various IPMI sensors as input to the fan speed control. Some of the sensors are
IPMI models of actual physical sensors whereas some are “virtual” sensors whose values are
derived from physical sensors using calculations and/or tabular information.
The following IPMI thermal sensors are used as input to the fan speed control:
Front panel temperature sensor
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Baseboard temperature sensors
CPU DTS-Spec margin sensors
DIMM thermal margin sensors
Exit air temperature sensor
Global aggregate thermal margin sensors
SSB (Intel
On-board Ethernet controller temperature sensors (support for this is specific to the
®
C600 Series Chipset) temperature sensor
Ethernet controller being used)
Add-in Intel SAS/IO module temperature sensor(s) (if present)
Power supply thermal sensors (only available on PMBus-compliant power supplies)
The following illustration provides a simple model showing the fan speed control structure that
implements the resulting fan speeds.
Figure 20. High Level Fan Speed Control Structure
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6.9.4 Memory Thermal Throttling
The server board provides support for system thermal management through open loop throttling
(OLTT) and closed loop throttling (CLTT) of system memory. Normal system operation uses
closed-loop thermal throttling (CLTT) and DIMM temperature monitoring as major factors in
overall thermal and acoustics management. In the event that BIOS is unable to configure the
system for CLTT, it defaults to open-loop thermal throttling (OLTT). In the OLTT mode, it is
assumed that the DIMM temperature sensors are not available for fan speed control.
Throttling levels are changed dynamically to cap throttling based on memory and system
thermal conditions as determined by the system and DIMM power and thermal parameters. The
BMC’s fan speed control functionality is linked to the memory throttling mechanism used.
The following terminology is used for the various memory throttling options:
Static Open Loop Thermal Throttling (Static-OLTT): OLTT control registers are
configured by BIOS MRC remain fixed after post. The system does not change any of
the throttling control registers in the embedded memory controller during runtime.
Static Closed Loop Thermal Throttling (Static-CLTT): CLTT control registers are
configured by BIOS MRC during POST. The memory throttling is run as a closed-loop
system with the DIMM temperature sensors as the control input. Otherwise, the system
does not change any of the throttling control registers in the embedded memory
controller during runtime.
Dynamic Open Loop Thermal Throttling (Dynamic-OLTT): OLTT control registers are
configured by BIOS MRC during POST. Adjustments are made to the throttling during
runtime based on changes in system cooling (fan speed).
Dynamic Closed Loop Thermal Throttling (Dynamic-CLTT): CLTT control registers
are configured by BIOS MRC during POST. The memory throttling is run as a closedloop system with the DIMM temperature sensors as the control input. Adjustments are
made to the throttling during runtime based on changes in system cooling (fan speed).
Both Static and Dynamic CLTT modes implement a Hybrid Closed Loop Thermal Throttling
mechanism whereby the Integrated Memory Controller estimates the DRAM temperature in
between actual reads of the memory thermal sensors.
6.10 Messaging Interfaces
The BMC supports the following communications interfaces:
Host SMS interface by means of low pin count (LPC)/keyboard controller style (KCS)
interface
Host SMM interface by means of low pin count (LPC)/keyboard controller style (KCS)
interface
Intelligent Platform Management Bus (IPMB) I2C interface
LAN interface using the IPMI-over-LAN protocols
Every messaging interface is assigned an IPMI channel ID by IPMI 2.0.
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Channel ID
Interface
Support Sessions
0
Primary IPMB
No
1
LAN 1
Yes 2 LAN 2
Yes
3
LAN 31 (Provided by the Intel®
Dedicated Server Management NIC)
Yes
4
Reserved
Yes 5 USB
No
6
Secondary IPMB
No
7
SMM
No
8 -0Dh
Reserved
-
0Eh
Self2
-
0Fh
SMS/Receive Message Queue
No
Table 18. Standard ID Channel Assignments
Notes:
1. Optional hardware supported by the server system.
2. Refers to the actual channel used to send the request.
6.10.1 User Model
The BMC supports the IPMI 2.0 user model. 15 user IDs are supported. These 15 users can be
assigned to any channel. The following restrictions are placed on user-related operations:
1. User names for User IDs 1 and 2 cannot be changed. These are always “” (Null/blank)
and “root” respectively.
2. User 2 (“root”) always has the administrator privilege level.
3. All user passwords (including passwords for 1 and 2) may be modified.
4. User IDs 3-15 may be used freely, with the condition that user names are unique.
Therefore, no other users can be named “” (Null), “root,” or any other existing user
name.
6.10.2 IPMB Communication Interface
The IPMB communication interface used the 100 KB/s version of an I
For more information on I2C specifications, see the I2C Bus and How to Use It. The IPMB
implementation in the BMC is compliant with the IPMB V1.0, REVISION 1.0.
The BMC IPMB slave address is 20h.
The BMC both sends and receives IPMB messages over the IPMB interface. Non-IPMB
messages received by means of the IPMB interface are discarded.
2
C bus as its physical medium.
Messages sent by the BMC can either be originated by the BMC, such as initialization agent
operation, or by another source. One example is KCS-IPMB bridging.
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6.10.3 LAN interface
The BMC implements both the IPMI 1.5 and IPMI 2.0 messaging models. These provide out-ofband local area network (LAN) communication between the BMC and the network.
See the Intelligent Platform Management Interface Specification Second Generation v2.0 for
details about the IPMI-over-LAN protocol.
Run-time determination of LAN channel capabilities can be determined by both standard IPMI
defined mechanisms.
6.10.3.1 RMCP/Alert Standard Forum (ASF Messaging)
The BMC supports RMCP ping discovery in which the BMC responds with a pong message to
an RMCP/ASF ping request. This is implemented per the Intelligent Platform Management
Interface Specification Second Generation v2.0.
6.10.3.2 BMC LAN Channels
The BMC supports three RMII/RGMII ports that can be used for communicating with Ethernet
devices. Two ports are used for communication with the on-board NICs and one is used for
communication with an Ethernet PHY located on an optional RMM4 add-in module.
6.10.3.2.1 Baseboard NICs
The on-board Ethernet controller provides support for a Network Controller Sideband Interface
(NC-SI) manageability interface. This provides a sideband high-speed connection for
manageability traffic to the BMC while still allowing for a simultaneous host access to the OS is
desired.
The NC-SI is a DMTF industry standard protocol for the side band management LAN interface.
This protocol provides a fast multi-drop interface for management traffic.
The baseboard NIC(s) are connected to a single BMC RMII/RGMII port that is configured for
RMII operation. The NC-SI protocol is used for this connection and provides a 100 Mb/s fullduplex multi-drop interface which allows multiple NICs to be connected to the BMC. The
physical layer is based upon RMII, however RMII is a point-to-point bus whereas NC-SI allows 1
master and up to 4 slaves. The logical layer (configuration commands) is incompatible with RMII.
The server board will provide support for a dedicated management channel that can be
configured to be hidden from the host and only used by the BMC. This mode of operations is
configured from a BIOS setup option.
6.10.3.2.2 Dedicated Management Channel
An additional LAN channel dedicated to BMC usage and not available to host SW is supported
by an optional RMM4 add-in card. There is only a PHY device present on the RMM4 add-in card.
The BMC has a built-in MAC module that uses the RGMII interface to link with the card’s PHY.
Therefore, for this dedicated management interface, the PHY and MAC are located in different
devices.
The PHY on the RMM4 connects to the BMC’s other RMII/RGMII interface (i.e. the one that is
not connected to the baseboard NICs). This BMC port is configured for RGMII usage.
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In addition to the use of an RMM4 add-in card for a dedicated management channel, on system
that support multiple Ethernet ports on the baseboard, the system BIOS provides a setup option
to allow one of these baseboard ports to be dedicated to the BMC for manageability purpose.
When this is enabled, that port is hidden from the OS.
6.10.3.2.3 Concurrent Server Management Use of Multiple Ethernet Controllers
The BMC FW supports concurrent OOB LAN management sessions for the following
combination:
Two on-board NIC ports
One on-board NIC ports and the optional dedicated RMM4 add-in management NIC
Two on-board NIC ports and the optional dedicated RMM4 add-in management NIC
All NIC ports must be on different subnets for the above concurrent usage models.
MAC addresses are assigned for management NICs from a pool of up to 3 MAC addresses
allocated specifically for manageability.
The server board has seven MAC addresses programmed at the factory. MAC addresses are
assigned as follows:
NIC 1 MAC address (for OS usage)
NIC 2 MAC address = NIC 1 MAC address + 1 (for OS usage)
NIC 3 MAC address = NIC 1 MAC address + 2 (for OS usage)
NIC 4 MAC address = NIC 1 MAC address + 3 (for OS usage)
BMC LAN channel 1 MAC address = NIC1 MAC address + 4
BMC LAN channel 2 MAC address = NIC1 MAC address + 5
BMC LAN channel 3 (RMM) MAC address = NIC1 MAC address + 6
The printed MAC address on the server board and/or server system is assigned to NIC1 on the
server board.
For security reasons, embedded LAN channels have the following default setting:
IP Address: Static
All users disabled
IPMI-enabled network interfaces may not be placed on the same subnet. This includes the
Intel® Dedicated Server Management NIC and either of the BMC’s embedded network
interfaces.
Host-BMC communication over the same physical LAN connection =also known as “loopback” –
is not supported. This includes “ping” operations.
On server boards with more than two onboard NIC ports, only the first two ports can be used as
BMC LAN channels. The remaining ports have no BMC connectivity.
Maximum bandwidth supported by BMC LAN channels are as follows:
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BMC LAN1 (Baseboard NIC port) ----- 100Mb (10Mb in DC off state)
BMC LAN2 (Baseboard NIC port) ----- 100Mb (10Mb in DC off state)
BMC LAN3 (Dedicated NIC) ----- 1000Mb (10Mb in DC off state)
6.10.3.3 IPV6 Support
In addition to IPv4, the server board has support for IPV6 for manageability channels.
Configuration of IPv6 is provided by extensions to the IPMI Set and Get LAN Configuration
Parameters commands as well as through a Web Console IPv6 configuration web page.
The BMC supports IPv4 and IPv6 simultaneously so they are both configured separately and
completely independently. For example, IPv4 can be DHCP configured while IPv6 is statically
configured or vice versa.
The parameters for IPv6 are similar to the parameters for IPv4 with the following differences:
An IPv6 address is 16 bytes vs. 4 bytes for IPv4.
An IPv6 prefix is 0 to 128 bits whereas IPv4 has a 4 byte subnet mask.
There are two variants of automatic IP Address Source configuration vs. just DHCP for IPv4.
The three possible IPv6 IP Address Sources for configuring the BMC are:
Static (Manual): The IP, Prefix, and Gateway parameters are manually configured by the user.
The BMC ignores any Router Advertisement messages received over the network.
DHCPv6: The IP comes from running a DHCPv6 client on the BMC and receiving the IP from a
DHCPv6 server somewhere on the network. The Prefix and Gateway are configured by Router
Advertisements from the local router. The IP, Prefix, and Gateway are read-only parameters to
the BMC user in this mode.
Static (Manual): The IP, Prefix, and Gateway parameters are manually configured by the user.
The BMC ignores any Router Advertisement messages received over the network.
DHCPv6: The IP comes from running a DHCPv6 client on the BMC and receiving the IP from a
DHCPv6 server somewhere on the network. The Prefix and Gateway are configured by Router
Advertisements from the local router. The IP, Prefix, and Gateway are read-only parameters to
the BMC user in this mode.
Stateless auto-config: The Prefix and Gateway are configured by the router through Router
Advertisements. The BMC derives its IP in two parts: the upper network portion comes from the
router and the lower unique portion comes from the BMC’s channel MAC address. The 6-byte
MAC address is converted into a 8-byte value per the EUI-64* standard. For example, a MAC
value of 00:15:17:fe:2f:62 converts into a EUI-64 value of 215:17ff:fefe:2f62. If the BMC
receives a Router Advertisement from a router at IP 1:2:3:4::1 with a prefix of 64, it would then
generate for itself an IP of 1:2:3:4:215:17ff:fefe:2f62. The IP, Prefix, and Gateway are read-only
parameters to the BMC user in this mode.
IPv6 can be used with the BMC’s Web Console, JViewer (remote KVM and Media), and
Systems Management Architecture for Server Hardware –Command Line Protocol (SMASH-
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CLP) interface (ssh). There is no standard yet on how IPMI RMCP or RMCP + should operate
over IPv6 so that is not currently supported.
6.10.3.4 LAN Failover
The BMC FW provides a LAN failover capability such that the failure of the system HW
associated with one LAN link will result in traffic being rerouted to an alternate link. This
functionality is configurable by IPMI methods as well as by the BMC’s Embedded UI, allowing
for user to specify the physical LAN links constitute the redundant network paths or physical
LAN links constitute different network paths. BMC will support only a all or nothing approach –
that is, all interfaces bonded together, or none are bonded together.
The LAN Failover feature applies only to BMC LAN traffic. It bonds all available Ethernet
devices but only one is active at a time. When enabled, if the active connection’s leash is lost,
one of the secondary connections is automatically configured so that it has the same IP address.
Traffic immediately resumes on the new active connection.
The LAN Failover enable/disable command may be sent at any time. After it has been enabled,
standard IPMI commands for setting channel configuration that specify a LAN channel other
than the first will return an error code.
6.10.3.5 BMC IP Address Configuration
Enabling the BMC’s network interfaces requires using the Set LAN Configuration Parameter
command to configure LAN configuration parameter 4, IP Address Source. The BMC supports
this parameter as follows:
1h, static address (manually configured): Supported on all management NICs. This is
the BMC’s default value.
2h, address obtained by BMC running DHCP: Supported only on embedded
management NICs.
IP Address Source value 4h, address obtained by BMC running other address assignment
protocol, is not supported on any management NIC.
Attempting to set an unsupported IP address source value has no effect, and the BMC returns
error code 0xCC, Invalid data field-in request. Note that values 0h and 3h are no longer
supported, and will return a 0Xcc error completion code.
6.10.3.5.1 Static IP Address (IP Address Source Values 0h, 1h, and 3h)
The BMC supports static IP address assignment on all of its management NICs. The IP address
source parameter must be set to “static” before the IP address; the subnet mask or gateway
address can be manually set.
The BMC takes no special action when the following IP address source is specified as the IP
address source for any management NIC:
1h – Static address (manually configured)
The Set LAN Configuration Parameter command must be used to configure LAN configuration
parameter 3, IP Address, with an appropriate value.
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The BIOS does not monitor the value of this parameter, and it does not execute DHCP for the
BMC under any circumstances, regardless of the BMC configuration.
6.10.3.5.2 Static LAN Configuration Parameters
When the IP Address Configuration parameter is set to 01h (static), the following parameters
may be changed by the user:
LAN configuration parameter 3 (IP Address)
LAN configuration parameter 6 (Subnet Mask)
LAN configuration parameter 12 (Default Gateway Address)
When changing from DHCP to Static configuration, the initial values of these three parameters
will be equivalent to the existing DHCP –set parameters. Additionally, the BMC observes the
following network safety precautions:
1. The user may only set a subnet mask that is valid, per IPv4 and RFC 950 (Internet Standard
Subnetting Procedure). Invalid subnet values return a 0Xcc (Invalid Data Field in Request)
completion code, and the subnet mask is not set. If no valid mask has been previously set,
default subnet mask is 0.0.0.0.
2. The user may only set a default gateway address that can potentially exist within the subnet
specified above. Default gateway addresses outside the BMC’s subnet are technically
unreachable and the BMC will not set the default gateway address to an unreachable value.
The BMC returns a 0Xcc (Invalid Data Field in Request) completion code for default
gateway addresses outside its subnet.
3. If a command is issued to set the default gateway IP address before the BMC’s IP address
and subnet mask are set, the default gateway IP address is not updated and the BMC
returns 0Xcc.
If the BMC’s IP address on a LAN channel changes while a LAN session is in progress over that
channel, the BMC does not take action to close the session except through a normal session
timeout. The remote client must re-sync with the new IP address. The BMC’s new IP address is
only available in-band through the “Get LAN Configuration Parameters” command.
6.10.3.5.3 Enabling/Disabling Dynamic Host Configuration (DHCP) Protocol
The BMC DHCP feature is activated by using the Set LAN Configuration Parameter command
to set LAN configuration parameter 4, IP Address Source, to 2h:”address obtained by BMC
running DHCP”. Once this parameter is set, the BMC initiates the DHCP process within
approximately 100ms.
If the BMC has previously been assigned an IP address through DHCP or the Set LAN
Configuration Parameter command, it requests that same IP address to be reassigned. If the
BMC does not receive the same IP address, system management software must be
reconfigured to use the new IP address. The new address is only available in-band, through the
IPMI Get LAN Configuration Parameters command.
Changing the IP Address Source parameter from 2h to any other supported value will cause the
BMC to stop the DHCP process. The BMC uses the most recently obtained IP address until it is
reconfigured.
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If the physical LAN connection is lost (that is, the cable is unplugged), the BMC will not reinitiate the DHCP process when the connection is re-established.
6.10.3.5.4 DHCP-related LAN Configuration Parameters
Users may not change the following LAN parameters while the DHCP is enabled:
LAN configuration parameter 3 (IP Address)
LAN configuration parameter 6 (Subnet Mask)
LAN configuration parameter 12 (Default Gateway Address)
To prevent users from disrupting the BMC’s LAN configuration, the BMC treats these
parameters as read-only while DHCP is enabled for the associated LAN channel. Using the Set
LAN Configuration Parameter command to attempt to change one of these parameters under
such circumstances has no effect, and the BMC returns error code 0Xd5, “Cannot Execute
Command. Command, or request parameter(s) are not supported in present state.”
6.10.3.6 DHCP BMC Hostname
The BMC allows setting a DHCP Hostname using the Set/Get LAN Configuration Parameter
command.
DHCP Hostname can be set regardless of the IP Address source configured on the BMC.
But this parameter is only used if the IP Address source is set to DHCP.
When Byte 2 is set to “Update in progress”, all the 16 Block Data Bytes (Bytes 3 – 18)
must be present in the request.
When Block Size <16, it must be the last Block request in this series. In other words Byte
2 is equal to “Update is complete” on that request.
Whenever Block Size < 16, the Block data bytes must end with a NULL Character or
Byte (=0).
All Block write requests are updated into a local Memory byte array. When Byte 2 is set
to “Upgrade is Complete”, the Local Memory is committed to the NV Storage. Local
Memory is reset to NULL after changes are committed.
When Byte 1 (Block Selector = 1), firmware resets all the 64 bytes local memory. This
can be used to undo any changes after the last “Update in Progress”.
User should always set the hostname starting from block selector 1 after the last
“Update is complete”. If the user skips block selector 1 while setting the hostname, the
BMC will record the hostname as “NULL”, because the first block contains NULL data.
This scheme effectively does not allow a user to make a partial Hostname change. Any
Hostname change needs to start from Block 1.
Byte 64 (Block Selector 04h byte 16) is always ignored and set to NULL by BMC which
effectively means we can set only 63 bytes.
User is responsible for keeping track of the Set series of commands and Local Memory
contents.
While BMC firmware is in “Set Hostname in Progress” (Update not complete), the firmware
continues using the Previous Hostname for DHCP purpose.
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6.10.4 Address Resoluton Protocol (ARP)
The BMC can receive and respond to ARP requests on BMC NICs. Gratuitous ARPs supported,
and disabled by default.
6.10.5 Internet Control Message Protocol (ICMP)
The BMC supports the following ICMP message types targeting the BMC over integrated NICs:
Echo request (ping): The BMC sends an Echo Reply.
Destination unreachable: If message is associated with an active socket connection
within the BMC, the BMC closes the socket.
6.10.6 Virtual Local Area Network (VLAN)
The BMC supports VLAN as defined by IPMI 2.0 specifications. VLAN is supported internally by
the BMC, not through switches. VLAN provides a way of grouping a set of systems together so
that they form a logical network. This feature can be used to set up a management VLAN where
only devices which are members of the VLAN will receive packets related to management and
members of the VLAN will be isolated from any other network traffic. Please note that VLAN
does not change the behavior of the host network setting, it only affects the BMC LAN
communication.
LAN configuration options are now supported (by means of the Set LAN Config Parameters
command, parameters 20 and 21) that allow support for 802.1Q VLAN (Layer 2). This allows
VLAN headers/packets to be used for IPMI LAN sessions. VLAN ID’s are entered and enabled
by means of parameter 20 of the Set LAN Config Parameters IPMI command. When a VLAN ID
is configured and enabled, the BMC only accepts packets with that VLAN tag/ID. Conversely, all
BMC generated LAN packets on the channel include the given VLAN tag/ID. Valid VLAN ID’s
are 1 through 4094, VLAN ID’s of 0 and 4095 are reserved, per the 802.1Q VLAN specification.
Only one VLAN can be enabled at any point in time on a LAN channel. If an existing VLAN is
enabled, it must first be disabled prior to configuring a new VLAN on the same LAN channel.
Parameter 12(VLAN Priority) of the Set LAN Config Parameters IPMI command is now
implemented and a range from 0-7 will be allowed for VLAN Priorities. Please note that bit 3 and
4 of parameter 21 are considered reserved bits.
Parameter 25 (VLAN Destination Address) of the Set LAN Config Parameters IPMI command is
not supported and returns a completion cod of 0x80 (parameter not supported) for any
read/write of parameter 25.
If the BMC IP address source is DHCP, then the following behavior is seen:
If the BMC is first configured for DHCP (prior to enabling VLAN), when VLAN is enabled,
the BMC performs a discovery on the new VLAN in order to obtain a new BMC IP
address.
If the BMC is configured for DHCP (prior to disabling VLAN), when VLAN is disabled, the
BMC performs a discovery on the LAN in order to obtain a new BMC IP address.
If the BMC IP address source is Static, then the following behavior is seen:
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Event Filter Number
Offset Mask
Events
1
Non-critical, critical and non-recoverable
Temperature sensor out of range
2
Non-critical, critical and non-recoverable
Voltage sensor out of range
3
Non-critical, critical and non-recoverable
Fan failure
4
General chassis intrusion
Chassis intrusion (security violation)
5
Failure and predictive failure
Power supply failure
If the BMC is first configured for static (prior to enabling VLAN), when VLAN is enabled,
the BMC has the same IP address that was configured before. It is left to management
application to configure a different IP address if that is not suitable for VLAN.
If the BMC is configured for static (prior to disabling VLAN), when VLAN is disabled, the
BMC has the same IP address that was configured before. It is left to management
application to configure a different IP address if that is not suitable for VLAN.
6.10.7 Secure Shell (SSH)
Secure Shell (SSH) connections are supported for SMASH-CLP sessions to the BMC.
6.10.8 Serial-over-LAN (SOL 2.0)
The BMC supports IPMI 2.0 SOL.
IPMI 2.0 introduced a standard serial-over-LAN feature. This is implemented as a standard
payload type (01h) over RMCP+.
Three commands are implemented for SOL 2.0 configuration.
“Get SOL 2.0 Configuration Parameters” and “Set SOL 2.0 Configuration Parameters”:
these commands are used to get and set the values of the SOL configuration
parameters. The parameters are implemented on a pre-channel basis. “Activating SOL”:
This command is not accepted by the BMC. It is sent by the BMC when SOL is activated
to notify a remote client of the switch to SOL.
Activating a SOL session requires an existing IPMI-over-LAN session. If encryption is
used, it should be negotiated when the IPMI-over-LAN session is established.
6.10.9 Platform Event Filter
The BMC includes the ability to generate a selectable action, such as a system power-off or
reset, when a match occurs to one of a configurable set of events. This capability is called
Platform Event Filtering, or PEF. One of the available PEF actions is to trigger the BMC to send
a LAN alert to one or more destinations.
The BMC supports 20 PEF filters. The first twelve entries in the PEF filter table are preconfigured (but may be changed by the user). The remaining entries are left blank, and may be
configured by the user.
Table 19. Factory Configured PEF Table Entries
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Event Filter Number
Offset Mask
Events
6
Uncorrectable ECC
BIOS
7
POST error
BIOS: POST code error
8
FRB2
Watchdog Timer expiration for FRB2
9
Policy Correction Time
Node Manager
10
Power down, power cycle, and reset
Watchdog timer
11
OEM system boot event
System restart (reboot)
12
Drive Failure, Predicated Failure
Hot Swap Controller
Additionally, the BMC supports the following PEF actions:
Power off
Power cycle
Reset
OEM action
Alerts
The “Diagnostic interrupt” action is not supported.
6.10.10 LAN Alterting
The BMC supports sending embedded LAN alerts, called SNMP PET (Platform Event traps),
and SMTP email alerts.
The BMC supports a minimum of four LAN alert destinations.
6.10.10.1 SNMP Platform Event Traps (PETs)
This feature enables a target system to send SNMP traps to a designated IP address by means
of LAN. These alerts are formatted per the Intelligent Platform Management Interface
Specification Second Generation v2.0. A Module Information Block (MIB) file associated with
the traps is provided with the BMC firmware to facilitate interpretation of the traps by external
software. The format of the MIB file is covered under RFC 2578.
6.10.11 Altert Policy Table
Associated with each PEF entry is an alert policy that determines which IPMI channel the alert
is to be sent. There is a maximum of 20 alert policy entries. There are no pre-configured entries
in the alert policy table because the destination types and alerts may vary by user. Each entry in
the alert policy table contains four bytes for a maximum table size of 80 bytes.
6.10.11.1 E-mail Alerting
The Embedded Email Alerting feature allows the user to receive e-mails alerts indicating issues
with the server. This allows e-mail alerting in an OS-absent (for example, Pre-OS and OS-Hung)
situation. This feature provides support for sending e-mail by means of SMTP
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6.10.12 SM-CLP (SM-CLP Lite)
SMASH refers to Systems Management Architecture for Server Hardware. SMASH is defined
by a suite of specifications, managed by the DMTF, that standardize the manageability
interfaces for server hardware. CLP refers to Command Line Protocol. SM-CLP is defined by
the Server Management Command Line Protocol Specification (SM-CLP) ver1.0, which is part
of the SMASH suite of specifications. The specifications and further information on SMASH can
be found at the DMTF website (http://www.dmtf.org/).
The BMC provides an embedded “lite” version of SM-CLP that is syntax-compatible but not
considered fully compliant with the DMTF standards.
The SM-CLP utilized by a remote user by connecting a remote system from one of the system
NICs. It is possible for third party management applications to create scripts using this CLP and
execute them on server to retrieve information or perform management tasks such as reboot the
server, configure events, and so on.
The BMC embedded SM-CLP feature includes the following capabilities:
Power on/off/reset the server.
Get the system power state.
Clear the System Event Log (SEL).
Get the interpreted SEL in a readable format.
Initiate/terminate a Serial Over LAN session.
Support “help” to provide helpful information
Get/set the system ID LED.
Get the system GUID
Get/set configuration of user accounts.
Get/set configuration of LAN parameters.
Embedded CLP communication should support SSH connection.
Provide current status of platform sensors including current values. Sensors include
voltage, temperature, fans, power supplies, and redundancy (power unit and fan
redundancy).
The embedded web server is supported over any system NIC port that is enabled for server
management capabilities.
6.10.13 Embeded Web Server
IBMC Base manageability provides an embedded web server and an OEM-customizable web
GUI which exposes the manageability features of the IBMC base feature set. It is supported
over all on-board NICs that have management connectivity to the IBMC as well as an optional
dedicated add-in management NIC. At least two concurrent web sessions from up to two
different users is supported.
The embedded web user interface supports strong security (authentication, encryption, and
firewall support) since it enables remote server configuration and control. The user interface
presented by the embedded web user interface shall authenticate the user before allowing a
web session to be initiated. Encryption using 128-bit SSL is supported. User authentication is
based on user id and password.
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The GUI presented by the embedded web server authenticates the user before allowing a web
session to be initiated. It presents all functions to all users but grays-out those functions that the
user does not have privilege to execute (for example, if a user does not have privilege to power
control, then the item shall be displayed in grey-out font in that user’s UI display). The web GUI
also provides a launch point for some of the advanced features, such as KVM and media
redirection. These features are grayed out in the GUI unless the system has been updated to
support these advanced features.
A partial list of additional features supported by the web GUI includes:
Presents all the Basic features to the users.
Power on/off/reset the server and view current power state.
Displays BIOS, BMC, ME and SDR version information.
Display overall system health.
Configuration of various IPMI over LAN parameters for both IPV4 and IPV6
Display system asset information for the product, board, and chassis.
Display of BMC-owned sensors (name, status, current reading, enabled thresholds),
including color-code status of sensors.
Provides ability to filter sensors based on sensor type (Voltage, Temperature, Fan and
Power supply related)
Automatic refresh of sensor data with a configurable refresh rate.
On-line help.
Display/clear SEL (display is in easily understandable human readable format).
Supports major industry-standard browsers (Microsoft Windows Internet Explorer* and
Mozilla Firefox*).
Automatically logs out after user-configurable inactivity period.
The GUI session automatically times-out after a user-configurable inactivity period. By
default, this inactivity period is 30 minutes.
Embedded Platform Debug feature - Allow the user to initiate a “diagnostic dump” to a
file that can be sent to Intel for debug purposes.
Virtual Front Panel. The Virtual Front Panel provides the same functionality as the local
front panel. The displayed LEDs match the current state of the local panel LEDs. The
displayed buttons (for example, power button) can be used in the same manner as the
local buttons.
Display of ME sensor data. Only sensors that have associated SDRs loaded will be
displayed.
Ability to save the SEL to a file.
Ability to force HTTPS connectivity for greater security. This is provided through a
configuration option in the UI.
Display of processor and memory information as is available over IPMI over LAN.
Ability to get and set Node Manager (NM) power policies.
Display of power consumed by the server.
Ability to view and configure VLAN settings.
Warn user the reconfiguration of IP address will cause disconnect.
Capability to block logins for a period of time after several consecutive failed login
attempts. The lock-out period and the number of failed logins that initiates the lock-out
period are configurable by the user.
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Server Power Control - Ability to force into Setup on a reset.
6.10.14 Virtual Front Panel
Virtual Front Panel is the module present as “Virtual Front Panel” on the left side in the
embedded web server when "remote Control" tab is clicked.
Main Purpose of the Virtual Front Panel is to provide the front panel functionality virtually.
Virtual Front Panel (VFP) will mimic the status LED and Power LED status and Chassis
ID alone. It is automatically in sync with BMC every 40 seconds.
For any abnormal status LED state, Virtual Front Panel will get the reason behind the
abnormal or status LED changes and displayed in VFP side.
As Virtual Front Panel uses the chassis control command for power actions. It won’t log
the Front button press event since Logging the front panel press event for Virtual Front
Panel press will mislead the administrator.
For Reset through Virtual Front Panel, the reset will be done by a “Chassis control”
command.
For Reset through Virtual Front Panel, the restart cause will be because of “Chassis
control” command.
During Power action, Power button/Reset button should not accept the next action until
current Power action is complete and the acknowledgment from BMC is received.
EWS will provide a valid message during Power action until it completes the current
Power action.
The VFP does not have any effect on whether the front panel is locked by “Set Front
Panel Enables” command.
The chassis ID LED provides a visual indication of a system being serviced. The state of
the chassis ID LED is affected by the following actions:
Toggled by turning the chassis ID button on or off.
There is no precedence or lock-out mechanism for the control sources. When a new
request arrives, previous requests are terminated. For example, if the chassis ID button
is pressed, then the chassis ID LED changes to solid on. If the button is pressed again,
then the chassis ID LED turns off.
Note that the chassis ID will turn on because of the original chassis ID button press and
will reflect in the Virtual Front Panel after VFP sync with BMC. Virtual Front Panel won’t
reflect the chassis LED software blinking by the software command as there is no
mechanism to get the chassis ID Led status.
Only Infinite chassis ID ON/OFF by the software command will reflect in EWS during
automatic /manual EWS sync up with BMC.
Virtual Front Panel help should available for virtual panel module.
At present, NMI button in VFP is disabled in Intel® S1400/S1600/S2400/S2600 Server
Platforms. It can be used in future.
6.10.15 Embedded Platform Debug
The Embedded Platform Debug feature supports capturing low-level diagnostic data (applicable
MSRs, PCI config-space registers, and so on). This feature allows a user to export this data into
a file that is retrievable from the embedded web GUI, as well as through host and remote IPMI
methods, for the purpose of sending to an Intel engineer for an enhanced debugging capability.
The files are compressed, encrypted, and password protected. The file is not meant to be
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viewable by the end user but rather to provide additional debugging capability to an Intel support
engineer.
A list of data that may be captured using this feature includes but is not limited to:
Platform sensor readings – This includes all “readable” sensors that can be accessed by
the BMC FW and have associated SDRs populated in the SDR repository. This does not
include any “event-only” sensors. (All BIOS sensors and some BMC and ME sensors are
“event-only”; meaning that they are not readable using an IPMI Get Sensor Reading
command but rather are used just for event logging purposes).
SEL – The current SEL contents are saved in both hexadecimal and text format.
CPU/memory register data useful for diagnosing the cause of the following system errors:
CATERR, ERR[2], SMI timeout, PERR, and SERR. The debug data is saved and
timestamped for the last 3 occurrences of the error conditions.
o PCI error registers
o MSR registers
o Integrated Memory Controller(Imc) and Integrated I/O (IIO) modules registers
BMC configuration data
BMC FW debug log (that is, SysLog) – Captures FW debug messages.
Non-volatile storage of captured data. Some of the captured data will be stored
persistently in the BMC’s non-volatile flash memory and preserved across AC power
cycles. Due to size limitations of the BMC’s flash memory, it is not feasible to store all of
the data persistently.
SMBIOS table data. The entire SMBIOS table is captured from the last boot.
PCI configuration data for on-board devices and add-in cards. The first 256 bytes of PCI
configuration data is captured for each device for each boot.
System memory map. The system memory map is provided by BIOS on the current boot.
This includes the EFI memory map and the Legacy (E820) memory map depending on
the current boot.
Power supplies debug capability.
o Capture of power supply “black box” data and power supply asset information.
Power supply vendors are adding the capability to store debug data within the
power supply itself. The platform debug feature provides a means to capture this
data for each installed power supply. The data can be analyzed by Intel for failure
analysis and possibly provided to the power supply vendor as well. The BMC
gets this data from the power supplies from the PMBus manufacturer-specific
commands.
o Storage of system identification in power supply. The BMC copies board and
system serial numbers and part numbers into the power supply whenever a new
power supply is installed in the system or when the system is first powered on.
This information is included as part of the power supply black box data for each
installed power supply.
Accessibility from IPMI interfaces. The platform debug file can be accessed by an
external IPMI interface (KCS or LAN).
POST code sequence for the two most recent boots. This is a best-effort data collection
by the BMC as the BMC real-time response cannot guarantee that all POST codes are
captured.
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Category
Data
Internal BMC Data
BMC uptime/load
Process list
Free Memory
Detailed Memory List
Filesystem List/Info
BMC Network Info
BMC Syslog
BMC Configuration Data
External BMC Data
Hex SEL listing
Human-readable SEL listing
Human-readable sensor listing
External BIOS Data
POST codes for the two most recent boots
System Data
SMBIOS table for the current boot
256 bytes of PCI config data for each PCI device
Category
Data
System Data
First 256 bytes of PCI config data for each PCI
device
PCI error registers
MSR registers
Support for multiple debug files. The platform debug feature provides the ability to save
data to 2 separate files that are encrypted with different passwords.
o File #1 is strictly for viewing by Intel engineering and may contain BMC log
messages (a.k.a. syslog) and other debug data that Intel FW developers deem
useful in addition to the data specified in this document.
o File #2 can be viewed by Intel partners who have signed an NDA with Intel and
its contents are restricted to specific data items specified in this with the
exception of the BMC syslog messages and power supply “black box” data.
6.10.15.1 Output Data Format
The diagnostic feature shall output a password-protected compressed HTML file containing
specific BMC and system information. This file is not intended for end-customer usage, this file
is for customer support and engineering only.
6.10.15.2 Output Data Availability
The diagnostic data shall be available on-demand from the embedded web server, KCS, or IPMI
over LAN commands.
6.10.15.3 Output Data Categories
The following tables list the data to be provided in the diagnostic output. For items in Table 20,
this data is collected on detection of CATERR, ERR2, PERR, SERR, and SMI timeout. The data
in Table 21 is accumulated for the three most recent overall errors.
Table 20. Diagnostic Data.
Table 21. Additional Diagnostics on Error.
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6.10.16 Data Center Management Interface (DCMI)
The DCMI Specification is an emerging standard that is targeted to provide a simplified
management interface for Internet Portal Data Center (IPDC) customers. It is expected to
become a requirement for server platforms which are targeted for IPDCs. DCMI is an IPMIbased standard that builds upon a set of required IPMI standard commands by adding a set of
DCMI-specific IPMI OEM commands. Intel® S1400/S1600/S2400/S2600 Server Platforms will
be implementing the mandatory DCMI features in the BMC firmware (DCMI 1.1 Errata 1
compliance). Please refer to DCMI 1.1 errata 1 spec for details. Only mandatory commands will
be supported. No support for optional DCMI commands. Optional power management and SEL
roll over feature is not supported. DCMI Asset tag will be independent of baseboard FRU asset
Tag. Please refer table DCMI Group Extension Commands for more details on DCMI
commands.
6.10.17 Lightweight Directory Authentication Protocol (LDAP)
The Lightweight Directory Access Protocol (LDAP) is an application protocol supported by the
BMC for the purpose of authentication and authorization. The BMC user connects with an LDAP
server for login authentication. This is only supported for non-IPMI logins including the
embedded web UI and SM-CLP. IPMI users/passwords and sessions are not supported over
LDAP.
LDAP can be configured (IP address of LDAP server, port, and do on) from the BMC’s
Embedded Web UI. LDAP authentication and authorization is supported over the any NIC
configured for system management. The BMC uses a standard Open LDAP implementation for
Linux.
Only open LDAP is supported by BMC. Windows and Novel LDAP are not supported.
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Intel Product Code
Description
Kit Contents
Benefits
AXXRMM4LITE
Intel® Remote
Management Module 4
Lite
RMM4 Lite Activation Key
Enable KVM and Media
redirection from onboard
NIC
AXXRMM4
Intel® Remote
Management Module 4
RMM4 Lite Activation Key
Dedicated NIC Port
Module
Dedicated NIC for
management traffic. Higher
bandwidth connectivity for
KVM and media
Redirection.
Manageability Hardware
Benefits
Intel® Integrated BMC
Comprehensive IPMI based base manageability features
Intel® Remote Management Module 4 – Lite
Package contains one module –
1- Key for advance Manageability features.
No dedicated NIC for management
Enables KVM and media redirection from onboard NIC
Intel® Remote Management Module 4
Package includes 2 modules –
1 - key for advance features
2 - Dedicated NIC for management
Dedicated NIC for management traffic. Higher bandwidth
connectivity for KVM and media Redirection.
7. Advanced Management Features Support (RMM4)
The integrated baseboard management controller has support for advanced management
features which are enabled when an optional Intel® Remote Management Module 4 (RMM4) is
installed. The Intel® RMM4 is available as two option kits:
Table 22. Intel® RMM4 options kits
Table 23. Enabling Advanced Management Features
If the optional Dedicated Server Management NIC is not used then the traffic can only go
through the onboard Integrated BMC-shared NIC and will share network bandwidth with the
host system. Advanced manageability features are supported over all NIC ports enabled for
server manageability.
7.1 Keyboard, Video, and Mouse (KVM) Redirection
The BMC firmware supports keyboard, video, and mouse redirection (KVM) over LAN. This
feature is available remotely from the embedded web server as a Java applet. This feature is
only enabled when the Intel® RMM4-lite is present. The client system must have a Java Runtime
Environment (JRE) version 6.0 or later to run the KVM or media redirection applets.
The Integrated BMC supports an embedded KVM application (Remote Console) that can be
launched from the embedded web server from a remote console. USB1.1 or USB 2.0 based
mouse and keyboard redirection are supported. It is also possible to use the KVM-redirection
(KVM-r) session concurrently with media-redirection (media-r). This feature allows a user to
interactively use the keyboard, video, and mouse (KVM) functions of the remote server as if the
user were physically at the managed server.
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KVM redirection includes a “soft keyboard” function. The “soft keyboard” is used to simulate an
entire keyboard that is connected to remote system. The “soft keyboard” functionality supports
the following layouts: English, Dutch, French, German, Italian, Russian, and Spanish.
KVM-redirection feature automatically senses video resolution for best possible screen capture
and provides high-performance mouse tracking and synchronization. It allows remote viewing
and configuration in pre-boot POST and BIOS setup, once BIOS has initialized video.
Other attributes of this feature include:
Encryption of the redirected screen, keyboard, and mouse
Compression of the redirected screen
An option to select a mouse configuration based on the OS type.
Supports user definable keyboard macros.
KVM redirection feature supports the following resolution and refresh rates:
640x480 at 60Hz, 72Hz, 85Hz, 100Hz
800x600 at 60Hz, 72Hz, 75Hz, 85Hz
1024x768 at 60Hz, 72Hz, 75Hz, 85Hz
1280X960 at 60Hz
1280x1024 at 60Hz
1600x1200 at 60Hz
1920x1080 at 60Hz
1920x1200 at 60Hz
1920x1080 (1080p)
1920x1200 (WUXGA)
1650X1080 (WSXGA+)
7.1.1 Remote Console
The Remote Console is the redirected screen, keyboard and mouse of the remote host system.
To use the Remote Console window of your managed host system, the browser must include a
Java* Runtime Environment plug-in. If the browser has no Java support, such as with a small
handheld device, the user can maintain the remote host system using the administration forms
displayed by the browser.
The Remote Console window is a Java Applet that establishes TCP connections to the BMC.
The protocol that is run over these connections is a unique KVM protocol and not HTTP or
HTTPS. This protocol uses ports #7578 for KVM, #5120 for CDROM media redirection, and
#5123 for Floppy/USB media redirection. When encryption is enabled, the protocol uses ports
#7582 for KVM, #5124 for CDROM media redirection, and #5127 for Floppy/USB media
redirection. The local network environment must permit these connections to be made, i.e. the
firewall and, in case of a private internal network, the NAT (Network Address Translation)
settings have to be configured accordingly.
7.1.2 Performance
The remote display accurately represents the local display. The feature adapts to changes to
the video resolution of the local display and continues to work smoothly when the system
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transitions from graphics to text or vice-versa. The responsiveness may be slightly delayed
depending on the bandwidth and latency of the network.
Enabling KVM and/or media encryption will degrade performance. Enabling video compression
provides the fastest response while disabling compression provides better video quality.
For the best possible KVM performance, a 2Mb/sec link or higher is recommended.
The redirection of KVM over IP is performed in parallel with the local KVM without affecting the
local KVM operation.
7.1.3 Security
The KVM redirection feature supports multiple encryption algorithms, including RC4 and AES.
The actual algorithm that is used is negotiated with the client based on the client’s capabilities.
7.1.4 Availability
The remote KVM session is available even when the server is powered-off (in stand-by mode).
No re-start of the remote KVM session shall be required during a server reset or power on/off.
An BMC reset (for example, due to an BMC Watchdog initiated reset or BMC reset after BMC
FW update) will require the session to be re-established.
KVM sessions persist across system reset, but not across an AC power loss.
7.1.5 Usage
As the server is powered up, the remote KVM session displays the complete BIOS boot
process. The user is able interact with BIOS setup, change and save settings as well as enter
and interact with option ROM configuration screens.
At least two concurrent remote KVM sessions are supported. It is possible for at least two
different users to connect to same server and start remote KVM sessions
7.1.6 Force-enter BIOS Setup
KVM redirection can present an option to force-enter BIOS Setup. This enables the system to
enter F2 setup while booting which is often missed by the time the remote console redirects the
video.
7.2 Media Redirection
The embedded web server provides a Java applet to enable remote media redirection. This may
be used in conjunction with the remote KVM feature, or as a standalone applet.
The media redirection feature is intended to allow system administrators or users to mount a
remote IDE or USB CD-ROM, floppy drive, or a USB flash disk as a remote device to the server.
Once mounted, the remote device appears just like a local device to the server, allowing system
administrators or users to install software (including operating systems), copy files, update
BIOS, and so on, or boot the server from this device.
The following capabilities are supported:
The operation of remotely mounted devices is independent of the local devices on the
server. Both remote and local devices are useable in parallel.
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Either IDE (CD-ROM, floppy) or USB devices can be mounted as a remote device to the
server.
It is possible to boot all supported operating systems from the remotely mounted device
and to boot from disk IMAGE (*.IMG) and CD-ROM or DVD-ROM ISO files. See the
Tested/supported Operating System List for more information.
Media redirection shall support redirection for a minimum of two virtual devices
concurrently with any combination of devices. As an example, a user could redirect two
CD or two USB devices.
The media redirection feature supports multiple encryption algorithms, including RC4
and AES. The actual algorithm that is used is negotiated with the client based on the
client’s capabilities.
A remote media session is maintained even when the server is powered-off (in standby
mode). No restart of the remote media session is required during a server reset or power
on/off. An Integrated BMC reset (for example, due to an Integrated BMC reset after
Integrated BMC FW update) will require the session to be re-established
The mounted device is visible to (and useable by) managed system’s OS and BIOS in
both pre-boot and post-boot states.
The mounted device shows up in the BIOS boot order and it is possible to change the
BIOS boot order to boot from this remote device.
It is possible to install an operating system on a bare metal server (no OS present) using
the remotely mounted device. This may also require the use of KVM-r to configure the
OS during install.
USB storage devices will appear as floppy disks over media redirection. This allows for the
installation of device drivers during OS installation.
If either a virtual IDE or virtual floppy device is remotely attached during system boot, both
the virtual IDE and virtual floppy are presented as bootable devices. It is not possible to
present only a single-mounted device type to the system BIOS.
7.2.1 Availability
The default inactivity timeout is 30 minutes and is not user-configurable. Media redirection
sessions persist across system reset but not across an AC power loss or BMC reset.
7.2.2 Network Port Usage
The KVM and media redirection features use the following ports:
5120 – CD Redirection
5123 – FD Redirection
5124 – CD Redirection (Secure)
5127 – FD Redirection (Secure)
7578 – Video Redirection
7582 – Video Redirection
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Pin
Signal name
Pin
Signal name
1
P3V3
13
P3V3
2
P3V3
14
N12V
3
GND
15
GND
4
P5V
16
FM_PS_EN_PSU_N
5
GND
17
GND
6
P5V
18
GND
7
GND
19
GND
8
PWRGD_PS_PWROK_PSU_R1
20
NC_PS_RES_TP
9
P5V_STBY_PSU
21
P5V
10
P12V
22
P5V
11
P12V
23
P5V
12
P3V3
24
GND
Pin
Signal name
Pin
Signal name
1
GND
5
+12V
2
GND
6
+12V
3
GND
7
+12V
4
GND
8
+12V
8. On-board Connector/Header Overview
This section identifies the location and pin-out for on-board connectors and headers of the
server board that provide an interface to system options/features, on-board platform
management, or other user accessible options/features.
8.1 Power Connectors
The server board includes several power connectors that are used to provide DC power to
various devices.
8.1.1 Main Power
Main server board power is supplied from a 24-pin power connector. The connector is labeled
as “MAIN PWR” on the server board. The following tables provide the pin-out of “MAIN PWR”
connector.
Table 24. Main Power Connector Pin-out (“MAIN PWR”)
8.1.2 CPU Power Connectors
On the server board there are two white 8-pin 12V CPU power connectors labeled “CPU_1
PWR” and “CPU_2 PWR”. The following table provides the pin-out for both connectors.
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Table 25. CPU Power Connector Pin-out (“CPU_1 PWR” and “CPU_2 PWR”)
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Pin
Signal name
Pin
Signal name
1
GND
3
+12V
2
GND
4
+12V
Pin
Signal Name
Pin
Signal Name
1
SB3.3V
2
SB3.3V
KEY
4
SB5V
5
Power LED Cathode
6
System ID LED Cathode
7
3.3V
8
System Fault LED Anode
9
HDD Activity LED Cathode
10
System Fault LED Cathode
11
Power Switch
12
NIC#1 Activity LED
13
GND (Power Switch)
14
NIC#1 Link LED
15
Reset Switch
16
I2C SDA
17
GND (Reset/ID/NMI Switch)
18
I2C SCL
19
System ID Switch
20
Chassis Intrusion
21
Pull Down
22
NIC#2 Activity LED
23
NMI to CPU Switch
24
NIC#2 Link LED KEY
KEY
27
NIC#3 Activity LED
28
NIC#4 Activity LED
8.1.3 PCIe Card Power Connectors
The server board includes one 4-pin power connectors that provide support for add-in cards that
require more power than is supported from the PCIe slots direct. The connector is labeled as
OPT_12V_PWR.
Table 26. PCIe Card Power Connector Pin-out (“OPT_12V_PWR”)
8.2 Front Panel Headers and Connectors
The server board includes several connectors that provide various possible front panel options.
This section provides a functional description and pin-out for each connector.
8.2.1 SSI Front Panel Header
Included on the front edge of the server board is a 30-pin SSI compatible front panel header
which provides for various front panel features including:
Power/Sleep Button
System ID Button
System Reset Button
NMI Button
NIC Activity LEDs
Hard Drive Activity LEDs
System Status LED
System ID LED
On the server board, this header is labeled “SSI FRONT PANEL”. The following table provides
the pin-out for this header.
Table 27. SSI Front Panel Header Pin-out (“SSI Front Panel”)
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Pin
Signal Name
Pin
Signal Name
29
NIC#3 Link LED
30
NIC#4 Link LED
State
Power Mode
LED
Description
Power-off
Non-ACPI
Off
System power is off, and the BIOS has not initialized the chipset.
Power-on
Non-ACPI
On
System power is on
S5
ACPI
Off
Mechanical is off, and the operating system has not saved any context
to the hard disk.
S4
ACPI
Off
Mechanical is off. The operating system has saved context to the hard
disk.
S3-S1
ACPI
Slow blink1
DC power is still on. The operating system has saved context and
gone into a level of low-power state.
S0
ACPI
Steady on
System and the operating system are up and running.
8.2.1.1 Power/Sleep Button and LED Support
Pressing the Power button will toggle the system power on and off. This button also functions
as a sleep button if enabled by an ACPI compliant operating system. Pressing this button will
send a signal to the integrated BMC, which will power on or power off the system. The power
LED is a single color and is capable of supporting different indicator states as defined in the
following table.
Table 28. Power/Sleep LED Functional States
8.2.1.2 System ID Button and LED Support
Pressing the System ID Button will toggle both the ID LED on the front panel and the Blue ID
LED on the server board on and off. The System ID LED is used to identify the system for
maintenance when installed in a rack of similar server systems. The System ID LED can also
be toggled on and off remotely using the IPMI “Chassis Identify” command which will cause the
LED to blink for 15 seconds.
8.2.1.3 System Reset Button Support
When pressed, this button will reboot and re-initialize the system
8.2.1.4 NMI Button Support
When the NMI button is pressed, it puts the server in a halt state and causes the BMC to issue
a non-maskable interrupt (NMI). This can be useful when performing diagnostics for a given
issue where a memory download is necessary to help determine the cause of the problem.
Once an NMI has been generated by the BMC, the BMC does not generate another NMI until
the system has been reset or powered down.
The following actions cause the BMC to generate an NMI pulse:
Receiving a Chassis Control command to pulse the diagnostic interrupt. This
command does not cause an event to be logged in the SEL.
Watchdog timer pre-timeout expiration with NMI/diagnostic interrupt pre-timeout
action enabled.
The following table describes behavior regarding NMI signal generation and event logging by
the BMC.
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Causal Event
NMI
Signal
Generation
Front Panel Diag Interrupt Sensor Event Logging Support
Chassis Control command (pulse diagnostic interrupt)
X
–
Front panel diagnostic interrupt button pressed
X
X
Watchdog Timer pre-timeout expiration with
NMI/diagnostic interrupt action
X
X
Color
State
Criticality
Description
Off
System is
not
operating
Not ready
1. System is powered off (AC and/or DC).
2. System is in EuP Lot6 Off Mode.
3. System is in S5 Soft-Off State.
4. System is in S4 Hibernate Sleep State.
Green
Solid on
Ok
Indicates that the System is running (in S0 State) and its status is
‘Healthy’. The system is not exhibiting any errors. AC power is
present and BMC has booted and manageability functionality is up
and running.
Green
~1 Hz blink
Degraded system is
operating in a
degraded state
although still
functional, or
system is
operating in
a redundant state
but with an
impending failure
warning
System degraded:
Redundancy loss, such as power-supply or fan. Applies only if the
associated platform sub-system has redundancy capabilities.
Fan warning or failure when the number of fully operational fans is
more than minimum number needed to cool the system.
Non-critical threshold crossed – Temperature (including HSBP temp),
voltage, input power to power supply, output current for main power
rail from power supply and Processor Thermal Control (Therm Ctrl)
sensors.
Power supply predictive failure occurred while redundant power
supply configuration was present.
Unable to use all of the installed memory (one or more DIMMs
Table 29. NMI Signal Generation and Event Logging
8.2.1.5 NIC Activity LED Support
The Front Control Panel includes an activity LED indicator for each on-board Network Interface
Controller (NIC). When a network link is detected, the LED will turn on solid. The LED will blink
once network activity occurs at a rate that is consistent with the amount of network activity that
is occurring.
8.2.1.6 Hard Drive Activity LED Support
The drive activity LED on the front panel indicates drive activity from the on-board hard disk
controllers. The server board also provides a header giving access to this LED for add-in
controllers.
8.2.1.7 System Status LED Support
The System Status LED is a bi-color (Green/Amber) indicator that shows the current health of
the server system. The system provides two locations for this feature; one is located on the
Front Control Panel, the other is located on the back edge of the server board, viewable from
the back of the system. Both LEDs are tied together and will show the same state. The System
Status LED states are driven by the on-board platform management sub-system. The following
table provides a description of each supported LED state.
Table 30. System Status LED State Definitions
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Color
State
Criticality
Description
failed/disabled but functional memory remains available)
Correctable Errors over a threshold and migrating to a spare DIMM
(memory sparing). This indicates that the user no longer has spared
DIMMs indicating a redundancy lost condition. Corresponding DIMM
LED lit.
Uncorrectable memory error has occurred in memory Mirroring Mode,
causing Loss of Redundancy.
Correctable memory error threshold has been reached for a failing
DDR3 DIMM when the system is operating in fully redundant RAS
Mirroring Mode.
Battery failure.
BMC executing in uBoot. (Indicated by Chassis ID blinking at Blinking
at 3Hz). System in degraded state (no manageability). BMC uBoot is
running but has not transferred control to BMC Linux. Server will be in
this state 6-8 seconds after BMC reset while it pulls the Linux image
into flash
BMC booting Linux. (Indicated by Chassis ID solid ON). System in
degraded state (no manageability). Control has been passed from
BMC uBoot to BMC Linux itself. It will be in this state for ~10-~20
seconds.
BMC Watchdog has reset the BMC.
Power Unit sensor offset for configuration error is asserted.
HDD HSC is off-line or degraded.
Amber
~1 Hz blink
Non-critical System is
operating in a
degraded state
with an impending
failure warning,
although still
functioning
Non-fatal alarm – system is likely to fail:
Critical threshold crossed – Voltage, temperature (including HSBP
temp), input power to power supply, output current for main power rail
from power supply and PROCHOT (Therm Ctrl) sensors.
VRD Hot asserted.
Minimum number of fans to cool the system not present or failed
Hard drive fault
Power Unit Redundancy sensor – Insufficient resources offset
(indicates not enough power supplies present)
In non-sparing and non-mirroring mode if the threshold of correctable
errors is crossed within the window
Correctable memory error threshold has been reached for a failing
DDR3 DIMM when the system is operating in a non-redundant mode
Amber
Solid on
Critical, nonrecoverable –
System is halted
Fatal alarm – system has failed or shutdown:
CPU CATERR signal asserted
MSID mismatch detected (CATERR also asserts for this case).
CPU 1 is missing
CPU Thermal Trip
No power good – power fault
DIMM failure when there is only 1 DIMM present and hence no good
memory present1.
Runtime memory uncorrectable error in non-redundant mode.
DIMM Thermal Trip or equivalent
SSB Thermal Trip or equivalent
CPU ERR2 signal asserted
BMC\Video memory test failed. (Chassis ID shows blue/solid-on for
this condition)
Both uBoot BMC FW images are bad. (Chassis ID shows blue/solidon for this condition)
240VA fault
Fatal Error in processor initialization:
Processor family not identical
Processor model not identical
Processor core/thread counts not identical
Processor cache size not identical
Unable to synchronize processor frequency
Unable to synchronize QPI link frequency
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Pin
Signal Name
Pin
Signal Name
1
+5V 2 +5V
3
USB_N 4 USB_N
5
USB_P 6 USB_P
7
GND 8 GND
10
Pin
Signal Name
1
SMB_SENSOR_3V3STBY_DATA_R0
2
GROUND
3
SMB_SENSOR_3V3STBY_CLK
4
P3V3_AUX
5
FM_LCP_ENTER_N_R
6
FM_LCP_LEFT_N_R
7
FM_LCP_RIGHT_N_R
Pin
Signal Name
1
GND
2
SATA_TX_P
3
SATA_TX_N
4
GND
5
SATA_RX_N
6
SATA_RX_P
7
GND
8.2.2 Front Panel USB Connector
The server board includes a 10-pin connector, that when cabled, can provide up to two USB
ports to a front panel. On the server board the connector is labeled “USB5-6”. The following
table provides the connector pin-out.
Table 31. Front Panel USB Connector Pin-out (USB5-6)
8.2.3 Intel Local Control Panel Connector
The server board includes a 7-pin connector that is used when the system is configured with
Intel Local Control Panel with LCD support. On the server board this connector is labeled
LCPand is located on the front edge of the board. The following table provides the pin-out for
this connector.
Table 32. Intel Local Control Pane Connector Pin-out (LCP)
8.3 On-Board Storage Connectors
The server board provides connectors for support of several storage device options. This
section provides a functional overview and pin-out of each connector.
8.3.1 SATA Only Connectors: 6 Gbps
The server board includes two white single port SATA only connectors capable of transfer rates
of up to 6Gb/s. On the server board these connectors are labeled as SATA_0 and SATA_1. The
following table provides the pin-out for both connectors.
Table 33. SATA Only Connector Pin-out (SATA_0 and SATA_1)
Note: As an option, SATA_0 supports vertical, high profile SATA_DOM.
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Pin
Signal Name
1
GND
2
SATA_TX_P
3
SATA_TX_N
4
GND
5
SATA_RX_N
6
SATA_RX_P
7
GND
Pin
Signal Name
Pin#
Signal Name
1
CLOCK 2 LOAD
3
GND
4
DATAOUT
5
DATAIN
Pin
Signal Name
1
GND
2
FM_PBG_DYN_SKU_KEY
3
GND
4
FM_SSB_SAS_SATA_RAID_KEY
Pin
Signal Name
1
SMB_HSBP_3V3STBY_DATA
2
GND
8.3.2 SATA/SAS Connectors
The server board includes eight SATA/SAS connectors. On the server board, these connectors
are labeled as SATA/SAS_ 0 to SATA/SAS_7. By default, only the connector labeled
SATA/SAS_0 to SATA/SAS_3 are enabled and has support for up to four SATA ports capable
of transfer rates of up to 3Gb/s. The connector labeled SATA/SAS_4 to SATA/SAS_7 is only
enabled when an optional Intel® RAID C600 Upgrade Key is installed. See Table 10 for a
complete list of supported storage upgrade keys. The following tables provide the pin-out for
each connector.
Table 34. SATA/SAS Connector Pin-out (SATA/SAS_0 to SATA/SAS_7)
8.3.3 SAS SGPIO Connectors
Table 35. SAS SGPIO Connector Pin-out (SAS_SPGIO_0 and SAS_SPGIO_1)
8.3.4 Intel
®
RAID C600 Upgrade Key Connector
The server board provides one connector to support Intel® RAID C600 Upgrade Key. The Intel®
RAID C600 Upgrade Key is a small PCB board that enables different versions of RAID 5
software stack and/or upgrade from SATA to SAS storage functionality. On the server board,
the connector is labeled as STRO UPG KEY. The pin configuration of connector is identical and
defined in the following table.
Table 36. Intel® RAID C600 Upgrade Key Connector Pin-out (STRO UPG KEY)
8.3.5 HSBP_I2C Header
Revision 1.0
Table 37. HSBP_I2C Header Pin-out (HSBP_I2C)
Intel order number G42278-002
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