Intel IXP46X, IXP45X User Manual

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Intel

IXP45X and Intel

IXP46X

Product Line of Network Processors

Hardware Design Guidelines

February 2007

Document No:305261; Revision:004

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Contents—Intel

IXP45X and Intel® IXP46X Product Line of Network Processors

1.0 Introduction..............................................................................................................9

1.1 Content Overview................................................................................................9

1.2 Related Documentation......................................................................................10

1.3 Acronyms and Abbreviations.................................................... .. .. .. .....................11

1.4 Overview .........................................................................................................11

1.5 Typical Applications ...........................................................................................14

2.0 System Architecture ................................................................................................15

2.1 System Architecture Description..........................................................................15

2.2 System Memory Map .........................................................................................15

3.0 General Hardware Design Considerations................................................................17

3.1 Soft Fusible Features .........................................................................................17

3.2 DDR-266 SDRAM Interface....................................... ......................... ... .. .. ..........18

3.2.1 Signal Interface .......................... .. .. .......................... .. .. .........................18

3.2.2 DDR SDRAM Memory Interface.................................................................20

3.2.3 DDR SDRAM Initialization ........................................................................20

3.3 Expansion Bus ..................................................................................................20

3.3.1 Signal Interface .......................... .. .. .......................... .. .. .........................21

3.3.2 Reset Configuration Straps ............................ .. .. .. ............................ .. ......21

3.3.3 8-Bit Device Interface.............................................................................23

3.3.4 16-Bit Device Interface ...........................................................................23

3.3.5 32-Bit Device Interface ...........................................................................24

3.3.6 Flash Interface.......................................................................................27

3.3.7 SRAM Interface......................................................................................28

3.3.8 Design Notes .........................................................................................28

3.4 UART Interface .................................................................................................28

3.4.1 Signal Interface .......................... .. .. .......................... .. .. .........................29

3.5 MII/SMII Interface ............................................................................................30

3.5.1 Signal Interface MII................................................................................31

3.5.2 Device Connection, MII ........................... .. .. ........................... .................33

3.5.3 Signal Interface, SMII................................................ .. .. .........................34

3.5.4 Device Connection, SMII ........................................ .. .. .. ...........................35

3.6 GPIO Interface..................................................................................................35

3.6.1 Signal Interface .......................... .. .. .......................... .. .. .........................36

3.6.2 Design Notes .........................................................................................36

3.7 I

3.8 USB Interface................................ .. ......................... .. .......................... ............38

3.9 UTOPIA Level 2 Interface ...................................................................................41

3.10 HSS Interface...................................................................................................43

3.11 SSP Interface ...................................................................................................46

3.12 PCI Interface ....................................................................................................48

C Interface ........................ .......................... .. .. ......................... .. ...................37

3.7.1 Signal Interface .......................... .. .. .......................... .. .. .........................37

3.7.2 Device Connection................................ .. ......................... .. .. ...................37

3.8.1 Signal Interface .......................... .. .. .......................... .. .. .........................39

3.8.2 Device Connection................................ .. ......................... .. .. ...................40

3.9.1 Signal Interface .......................... .. .. .......................... .. .. .........................42

3.9.2 Device Connection................................ .. ......................... .. .. ...................42

3.10.1 Signal Interface ............................................. ........................................44

3.10.2 Device Connection................................................. .. .. .. ......................... ..46

3.11.1 Signal Interface ............................................. ........................................47

3.11.2 Device Connection................................................. .. .. .. ......................... ..47

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Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—Contents

3.12.1 Signal Interface......................................................................................48

3.12.2 PCI Interface Block Diagram.....................................................................49

3.12.3 Supporting 5 V PCI Interface............................................. .. .. .. .................50

3.12.4 PCI Option Interface................................................................................51

3.12.5 Design Notes............................................ .. ......................... ...................53

3.13 JTAG Interface ..................................................................................................53

3.13.1 Signal Interface......................................................................................54

3.14 Input System Clock............................................................... .. .. .. .......................54

3.14.1 Clock Signals .........................................................................................54

3.14.2 Clock Oscillator.......................................................................................54

3.14.3 Device Connection ..................................................................................55

3.15 Power ..............................................................................................................55

3.15.1 De-Coupling Capacitance Recommendations...............................................56

3.15.2 VCC De-Coupling....................................................................................56

3.15.3 VCCP De-Coupling ..................................................................................56

3.15.4 VCCM De-Coupling..................................................................................56

3.15.5 Power Sequence.................................................................... .. ...............56

3.15.6 Reset Timing..........................................................................................56

4.0 General PCB Guide ...................................................................................................59

4.1 PCB Overview ...................................................................................................59

4.2 General Recommendations..................................................................................59

4.3 Component Selection .........................................................................................59

4.4 Component Placement........................................................................................59

4.5 Stack-Up Selection................................................... .. .. .. .......................... .. .. ......60

5.0 General Layout and Routing Guide...........................................................................63

5.1 Overview..........................................................................................................63

5.2 General Layout Guidelines...................................................................................63

5.2.1 General Component Spacing ....................................................................64

5.2.2 Clock Signal Considerations......................................................................66

5.2.3 SMII Signal Considerations ......................................................................67

5.2.4 MII Signal Considerations ........................................................................67

5.2.5 USB Considerations.................................................................................67

5.2.6 Cross-Talk .............................................................................................68

5.2.7 EMI-Design Considerations............................... .. ......................................68

5.2.8 Trace Impedance....................................................................................69

5.2.9 Power and Ground Plane..........................................................................69

6.0 PCI Interface Design Considerations.......................................................................71

6.1 Electrical Interface............................................. .. ..............................................71

6.2 Topology ..........................................................................................................71

6.3 Clock Distribution ................................................ ..............................................72

6.3.1 Trace Length Limits.................................................................................73

6.3.2 Routing Guidelines.............................................. .. .......................... .. .. ....74

6.3.3 Signal Loading........................................................................................74

7.0 DDR-SDRAM.............................................................................................................75

7.1 Introduction......................................................................................................75

7.1.1 Selecting VTT Power Supply.....................................................................80

7.1.2 Signal-Timing Analysis ................................ ............................................81

7.1.3 Printed Circuit Board Layer Stackup ..........................................................84

7.1.4 Printed Circuit Board Controlled Impedance................................................85

7.1.5 Timing Relationships ...............................................................................87

7.1.6 Resistive Compensation Register (Rcomp)..................................................88

7.1.7 Routing Guidelines.............................................. .. .......................... .. .. ....88

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Contents—Intel

IXP45X and Intel® IXP46X Product Line of Network Processors

7.1.7.1 Clock Group.............................................................................88

7.1.7.2 Data, Command, and Control Groups...........................................89

7.2 Simulation Results.............................................................................................90

7.2.1 Clock Group...........................................................................................90

7.2.2 Data Group ...........................................................................................92

7.2.3 Control Group........................................................................................98

7.2.4 Command Group.................................................................................. 100

7.2.5 RCVENIN and RCVENOUT ...................................................................... 105

Figures

1Intel® IXP465 Component Block Diagram....................................................................13

2Intel® IXP465 Example System Block Diagram ............................................................16

3 8/16/32-Bit Device Interface: No Byte-Enable..............................................................25

4 8/16/32-Bit Device Interface: Byte Enable...................................................................26

5 Flash Interface Example............................................................................................27

6 Expansion Bus SRAM Interface...................................................................................28

7 UART Interface Example ....................................... ......................... .. .. .......................30

8 MII Interface Example ..............................................................................................33

9 SMII Interface Example ............................................................................................35

C EEPROM Interface Example.................................... .. ............................................38

10 I

11 USB Host Down Stream Interface Example..................................................................40

12 USB Device Interface Example....................................... ............................................41

13 UTOPIA Interface Example ........................................................................................43

14 HSS Interface Example.......................... .. ......................... .. .. ... ......................... .. .. ....46

15 Serial Flash and SSP Port (SPI) Interface Example........................................................47

16 PCI Interface...........................................................................................................50

17 PCI 3.3 V to 5 V Logic Translation Interface.................................................................51

18 Clock Oscillator Interface Example.............................................................................. 55

19 Component Placement on a PCB.................................................................................60

20 8-Layer Stackup ......................................................................................................62

21 6-Layer Stackup ......................................................................................................62

22 Signal Changing Reference Planes..............................................................................64

23 Good Design Practice for VIA Hole Placement...............................................................65

24 Poor Design Practice for VIA Placement.......................................................................65

25 Pad-to-Pad Clearance of Passive Components to a PGA or BGA.......................................66

26 PCI Address/Data Topology.......................................................................................72

27 PCI Clock Topology ..................................................................................................73

28 Processor-DDR Interface...........................................................................................76

29 Processor-DDR Interface: x16 Devices with ECC...........................................................79

30 VTT Terminating Circuitry..........................................................................................80

31 DDR Command and Control Setup and Hold.................................................................81

32 DDR Data to DQS Read Timing Parameters..................................................................82

33 DDR-Data-to-DQS-Write Timing Parameters ................................................................83

34 DDR-Clock-to-DQS-Write Timing Parameters ...............................................................83

35 Printed Circuit Board Layer Stackup............................................................................85

36 Printed Circuit Board Controlled Impedance .................................................................86

37 DDR Clock Topology: Two-Bank x16 Devices ...............................................................91

38 DDR Clock Simulation Results: Two-Bank x16 Devices ..................................................92

39 DDR Data Topology: Two-Bank x16 Devices ................................................................94

40 DDR Data Write Simulation Results: Two-Bank x16 Devices...........................................95

41 DDR Data Read Simulation Results: Two-Bank x16 Devices

(Reduced Drive Strength) .........................................................................................96

42 DDR Data Read Simulation Results: Two-Bank x16 Devices (Full Drive Strength)........... ... 97

43 DDR Control (CS0) Topology: Two-Bank x16 Devices....................................................98

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Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—Contents

44 DDR RAS Simulation Results: Two-Bank x16 Devices ....................................................99

45 DDR Command (MA3) Topology: Two-Bank x16 Devices..............................................101

46 DDR Address Simulation Results: Two-Bank x16 Devices .............................................102

47 DDR Command (RAS) Topology: Two-Bank x16 Devices........................................ .. ....103

48 DDR RAS Simulation Results: Two-Bank x16 Devices ..................................................104

49 DDR RCVENIN/RCVENOUT Topology..........................................................................105

50 DDR RCVENIN/RCVENOUT Simulation Results (Rseries = 0 W) .....................................106

51 DDR RCVENIN/RCVENOUT Simulation Results (Rseries = 60 W)....................................107

Tables

1 List of Acronyms and Abbreviations.............................................................................11

2 Signal Type Definitions.............................................. .. .. ......................... .. .. ...............17

3 Soft Fusible Features ................................................................................................18

4 DDR SDRAM Interface Pin Description .........................................................................18

5 Expansion Bus Signal Recommendations......................................................................21

6 Boot/Reset Strapping Configuration ............................................................................22

7 UART Signal Recommendations..................................................................................29

8 MII NPE A Signal Recommendations............................................................................31

9 MII NPE B Signal Recommendations............................................................................31

10 MII NPE C Signal Recommendations............................................................................32

11 MAC Management Signal Recommendations NPE A,B,C..................................................33

12 SMII Signal Recommendations: NPE A, B, C.................................................................34

13 GPIO Signal Recommendations...................................................................................36

14 I2C Signal Recommendations....................................... .. ........................... .. ... ............37

15 USB Host/Device Signal Recommendations ..................................................................39

16 UTOPIA Signal Recommendations...............................................................................42

17 High-Speed, Serial Interface 0 .............................. ... ........................... .......................44

18 High-Speed, Serial Interface 1 ...................................................................................45

19 Synchronous Serial Peripheral Port Interface................................................................47

20 PCI Controller ..........................................................................................................48

21 PCI Host/Option Interface Pin Description....................................................................51

22 Synchronous Serial Peripheral Port Interface................................................................54

23 Clock Signals ...........................................................................................................54

24 Power Interface........................................................................................................55

25 PCI Address/Data Routing Guidelines ..........................................................................72

26 PCI Clock Routing Guidelines......................................................................................73

27 DDR Signal Groups...................................................................................................75

28 Supported Memory Configurations..............................................................................78

29 DDR Command and Control Setup and Hold Values.......................................................81

30 DDR Data to DQS Read Timing Parameters..................................................................82

31 DDR Data to DQS Write Timing Parameters..................................................................83

32 DDR-Clock-to-DQS-Write Timing Parameters................................................................84

33 Timing Relationships.................................................................................................87

34 Clock Signal Group Routing Guidelines ........................................................................89

35 Data, Command, and Control Group Routing Guidelines.................................................89

36 Clock Group Topology Transmission Line Characteristics ................................................90

37 Data Group Topology Transmission Line Characteristics.................................................93

38 Control Group Topology Transmission Line Characteristics..............................................98

39 Command Group Topology Transmission Line Characteristics........................................100

40 Control Group Topology Transmission Line Characteristics............................................105

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Revision History—Intel

IXP45X and Intel® IXP46X Product Line of Network Processors

Revision History

Date Revision Description

• Section 1.4, Figure 1, Figure 2, Section 3.5: Updated the number of supported SMII ports from six to three.

• Table 11, Table 12, Table 16: Updated pi n type for UTP_OP_ADDR[4:0], UTP_IP_ADDR[4:0], and ETH_MDC.

February 2007 004

August 2005 003

May 2005 002

March 2005 001 Initial release of document.

• Section 7.0, “DDR-SDRAM” : Updated design information.

• Removed SS-SMII references since this feature is not supported.

• Incorporated specification changes, specification clarifications and document changes from the Intel Network Processors Specification Update (306428-006)

•Updated Intel

The following changes were made in this release:

• Table 4: added ECC signal interface recommendation.

• Table 5: corrected EX_IOWAIT_N and EX_WAIT_N pull-up recommendations.

• Section 3.3.2, Tab le 5, Section 3.3.3, Section 3.3.4, and

Section 3.3.6: changed pull-down resistor value from 10K to 4.7K.

• Table 16: corrected UTP_OP_SOC pull-down recommendation.

• Section 3.12.2: clarified description.

• Added new information: Section 3.12.3, “Supporting 5 V PCI

Interface” and Section 3.12.4, “PCI Option Interface” .

• Section 3.12.5: clarified 5V support.

• Table 24: updated power supply requ irements for 667 MHz core speed processor.

• Section 6.2 and Section 6.3: enhanced description, figure, and tables.

• Section 7.1.7.1: enhanced clock group routing guidelines.

Updated to add support for Intel

Section 3.2.1: enhanced signal descriptions for DDRI_CK[2:0] and

DDRI_CB[7:0].

product branding.

IXP4XX Product Line of

IXP455 Network Processor.

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Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—Revision History

IXP45X and Intel® IXP46X Product Line of Network Processors

Intel HDD February 2007 8 Document Number: 305261, Revision: 004

Introduction—Intel

IXP45X and Intel® IXP46X Product Line of Network Process or s

1.0 Introduction

This design guide provides recommendations for hardware and system designers who are developing with the Intel Processors. This document should be used in conjunction with the Intel

Intel

IXP46X Product Line of Network Processors Datasheet and sample schematics

provided for the Intel

IXP45X and Intel® IXP46X Product Line of Network

IXDP465 Development Platform in that platform’s

documentation kit. Design Recommendations are necessary to meet the timing and signal quality

specifications. The guidelines recommended in this document are based on experience and simulation

work done at Intel while developing the Intel

IXDP465 Development Platform. These

recommendations are subject to change.

Note: This document discusses all features supported on the Intel

Processor. A subset of these features is supported by certain processors in the IXP45X/ IXP46X product line, such as the Intel® IXP460 or Intel® IXP455 network processors. For details on feature support listed by processor, see the Intel IXP46X Product Line of Network Processors Datasheet.

1.1 Content Overview

Chapter Name Description

Chapter 1.0, “Introduction” Conventions used in this manual and related documentation Chapter 2.0, “System Architecture” System architectural block diagram and system memory map Chapter 3.0, “General Hardware Design

Considerations” Chapter 4.0, “General PCB Guide” General PCB design practice and layer stack-up description Chapter 5.0, “General Layout and Routing

Guide” Chapter 6.0, “PCI Interface Design

Considerations”

Chapter 7.0, “DDR-SDRAM”

Graphical representation of most common peripheral interfaces.

More specific layout and routing recommendations for board designers

Board-design recommendations when implementing PCI interface

Board-design recommendations when implementing DDRI memory interface

IXP45X and

IXP465 Network

IXP45X and Intel®

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Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—Introduction

1.2 Related Documentation

The reader of this design guide should also be familiar with the material and concepts presented in the following documents:

Title Document #

Hardware-Assisted IEEE 1588* Implementation in the Intel Product Line White Paper

IXP45X and Intel® IXP46X Product Line of Network Processors

Intel Developer’s Manual

Intel

IXP45X and Intel® IXP46X Product Line of Network Processors

Datasheet

IXP4XX Product Line of Network Processors Specification

Intel Update

IXP400 Software Programmer’s Guide 252539

Intel

IXP400 Software Specification Update 273795

Intel

XScale™ Core Developer’s Manual 273473

Intel

IXDP465 Development Platform Documentation Kit N/A

Intel XScale

Intel StrataFlash® Memory (J3) to Intel® Embedded Memory (J3 v.D) Conversion Guide - Application Note 835

Migration Guide for Intel StrataFlash® Synchronous Memory (J3) to Intel StrataFlash® Embedded Memory (P30 and P33) - Application Note 812

Migration Guide for Intel StrataFlash® Synchronous Memory (K3/ K18) to Intel StrataFlash® Embedded Memory (P30) - Application Note 825

Double Data Rate (DDR) SDRAM Specification, 2004; JEDEC Solid State Technology Association

C-Bus Specification from Philips Semiconductors* Available at http://www.nxp.com

IEEE 802.3 Specification IEEE 1149.1 Specification

PCI Local Bus Specification, Rev. 2.2 Universal Serial Bus Specification, Revision 1.1 UTOPIA Level 2 Specification, Revision 1.0

Note: For Intel documentation, see the Intel Technical Documentation Center, available through the

following link:

http://www.intel.com/products/index.htm

Microarchitecture Technical Summary —

IXP46X

305068

306262

306261

306428

308555

306667

306669

JESD79D

N/A

IXP45X and Intel® IXP46X Product Line of Network Processors

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Introduction—Intel

IXP45X and Intel® IXP46X Product Line of Network Process or s

1.3 Acronyms and Abbreviations

Table 1 lists the acronyms and abbreviations used in this guide.

Table 1. List of Acronyms and Abbreviations

Term Explanation

AHB Advanced High-Performance Bus

APB Advanced Peripheral Bus ATM Asynchronous Transfer Mode DDR Double Data Rate

EMI Electro-Magnetic Interference

GPIO General Purpose Input/Output

HSS High Speed Serial

I2C Inter-Integrated Circuit

IP Internet Protocol

ISA Instruction Set Architecture

LAN Local Area Network

MII Media-Independent Interface NPE Network Processor Engine PCB Printed Circuit Board

PCI Peripheral Component Interface PHY Physical Layer Interface

PLL Phase-Locked Loop

PMU Performance Monitoring Unit

SDRAM Synchronous Dynamic Random Access Memory

SME Small-to-Medium Enterprise

SMII Serial Media-Independent Interface

SSP Synchronous Serial Protocol

UART Universal Asynchronous Receiver-Transmitter

USB Universal Serial Bus

VTT Termination Voltage Supply

1.4 Overview

The IXP45X/IXP46X network processors are highly integrated devices, capable of interfacing with most common industry standard peripherals, required for highperformance control applications.

Note: This document discusses all features supported on the Intel

Processor. A subset of these features is supported by certain processors in the IXP45X/ IXP46X product line, such as the Intel

IXP460 or Intel® IXP455 network processors. For details on feature support listed by processor, see the Intel IXP46X Product Line of Network Processors Datasheet.

Some of the key features of the IXP45X/IXP46X network processors, when used as a single-chip solution for embedded applications, are as follows:

•Intel XScale

Processor (compliant with Intel® StrongARM* architecture) — Up to

667 MHz

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Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

IXP465 Network

IXP45X and Intel®

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—Introduction

• 32-bit PCI interface Master/Target 33/66 MHz

• Device Universal Serial Bus (USB) Controller

• Host Universal Serial Bus (USB) Controller

• DDRI-266 SDRAM (133-MHz Clock, 266-Mbps per data line) — User-enabled ECC, supports up to 1 Gbyte of external memory

• 32-bit Expansion Bus Interface — Master/Target interface

•Two UART ports

• Up to three Ethernet ports (consult device part number for enabled features) MII/ SMII

• Up to three NPEs

•UTOPIA Level 2 Interface

• Synchronous Serial Port Interface (SSP)

• Two High-Speed Serial Port Interfaces (HSS)

• Inter-Integrated Circuit (IIC or I2C) Interface

• 16 GPIO (General Purpose Input Output)

•Packaging

—544-pin PBGA package — Commercial temperature (0° to +70° C) — Extended temperature (-40° to +85° C)

For a complete features list and block diagram description, see the Intel

Intel

IXP46X Product Line of Network Processors Datasheet.

IXP45X and

Note: Some features require Intel-supplied software. T o determine if a feature is enabled in a

particular software release, refer to the Intel

IXP400 Software Specification Update.

A block diagram of all major internal hardware components of the IXP465 network processor is given in Figure 1. The illustration also shows how the components interface with each other through the various bus interfaces such as the North AHB, South AHB, and APB.

IXP45X and Intel® IXP46X Product Line of Network Processors

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Introduction—Intel

Figure 1. Intel

UTOPIA 2/MII/SMII

IXP45X and Intel® IXP46X Product Line of Network Process or s

IXP465 Component Block Diagram

HSS 0 HSS 1

NPE A

16 GPIO

MII/SMII

IEEE 1588

I2C

SSP

USB Device Version 1.1

UART 0

921 KBaud

UART 1

921 KBaud

GPIO

Interrupt

Controller

IBPMU

AES/DES/SHA/

Cryptography

Unit

APB 66.66 MHz x 32 Bits

Hardware RNG Hashing SHA1

Exponentiation Unit

AHB Slave /

APB Master Bridge

USB-Host

Controller V. 2.0

High-Speed is not

Supported

NPE B

NPE C

MD-5

North AHB 133.32 MHz x 32 bits

North AHB

Arbiter

Queue

Manager

AHB/AH B

Bridge

South AHB 133.32 MHz x 32 bits

South AHB

Arbiter

Expansion Bus

Controller

PCI C ont ro ller

DDRI Memory Controller Unit

MPI

133 MHz x 64

Intel XScale® Processor

32-Kbyte I -Cache

32-Kbyte D-Cache

2-Kbyte Mini D-Cache

32 Bit + ECC

Timers

32 bit at 33/66 MHz8/16/32 bit + Parity

Slave Only

Master on South AHB

Master on North AHB

Bus Arbiters

AHB Slave / APB Master

B3777 -007

Note: Figure 1 shows the Intel® IXP465 Network Processor. For details on feature support

listed by processor, see the Intel

IXP45X and Intel® IXP46X Product Line of Network

Processors Datasheet.

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Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—Introduction

1.5 Typical Applications

• High-performance DSL modem

• High-performance cable modem

•Residential gateway

•SME router

• Integrated access device (IAD)

•Set-top box

• DSLAM

• Access points — 802.11a/b/g

• Industrial controllers

• Network printers

•VoIP Gateways

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System Architecture—Intel

IXP45X and Intel® IXP46X Product Line of Network Processors

2.0 System Architecture

2.1 System Architecture Description

The Intel® IXP45X and Intel® IXP46X Product Line of Network Processors are multifunction processors that integrate the Intel XScale compliant) with highly integrated peripheral controllers and intelligent network processor engines.

The processor is a highly integrated design, manufactured with Intel’s 0.18-micron production semiconductor process technology. This process technology — along with numerous, dedicated-function peripheral interfaces and many features with the Intel XScale processor — addresses the needs of many system applications and helps reduce system costs. The processors can be configured to meet many system application and implementation needs.

Figure 2 illustrates one of many applications for which the IXP45X/IXP46X network

processors can be implemented. For detailed functional descriptions, see the Intel

IXP45X and Intel

IXP46X Product Line of Network Processors Developer’s Manual.

2.2 System Memory Map

For a complete memory map and register description of each individual module, refer to the Intel

Developer’s Manual.

IXP45X and Intel® IXP46X Product Line of Network Processors

Processor (ARM* architecture

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Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

Intel® IXP45X and Intel® IXP46X Product Line of Ne twork Processors—System Architecture

Figure 2. Intel® IXP465 Example System Block Diagram

JTAG

Header

Flash

32 Mbyte

Board

Configuration

Reset Logic

CS_N0

D[31:0]

A[24:0]

Ex pansion Bus

Intel

IXP46X Product

SDRAM Memory Bus

RAS, CAS, WE, CS,CLK

Line of Network

LCD/LED

Diagnostics

Display

Buff

Processors

DDR

CB[7:0]

D[31:0]

BA[1:0]

A[13:0]

HSS 1

SSP CODEC or

DDR

SDRAM

16Mx4x16

DDR

16Mx4x16

512 Mbyte

SDRAM

512 Mbyte

(Four Chips)

Max 1 Gbyt e

(Four Chips)

SLIC/CODEC or T1/E1/J1 FramerHSS 0

A/D

DB9

RJ45 Port 0

RJ45 Port 2

RS 232

Serial Port 0

RS 232

Serial Port 1

10/100

PHYs

Up to 3Ports

USB Host

Connector

USB Device

Connector

I2C

UTOPIA Level 2

Clock Buff er

3-MII/

3-SMII/

PCI Bus

USB v2.0 3.3 V

USB v1.1

Transparent PCI Bridge

PCI Slots

Ether net

Clocks

I2C

cPCI Bus

cPCI J2

cPCI J1

2.5 V

1.3 V

xDSL

PCI

Clock

Power Supply

xDSL

PLL

OSC

B4835 -002

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General Hardware Design Considerations—Intel Network Processors

IXP45X and Intel® IXP46X Product Line of

3.0 General Hardware Design Considerations

This chapter contains information for implementing and interfacing to major hardware blocks of the Intel

IXP45X and Intel® IXP46X Product Line of Network Processors. Such blocks include DDR SDRAM, Flash, SRAM, Ethernet PHYs, UART and most other peripherals interfaces. Signal definition tables list resistor recommendations for pullups and pull-downs.

Features disabled by a specific part number, do not require pull-ups or pull-downs. Therefore, all pins can be left unconnected. Features enabled by a specific part number and required to be Soft Fuse-disabled, only require pull-ups or pull-downs in the clock- input signals. Other conditions may require pull-up or pull-down resistors for configuration purposes at power on or reset. Likewise, open-collector outputs must be pulled-high.

Warning: The IXP45X/IXP46X network processors’ I/O pins are 3.3 V only, except for DDR

SDRAM which is 2.5 V. None of the I/Os are 5-V tolerant.

Table 2 gives the legend for interpreting the Type field used in this chapter’s signal-

definition tables.

Table 2. Signal Type Definition s

Symbol Description

I Input pin only

O Output pin only I/O Pin can be either an input or output OD Open-drain pin TRI Tri-State pin

PWR Power pin GND Ground pin

3.1 Soft Fusible Features

Soft Fuse Enable/Disable is a method to enable or disable features in hardware, virtually disconnecting the hardware modules from the processor.

Some of the features offered in the IXP45X/IXP46X product line can be Sof t Fus e Enabled/Disabled during boot. It is recommended that if a feature is not used in the design, the feature be Soft disabled. This helps reduce power and maintain the part running at a cooler temperature. When Soft Fuse Disabled, a pull-up resistor must be connected to each clock input pins of the disabled feature interface. All other signals can be left unconnected.

Soft Fuse Enable/Disable can be done by writing to EXP_UNIT_FUSE_RESET register, for more information refer to the Intel Network Processors Developer’s Manual and review the register description.

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Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—General Hardware

Table 3. Soft Fusible Features

Name Description

PCI The complete bus must be enabled or disable.

HSS0/1 Can only be disable as a pair.

UTOPIA

ETHERNET

USB Host Each USB can be Enable separately.

USB Device Each USB can be Enable separately.

DDR ECC DDR can be disabled separately form the rest of the DDR interface.

If enabling UTOPIA, MACs on NPE A are disabled. If enabling MACs on NPE A, UTOPIA are disabled.

Can Enable either MII MACs or SMII MACs, but not both at the same time. Enable of MACs can be separately done per each NPE.

3.2 DDR-266 SDRAM Interface

The IXP45X/IXP46X network processors support unbuffered, DDR-266 SDRAM technology, capable of addressing two memory banks (one bank per CS). Each bank can be configured to support 32/64/128/256/512-Mbyte for a total combined memory support of 1 Gbyte.

Design Considerations

The device supports non-ECC and ECC for error correction, which can be enable or disable by software as required. Banks have a bus width of 32 bits for non ECC or 40 bits for ECC enable (32-bit data + 8-bit ECC).

For a complete feature list, see the Intel

IXP45X and Intel® IXP46X Product Line of

Network Processors Datasheet.

General DDR SDRAM routing guidelines can be found in Section 7.1.7, “Routing

Guidelines” on page 88. For more detailed information, see the PC266 DDR SDRAM

specification.

3.2.1 Signal Interface

Table 4. DDR SDRAM Interface Pin Description (Sheet 1 of 2)

Name

DDRI_CK[2:0] O

DDRI_CK_N[2:0] O Same as above No

DDRI_CS_N[1:0] O

DDRI_RAS_N O

DDRI_CAS_N O

Input Outpu

Device-Pin Connection

Connect a pair of differential clock signals to every device; When using both banks, daisy chain devices with same data bit sequence.

Use the same CS to control 32-bi t data + 8-bit ECC, per bank

The RAS signal must be connected to each device in a daisy chain manner

The CAS signal must be connected to each device in a daisy chain manner

VTT

Terminatio

Yes

DDR SDRAM Clock Out — Provides the positive differential clocks to the external SDRAM memory subsystem.

DDR SDRAM Clock Out — Provides the negative differential clocks to the external SDRAM memory subsystem.

Chip Select — Must be asserted for all transactions to the DDR SDRAM device. One per bank.

Row Address Strobe — Indicates that the current address on DDRI_MA[13:0] is the row.

Column Address Strobe — Indicates that the current address on DDRI_MA[13:0] is the column.

Description

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IXP45X and Intel® IXP46X Product Line of

Table 4. DDR SDRAM Interface Pin Description (Sheet 2 of 2)

Name

DDRI_WE_N O

DDRI_DM[4:0] O

DDRI_BA[1:0] O

DDRI_MA[13:0] O

DDRI_DQ[31:0] I/O

DDRI_CB[7:0] I/O Connect to ECC memory devices. Yes

DDRI_DQS[4:0] I/O

DDRI_CKE[1:0] O

DDRI_RCVENOUT_N O

DDRI_RCVENIN_N I Same as above No

DDRI_RCOMP O Tied off to a resistor

DDRI_VREF I VCCM/2 VCCM/2

Input

Outpu

Device-Pin Connection

The WE signal must be connected to each device in a daisy chain manner

Connect to each DM device pin. For the 8-bit devices connect one DM signal per device.

For the 16-bit devices connect two DM signal per device (depending on how many data bits are being used).

The BA signals must be connected to each device in a daisy chain manner.

All address signals need to be connected to each device in a daisy chain manner.

Need to be connected in parallel to achieve a 32-bit bus width.

Connect DQS[3:0] to devices wi th data signals and DQS[4] to devices with ECC signals.

Use one CKE per bank, never mix the CKE on the same bank. Use CKE[0] for bank0 and CKE[1] for bank1

Connect RCVEOUT to RCVENIN and follow note on pin description in this table.

VTT

Terminatio

Yes

Yes Data Bus — 32-bit wide data bus.

Yes

Tied off to a

resistor

Description

Write Strobe — Defines whether or not the current operation by the DDR SDRAM is to be a read or a write.

Data Bus Mask — Controls the DDR SDRAM data input buffers. Asserting DDRI_WE_N causes the data on DDRI_DQ[31:0] and DDRI_CB[7:0] to be written into the DDR SDRAM devices.

DDRI_DM[4:0] controls this operation on a per-byte basis. DDRI_DM[3:0] are intended to correspond to each byte of a word of data. DDRI_DM[4] is intended to be utilized for the ECC byte of data.

DDR SDRAM Bank Selects — Controls which of the internal DDR SDRAM banks to read or write. DDRI_BA[1:0] are used for all technology types supported.

Address bits 13 through 0 — Indicates the row or column to access depending on the state of DDRI_RAS_N and DDRI_CAS_N.

ECC Bus — Eight-bit error correction code which accompanies the data on DDRI_DQ[31:0].

When ECC is disabled and not being used in a system design, these signals can be left unconnected.

Data Strobes Differential — Strobes that accompany the data to be read or written from the DDR SDRAM devices. Data is sampled on the negative and positive edges of these strobes. DDRI_DQS[3:0] are intended to correspond to each byte of a word of data. DDRI_DQS4] is intended to be utilized for the ECC byte of data.

Clock enables — One clock after DDRI_CKE[1:0] is de-asserted, data is latched on DQ[31:0] and DDRI_CB[7:0]. Burst counters within DDR SDRAM device are not incremented. De-asserting this signal places the DDR SDRAM in self-refresh mode. For normal operation, DDRI_CKE[1:0] must be asserted.

RECEIVE ENABLE OUT must be connected to DDRI_RCVENIN_N signal of the IXP45X/ IXP46X product line and the propagation delay of the trace length must be matched to the clock trace plus the average DQ Traces.

RECEIVE ENABLE IN provides delay information for enabling the input receivers and must be connected to the DDRI_RCVENOUT_N signal IXP46X network processors.

20 Ohm Resistor connected to ground used for process/temperature adjustments.

DDR SDRAM Voltage Reference — is used to supply the reference voltage to the di fferential inputs of the memory controller pins.

of the IXP45X/

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Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—General Hardware

3.2.2 DDR SDRAM Memory Interface

The IXP45X/IXP46X network processors support compatible DDR-266 SDRAM, 8- and 16-bit wide devices, with a total bus width of 32 bits. Only 32-bit-wide accesses are supported.

The maximum supported memory is 1 Gbyte, configured by enabling both physical banks of DDR-266 SDRAM devices. Each bank can be composed of four 1-Gbit (32 Mbit X 8 X 4) devices and use one chip-selects per bank. The minimum supported memory is 32 Mbyte, configured by enabling a single physical bank of DDR-266 SDRAM devices. The bank would consist of two 128-Mbit (2 Mbit X 16 X 4) devices and using a single chip-select.

All supported memory configurations are listed in T able 28 on page 78. Remember that these are all non-buffer devices, as the IXP45X/IXP46X network processors only support non-buffer memory devices.

For a complete description on how the IXP45X/IXP46X network processors interface to DDR SDRAM, see Chapter 7.0, “DDR-SDRAM”.

3.2.3 DDR SDRAM Initialization

For instructions on DDR SDRAM initialization, refer to the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Developer’s Manual and its section titled

“DDR SDRAM Initialization.”

Design Considerations

3.3 Expansion Bus

The Expansion Bus of the IXP45X/IXP46X network processors is specifically designed for compatibility with Intel- and Motorola*-style microprocessor interfaces and Texas Instruments* DSP standard Host-Port Interfaces* (HPI).

The expansion bus controller includes a 25-bit address bus and a 32-bit wide data path, running at a maximum speed of 80 MHz from an external clock oscillator. The bus can be configure to support the following target devices:

• Intel multiplexed • Intel non-multiplexed

•Intel StrataFlash

• Micron* Flow-Through ZBT • Motorola multiplexed

• Motorola non multiplexed • Texas Instruments* Host Port Interface

The expansion bus controller also has an arbiter that supports up to four external devices that can master the expansion bus. External masters can be used to access external slave devices that reside on the expansion bus, including access to internal memory mapped regions within the IXP45X/IXP46X network processors.

All supported modes are seamless and no additional glue logic is required. Other cycle types may be supported by configuring the Timing and Control Register for Chip Select.

Applications having less than 32 data bits may connect to less than the full 32 bits. Devices with wider than 32-bit data bus are not supported. A total of eight chip selects are supported with an address space of up to 32 Mbytes per chip select.

• Synchronous Intel StrataFlash

Memory

(HPI)

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General Hardware Design Considerations—Intel Network Processors

IXP45X and Intel® IXP46X Product Line of

3.3.1 Signal Interface

Table 5. Expansion Bus Signal Recommendations

Name

EX_CLK I No Use series termination resistor, 10Ω to 33Ω at the source. EX_ALE TRI O No Use series termination resistor, 10Ω to 33Ω at the source.

EX_ADDR[24:0] I/O Yes

EX_WR_N I/O No Use series termination resistor, 10Ω to 33Ω at the source. EX_RD_N I/O No Use series termination resistor, 10Ω to 33Ω at the source.

EX_CS_N[7:0] I/O Yes

EX_DATA[31:0] I/O No EX_BE_N[3:0] I/O No EX_IOWAIT_N I Yes Should be pulled high through a 10-KΩ resistor when not being utilized in the system. EX_RDY_N[3:0] I Yes Should be pulled high through a 10-KΩ resistor when not being utilized in the system. EX_PARITY[3:0] I/O No EX_REQ_N[3:1] I Yes Should be pulled high through a 10-KΩ resistor when not being utilized in the system. EX_REQ_GNT_N I Yes Should be pulled high through a 10-KΩ resistor when not being utilized in the system. EX_GNT_N[3:1] O No EX_GNT_REQ_N O No EX_SLAVE_CS_N I Yes Should be pulled high through a 10-KΩ resistor when not being utilized in the system. EX_BURST I Yes Should be pulled high through a 10-KΩ resistor when not being utilized in the system. EX_WAIT_N TRI O No

Input

Output

Pull

Down

Use 4.7-KΩ resistors for pull-downs; required for boot strapping for initial configuration of Configuration Register 0. Pull-ups are not required as for when the system comes out of reset, all bits are initially set HIGH. For more details, see Table 6.

For additional details on address strapping, see the Intel Product Line of Network Processors Developer’s Manual.

Use series termination resistor, 10Ω to 33Ω at the source. Use 10KΩ resistors pull-ups to ensure that the signal remains de-asserted.

Recommendations

IXP45X and Intel® IXP46X

3.3.2 Reset Configuration Straps

At power up or whenever RESET_IN_N is asserted, the Expansion-bus address outputs are switched to inputs and the state of the inputs are captured and stored in Configuration Register 0, bits 24 through 0. This occurs when PLL_LOCKED is deasserted.

The strapping of Expansion-bus address pins can be done by placing external pull-down resistors at the required address pin. It is not required to use external pull-up resistors, by default upon reset all bits on Configuration Register 0 are set High, unless an external pull down is used to set them Low. For example to register a bit low or high in the Configuration Register 0, do the following:

Place an external 4.7-KΩ pull-down resistor to set a bit LOW. No external pull-up is required, by default upon reset, bits are set HIGH. The state of the boot-strapping resistor is register on the first cycle after the

synchronous de-assertion of the reset signal. These bits can be read or written as needed for desired configurations. It is recommended that only Bit 31, Memory Map, be changed from 1 to 0 after execution of boot code from external flash.

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Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—General Hardware

For a complete bit description of Configuration Register 0, see the Intel® IXP45X and

Intel

IXP46X Product Line of Network Processors Developer’s Manual.

Design Considerations

Table 6. Boot/Reset Strapping Configuration (Sheet 1 of 2)

Name Function Description

EX_ADDR[24] (Reserved) (Reserved)

Intel XScale

EX_ADDR[23:21]

EX_ADDR[20:17] Customer Customer-defined bits. (Might be used for board revision.) EX_ADDR[16:11] (Reserved) (Reserved)

EX_ADDR[10] IOWAIT_CS0

EX_ADDR[9] EXP_MEM_DRIVE Refer to table found in EX_ADDR[5].

EX_ADDR[8] USB Clock

EX_ADDR[7] 32_FLASH Refer to table found in EX_ADDR[0]

EX_ADDR[6] EXP_ARB

EX_ADDR[5] EXP_DRIVE

EX_ADDR[4] PCI_CLK

EX_ADDR[3] (Reserved) (Reserved). EX_ADDR[3] must not be pulled down during address strapping.

Processor

Clock Set[2:0]

Allows changing Intel XScale settings. However cannot be used to over-clock core speed.

1 = EX_IOWAIT_N is sampled during the read/write expansion bus cycles for Chip Select 0.

0 = EX_IOWAIT_N is ignored for read and write cycles to Chip select 0 if EXP_TIMING_CS0 is configured to Intel mode.

Typically, IOWAIT_CS0 must be pulled down to Vss when attaching a Synchronous Intel StrataFlash Intel mode and EX_IOWAIT_N is an unknown value for Synchronous Intel StrataFlash.

If the board does not connect the Synchronous Intel StrataFlash WAIT pin to EX_WAIT_N (and the board guarantees EX_IOWAIT_N is pulled up), the value of IOWAIT_CS0 is a don’t-care, since EX_IOWAIT_N will not be asserted.

When EXP_TIMING_CS0 is reconfigure to Intel Synchronous mode during boot-up (for synchronous Intel chips), the expansion bus controller ignores EX_IOWAIT_N during read and write cycles since the WAIT functionality is determined from the EXP_SYNCINTEL_COUNT and EXP_TIMING_CS registers.

Controls the USB clock select. 1 = USB Host/Device clock is generated internally 0 = USB Device clock is generated from GPIO[0]. USB Host clock is generated from GPIO[1]. When generating a spread spectrum

clock on OSC_IN, GPIO[0] can be driven from the system board to generate a 48-MHz clock for the USB Device and GPIO[1] can be driven from the system board to generate a 60-MHz clock for the USB Host.

Configures the Expansion bus arbiter. 0 = External arbiter for Expansion bus. 1 = Expansion bus controller arbiter enabled

Expansion bus low/medium/high drive strength. The drive strength depends on EXP_DRIVE and EXP_MEM_DRIVE configuration bits.

B9. B5

--------------------------------------------------------------------------------------0 . . 0 Reserved 0 . . 1 Medium Drive 1 . . 0 Low Drive 1 . . 1 High Drive

Sets the clock speed of the PCI Interface 0 = 33 MHz 1 = 66 MHz

on Chip Select 0 since the default mode for EXP_TIMING_CS0 is

Processor clock speed. This overrides device fuse

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Intel HDD February 2007 22 Document Number: 305261; Revision: 004

General Hardware Design Considerations—Intel Network Processors

IXP45X and Intel® IXP46X Product Line of

Table 6. Boot/Reset Strapping Configuration (Sheet 2 of 2)

Name Function Description

Enables the PCI Controller Arbiter

EX_ADDR[2] PCI_ARB

EX_ADDR[1] PCI_HOST

EX_ADDR[0] 8/16_FLASH

0 = PCI arbiter disabled 1 = PCI arbiter enabled

Configures the PCI Controller as PCI Bus Host 0 = PCI as non-host 1 = PCI as host

Specifies the data bus width of the FLASH memory device found on Chip Select 0. The data bus is based upon bits 0 and 7 of Configuration Register 0.

32_FLASH 8/16_FLASH Data bus size

B7 . B0

------------------------------------------------------------------------------------0 . . 0 16-bit 0 . . 1 8-bit 1 . . 0 (Reserved) 1 . . 1 32-bit

3.3.3 8-Bit Device Interface

The IXP45X/IXP46X network processors support 8-bit-wide data bus devices (byte mode). For Intel interface cycles, the data lines and control signals can be connected as shown in Figure 3 on page 25 and Figure 4 on page 26. During byte mode accesses, the remaining data signals not being used EX_DAT A[31:8], are driven by the processor to an unpredictable state on WRITE cycles and tri-stated during READ cycles.

When booting an 8-bit flash device, the expansion bus must be configured during reset to the 8-bit mode (see Configuration Register 0). To accomplish this, boot-strapping is required in certain address pins of the Expansion bus. For example, as in this case when booting of an 8-bit flash device, bit 0 and 7 of Configuration Register 0 must be set as follows:

Bit 0 = 1. By default this bit is set high when coming off reset or any time reset is asserted.

Bit 7 = 0. This can be done by placing an external 4.7-KΩ pull-down resistor to pin EX_ADDR[7].

If it is required to change access mode, after the system has booted, and during normal operation; the Timing and Control Register for Chip Select must be configured to perform the desired mode access. For a complete description on accomplishing this refer to the “Expansion Bus” chapter in the Intel Line of Network Processors Developer’s Manual.

3.3.4 16-Bit Device Interface

The IXP45X/IXP46X network processors support 16-bit wide data bus devices (16-bit word mode). For Intel interface cycles, the data lines and control signals can be connected as shown in Figure 3 on page 25 and Figure 4 on page 26. During word mode accesses, the remaining data signals not being used EX_DAT A[31:16], are driven by the processor to an unpredictable state on WRITE cycles and tri-stated during READ cycles.

When booting a 16-bit flash device, the expansion bus must be configured during reset to the 16-bit mode (see Configuration Register 0). To accomplish this, boot-strapping is required in certain address pins of the Expansion bus.

IXP45X and Intel® IXP46X Product

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Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—General Hardware

For example, as in this case when booting of a 16-bit flash device, bit 0 and 7 of Configuration Register 0 must be set as follows:

• Bit 0 = 0. This can be done by placing an external 4.7-KΩ pull-down resistor to pin

EX_ADDR[0].

• Bit 7 = 0. This can be done by placing an external 4.7-KΩ pull-down resistor to pin

EX_ADDR[7].

3.3.5 32-Bit Device Interface

The IXP45X/IXP46X network processors support 32-bit wide data bus devices (32-bit word mode). For Intel interface cycles, the data lines and control signals can be connected as shown in Figure 3 on page 25 and Figure 4 on page 26.

When booting a 32-bit flash device, the expansion bus must be configured during reset to the 32-bit mode (see Configuration Register 0). To accomplish this, boot-strapping is required in certain address pins of the Expansion bus. For example, as in this case when booting of a 32-bit flash device, bit 0 and 7 of Configuration Register 0 must be set as follows:

• Bit 0 = 1. By default this bit is set high when coming off reset or any time reset is asserted.

• Bit 7 = 1. By default this bit is set high when coming off reset or any time reset is asserted.

Design Considerations

IXP45X and Intel® IXP46X Product

Line of Network Processors Developer’s Manual.

IXP45X and Intel® IXP46X Product Line of Network Processors

Intel HDD February 2007 24 Document Number: 305261; Revision: 004

General Hardware Design Considerations—Intel Network Processors

IXP45X and Intel® IXP46X Product Line of

Figure 3. 8/16/32-Bit Device Interface: No Byte-Enable

EX_DAT A[31:0]

Intel® IXP46X

Product Line of

N etwo rk Pro cessor s

EX_ADDR[24:0]

EX_CS_N

EX_RD_N

EX_WR_N

EX_DAT A[31:0]

Intel

IXP46X

Product Line of

Netw or k P r ocesso r s

EX_ADDR[24:0]

EX_CS_N

EX_RD_N

EX_WR_N

EX_DATA[7:0]

EX_ADDR[24:0]

CS OE WR

EX_DAT A[15:0]

EX_ADDR[24:0]

CS OE WR

DATA[7:0]

8-Bit Device

B yte Access

ADDR[24:0]

CS_N OE_N WR_N

DATA[15:0]

16-Bit Device

16 -Bit-Word Access

ADDR[24:0]

CS_N OE_N WR_N

EX_DAT A[31:0]

Intel

IXP46X

Product Line of

Netw or k P r ocesso r s

EX_ADDR[24:0]

EX_CS_N

EX_RD_N

EX_WR_N

February 2007 HDD Document Number: 305261; Revision: 004 25

EX_DAT A[31:0]

DATA[31:0]

32-Bit Device

32 -Bit-Word Access

EX_ADDR[24:0]

CS OE WR

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

ADDR[24:0]

CS_N OE_N WR_N

B4095-002

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—General Hardware

Figure 4. 8/16/32-Bit Device Interface: Byte Enable

Design Considerations

EX_DAT A[31:0]

Intel® IXP46X

Product Line of

N etwo rk Pro cessor s

EX_ADDR[24:0]

EX_CS_N EX_RD_N

EX_BE_N0

EX_DAT A[31:0]

Intel

IXP46X

Product Line of

N etwo rk Pro cessor s

EX_ADDR[24:0]

EX_CS_N

EX_RD_N EX_BE_N0 EX_BE_N1 WR_N1

EX_DAT A[7:0]

EX_ADDR[24:0]

CS OE

WR0

EX_DAT A[15:0]

EX_ADDR[24:0]

OE WR0 WR1

DATA[7:0]

8-Bit Device

Byte Access

ADDR[24:0]

CS_N OE_N WR_N

DATA[15:0]

16-Bit Device

16 -Bi t-Word Access

ADDR[24:0]

CS_N OE_N WR_N0

EX_DAT A[31:0]

Intel

IXP46X

Product Line of

N etwo rk Pro cessor s

EX_ADDR[24:0]

EX_CS_N

EX_RD_N EX_BE_N0 EX_BE_N1 WR_N1 EX_BE_N2 WR_N2 EX_BE_N3 WR_N3

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EX_DAT A[31:0]

EX_ADDR[24:0]

OE WR0 WR1 WR2 WR3

DATA[31:0]

32-Bit Device

32 -Bi t-Word Access

ADDR[24:0]

CS_N OE_N WR_N0

B4096-003

General Hardware Design Considerations—Intel Network Processors

3.3.6 Flash Interface

IXP45X and Intel® IXP46X Product Line of

Figure 5 illustrates how a boot ROM is connected to the expansion bus. The flash (ROM)

used in the block diagram is the Intel StrataFlash 32-Mbyte, 16-bit, flash in the 56-TSOP package. The Intel StrataFlash memory TE28F256J3D is part of the 0.13-micron, 3.3-V Intel StrataFlash memory.

The E28F256J3D supports common flash interface (CFI). For information on migrating from J3 to J3D Intel StrataFlash memory, see the Intel StrataFlash

Embedded Flash Memory (J3 v.D) Conversion Guide - Application Note 835

Intel

(document 308555). For information on migrating from J3 to P30 Intel StrataFlash memory, see the

Migration Guide for Intel StrataFlash Memory (P30 and P33) - Application Note 835 (document 308555).

The example in Figure 5 shows a 16-bit flash memory device connected to the IXP45X/ IXP46X network processors. Boot-strapping is required in the address bus, both EX_ADDR[0] and EX_ADDR[7] need external, 4.7-KΩ pull-down resistors (not shown on diagram). The pull-down resistors sets Bits 0 and 7 low in the Configuration Register

0. This in turn sets the processor into a 16-bit-mode access.

Figure 5. Flash Interface Example

EX_DAT A[31:0]

Intel® IXP46X

Product Line of

Netw or k Pro cessor s

EX_ADDR[24:0]

Memory (J3) to Intel StrataFlash® Embedded

EX_DAT A[15:0]

[

memory device TE28F256J3D —

Memory J3 to

DATA[15:0]

16-Bit Device

16 -Bi t-Wo rd Access

]

ADDR[24:0]

EX_CS_N EX_RD_N

EX_WR_N

4.7 KΩ 4.7 KΩ

CS OE

3.3 V RST#

CE0 OE_N WR_N

Intel® Flash

RP_N

CE1 CE2

BYTE_N

VPEN_N

4. 7 KΩ

B4097- 003

February 2007 HDD Document Number: 305261; Revision: 004 27

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—General Hardware

3.3.7 SRAM Interface

A typical connection between an 8-bit SRAM memory device and the IXP45X/IXP46X network processors expansion bus is shown in Figure 6 on page 28. When attempting to communicate to this device, the Timing and Control Register for Chip Select must be configured for proper access. For more information, see the Intel

Figure 6. Expansion Bus SRAM Interface

IXP46X Product Line of Network Processors Developer’s Manual.

Design Considerations

IXP45X and Intel®

Intel® IXP46X

Product Line of

N etwo rk Pro cesso rs

3.3.8 Design Notes

Care must be taken when loading the bus with too many devices. As more devices are added, the loading capacity adds up — to the point where timing can become critical.

To account for this, timing on the expansion bus may be adjusted in the Timing and Control Register for Chip Select. If an edge rises slowly due to low drive strength, the processors should wait an extra cycle before the value is read. For more information, see the documentation on Timing and Control Register for Chip Select bits [29:16] in the Intel

Manual.

IXP45X and Intel® IXP46X Product Line of Network Processors Developer’s

EX_DATA[31:0]

EX_ADDR[24:0]

EX_CS_N EX_RD_N

EX_WR_N

EX_DATA[7:0]

EX_ADDR[18:0]

CS OE

DATA[7:0]

8-Bit Device

Byte Access

ADDR[18:0]

E# G# W#

512 Kbyte-x-8

SRAM

Inte rfa ce

B 4098-003

3.4 UART Interface

The IXP45X/IXP46X network processors provide two dedicated, Universal Asynchronous Receiver/Transmitter Serial Ports (UARTs). These are high-speed UART s, capable of supporting baud rates from 1,200 Baud to 921.6 KBaud.

The hardware supports a four-wire interface:

• Transmit Data

• Receive Data

•Request to Send

•Clear to Send

IXP45X and Intel® IXP46X Product Line of Network Processors

Intel HDD February 2007 28 Document Number: 305261; Revision: 004

General Hardware Design Considerations—Intel Network Processors

IXP45X and Intel® IXP46X Product Line of

Note: The UART module does not support full modem functionality. However, this can be

implemented, by using GPIO ports to generate DTR, DSR, RI, and DCD and making some changes to the driver.

3.4.1 Signal Interface

Table 7. UART Signal Recommendations

Name

RXDATA0 I Yes

TXDATA0 O No Serial data output Port 0.

CTS0_N I Yes

RTS0_N O No Request-To-Send Port 0.

RXDATA1 I Yes

TXDATA1 O No Serial data output Port 1.

CTS1_N I Yes

RTS1_N O No Request-To-Send Port 1.

Input

Output

Pull

Down

Serial data input Port 0. When signal is not being used in the system, this pin should be pulled high with a 10-KΩ

resistor.

Clear-To-Send Port 0. \When signal is not being used in the system, this pin should be pulled high with a 10-KΩ

resistor.

Serial data input Port 1. When signal is not being used in the system, this pin should be pulled high with a 10-KΩ

resistor.

Clear-To-Send Port 1. When signal is not being used in the system, this pin should be pulled high with a 10-KΩ

resistor.

The following figure contain a typical four signal interface between the UART and an RS-232 transceiver driver, required to interface with external devices. Unused inputs to the RS-232 driver can be connected to ground. This avoids signals floating to undetermined states which can cause over heating of the driver leading to permanent damage.

Recommendations

February 2007 HDD Document Number: 305261; Revision: 004 29

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—General Hardware

Figure 7. UART Interface Example

CTS1_N

RTS1_N

UART

Interface

RXDATA1

TXDATA1

Intel® IXP46X

Product Line of

Netw or k P r ocesso r s

N etwo rk Pro cesso rs

OUT4

IN3

OUT3

OUT1

OUT2

IN2

RS-232

Transceiver

IN1

IN4

DB9

Con nector

Design Considerations

1 DC D

2 RX

3 TX

4 DTR

5 GND

6 DSR

7 RTS

8 CTS

9 RI

3.5 MII/SMII Interface

The IXP45X/IXP46X network processors support a maximum of three Ethernet MACs. Depending on the IXP45X/IXP46X network processors part number used, various combinations can be used. For the various features that can be enable a variety of needs, see the Intel Datasheet.

All MACs contained in the NPEs are compliant to the IEEE 802.3 specification and handle flow control for the IEEE 802.3Q VLAN specification.

The Management Data Interface (MDI) supports a maximum of 32 PHY addresses. MDI signals are required to be connected to every PHY chip. Each PHY port is assign a unique address in the external PHY chip from 0 to 31, totaling a maximum of 32 PHY addresses. The maximum number of MACs supported by the IXP45X/IXP46X network processors is three.

The MII interface supports clock rates of 25 MHz for 100-Mbps operation or 2.5 MHz for 10-Mbps operation.

SMII interface supports clock rate of 125 MHz for 10/100-Mbps operation. General PHY Ethernet devices routing guidelines can be found in Section 5.2.3, “SMII

Signal Considerations” on page 67. For more detailed information, see the IEEE 802.3

specification.

IXP45X and Intel® IXP46X Product Line of Network Processors

B4099 -003

IXP45X and Intel® IXP46X Product Line of Network Processors

Intel HDD February 2007 30 Document Number: 305261; Revision: 004

General Hardware Design Considerations—Intel Network Processors

IXP45X and Intel® IXP46X Product Line of

3.5.1 Signal Interface MII

Table 8. MII NPE A Signal Recommendations

Name

ETHA_TXCLK I Yes

ETHA_TXDATA[3:0] O No Transmit Data. ETHA_TXEN O No Transmit Enable.

ETHA_RXCLK I Yes

ETHA_RXDATA[3:0] I Yes

ETHA_RXDV I Yes

ETHA_COL I Yes

ETHA_CRS I Yes

Notes:

1. Features disabled/enabled by Soft Fuse must be done during the boot-up sequence. A feature cannot be enabled after being disabled without asserting a system reset.

2. Features disabled by a specific part number, do not require pull-ups or pull-downs. Therefore, all pins can be left unconnected.

3. Features enabled by a specific part number — and required to be Soft Fuse-disabled, as stated in Note 1 — only require pull-ups or pull-downs in the clock-input signals.

Input/ Output

Pull

Down

Transmit Clock. When this interface/signal is enabled and is not being used in a system design, the

interface/signal should be pulled high with a 10-KΩ resistor.

Receive Clock. When this interface/signal is enabled and is not being used in a system design, the

interface/signal should be pulled high with a 10-KΩ resistor. Receive Data.

When this interface/signal is enabled and is not being used in a system design, the interface/signal should be pulled high with a 10-KΩ resistor.

Receive Data Valid. When this interface/signal is enabled and is not being used in a system design, the

interface/signal should be pulled high with a 10-KΩ resistor. Collision Detect.

If operating in a full duplex mode and there is no requirement to use the Collision Detect signal, then the pin must be pulled low with a 10-KΩ resistor.

Carrier Sense. When this interface/signal is enabled and is not being used in a system design, the

interface/signal should be pulled high with a 10-KΩ resistor.

Recommendations

Table 9. MII NPE B Signal Recommendations (Sheet 1 of 2)

Name

ETHB_TXCLK I Yes

ETHB_TXDATA[3:0] O No Transmit Data. ETHB_TXEN O No Transmit Enable.

ETHB_RXCLK I Yes

ETHB_RXDATA[3:0] I Yes

ETHB_RXDV I Yes

February 2007 HDD Document Number: 305261; Revision: 004 31

Input/ Output

Pull Up/