Intel IXP43X User Manual

Intel® IXP43X Product Line of Network Processors

Hardware Design Guidelines

April 2007

Document Number: 316844; Revision: 001US

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Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserv ed” or “undefined.” Intel reserves these for fut ure definition and shall ha ve no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information.

The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-

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Hardware Design Guidelines—Intel

IXP43X Product Line of Network Processors

1.0 Introduction..............................................................................................................9

1.1 Content Overview................................................................................................9

1.2 Related Documentation...................................................................................... 10

1.3 Acronyms.........................................................................................................10

1.4 Overview .........................................................................................................11

1.5 Typical Applications ...........................................................................................14

2.0 System Architecture ................................................................................................15

2.1 System Architecture Description..........................................................................15

2.2 System Memory Map .........................................................................................15

3.0 General Hardware Design Considerations................................................................17

3.1 Soft Fusible Features ......................................................................................... 17

3.2 DDRII/I SDRAM Interface................................................................................... 18

3.2.1 Signal Interface .......................... .. .. .................................. .. .. .................19

3.2.2 DDRII/I SDRAM Initialization ...................................................................20

3.3 Expansion Bus ..................................................................................................21

3.3.1 Signal Interface .......................... .. .. .................................. .. .. .................21

3.3.2 Reset Configuration Straps .................................................................. .... 22

3.3.3 8-Bit Device Interface.............................................................................24

3.3.4 16-Bit Device Interface ...........................................................................25

3.3.5 Flash Interface.......................................................................................26

3.4 UART Interface .................................................................................................26

3.4.1 Signal Interface .......................... .. .. .................................. .. .. .................27

3.5 MII Interface .................................................................................................... 28

3.5.1 Signal Interface MII........................................ .. .................................. .. ..29

3.5.2 Device Connection, MII ............................... .. .. .................................... .... 30

3.6 GPIO Interface..................................................................................................31

3.6.1 Signal Interface .......................... .. .. .................................. .. .. .................32

3.6.2 Design Notes .........................................................................................32

3.7 USB Interface.................................. .. .................................. .............................32

3.7.1 Signal Interface .......................... .. .. .................................. .. .. .................33

3.8 UTOPIA Level 2 Interface ................................................................................... 36

3.8.1 Signal Interface .......................... .. .. .................................. .. .. .................36

3.8.2 Device Connection.................................... .. .. .................................. .. .. .... 40

3.9 HSS Interface................................................................................................... 40

3.9.1 Signal Interface .......................... .. .. .................................. .. .. .................41

3.9.2 Device Connection.................................... .. .. .................................. .. .. .... 41

3.10 SSP Interface ...................................................................................................42

3.10.1 Signal Interface ............................................. .................................. .. .. ..43

3.10.2 Device Connection........................................................... .. .. ...................43

3.11 PCI Interface ....................................................................................................44

3.11.1 Signal Interface ............................................. .................................. .. .. ..45

3.11.2 PCI Interface Block Diagram.................................................................... 46

3.11.3 PCI Option Interface...............................................................................47

3.11.4 Design Notes.........................................................................................49

3.12 JTAG Interface..................................................................................................49

3.12.1 Signal Interface ............................................. .................................. .. .. ..50

3.13 Input System Clock ...........................................................................................50

3.13.1 Clock Signals......................................................................................... 50

3.13.2 Clock Oscillator ...................................................................................... 50

3.13.3 Recommendations for Crystal Selection..................................................... 51

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Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

3.14 Power ..............................................................................................................52

3.14.1 Decoupling Capacitance Recommendations.................................................53

3.14.2 VCC Decoupling......................................................................................53

3.14.3 VCC33 Decoupling .................................. ................................. ... ............53

3.14.4 VCCDDR Decoupling................................................................................53

3.14.5 Power Sequence............................................. .................................. ......53

3.14.6 Reset Timing..........................................................................................53

4.0 General PCB Guide...................................................................................................55

4.1 PCB Overview ...................................................................................................55

4.2 General Recommendations..................................................................................55

4.3 Component Selection .........................................................................................55

4.4 Component Placement........................................................................................55

4.5 Stack-Up Selection........................................................... ... .. .............................56

5.0 General Layout and Routing Guide ...........................................................................59

5.1 Overview..........................................................................................................59

5.2 General Layout Guidelines...................................................................................59

5.2.1 General Component Spacing ....................................................................60

5.2.2 Clock Signal Considerations......................................................................62

5.2.3 MII Signal Considerations ........................................................................63

5.2.4 USB V2.0 Considerations .........................................................................63

5.2.5 Crosstalk ...............................................................................................63

5.2.6 EMI Design Considerations............................................ .. .. .......................64

5.2.7 Trace Impedance....................................................................................64

5.2.8 Power and Ground Plane..........................................................................64

6.0 PCI Interface Design Considerations........................................................................66

6.1 Electrical Interface............................................. .. .. .................................. .. .. .. ....66

6.2 Topology ..........................................................................................................66

6.3 Clock Distribution ................................................ .................................. .. .. ........67

6.3.1 Trace Length Limits.................................................................................68

6.3.2 Routing Guidelines..................... .. .. .................................. .. .....................69

6.3.3 Signal Loading........................................................................................69

7.0 DDRII / DDRI SDRAM ..............................................................................................70

7.1 Introduction......................................................................................................70

7.2 DDRII/DDRI RCOMP and Slew Resistances Pin Requirements...................................74

7.3 DDRII OCD Pin Requirements..............................................................................75

7.3.1 Signal-Timing Analysis .................................. .. .................................. .. .. ..75

7.3.2 Timing Relationships ...............................................................................78

7.3.3 Routing Guidelines..................... .. .. .................................. .. .....................81

7.3.3.1 Clock Group..............................................................................81

7.3.3.2 Data and Control Groups............................................................82

7.3.3.3 Command Groups .....................................................................84

Figures

1Intel® IXP435 Network Processor Block Diagram ................................ .... .... .... ..............13

2Example: Intel

3 8/16-Bit Device Interface ..........................................................................................25

4 Flash Interface Example............................................................................................26

5 UART Interface Example............................................................................................28

6 MII Interface Example...............................................................................................31

7 Common Mode Choke ................................ .. .. .................................. .........................34

8 USB RCOMP and ICOMP Pin Requirement.....................................................................35

9 USB Host Down Stream Interface Example................... .. .. .. .................................... .. .. ..35

10 UTOPIA Interface Example.........................................................................................40

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Hardware Design Guidelines—Intel

IXP43X Product Line of Network Processors

11 HSS Interface Example........................ .. .................................. .. ...............................42

12 Serial Flash and SSP Port (SPI) Interface Example........................................................44

13 PCI Interface...........................................................................................................47

14 Clock Oscillator Interface Example.............................................................................. 51

15 Recommended circuit design on PCB for crystal oscillator .............................................. 52

16 Component Placement on a PCB.................................................................................56

17 8-Layer Stackup ...................................................................................................... 58

18 6-Layer Stackup ...................................................................................................... 58

19 Signal Changing Reference Planes..............................................................................60

20 Good Design Practice for VIA Hole Placement...............................................................61

21 Poor Design Practice for VIA Placement.......................................................................61

22 Pad-to-Pad Clearance of Passive Components to a PGA or BGA.......................................62

23 PCI Address/Data Topology.......................................................................................67

24 PCI Clock Topology ..................................................................................................68

25 Processor-DDRII/I SDRAM Interface...........................................................................72

26 DDRII/DDRI RCOMP Pin External Resistor Requirements ...............................................74

27 DDRII OCD Pin Requirements....................................................................................75

28 DDR Clock Timing Waveform.....................................................................................75

29 DDR SDRAM Write Timings........................................................................................ 76

30 DDR SDRAM Read Timings ........................................................................................76

31 DDR - Write Preamble/Postamble Duration..................................................................77

32 DDRII Clock Simulation Results: CK Signals.................................................................82

33 DDRII Data and Control Simulation Results: DQ and DQS signals ................................... 83

34 DDRII Command Simulation Results: ADDRESS signals.................................................84

Tables

1 List of Acronyms and Abbreviations ................................................. .. .. .......................10

2 Signal Type Definitions .............................................................................................17

3 Soft Fusible Features................................................................................................17

4 DDRII/I SDRAM Interface Pin Description.................................................................... 19

5 Expansion Bus Signal Recommendations.....................................................................21

6 Boot/Reset Strapping Configuration............................................................................22

7 Setting Intel XScale

8 UART Signal Recommendations.............................................. ....................................27

9 MII NPE A Signal Recommendations ....................................... ... .................................29

10 MII NPE C Signal Recommendations ..................................... .. ....................................29

11 MAC Management Signal Recommendations NPE A and NPE C........................................30

12 GPIO Signal Recommendations.......................................... .................................... .. ..32

13 USB Host Signal Recommendations............................................................................ 33

14 UTOPIA Level 2/MII_A..............................................................................................36

15 High-Speed, Serial Interface 0 ................................................................................... 41

16 Synchronous Serial Peripheral Port Interface................................................................ 43

17 PCI Controller..........................................................................................................45

18 PCI Host/Option Interface Pin Description....................................................................47

19 Synchronous Serial Peripheral Port Interface................................................................ 50

20 Clock Signals...........................................................................................................50

21 Power Supply ..........................................................................................................52

22 PCI Address/Data Routing Guidelines..........................................................................67

23 PCI Clock Routing Guidelines.....................................................................................68

24 DDRII/I Signal Groups..............................................................................................71

25 Supported DDRI 32-bit SDRAM Configurations.............................................................73

26 Supported DDRII 32-bit SDRAM Configurations.................................................. .. .. .. .... 73

27 Supported DDRI 16-bit SDRAM Configurations.............................................................73

28 Supported DDRII 16-bit SDRAM Configurations.................................................. .. .. .. .... 74

Processor Operation Speed.........................................................24

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29 DDR Clock Timings ...................................................................................................75

30 DDRII-400 MHz Interface -- Signal Timings..................................................................77

31 DDR II/I SDRAM Interface -- Signal Timings.................................................................78

32 Timing Relationships.................................................................................................79

33 Signal Package Lengths............................ .. .................................. .............................79

34 Clock Signal Group Routing Guidelines ........................................................................82

35 DDRII Data and Control Signal Group Routing Guidelines...............................................83

36 DDRII Command Signal Group Routing Guidelines ........................................................84

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IXP43X Product Line of Network Processors

Revision History

Date Revision Description

April 2007 001 Initial release

§ §

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Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

IXP43X Product Line of Network Processors

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Hardware Design Guidelines—Intel

IXP43X Product Line of Network Processors

1.0 Introduction

This design guide provides recommendations for hardware and system designers who are developing with the Intel document should be used in conjunction with the Intel Network Processors Datasheet and sample schematics provided for the Intel

IXP43X Product Line of Network Processors. This

IXP43X Product Line of

IXP435

Multi-Service Residential Gateway Reference Platform. Design recommendations are necessary to meet the timing and signal quality

specifications. The guidelines recommended in this document are based on experience and simulation work done at Intel while developing the Intel® IXP435 Multi-Service Residential Gateway Reference Platform. These recommendations are subject to change.

Note: This document discusses all features supported on the IXP43X product line of network

processors. A subset of these features is supported by certain processors in the IXP43X network processors, such as the Intel

IXP432 Network Processor. Refer to the Intel® IXP43X Product Line of Network Processors Datasheet for detailed information on various features listed by processor.

1.1 Content Overview

Chapter Name Description

Chapter 1.0, “Introduction” Conventions used in this manual and related documentation Chapter 2.0, “System Architecture” System architectural block diagram and system memory map Chapter 3.0, “General Hardware Design

Considerations” Chapter 4.0, “General PCB Guide” General PCB design practice and layer stack-up description Chapter 5.0, “General Layout and Routing

Guide” Chapter 6.0, “PCI Interface Design

Considerations”

Chapter 7.0, “DDRII / DDRI SDRAM”

Graphical representation of most common peripheral interfaces

More specific layout and routing recommendations for board designers

Board-design recommendations when implementing PCI interface

Board-design recommendations when implementing DDRII/I memory interface

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1.2 Related Documentation

The reader of this design guide should also be familiar with the material and concept presented in the following documents:

Title Document #

Intel

IXP43X Product Line of Network Processors Datasheet 316842

Intel

IXP43X Product Line of Network Processors Developer’s

Manual

IXP43X Product Line of Network Processors: Migrating from

Intel the Intel

Intel Intel Intel

Intel StrataFlash

Intel XScale

Double Data Rate (DDR) SDRAM Specification, 2004; JEDEC Solid State Technology Association

IEEE 802.3 Specification

PCI Local Bus Specification, Rev. 2.2 Universal Serial Bus Specification, Revision 2.0 UTOPIA Level 2 Specification, Revision 1.0

IXP42X Product Line

IXP400 Software Programmer’s Guide 252539

IXP400 Software Specification Update 273795

XScale™ Core Developer’s Manual 273473

Embedded Memory (P30) Application Note __

Microarchitecture Technical Summary —

316843

316845

JESD79D

N/A

1.3 Acronyms

Table 1 lists the acronyms and abbreviations used in this guide.

Table 1. List of Acronyms and Abbreviations (Sheet 1 of 2)

Term Explanation

AHB Advanced High-Performance Bus APB Advanced Peripheral Bus ATM Asynchronous Transfer Mode DDR Double Data Rate EMI Electro-Magnetic Interference GPIO General Purpose Input/Output HSS High Speed Serial IP Internet Protocol ISA Instruction Set Architecture LAN Local Area Network MII Media-Independent Interface NPE Network Processor Engine PCB Printed Circuit Board PCI Peripheral Component Interface PHY Physical Layer Interface PLL Phase-Locked Loop

IXP43X Product Line of Network Processors

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IXP43X Product Line of Network Processors

Table 1. List of Acronyms and Abbreviations (Sheet 2 of 2)

Term Explanation

PMU Performance Monitoring Unit SME Small-to-Medium Enterprise SSP Synchronous Serial Protocol UART Universal Asynchronous Receiver-Transmitter USB Universal Serial Bus VTT Termination Voltage Supply

1.4 Overview

The Intel® IXP43X Product Line of Network Processors is a highly integrated device, capable of interfacing with most common industry standard peripherals, required for high-performance control applications.

Note: This document discusses all features supported on the IXP43X network processors.

Refer to the Intel

IXP43X Product Line of Network Processors Datasheet for details on

feature support listed by processor. Some of the key features of the IXP43X network processors, when used as a

single-chip solution for embedded applications are as follows:

•Intel XScale® Processor (compliant with Intel® StrongARM* architecture) up to 667 MHz

• 32-bit PCI interface Master/Target 33 MHz

• Two Universal Serial Bus (USB) V2.0 Host Controller

• DDRI-266 SDRAM or DDRII-400 SDRAM—

— Support for 16 MB, minimum for DDR II/I, 32 MB minimum for DDRII-400;

1 GB, maximum for DDR II/I, 512 MBs maximum for DDRII-400

— User-enabled ECC.

• 16bit Data / 24bit Address Expansion Bus Interface

•One UART interface

•Two NPEs

•UTOPIA Level 2 Interface

• Synchronous Serial Port Interface (SSP)

• One High-Speed Serial Port Interfaces (HSS)

• Network interfaces that can be configured in the following manner:

Note 1

— Two MII interfaces — One MII interface + 1 UTOPIA Level 2 interface

• MII interfaces are:

Note 1

— 802.3 MII interfaces — Single MDIO interface to control the MII interfaces

• UTOPIA Level 2 Interface is :

Note 1

— Eight-bit interface — Up to 33-MHz clock speed — Five transmit and five receive address lines

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Note:

Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

• 16 GPIO (General Purpose Input Output)

•Packaging —460-pin PBGA — 31 mm by 31 mm — Commercial temperature (0° to 70° C) — Lead free support

Refer to the Intel

IXP43X Product Line of Network Processors Datasheet for complete

feature list and block diagram description.

1. This feature requires Intel-supplied software. T o determine if this feature is enabled in a particular software release, refer to the Intel

IXP400 Software Programmer’s

Guide.

A block diagram of all major internal hardware components of IXP43X network processors is shown in Figure 1. The illustration also shows how the components interface with each other through the various bus interfaces such as the North AHB, South AHB, and APB.

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IXP43X Product Line of Network Processors

Figure 1. Intel® IXP435 Network Processor Block Diagram

HSS

UTOPIA 2/ MII

NPE A

16 GPIO

SSP

High Speed

UART

921 Kbaud

GPIO

Interrupt

Controller

IBPMU

Timers

MII

APB 6 6. 66MHz x 32 bi ts

AHB

Slave /

APB

Master

BRIDGE

CONTROLLER

USB Port

HOST

VERSION 2.0

UTMI

2. 0 P HY

NPE C

AES/ 3DES/

DES/

SHA/ MD -5

North AHB 133. 32 MHz x 32 bits

North AHB

Queue Status Bus

QUEUE

MANAGER

South AHB 133.32 MHz x 32 bits

South AHB

USB Port

HOST

CONTROLLER

VERSION 2.0

UTMI

2.0 PHY

EXPANSION

BUS Controller

8/16 bit 80 MHz

Arbiter

AHB/ AHB

BRIDGE

PCI

CONTROLLER

32 bit 33 MHz

DDRII/ I MEMORY

CONTROLLER

UNIT

266/ 400

MPI

64 bits

/200MHzx

133.32MH

XScale Processor

32 KB I - CACHE

32 KB D - CACHE 2KB MINI D- CACHE 266/400/533/667 MHz

16/ 32 BITS

+ ECC DDR 266 / DDRII 400

Master on South AHB

Master on North AHB

Bus Arbiters

Slave Only

AHB Slave/APB Master

Note: Figure 1 shows the Intel® IXP435 Network Processor. For details on feature and SKU

support listed by processor, see the Intel

IXP43X Product Line of Network Processors

Datasheet.

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Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

1.5 Typical Applications

• SOHO-Small Business/Residential

• Modular Router

• Wireless Gateway(802.11a/b/g)

• Network-Attached Storage

• Wired/Wireless RFID Readers

• Digital Media Adapter

• Digital Media Player

•VoIP Router

•Video Phone

• Secure Gateway/Router

•Network Printer

• Wireless Media Gateway

• IP Set Top box

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2.0 System Architecture

2.1 System Architecture Description

The Intel® IXP43X Product Line of Network Processors is a multifunction processor that integrates the Intel XScale

Processor (ARM* architecture compliant) with highly

integrated peripheral controllers and network processor engines. The processor is a highly integrated design, manufactured with Intel’s 0.13-µm

production semiconductor process technology. This process technology, along with numerous, dedicated function peripheral interfaces and many features with the Intel XScale processor, addresses the needs of many system applications and helps reduce system costs. The processors can be configured to meet many system application and implementation needs.

Figure 2 illustrates one of the many applications for which the IXP43X network

processors can be implemented. For detailed functional description, see the Intel IXP43X Product Line of Network Processors Developer’s Manual.

2.2 System Memory Map

Refer to the Intel® IXP43X Product Line of Network Processors Developer’s Manual for a complete memory map and register description of each individual module.

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Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

Figure 2. Example: Intel® IXP43X Product Line of Network Processors System Block

Diagram

JTAG

Header

DDR

SDRAM

16Mx4x16

DDRII/I

16Mx4x16

512 Mbyte

SDRAM

512 Mbyte

(Four Chips)

Max 1 Gbyte

(Four Chips)

SLIC/CODEC or

T1/E1/J1 FramerHSS 0

A/D

Configuration

Reset Logic

LCD/LED

Diagnostics

Display

Flash

32 Mbyte

Board

Buff

CS_N0

D[1 5: 0]

A[23:0]

Memory Bus

Expansion Bus

Intel® IXP 43X Product

Line of Network

Processors

DDRII/I SDRAM

RAS, CAS, WE, CS,CLK

SSP

SSP CODEC or

CB[7:0]

D[31:0] BA[1:0]

A[13:0]

DB9

RJ45

Port 0

RJ45

Port 1

RS 232

Serial Port 0

10/100

PHYs

Up to 2 Ports

USB Host Connector

USB Host

Connector

2-MII

USB v2.0

PCI Bus

Transparent PCI Bridge

cPCI Bus

cPC I J2

cPC I J1

UTOPIA Level 2

PCI Slots

Ethernet

Clocks

Clock Buff er

5 V

3.3 V

2.5/1.8 V

1.3 V

PCI

Clock

xDSL

PLL

Power Supply

OSC

B4835 -003

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IXP43X Product Line of Network Processors

3.0 General Hardware Design Considerations

This chapter contains information for implementing and interfacing with major hardware blocks of the Intel

IXP43X Product Line of Network Processors. Such blocks include DDRII/I SDRAM, Flash, Ethernet PHYs, UART and other peripherals interfaces. Signal definition tables list resistor recommendations for pull-ups and pull-downs.

Features disabled by a specific part number, do not require pull-ups or pull-downs. Therefore, all pins can be left unconnected. Features enabled by a specific part number and required to be Soft Fuse-disabled, only require pull-ups or pull-downs in the clock-input signals. Other conditions can require pull-up or pull-down resistors for configuration purposes at power on or reset. In the same way, open-drain outputs must be pulled high.

Warning: With the exception of USB_V5REF all other I/O pins of the IXP43X network processors

are not 5.0-V tolerant.

Table 2 gives the legend for interpreting the Type field used in the signal-definition

tables that are covered in this chapter.

Table 2. Signal Type Definitions

Symbol Description

I Input pin only O Output pin only I/O Pin can be an input or output OD Open-drain pin TRI Tri-State pin PWR Power pin GND Ground pin

3.1 Soft Fusible Features

Soft Fuse Enable/Disable is a method to enable or disable features in hardware, virtually disconnecting the hardware modules from the processor.

Some of the features offered in the IXP43X product line of network processors can be Soft Fuse Enabled/Disabled during boot. It is recommended that if a feature is not used in the design, the feature be soft disabled. This helps reduce power and maintain the part running at a cooler temperature. When Soft Fuse Disabled, a pull-up resistor must be connected to each clock input pins of the disabled feature interface. All other signals can be left unconnected.

Soft Fuse Enable/Disable can be done by writing to EXP_UNIT_FUSE_RESET register. For more information refer to the Intel Developer’s Manual and review the register description.

Table 3. Soft Fusible Features (Sheet 1 of 2)

Name Description

PCI The complete bus must be enabled or disable. HSS0 Can only be disable as a pair.

UTOPIA

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while enabling UTOPIA, MACs on NPE A is disabled. while enabling MACs on NPE A, UTOPIA is disabled.

IXP43X Product Line of Network Processors

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Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

Table 3. Soft Fusible Features (Sheet 2 of 2)

Name Description

ETHERNET Can enable MII MACs. Enable of MACs can be separately done per each NPE. USB Host Each USB can be Enable separately. DDR ECC ECC can be enabled or disabled separately from the rest of the DDR interface.

3.2 DDRII/I SDRAM Interface

The IXP43X network processors support unbuffered, DDRI-266 or DDRII-400 SDRAM technology, capable of addressing two memory banks (one bank per CS). Each bank can be configured to support 32/64/128/256/512-Mbyte for a total combined memory support of 1 Gbyte.

The IXP43X network processors integrate a high-performance, multi-ported Memory Controller Unit (MCU) to provide a direct interface with its local memory subsystem. The MCU supports:

• DDR II/I or DDRII-400 SDRAM

• 128/256/512-Mbit, 1-Gbit DDRI SDRAM technology support

• Supports 256/512-Mbit technologies for the DDRII-400

• Only unbuffered DRAM support (No registered DRAM support)

• Dedicated port for Intel XScale processor to the DDRII/DDRI SDRAM

• Between 32 MBs and 1-GB of 32-bit DDRI SDRAM

• Between 64MBs and 512 MBs of 32-bit DDRII SDRAM

• 16MB for 16-bit memory systems for DDRI SDRAM (non-ECC) supporting 128-Mbit technology only

• 32MB for 16-bit memory systems for DDRII SDRAM (non-ECC) supporting 256-Mbit technology only

• Single-bit error correction, multi-bit detection support (ECC)

• 32-bit, 40-bit wide memory interfaces (non-ECC and ECC support), and 16-bit wide memory interfaces (non-ECC)

The DDRII/DDRI SDRAM interface provides a direct connection to a high-bandwidth and reliable memory subsystem. The DDRII/DDRI SDRAM interface is a 16 or 32-bit-wide data path.

The device supports non-ECC and ECC for error correction, which can be enable or disable by software as required. Banks have a bus width of 32 bits for non ECC or 40 bits for ECC enable (32-bit data + 8-bit ECC).

An 8-bit Error Correction Code (ECC) across each 32-bit word improves system reliability. It is important to note that ECC is also referred to as CB in many DIMM specifications. The pins on the IXP43X network processors are called DDR_CB[7:0]. ECC is only implemented in the 32-bit mode of operation, while the algorithm used to generate the 8-bit ECC is implemented over 64-bit.

The ECC circuitry is designed to operate always on a 64-bit data and when operating in 32-bit mode, the upper 32 bits are driven to zeros internally. To summarize the impact to the customer, the full 8 bits of ECC is stored and read from a memory array for the ECC logic to work. An 8-bit-wide memory is used when implementing ECC.

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Hardware Design Guidelines—Intel

IXP43X Product Line of Network Processors

The memory controller only corrects single bit ECC errors on read cycles. The ECC is stored into the DDRII/DDRI SDRAM array along with the data and is checked when the data is read. If the code is incorrect, the MCU corrects the data before reaching the initiator of the read. ECC error scrubbing is done with software. User-defined fault correction software is responsible for The value written back into the memory location contains the 32-bit word with the modified byte and the new ECC value.

Refer to the Intel

IXP43X Product Line of Network Processors Datasheet for a detailed

list of features. General DDRII/I SDRAM routing guidelines can be found in Section 7.3.3, “Routing

Guidelines” on page 82. For more detailed information, see the PC266 and PC400 DDR

SDRAM specification.

3.2.1 Signal Interface

Table 4. DDRII/I SDRAM Interface Pin Description (Sheet 1 of 2)

Name

D_CK[2:0] / DDR_CK[2:0]

D_CK_N[2:0] / DDR_CK_N[2:0]

D_CS_N[1:0] / C_CS_N[1:0]

D_RAS_N / DDR_RAS_N

D_CAS_N / DDR_CAS_N

D_WE_N / DDR_WE_N O

D_DM[4:0] / DDR_DM[4:0]

D_BA[1:0] / DDR_BA[1:0]

D_MA[13:0] / DDR_MA[13:0]

D_DQ[31:0] / DDR_DQ[31:0]

Type Field

I/O

Device-Pin Connection

Connect a pair of differential clock signals to every device; When

using both banks, daisy chain devices with same data bit sequence.

O Same as above No

Use the same CS to control 32-bit

data + 8-bit ECC, per bank

The RAS signal must be connected

to each device in a daisy chain manner

The CAS signal must be connected

to each device in a daisy chain manner

The WE signal must be connected to each device in a daisy chain manner

Connect to each DM device pin. For the 8-bit devices connect one DM signal per device.

For the 16-bit devices connect two DM signal per device (depending on how many data bits are being used).

The BA signals must be connected

to each device in a daisy chain manner.

All address signals must be

connected to each device in a daisy chain manner.

Must be connected in parallel to achieve a 32-bit bus width.

VTT

Terminatio

Yes

Yes Data Bus — 32-bit wide data bus.

DDRII/I SDRAM Clock Out — Provides the positive differential clocks to the external SDRAM memory subsystem.

DDRII/I SDRAM Clock Out — Provides the negative differential clocks to the external SDRAM memory subsystem.

Chip Select — Must be asserted for all transactions to the DDRII/I SDRAM device. One per bank.

Row Address Strobe — Indicates that the current address on D_MA[13:0] / DDR_MA[13:0] is the row.

Column Address Strobe — Indicates that the current address on D_MA[13:0] / DDR_MA[13:0] is the column.

Write Strobe — Defines whether or not the current operation by the DDRII/I SDRAM is to be a read or a write.

Data Bus Mask — Controls the DDRII/I SDRAM data input buffers. Asserting D_WE_N/ DDR_WE_N causes the data on D_DQ[31:0]/ DDR_DQ[31:0] and D_CB[7:0]/DDR_CB[7:0] to be written into the DDRII/I SDRAM devices.

D_DM[4:0]/DDR_DM[4:0] controls this operation on a per-byte basis. D_DM[3:0]/ DDR_DM[3:0] are intended to correspond to each byte of a word of data. D/DM[4]/ DDR_DM[4] is intended to be utilized for the ECC byte of data.

DDRII/I SDRAM Bank Selects — Controls which of the internal DDRII/I SDRAM banks to read or write. D_BA[1:0]/DDR_BA[1:0] are used for all technology types supported.

Address bits 13 through 0 — Indicates the row or column to access depending on the state of D_RAS_N/DDR_RAS_N and D_CAS_N/ DDR_CAS_N.

Description

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Table 4. DDRII/I SDRAM Interface Pin Description (Sheet 2 of 2)

Name

D_CB[7:0] / DDR_CB[7:0]

D_DQS[4:0] / DDR_DQS[4:0]

D_CKE[1:0] / DDR_CKE[1:0]

D_ODT[1:0]

D_RES[2:1] Refer to Figure 27

D_SLWCRES Refer to Figure 27

D_IMPCRES Refer to Figure 27

D_CRES0 O Tied off to a resistor

D_VREF / DDR_VREF I VCCDDR/2 VCCDDR/2

Type Field

I/O Connect to ECC memory devices. Yes

I/O

Device-Pin Connection

Connect DQS[3:0] to devices with data signals and DQS[4] to devices with ECC signals.

Use one CKE per bank, never mix the CKE on the same bank. Use CKE[0] for bank0 and CKE[1] for bank1

VTT

Terminatio

Yes

Tied off to a

resistor

Description

ECC Bus — Eight-bit error correction code which accompanies the data on D_DQ[31:0]/ DDR_DQ[31:0].

When ECC is disabled and not being used in a system design, these signals can be left unconnected.

Data Strobes Differential — Strobes that accompany the data to be read or written from the DDRII/I SDRAM devices. Data is sampled on the negative and positive edges of these strobes. D_DQS[3:0]/DDR_DQS[3:0] are intended to correspond to each byte of a word of data. D_DQS[4]/DDR_DQS[4] is intended to be utilized for the ECC byte of data.

Clock enables — One clock after D_CKE[1:0]/ DDR_CKE[1:0] is de-asserted, data is latched on D_DQ[31:0]/DDR_DQ[31:0] and D_CB[7:0]/DDR_CB[7:0]. Burst counters within DDRII/I SDRAM device are not incremented. De-asserting this signal places the DDRII/I SDRAM in self-refresh mode. For normal operation, D_CKE[1:0]/DDR_CKE[1:0] must be asserted.

On Die Termination Control — Turns on DDR II SDRAM termination during writes.

Compensation for DDR OCD (analog) DDRII mode only. This function is not enable and special connection is required.

Compensation Voltage Reference (analog) for DDR driver slew rate control connected through a resistor to D_CRES0.

Compensation Voltage Reference (analog) for DDR driver impedance control connected

through a resistor to D_CRES0. Analog VSS Ref Pin (analog) both D_SLWCRES

and D_IMPCRES signals connect to this pin through a reference resistor. For DDRII/I respectively:

- 285 / 387Ohm Resistor connected to DDR_IMPCRES used for process and temperature adjustments.

- 825 / 845Ohm Resistor connected to DDR_SLWCRES used for process and temperature adjustments.

DDRII/IDDRII/I SDRAM Voltage Reference — is used to supply the reference voltage to the differential inputs of the memory controller pins.

3.2.2 DDRII/I SDRAM Initialization

For instructions on DDRII/I SDRAM initialization, refer to DDR SDRAM Initialization subsection in the Memory Controller chapter of the Intel Network Processors Developer’s Manual.

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IXP43X Product Line of

Hardware Design Guidelines—Intel

IXP43X Product Line of Network Processors

3.3 Expansion Bus

The Expansion Bus of the IXP43X network processors is specifically designed for compatibility with Intel-and Motorola* style microprocessor interfaces.

The expansion bus controller includes a 24-bit address bus and a 16-bit wide data path, running at a maximum speed of 80 MHz from an external clock oscillator. The bus can be configure to support the following target devices:

• Intel multiplexed • Intel non-multiplexed

•Intel StrataFlash

• Motorola non multiplexed • Motorola multiplexed

The expansion bus controller also has an arbiter that supports up to four external devices that can master the expansion bus. External masters can be used to access external slave devices that reside on the expansion bus, including access to internal memory mapped regions within the IXP43X network processors.

All supported modes are seamless and no additional glue logic is required. Other cycle types can be supported by configuring the Timing and Control Register for Chip Select.

The expansion interface functions support 8-bit or 16-bit data operation and allows an address range of 512 bytes to 16 MBs, using 24 address lines for each of the four independent chip selects.

• Synchronous Intel StrataFlash

Memory

Access to the expansion-bus interface is completed in five phases. Each of the five phases can be lengthened or shortened by setting various configuration registers on a per-chip-select basis. This feature allows the IXP43X network processors to connect to a wide variety of peripheral devices with varying speeds.The expansion interface supports Intel or Motorola* microprocessor style bus cycles. The bus cycles can be configured to be multiplexed address/data cycles or separate address/data cycles for each of the four chip-selects.

The expansion interface is an asynchronous interface to externally connected chips. A clock is supplied to the IXP43X network processors expansion interface for the interface to operate. This clock can be driven from GPIO 15 or an external source. Devices on the expansion bus can be clocked by an external clock at a rate of up to 80 MHz. If GPIO 15 is used as the clock source, the Expansion Bus interface can only be clocked at a maximum of 33.33 MHz. GPIO 15’s maximum clock rate is 33.33 MHz.

3.3.1 Signal Interface

Table 5. Expansion Bus Signal Recommendations (Sheet 1 of 2)

Name

EX_CLK I No Use series termination resistor, 10Ω to 33Ω at the source. EX_ALE TRI O No Use series termination resistor, 10Ω to 33Ω at the source.

EX_ADDR[23:0] I/O Yes

EX_WR_N I/O No Use series termination resistor, 10Ω to 33Ω at the source. EX_RD_N I/O No Use series termination resistor, 10Ω to 33Ω at the source.

Type Field

Pull

Down

Use 470Ω resistors for pull-downs; required for boot strapping for initial configuration of Configuration Register 0. Pull-ups are not required as for when the system comes out of reset, all bits are initially set HIGH. For more details, see Table 6.

For additional details on address strapping, see the Intel Processors Developer’s Manual.

Recommendations

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Table 5. Expansion Bus Signal Recommendations (Sheet 2 of 2)

Name

EX_CS_N[3:0] I/O Yes

EX_DATA[15:0] I/O No Expansion-bus, bidirectional data. EX_IOWAIT_N I Yes Should be pulled high through a 10-KΩ resistor when not being utilized in the system.

Type Field

Pull

Down

Use series termination resistor, 10Ω to 33Ω at the source. Use 10KΩ resistors pull-ups to ensure that the signal remains de-asserted.

Recommendations

3.3.2 Reset Configuration Straps

At power up or whenever RESET_IN_N is asserted, the Expansion-bus address outputs are switched to inputs and the state of the inputs are captured and stored in Configuration Register 0, bits 23 through 0. This occurs when PLL_LOCKED is deasserted.

The strapping of Expansion-bus address pins can be done by placing external pull-down resistors at the required address pin. It is not required to use external pull-up resistors, by default upon reset all bits on Configuration R egister 0 are set High, unless an external pull down is used to set them Low. For example to register a bit low or high in the Configuration Register 0, do the following:

Place an external 470Ω pull-down resistor to register a bit LOW in the Configuration Register 0.

No external pull-up is required; upon reset, bits are set high by default. The state of the boot-strapping resistor is registered on the first cycle after the

synchronous de-assertion of the reset signal. These bits can be read or written as needed for desired configurations. It is recommended that only Bit 31, Memory Map, be changed from 1 to 0 after execution of boot code from external flash.

Refer to the Intel a complete bit description of Configuration Register 0.

Table 6. Boot/Reset Strapping Configuration (Sheet 1 of 2)

IXP43X Product Line of Network Processors Developer’s Manual for

Name Function Description

Intel XScale

EX_ADDR[23:21]

EX_ADDR[20:17] Customer Customer-defined bits. (Might be used for board revision.) EX_ADDR[16:12] (Reserved) (Reserved)

EX_ADDR[11] DDR_MODE

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Processor

Clock Set[2:0]

Allow a slower Intel XScale But cannot be used to over clock core speed. Refer to Table 7 for additional information.

DDRI or DDRII mode selection: 0 - DDRII mode (400MHz) 1 - DDRI mode (266MHz) DDR_mode or DDR clock speed selection bit is read only and strapped in from exp

address bit 11 upon activation of reset_early_n and reset_cold_n.

Processor clock speed to override device fuse settings.

Hardware Design Guidelines—Intel

IXP43X Product Line of Network Processors

Table 6. Boot/Reset Strapping Configuration (Sheet 2 of 2)

Name Function Description

1 = EX_IOWAIT_N is sampled during the read/write expansion bus cycles for Chip Select 0.

0 = EX_IOWAIT_N is ignored for read and write cycles to Chip select 0 if EXP_TIMING_CS0 is configured to Intel mode that is mentioned in Intel

Product Line of Network Processors Datasheet and Intel Network Processors Developer’s Manual.

Typically, IOWAIT_CS0 must be pulled down to Vss when attaching a Synchronous

EX_ADDR[10] IOWAIT_CS0

Intel StrataFlash Intel mode and EX_IOWAIT_N is an unknown value for Synchronous Intel StrataFlash.

If the board does not connect the Synchronous Intel StrataFlash WAIT pin to EX_WAIT_N (and the board guarantees EX_IOWAIT_N is pulled up), the value of IOWAIT_CS0 is a don’t-care, since EX_IOWAIT_N will not be asserted.

When EXP_TIMING_CS0 is reconfigured to Intel Synchronous mode during boot-up (for synchronous Intel chips), the expansion bus controller ignores EX_IOWAIT_N during read and write cycles since the WAIT functionality is determined from the EXP_SYNCINTEL_COUNT and EXP_TIMING_CS registers.

EX_ADDR[9] EXP_MEM_DRIVE Refer to table found in EX_ADDR[5].

Controls the USB clock select. 1 = USB Host/Device clock is generated internally

EX_ADDR[8] USB Clock

0 = USB Device clock is generated from GPIO[0]. When generating a spread spectrum clock on OSC_IN, GPIO[1] can be driven from

the system board to generate a 48 MHz clock for the USB Host. Selects the data bus width of the FLASH memory device found on Chip Select 0.

EX_ADDR[7] 32_FLASH

Refer to 8/16_FLASH bit (Bit 0) of this register as well. 0 = 8 or 16-bit data bus size (must be pulled down during ad dress strapping) 1 = not supported

EX_ADDR[6] (Reserved) (Reserved)

Expansion bus low/medium/high drive strength. The drive strength depends on EXP_DRIVE and EXP_MEM_DRIVE configuration bits.

EXP_MEM_DRIVE EXP_DRIVE Expansion drive strength

EX_ADDR[5] EXP_DRIVE

----------------------------------------------------------------------------------- 0 0 Reserved 0 1 Medium Drive 1 0 Low Drive 1 1 High Drive

Sets the clock speed of the PCI Interface

EX_ADDR[4] PCI_CLK

0 = 33 MHz (must be pulled down during address strapping) 1 = not supported

EX_ADDR[3] (Reserved)

(Reserved). EX_ADDR[3] must not be pulled down during address strapping. This bit must be written to ‘1’ if performing a write to this register.

Enables the PCI Controller Arbiter

EX_ADDR[2] PCI_ARB

0 = PCI arbiter disabled 1 = PCI arbiter enabled

Configures the PCI Controller as PCI Bus Host

EX_ADDR[1] PCI_HOST

0 = PCI as non-host 1 = PCI as host

Specifies the data bus width of the FLASH memory device found on Chip Select 0.

EX_ADDR[0] 8/16_FLASH

8/16_FLASH Data bus size 0 16-bit 1 8-bit

on Chip Select 0 since the default mode for EXP_TIMING_CS0 is

IXP43X Product Line of

IXP43X

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Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

Table 7. Setting Intel XScale

Processor Operation Speed

Intel XScale® Processor

Speed

(Factory Part Speed)

667 MHz X X 1 667 MHz 667 MHz 0 0 0 667 MHz 667 MHz 1 0 0 533 MHz 667 MHz 0 1 0 266 MHz 667 MHz 1 1 0 400 MHz

533 MHz X X 1 533 MHz 533 MHz 0 0 0 533 MHz 533 MHz 1 0 0 533 MHz 533 MHz 0 1 0 266 MHz 533 MHz 1 1 0 400 MHz

400 MHz X X 1 400 MHz 400 MHz 0 0 0 400 MHz 400 MHz 1 0 0 400 MHz 400 MHz 0 1 0 266 MHz 400 MHz 1 1 0 400 MHz

266 MHz X X X 266 MHz

Cfg0

EX_ADDR[21]

Cfg1

EX_ADDR[22]

Cfg_en_n

EX_ADDR[23]

Actual Core Speed

(MHz)

Note: The Intel XScale processor can operate at slower speeds than the factory programmed

speed setting. This is done by placing a value on Expansion bus address bits 23,22,21 when PLL_LOCK is deasserted and knowing the speed grade of the part from the factory. Column 1 above denotes the speed grade of the part from the factory . Column 2, 3, and 4 denotes the values captured on the Expansion Bus address bits when PLL_LOCK is deasserted. Column 5 represents the speed at which the Intel XScale processor speed is operating at.

3.3.3 8-Bit Device Interface

The IXP43X network processors support 8-bit-wide data bus devices (byte mode). For interface cycles, the data lines and control signals can be connected as shown in

Figure 3 on page 26. During byte mode accesses, the remaining data signals not being

used EX_DATA [15:8], are driven by the processor to an unpredictable state on WRITE cycles and tri-stated during READ cycles.

When booting an 8-bit flash device, the expansion bus must be configured during reset to the 8-bit mode, bit 0 and 7 of Configuration Register 0 must be set as follows (see

Table 6):

Bit 0 = 1. By default this bit is set high when coming off reset or any time reset is asserted.

Bit 7 = 0. This can be done by placing an external 470 ohm pull-down resistor to the pin EX_ADDR[7].

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Hardware Design Guidelines—Intel

IXP43X Product Line of Network Processors

Boot-strapping is required in certain address pins of the Expansion bus. If it is required to change access mode, after the system has booted, and during normal operation; the Timing and Control Register for Chip Select must be configured to perform the desired mode access. For a complete description on accomplishing this refer to the Expansion

Bus chapter in the Intel® IXP43X Product Line of Network Processors Developer’s Manual.

3.3.4 16-Bit Device Interface

The IXP43X network processors support 16-bit wide data bus devices (16-bit word mode). For Intel interface cycles, the data lines and control signals can be connected as shown in Figure 3 on page 26.

When booting a 16-bit flash device, the expansion bus must be configured during reset to the 16-bit mode (see Configuration Register 0).

Bit 0 = 0. This can be done by placing an external 470 ohm pull-down resistor to the pin EX_ADDR[0].

Bit 7 = 0. This can be done by placing an external 470 ohm pull-down resistor to the pin EX_ADDR[7].

Boot-strapping is required in certain address pins of the Expansion bus.To change to access mode after booting the system and during normal operation, the Timing and Control Register for Chip Select must be configured to perform the desired mode access. For a complete description on how to accomplish this refer to the Expansion

Bus chapter in the Intel Manual.

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Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

Figure 3. 8/16-Bit Device Interface

EX_DATA[15:0]

Intel® IXP43X Product

Line of Network

Processors

EX_ADDR[23:0]

EX_CS_N

EX_RD_N

EX_WR_N

EX_DATA[15:0]

Intel® IXP43X Product

Line of Network

Processors

EX_ADDR[23:0]

EX_CS_N

EX_RD_N

EX_WR_N

EX_DATA[7:0]

EX_ADDR[23:0]

CS OE

EX_DATA[15:0]

EX_ADDR[23:0]

CS OE

DATA[7:0]

8-Bit Device

Byte Access

ADDR[23:0]

CS_N OE_N WR_N

DATA[15:0]

16-Bit Device

16 -Bit-W o r d Access

ADDR[23:0]

CS_N OE_N WR_N

B4095-004

3.3.5 Flash Interface

Figure 4 illustrates how a boot ROM is connected to the expansion bus. The flash (ROM)

used in the block diagram is the Intel StrataFlash 32-Mbyte, 16-bit, flash in the 56-TSOP package. The Intel StrataFlash memory

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TE28F256J3D is part of the 0.18-µm, 3.3-V Intel StrataFlash memory.

memory device TE28F256J3D —

Hardware Design Guidelines—Intel

Figure 4. Flash Interface Example

IXP43X Product Line of Network Processors

EX_DATA[15:0]

Intel® IXP43X Product

Line of Network

Processors

EX_ADDR[23:0]

EX_CS_N EX_RD_N

EX_WR_N

EX_DATA[15:0]

0 KΩ

3.3 V

CS OE

4.7 KΩ

[

RST#

DATA[15:0]

16-Bit Device

16 -Bit-Word Access

]

ADDR[23:0]

CE0 OE_N WR_N

Intel® Flash

RP_N

CE1 CE2

BYTE_N

VPEN_N

4.7 KΩ

B4097- 005

3.4 UART Interface

The UART interface are a 16550-compliant UART with the exception of transmit and receive buffers. Transmit and receive buffers are 64 bytes-deep versus the 16 bytes required by the 16550 UART specification.

The interface can be configured to support speeds from 1,200 Baud to 921 Kbaud. The interface supports the following configurations:

• Five, six, seven, or eight data-bit transfers

• One or two stop bits

• Even, odd, or no parity The request-to-send (RTS0_N) and clear-to-send (CTS0_N) modem control signals also

are available with the interface for hardware flow control. The hardware supports a four-wire interface:

• Transmit Data

•Receive Data

•Request to Send

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Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

•Clear to Send

Note: The UART module does not support full modem functionality. However, this can be

implemented, by using GPIO ports to generate DTR, DSR, RI, and DCD and making some changes to the driver.

3.4.1 Signal Interface

Table 8. UART Signal Recommendations

Name

RXDATA0 I Yes

TXDATA0 O No Serial data output Port 0.

CTS0_N I Yes

RTS0_N O No Request-To-Send Port 0.

Type Field

The following figure contain a typical four signal interface between the UART and an RS-232 transceiver driver, required to interface with external devices. Unused inputs to the RS-232 driver can be connected to ground. This avoids signals floating to undetermined states which can cause over heating of the driver leading to permanent damage.

Pull Up/

Down

Serial data input Port 0. When signal is not being used in the system, this pin should be pulled high with a 10-KΩ

resistor.

Clear-To-Send Port 0. \When signal is not being used in the system, this pin should be pulled high with a 10-KΩ

resistor.

Recommendations

IXP43X Product Line of Network Processors

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Hardware Design Guidelines—Intel

Figure 5. UART Interface Example

CTS0_N

RTS0_N

UART

Interface

RXDATA0

TXDATA0

IXP43X Product Line of Network Processors

Intel® IXP43X

Product Line of

Network Processors

OUT4

IN3

OUT1

IN2

Transceiver

IN1

OUT3

OUT2

IN4

RS-232

DB9

Connector (Female)

1 DCD

2 RX

3 TX

4 DTR

5 GND

6 DSR

7 RTS

8 CTS

9 RI

3.5 MII Interface

The IXP43X network processors support a maximum of two Ethernet MACs. Depending on the part number of the IXP43X network processors, various combinations can be used. Refer to the Intel detailed list of features that can be enabled depending upon your requirements.

All MACs contained in the NPEs are compliant to the IEEE 802.3 specification and handle flow control for the IEEE 802.3Q VLAN specification.

The Management Data Interface (MDI) supports a maximum of 32 PHY addresses. MDI signals are required to be connected to every PHY chip. Each PHY port is assign a unique address in the external PHY chip from 0 to 31, totaling a maximum of 32 PHY addresses. The maximum number of MACs supported by the IXP43X network processors is two.

The MII interface supports clock rates of 25 MHz for 100-Mbps operation or 2.5 MHz for 10-Mbps operation.

B4099-005

IXP43X Product Line of Network Processors Datasheet for a

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Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

3.5.1 Signal Interface MII

Table 9. MII NPE A Signal Recommendations

Name

ETHA_TXCLK I Yes

ETHA_TXDATA[3:0] O No Transmit Data. ETHA_TXEN O No Transmit Enable.

ETHA_RXCLK I Yes

ETHA_RXDATA[3:0] I Yes

ETHA_RXDV I Yes

ETHA_COL I Yes

ETHA_CRS I Yes

Notes:

1. Features disabled/enabled by Soft Fuse must be done during the boot-up sequence. A feature cannot be enabled after being disabled without asserting a system reset.

2. Features disabled by a specific part number, do not require pull-ups or pull-downs. Therefore, all pins can be left unconnected.

3. Features enabled by a specific part number — and required to be Soft Fus e-disabled , as st ated in Note 1 — only requ ire pull-ups or pull-downs in the clock-input signals.

Type Field

Pull

Up/

Down

Transmit Clock. When this interface/signal is enabled and is not being used in a system design, the

interface/signal should be pulled high with a 10-KΩ resistor.

Receive Clock. When this interface/signal is enabled and is not being used in a system design, the

interface/signal should be pulled high with a 10-KΩ resistor. Receive Data.

When this interface/signal is enabled and is not being used in a system design, the interface/signal should be pulled high with a 10-KΩ resistor.

Receive Data Vali d. When this interface/signal is enabled and is not being used in a system design, the

interface/signal should be pulled high with a 10-KΩ resistor. Collision Detect.

If operating in a full duplex mode and there is no requirement to use the Collision Detect signal, then the pin must be pulled low with a 10-KΩ resistor.

Carrier Sense. When this interface/signal is enabled and is not being used in a system design, the

interface/signal should be pulled high with a 10-KΩ resistor.

Recommendations

Table 10. MII NPE C Signal Recommendations (Sheet 1 of 2)

Name

ETHC_txclk I Yes

ETHC_txdATA[3:0] O No

ETHC_txen O Yes

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Type Field

Pull

Up/

Down

Externally supplied transmit clock.

• 25 MHz for 100 Mbps operation

• 2.5 MHz for 10 Mbps This MAC contains ha rdware hashing capabilities that are local to the interface. When this interface/signal is enabled and is not being used in a system design, the

interface/signal should be pulled high with a 10-KΩ resistor. Transmit data bus to PHY, asserted synchronously with respect to ETHC_TXCLK. This

MAC contains hardware hashing capabilities that are local to the interface. Indicates that the PHY is being presented with nibbles on the MII interface. Asserted

synchronously, with respect to ETHC_TXCLK, at the first nibble of the preamble, and remains asserted until all the nibbles of a frame are presented. This MAC contains hardware hashing capabilities that are local to the interface.

Recommendations

Hardware Design Guidelines—Intel

IXP43X Product Line of Network Processors

Table 10. MII NPE C Signal Recommendations (Sheet 2 of 2)

Name

ETHC_rxclk I Yes

ETHC_rxdATA[3:0] I Yes

ETHC_rxdv I Yes

ETHC_col I Yes

ETHC_crs I Yes

Notes:

1. Features disabled/enabled by Soft Fuse must be done during the boot-up sequence. A feature cannot be enabled after

2. Features disabled by a specific part number, do not require pull-ups or pull-downs. Therefore, all pins can be left

3. Features enabled by a specific part number — and required to be Soft Fuse-disabled, as stated in note 1 — only require

being disabled without asserting a system reset.

unconnected. pull-ups or pull-downs in the clock-input signals.

Type Field

Pull

Up/

Down

Externally supplied receive clock:

• 25 MHz for 100 Mbps operation

•2.5MHz for 10Mbps This MAC contains hardware hashing capabilities that are local to the interface. Should be pulled high through a 10-KΩ resistor when not being utilized in the system.

Receive data bus from PHY, data sampled synchronously , with respect to E THC_RXCLK. This MAC contains hardware hashing capabilities that are local to the interface.

Should be pulled high through a 10-KΩ resistor when not being utilized in the system. Receive data valid is used to inform the MII interface about data that is being sent by

the Ethernet PHY This MAC contains hardware hashing capabilities that are local to the interface. Should be pulled high through a 10-KΩ resistor when not being utilized in the system.

Asserted by the PHY when a collision is detected by the PHY. This MAC contains hardware hashing capabilities that are local to the interface.

Should be pulled high through a 10-KΩ resistor when not being utilized in the system When this interface is disabled through the NPE-C Ethernet soft fuse (refer to the

Expansion Bus Controller chapter of the Intel Processors Developer’s Manual) and is not being used a system design, this interface/ signal is not required for any connection.

Asserted by the PHY when the transmit medium or receive medium are active. De-asserted when both the transmit and receive medium are idle. Remains asserted throughout the duration of collision condition. PHY asserts CRS asynchronously and de-asserts synchronously with respect to ETHC_RXCLK.

This MAC contains hardware hashing capabilities that are local to the interface. Should be pulled high through a 10-KΩ resistor when not being utilized in the system.

Recommendations

IXP43X Product Line of Network

Table 11. MAC Management Signal Recommendations - NPE A and NPE C

Name

ETH_mdio IO Yes

ETH_mdc O No

Type Field

Pull

Up/

Down

NPE A and NPE C Management data input output. Provides the write data to both PHY devices connected to

each MII interface. An external pull-up resistor of 1.5K ohm is required on ETHC_MDIO to properly quantify the external PHYs used in the system. For specific implementation, see the IEEE 802.3 specification.

Should be pulled high through a 10-KΩ resistor when not being utilized in the system NPE A and NPE C

Management data clock. Management data interface clock is used to clock the MDIO sig nal as an output and sample the MDIO as an input. The ETHC_MDC is an input on power up and can be configured to be an output through Intel APIs documented in the Intel

Programmer’s Guide

Recommendations

IXP400 Software

3.5.2 Device Connection, MII

Figure 6 is a typical example of an Ethernet PHY device interfacing to one of the MACs

via the MII hardware protocol.

April 2007 HDG Document Number: 316844; Revision: 001US 31

Intel® IXP43X Product Line of Network Processors

Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

Figure 6. MII Interface Example

Intel® IXP43X

Product Line of

Netw ork Processors

10/100

PHY

ETH_TXEN

ETH_TXCLK

ETH_TXDATA[3:0]

ETH_RXDV

ETH_RXCLK

ETH_RXDATA[3:0]

ETH_COL

ETH_CRS

VCC ( 3.3 V)

ETH_MDIO

ETH_MDC

MI I Interface

3.6 GPIO Interface

1.5 KΩ

TXEN

TXCLK

TXDATA[ 3:0]

RXDV

RXCLK

RXDATA[3:0]

COL

CRS

MDIO

MDC

Magnetics RJ45

25 MHz

B4101 -004

The IXP43X network processors provide 16 general-purpose input/output pins to generate and capture application-specific input and output signals. Each individual pin can be programmed as an input or output.

When programmed as an input, GPIO 0 to GPIO 12 can be configured to be an interrupt source. Interrupt sources can be configured to detect either active high, active low, rising edge, falling edge, or transitional. In addition, GPIO14 and GPIO15 can be programmed to provide a user-programmable clock out.

During reset, all pins are configured as inputs and remain in this state until configured otherwise, with the exception of GPIO15, which by default provides a clock output. The driver strength of GPIO pins is sufficient to drive external LEDs with a proper limiting resistor.

IXP43X Product Line of Network Processors

Intel HDG April 2007 32 Document Number: 316844; Revision: 001US

Hardware Design Guidelines—Intel

IXP43X Product Line of Network Processors

3.6.1 Signal Interface

Table 12. GPIO Signal Recommendations

Name

GPIO[13:0] IO Yes

GPIO[14] IO Yes

GPIO[15] IO Yes

Type Field

Pull Up/

Down

General Purpose Input/Output. If used as an input interrupt (only GPIO [12:0]), should be pull-up or pull-down, depending

on the level of activation. For example: Active high, use a 10-KΩ pull-down resistor. Active low, use a 10-KΩ pull-up resistor. Should be pulled high through a 10-KΩ resistor when not used.

Note: Alternate function for GPIO[1] - External USB 48 MHz Bypass Clock

General Purpose Input/Output. Same recommendations as GPIO[13:0]. An additional feature includes Clock generation, max

clock out 33.33 MHz., set as input by default. General Purpose Input/Output.

Same recommendations as GPIO[13:0]. An additional feature includes Clock generation, max clock out 33.33 MHz., set as output by default.

3.6.2 Design Notes

The drive strength for GPIO[15:14] is limited to 8 mA, while GPIO [13:0] can output up to 16 mA. When used for driving high current devices such as LEDs or relays, make sure to place current-limiting resistor; else there could be permanent damage to the driver of the IXP43X network processors.

It is recommended that a 10-KΩ pull-up resistor be used when a GPIO port is configured as an input and not being used.

Recommendations

3.7 USB Interface

There are two USBV2.0 Host Controllers in the IXP43X network processors. It supports Low-Speed, 1.5 Mbps, Full-Speed, 12 Mbps, High-Speed, 480 Mbps rate and interface is EHCI compliant.

Supported features are:

• Host function

•Low-speed interface

• Full-speed interface

• High-speed interface

• EHCI register interface

• UTMI+ Level 2 Compliant

The following is a partial list of features that are not supported:

• Device function

• OTG function

April 2007 HDG Document Number: 316844; Revision: 001US 33

Intel® IXP43X Product Line of Network Processors

Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

3.7.1 Signal Interface

Table 13. U SB Host Signal Recommendations

Name

USB_P0_POS I/O Yes

USB_P0_NEG I/O Yes

USB_P0_PWREN O No Enables the external VBUS power source.

USB_P0_OC I No

USB_P1_POS I/O Yes

USB_P1_NEG I/O Yes

USB_P1_PWREN O No Enable the external VBUS power source.

USB_P1_OC I No

Type Field

Pull Up/

Down

Positive signal of the differential USB receiver/driver for the USB host interface. Use an 20Ω series termination resistor at the source. When this interface/signal is enabled and is not being used in a system design, the

interface/signal should be pulled low with a 10-KΩ resistor. When this interface is disabled through the USB Device soft fuse and is not being used in a system design, it is not required for any connection. Refer to Expansion Bus Controller chapter of the

IXP43X Product Line of Network Processors Developer’s Manual.

Intel

Negative signal of the differential USB receiver/driver for the USB host interface. Use an 20Ω series termination resistor at the source. When this interface/signal is enabled and is not being used in a system design, the

IXP43X Product Line of Network Processors Developer’s Manual.

Intel

External VBUS power is in over current condition When this interface/signal is enabled and is not being used in a system design, the

IXP43X Product Line of Network Processors Developer’s Manual.

Intel

interface/signal should be pulled low with a 10-KΩ resistor. When this interface is disabled through the USB Device soft fuse. Refer to Expansion Bus Controller chapter of the Intel

Intel

External VBUS power is in over current condition When this interface/signal is enabled and is not being used in a system design, the

Intel

IXP43X Product Line of Network Processors Developer’s Manual.

Description

A typical implementation of a USB interface Host down-stream is shown in Figure 9. The Host controller cannot be used as a Device controller.

Note: Depending on the data rate required, Low-speed, Full-speed or High-speed, the 1.5K

resistor shown near the device interface must be connected on the D+ or D-. Speed configuration at the Device can be set as stated in note 1 and 2 below. F or more

details, refer to the Universal Serial Bus Specification, Revision 2.0.

Note:

1. If a 1.5-KΩ, pull-up resistor is connected to USB_P_POS line, the USB port is identified as Full-speed and High-speed mode.

IXP43X Product Line of Network Processors

Intel HDG April 2007 34 Document Number: 316844; Revision: 001US

Hardware Design Guidelines—Intel

2. If a 1.5-KΩ, pull-up resistor is connected to USB_P_NEG line, the USB port is identified as Low-speed mode.

To maintain signal integrity and minimize end-users termination mismatch, the IXP43X network processors require external series termination resistors. The value of the terminating resistors is based on the operational speed and length of the transmission line.

Refer to following termination guidelines for High-speed:

1. High-speed USB designs require parallel termination at both the transmitter and receiver. For host controller designs that use external termination resistors, place the termination resistors as close as possible to the host controller signal pins. Recommend less than 200 mils if possible. Follow the manufacturer’s recommendation for the termination value needed to obtain the required 45 ohm to ground parallel HS termination.

2. For downstream ports, a 15 kΩ pull down resistor on the connector side of the termination is required for device connection detection purposes. Note that this pull down might be integrated into the host controller silicon. Follow the manufacturer’s recommendation for the specific part used.

3. A common mode (CM) choke should be used to terminate the high speed USB bus if they should pass EMI testing. Place the CM choke as close as possible to the connector as shown in Figure 8 on page 36. Common mode chokes can provide required noise attenuation. Design can include a common mode choke footprint to provide a stuffing option in the event the choke is needed to pass EMI testing.

IXP43X Product Line of Network Processors

Note: Common mode chokes degrade signal quality, thus they should only be used if EMI is a

known problem.

Figure 7. Common Mode Choke

April 2007 HDG Document Number: 316844; Revision: 001US 35

Intel® IXP43X Product Line of Network Processors

Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

Figure 8. USB RCOMP and ICOMP Pin Requirement

USB_ RBIASP

USB_ RBIASN

22.6

± 1

resistor

Figure 9. USB Host Down Stream Interface Example

Intel®

IXP43X

Product Line

of Network

Processors

USB_VDD

Host Device

Intel ® IXP43X

Product Line of

Network

Processors

USB_HPEN

USB_HPWR

USB_HPOS

USB_HNEG

(D+)

(D-)

USB Port

20 Ω

FERRITE

47 µF

0.1 µF

15 KΩ

4.7 µF

200 mA

0.1 µF

FERRITE

22 pF 22 pF

FERRITE

22 pF

USB_3V3V_BUS

1.5 KΩ

Look at

Note 1&2

D +

Device

D-

B4105-004

IXP43X Product Line of Network Processors

Intel HDG April 2007 36 Document Number: 316844; Revision: 001US

Hardware Design Guidelines—Intel

IXP43X Product Line of Network Processors

3.8 UTOPIA Level 2 Interface

The IXP43X network processors support the industry-standard UTOPIA Level 2 bus interface. A dedicated Network Processor Engine (NPE) handles segmentation and reassembly of ATM cells, CRC checking/generation, and transfer of data to/from memory. This allows parallel processing of data traffic on the UTOPIA interface, off-loading processor overhead required by the Intel XScale

The UTOPIA module is configured as a master and can support single-PHY (SPHY) or multi-PHY (MPHY).

The IXP43X network processors are in compliance with the A TM Forum, UTOPIA Level 2 Specification, Revision 1.0. For optimal design results, the guidelines of the specification should be followed.

3.8.1 Signal Interface

Table 14. UTOPIA Level 2/MII_A

Name

UTP_OP_CLK / ETHA_TXCLK

UTP_OP_FCO TRI Yes

UTP_OP_SOC TRI Yes

UTP_OP_DATA[3:0] / ETHA_TXDATA[3:0]

†† Refer to the Intel

interface.

Type Field

IYes

TRI No

IXP43X Product Line of Network Processors Developer’s Manual for information on how to select an

Pull

Up/

Down

UTOPIA Level 2 Mode of Operation: UTOPIA Level 2 Transmit clock input. Also known as UTP_TX_CLK. This signal is

used to synchronize all UTOPIA Level 2 transmit output to the rising edge of the UTP_OP_CLK.

MII Mode of Operation: Externally supplied transmit clock.

• 25 MHz for 100 Mbps operation

• 2.5 MHz for 10 Mbps

When this interface/signal is enabled and is not being used in a system design, the interface/signal should be pulled high with a 10-KΩ resistor.

UTOPIA Level 2 flow control output signal. Also known as the TXENB_N signal. Used to inform the selected PHY about data transmission. Placing the PHY’s

address on the UTP_OP_ADDR and bringing UTP_OP_FCO to logic 1 during the current clock, followed by the UTP_OP_FCO going to a logic 0, on the next clock cycle, selects the PHY that is active in MPHY mod e .

In SPHY configurations, UTP_OP_FCO is used to inform the PHY that the processor is ready to send data.

This signal is tied to Vcc with an external 10-KΩ resistor. Start of Cell. Also known as TX_SOC.

Active high signal is asserted when UTP_OP_DATA contains first valid byte of a transmitted cell.

This signal is tied to Vss with an external 10-KΩ resistor. UTOPIA Level 2 Mode of Operation:

UTOPIA Level 2 output data. Also known as UTP_TX_DATA. Used to send data from the processor to an ATM UTOPIA Level 2-compliant PHY.

MII Mode of Operation: Transmit data bus to PHY, asserted synchronously with respect to ETHA_TXCLK.

This MAC interface does not contain hardware hashing capabilities that are local to the interface. In this mode of operation the pins represented by this interface are ETHA_TXDATA[3:0].

Description

Processor.

April 2007 HDG Document Number: 316844; Revision: 001US 37

Intel® IXP43X Product Line of Network Processors

Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

Name

UTP_OP_DATA[4] / ETHA_TXEN

UTP_OP_DATA[7:5] TRI No

UTP_OP_ADDR[4:0] I/O Yes

UTP_OP_FCI I Yes

UTP_IP_CLK / ETHA_RXCLK

†† Refer to the Intel

interface.

Type Field

TRI No

IYes

IXP43X Product Line of Network Processors Developer’s Manual for information on how to select an

Pull

Up/

Down

Description

UTOPIA Level 2 Mode of Operation: UTOPIA Level 2 output data. Also known as UTP_TX_DATA. Used to send data

from the MII Mode of Operation: Indicates that the PHY is being presented with nibbles on the MII interface.

Asserted synchronously, with respect to ETHA_TXCLK, at the first nibble of the preamble, and remains asserted until all the nibbles of a frame are presented. This MAC does not contain hardware hashing capabilities that are local to the interface.

UTOPIA Level 2 Mode of Operation: UTOPIA Level 2 output data. Also known as UTP_TX_DATA. Used to send data

from the Transmit PHY address bus. Used by the

mode to poll and select a single PHY at any given time. When this interface/signal is enabled and is not being used in a system design,

the interface/signal should be pulled high with a 10-KΩ resistor. When this interface is disabled through the UTOPIA Level 2 and/or the NPE-A Ethernet soft fuse and is not being used in a system design, it is not required for any connection. Refer to Expansion Bus Controller chapter of the Intel

Product Line of Network Processors Developer’s Manual.

UTOPIA Level 2 Output data flow control input: Also known as the TXFULL/CLAV signal.

Used to inform the proc essor, the ability of each polled PHY to receive a complete cell. For cell-level flow control in an MPHY environment, TxClav is an active high tristateable signal from the MPHY to ATM layer.

The UTP_OP_FCI is connected to multiple MPHY devices. It sees the logic high generated by the PHY, one clock after the given PHY address is asserted and a full cell can be received by the PHY. The UTP_OP_FCI sees a logic low generated by the PHY one clock cycle, after the PHY address is asserted, and a full cell cannot be received by the PHY.

When this interface/signal is enabled and is not being used in a system design, the interface/signal should be pulled high with a 10-KΩ resistor. When this interface is disabled through the UTOPIA Level 2 and/or the NPE-A Ethernet soft fuse and is not being used in a system design, it is not required for any connection. Refer to Expansion Bus Controller chapter of the Intel

Product Line of Network Processors Developer’s Manual.

UTOPIA Level 2 Mode of Operation: UTOPIA Level 2 Receive clock input. Also known as UTP_RX_CLK. This signal is used to synchronize all UTOPIA Level 2-received inputs to the rising

edge of the UTP_IP_CLK. MII Mode of Operation: Externally supplied receive clock.

This MAC interface does not contain hardware hashing capabilities that are local to the interface.

When this interface/signal is enabled and is not being used in a system design, the interface/signal should be pulled high with a 10-KΩ resistor.

processor to an ATM UTOPIA Level 2-compliant PHY.

processor when operating in MPHY

• 25 MHz for 100 Mbps operation

•2.5MHz for 10Mbps

IXP43X

IXP43X Product Line of Network Processors

Intel HDG April 2007 38 Document Number: 316844; Revision: 001US

Hardware Design Guidelines—Intel

IXP43X Product Line of Network Processors

Name

Type Field

Pull

Up/

Down

UTP_IP_FCI I Yes

UTP_IP_SOC I Yes

UTP_IP_DATA[3:0] / ETHA_RXDATA[3:0]

UTP_IP_DATA[4] / ETHA_RXDV

†† Refer to the Intel

interface.

IYes

IXP43X Product Line of Network Processors Developer’s Manual for information on how to select an

Description

UTOPIA Level 2 Input Data flow control input signal. Also known as RXEMPTY/ CLAV.

Used to inform the processor of the ability of each polled PHY to send a complete cell. For cell-level flow control in an MPHY environment, RxClav is an active high tri-stateable signal from the MPHY to ATM layer. The UTP_IP_FCI, which is connected to multiple MPHY devices, sees logic high generated by the PHY, one clock after the given PHY address is asserted, when a full cell can be received by the PHY. The UTP_IP_FCI sees a logic low generated by the PHY, one clock cycle after the PHY address is asserted if a full cell cannot be received by the PHY.

In a SPHY mode, this signal is used to indicate to the processor that the PHY has an octet or cell available for transferring to the processor.

When this interface/signal is enabled and is not being used in a system design, the interface/signal should be pulled high with a 10-KΩ resistor. When this interface is disabled through the UTOPIA Level 2 and/or the NPE-A Ethernet soft fuse (refer to Expansion Bus Controller chapter of the Intel of Network Processors Developer’s Manual) and is not being used in a system design, the interface/signal is not required for any connection.

IXP43X Product Line

Start of Cell. RX_SOC Active-high signal that is asserted when UTP_IP_DATA contains the first valid

byte of a transmitted cell. When this interface/signal is enabled and is not being used in a system design,

the interface/signal should be pulled high with a 10KΩ resistor. When this interface is disabled through the UTOPIA Level 2 and/or the NPE-A Ethernet soft fuse and is not being used in a system design, it is not required for any connection. Refer to Expansion Bus Controller chapter of the Intel

Product Line of Network Processors Developer’s Manual.

IXP43X

UTOPIA Level 2 Mode of Operation: UTOPIA Level 2 input data. Also known as RX_DATA. Used by the processor to receive data from an ATM UTOPIA Level 2-compliant

PHY. MII Mode of Operation: Receives data bus from the PHY; asserted synchronously with respect to

ETHA_RXCLK. When the interface/signal is enabled and is not being used in a system desig n, it

should be pulled high with a 10KΩ resistor. When the interface is disabled through the UTOPIA Level 2 and/or the NPE-A

Ethernet soft fuse and is not being used in a system design, it is not required for any connection. (Refer to Expans ion Bus Cont roller chapter of the Intel

Product Line of Network Processors Developer’s Manual).

IXP43X

UTOPIA Level 2 Mode of Operation: UTOPIA Level 2 input data. Also known as RX_DATA. Used by to the processor to receive data from an ATM UTOPIA Level 2-compliant

PHY. MII Mode of Operation: Receive data valid used to inform the MII interface about data that is being sent

by the Ethernet PHY. This MAC does not contain hardware hashing capabilities that are local to the

interface. When the interface/signal is enabled and is not being used in a system design,

the interface/signal should be pulled high with a 10-KΩ resistor. When this interface is disabled through the UTOPIA Level 2 and/or the NPE-A Ethernet soft fuse (and is not being used in a system design, it is not required for any connection. Refer to Expansion Bus Controller chapter of the Intel

Product Line of Network Processors Developer’s Manual.

IXP43X

April 2007 HDG

Intel® IXP43X Product Line of Network Processors

Document Number: 316844; Revision: 001US 39

Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

Name

UTP_IP_DATA[5] / ETHA_COL

UTP_IP_DATA[6] / ETHA_CRS

Type Field

IYes

Pull

Up/

Down

UTP_IP_DATA[7] I Yes

UTP_IP_ADDR[4:0] I/O No

UTP_IP_FCO TRI Yes

†† Refer to the Intel

IXP43X Product Line of Network Processors Developer’s Manual for information on how to select an

interface.

Description

UTOPIA Level 2 Mode of Operation: UTOPIA Level 2 input data. Also known as RX_DATA. Used by the processor to receive data from an ATM UTOPIA Level 2-compliant

PHY.

• When an NPE A is configured in UTOPIA Level 2 mode of operation and the signal is not used, it should be pulled high through a 10-KΩ resistor.

MII Mode of Operation: Asserted by the PHY when a collision is detected by the PHY.

• When an NPE A is configured in MII mode of operation and the signal is not used, it should be pulled low through a 10-KΩ resistor.

When this interface is disabled through the UTOPIA Level 2 and/ or the NPE-A Ethernet soft fuse and is not being used in a system design, it is not required for any connection. Refer to Expansion Bus Controller chapter of the Intel

IXP43X

Product Line of Network Processors Developer’s Manual.

UTOPIA Level 2 Mode of Operation: UTOPIA Level 2 input data. Also known as RX_DATA. Used by the processor to receive data from an ATM UTOPIA Level 2-compliant

PHY. MII Mode of Operation: Asserted by the PHY when transmit medium or receive medium is active. De-

asserted when both the transmit and receive medium are idle. R emains asserted throughout the duration of collision condition. PHY asserts CRS asynchronously and de-asserts synchronously with respect to ETHA_RXCLK.

Product Line of Network Processors Developer’s Manual.

IXP43X

UTOPIA Level 2 Mode of Operation: UTOPIA Level 2 input data. Also known as RX_DATA. Used by the processor to receive data from an ATM UTOPIA Level 2-compliant

PHY. MII Mode of Operation: Not Used. When this interface/signal is enabled and is not being used in a system design,

Product Line of Network Processors Developer’s Manual.

IXP43X

Receive PHY address bus. Used by the processor

single PHY at any given point of time. UTOPIA Level 2 Input Data Flow Control Output signal: Also known as the

RX_ENB_N. In a SPHY configuration, UTP_IP_FCO is used to inform the PHY that the

processor is ready to accept data. In MPHY configurations, UTP_IP_FCO is used to select those PHY drives that

signals UTP_RX_DATA and UTP_RX_SOC. The PHY is selected by placing the PHY’s address on the UTP_IP_ADDR and bringing UTP_OP_FCO to logic 1 during the current clock, followed by the UTP_OP_FCO going to a logic 0 on the next clock cycle.

When this interface/signal is enabled and is not being used in a system design, the interface/signal should be pulled high with a 10-KΩ resistor.

while operating in an MPHY mode to poll and select a

IXP43X Product Line of Network Processors

Intel HDG April 2007 40 Document Number: 316844; Revision: 001US

Hardware Design Guidelines—Intel

IXP43X Product Line of Network Processors

3.8.2 Device Connection

The following example shown in Figure 10 shows a typical interface to an ADSL Framer via the UTOPIA bus. Notice that depending on the framer used some control signals might be required which can be derived from the Expansion bus or the GPIO signals.

Figure 10. UTOPIA Interface Example

Intel® IXP43X

Product Line of

Network

Processors

EX_BUS

ATM Layer Device

Control Signals

25 MHz

ADSL Framer

Multi-Channel

Analog Front

End

AFE RJ11

UTP_OP_CLK

UTP_OP_FCO

UTP_OP_ADDR[4:0]

UTP_OP_FCI

UTP_OP_SOC

UTP_OP_DATA[7:0]

UTP_IP_FCO

UTP_IP_ADDR[4:0]

UTP_IP_FCI RXCLAV

UTP_IP_SOC

UTP_IP_DATA[7:0]

UTP_IP_CLK

UTOPIA L evel 2

Interface

3.9 HSS Interface

25 MHz

TXCLK TXENB#

TXADDR[4:0] TXCLAV

TXSOC

TXDATA[ 7:0]

RXENB# RXADDR[4:0]

RXSOC

RXDATA[7:0]

RXCLK

SDRAM

Local Memory

AFE RJ11

B4107-005

NPE A has an integrated High-Speed Serial (HSS) module, whose primary function is to provide connectivity between the internal NPE A and the external HSS interface. There is one HSS port that can directly interface to SLIC/CODEC devices for voice applications, or serial DSL framers. The HSS ports are software configur able to support various serial protocols, such as T1/ E1/J1, and MVIP. For a list of supported protocols, see the Intel

April 2007 HDG Document Number: 316844; Revision: 001US 41

IXP400 Software Programmer’s Guide.

Intel® IXP43X Product Line of Network Processors

Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

3.9.1 Signal Interface

Table 15. High-Speed, Serial Interface 0

Name

HSS_TXFRAME0 I/O Yes

HSS_TXDATA0 OD Yes

HSS_TXCLK0 I/O Yes

HSS_RXFRAME0 I/O Yes

HSS_RXDATA0 I Yes

HSS_RXCLK0 I/O Yes

Notes:

1. Features disabled/enabled by Soft Fuse must be done during the boot-up sequence. A feature cannot be enabled after

2. Features disabled by a specific part number, do not require pull-ups or pull-downs. Therefore, all pins can be left

3. Features Enabled by a specific part number and required to be Soft Fuse-dis abled, as stated in Note 1 alone require pull-

being disabled without asserting a system reset.

unconnected. ups or pull-downs in the clock-input signals.

Type Field

Pull

Down

Transmit frame. When this interface/signal is enabled and is not being used in a system design, the

interface/signal should be pulled high with a 10-KΩ resistor. Transmit data out. Open Drain Output.

When this interface/signal is enabled and is used or not used in a system design, the interface/signal should be pulled high with a 10-KΩ resistor to Vcc33.

Transmit clock. When this interface/signal is enabled and is not being used in a system design, the

interface/signal should be pulled high with a 10-KΩ resistor. Receive frame.

When this interface/signal is enabled and is not being used in a system design, the interface/signal should be pulled high with a 10-KΩ resistor.

Receive data input. When this interface/signal is enabled and is not being used in a system design, the

interface/signal should be pulled high with a 10-KΩ resistor. Receive clock.

When this interface/signal is enabled and is not being used in a system design, the interface/signal should be pulled high with a 10-KΩ resistor.

Recommendations

3.9.2 Device Connection

Figure 11 shows a typical interface between the IXP43X network processors and a SLIC

CODEC, through the SSP and HSS ports, and a couple of GPIO signals.

IXP43X Product Line of Network Processors

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Hardware Design Guidelines—Intel

IXP43X Product Line of Network Processors

Figure 11. HSS Interface Example

Intel® IXP 43X

Product Line of

Netw ork Processo rs

GPIO_0

GPIO _1

SSP_EXT CLK

SSP_SCLK

SSP_SFRM

SSP_TXD

SSP_RXD

SSP Interface

HSS_TX_FRAME0

HSS_TXDATA0

HSS_ TXCLK0

HSS_RXFRAME0

HSS_RXDAT A0

HSS_ RXC LK0

HSS Interface

External Oscillator

Vccp (3. 3 V)

10 KΩ

or ext ernal osc ilator

Clock deriv ed internally

from 3.6864 M Hz

or ext ernal osc ilator

33 MHz

Cloc k deriv ed from

SLIC/CODEC

RESET_N

CLK CS_N

D I

DTX

FSYNC RXD PCLK

512 KHz to

8.192 MHz

Vccp (3.3 V)

INT_N

SLIC CODEC

10 KΩ

AFE

RJ11

B4108 -005

3.10 SSP Interface

The IXP43X network processors have a Synchronous Serial Peripheral Interface (SSP) module. Its primary function is to provide connectivity between the Intel XScale Processor and an external SSP interface.

The SSP module supports Texas Instruments synchronous serial protocol (SSP)*, Motorola serial peripheral interface (SPI)* and National Microwire*.

The clock rate can be selected from an internal, 3.6864-MHz source or external source fed at input pin SSP_EXTCLK. The clock can then be divided down anywhere from

7.2 KHz to 1.84 MHz by setting bits 15:08 in SSP Control Register 0 (SSCR0). For instructions on the SSP configuration register, refer to the Serial Clock Register (SCR) subsection in the Memory Controller chapter of the Intel

IXP43X Product Line of

Network Processors Datasheet.

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Intel® IXP43X Product Line of Network Processors

Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

3.10.1 Signal Interface

Table 16. Synchronous Serial Peripheral Port Interface

Name

SSP_SCLK O No Serial bit clock. SSP_SFRM O No Serial frame indicator. SSP_TXD O No Transmit data (serial data out).

SSP_RXD I Yes

SSP_EXTCLK I Yes

Type Field

Pull Up/

Down

Receive data (serial data in). Should be pulled high through a 10-KΩ resistor when not being utilized in the system.

External clock input. Should be pulled high through a 10-KΩ resistor when not being utilized in the system.

3.10.2 Device Connection

There are a number of devices available that can interface to SSP or SPI ports, these can range from RTC (Real-Time Clock), LCD (Liquid Crystal Displays), Digital Thermal Sensor to Flash memory devices.

One of the most common usage for SSP or SPI port, is serial flash code storage. Serial flash devices can be used to store board revision, serial numbers, or assembly information. Figure 12 provides an example of a Serial Flash device interface to the SSP port in the IXP43X network processors. For an additional example of SPI interface, refer to Figure 11, where a SLIC is connected to the SSP and HSS ports.

Recommendations

IXP43X Product Line of Network Processors

Intel HDG April 2007 44 Document Number: 316844; Revision: 001US

Hardware Design Guidelines—Intel

Figure 12. Serial Flash and SSP Port (SPI) Interface Example

IXP43X Product Line of Network Processors

Intel® IX P 43 X Product

Line of Network

Processors

SPI Fl ash

SSP Interface

3.11 PCI Interface

The PCI Controller of the IXP43X network processors is an industry-standard, 32-bit interface, high-performance bus that operates at 33 MHz(PCI Local Bus Specification, Rev. 2.2).

SSP_SCLK

SSP_SFRM

SSP_TXD

SSP_RXD

SSP_EXTCLK

CLK

CS_N

D I

7.2 KHz

to 3.6864 MHz

External Oscillator

B4109-003

The PCI interface is capable of operating as a host or an option. This PCI implementation supports 3.3 V I/O only.

As indicated in Figure 13, a PCI transparent bridge is required to support Compact PCI. General PCI routing guidelines can be found in Section 6.2, “Topology” on page 67. For

detailed information, see the PCI Local Bus Specification, Rev. 2.2.

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Intel® IXP43X Product Line of Network Processors

Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

3.11.1 Signal Interface

Table 17. PCI Controller (Sheet 1 of 2)

Name

PCI_AD[31:0] I/O Yes

PCI_CBE_N[3:0] I/O Yes

PCI_PAR I/O Yes

PCI_FRAME_N I/O Yes

PCI_TRDY_N I/O Yes

PCI_IRDY_N I/O Yes

PCI_STOP_N I/O Yes

PCI_PERR_N I/O Yes

PCI_SERR_N I/O Yes

PCI_DEVSEL_N I/O Yes

PCI_IDSEL I Yes

PCI_REQ_N[3:1] I Yes

PCI_REQ_N[0] I/O Yes

PCI_GNT_N[3:1] O No Arbitration Grant.

PCI_GNT_N[0] I/O Yes

Notes:

1. Features disabled/enabled by Soft Fuse must be done during the boot-up sequence. A feature cannot be enabled after

2. Features disabled by a specific part number, do not require pull-ups or pull-downs. Therefore, all pins can be left

3. Features enabled by a specific part number — and required to be Soft Fuse-disabled, as stated in Note 1 — only require

being disabled without asserting a system reset.

unconnected. pull-ups or pull-downs in the clock-input signals.

Type Field

Pull

Up/

Down

PCI Address/Data bus. When this interface/signal is enabled and is not being used in a system design, the interface/

signal should be pulled high with a 10-KΩ resistor. PCI Command/Byte Enables.

When this interface/signal is enabled and is not being used in a system design, the interface/ signal should be pulled high with a 10-KΩ resistor.

PCI Parity. When this interface/signal is enabled and is not being used in a system design, the interface/

signal should be pulled high with a 10-KΩ resistor. PCI Cycle Frame.

When this interface/signal is enabled and is being used or no t being used in a system desi gn, the interface/signal should be pulled high with a 10-KΩ resistor.

PCI Target Ready. When this interface/signal is enabled and is being used or no t being used in a system desi gn,

the interface/signal should be pulled high with a 10-KΩ resistor. Initiator Ready.

When this interface/signal is enabled and is being used or no t being used in a system desi gn, the interface/signal should be pulled high with a 10-KΩ resistor.

Stop. When this interface/signal is enabled and is being used or no t being used in a system desi gn,

the interface/signal should be pulled high with a 10-KΩ resistor. Parity Error.

When this interface/signal is enabled and is being used or no t being used in a system desi gn, the interface/signal should be pulled high with a 10-KΩ resistor.

System Error. When this interface/signal is enabled and is being used or no t being used in a system desi gn,

the interface/signal should be pulled high with a 10-KΩ resistor. Device Select:

When this interface/signal is enabled and is being used or no t being used in a system desi gn, the interface/signal should be pulled high with a 10-KΩ resistor.

Initialization Device Select. When this interface/signal is enabled and is not being used in a system design, the interface/

signal should be pulled high with a 10-KΩ resistor. Arbitration Request.

When this interface/signal is enabled and is not being used in a system design, the interface/ signal should be pulled high with a 10-KΩ resistor.

Arbitration Request: When this interface/signal is enabled and is not being used in a system design, the interface/

signal should be pulled high with a 10-KΩ resistor.

Arbitration Grant. When this interface/signal is enabled and is not being used in a system design, the interface/

signal should be pulled high with a 10-KΩ resistor.

Recommendations

IXP43X Product Line of Network Processors

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Hardware Design Guidelines—Intel

IXP43X Product Line of Network Processors

Table 17. PCI Controller (Sheet 2 of 2)

Name

PCI_INTA_N O/D Yes

PCI_CLKIN I Yes

Notes:

1. Features disabled/enabled by Soft Fuse must be done during the boot-up sequence. A feature cannot be enabled after

2. Features disabled by a specific part number, do not require pull-ups or pull-downs. Therefore, all pins can be left

3. Features enabled by a specific part number — and required to be Soft Fuse-disabled, as stated in Note 1 — only require

being disabled without asserting a system reset.

unconnected. pull-ups or pull-downs in the clock-input signals.

Type Field

Pull Up/

Down

Interrupt A. When this interface/signal is enabled and is used or not used in a system design, the

interface/signal should be pulled high with a 10-KΩ resistor. Clock input.

When this interface/signal is enabled and is not being used in a system design, the interface/ signal should be pulled high with a 10-KΩ resistor.

Recommendations

3.11.2 PCI Interface Block Diagram

While using the IXP43X network processors in Master mode, the PCI module can interface to up to four PCI cards (devices) at 33 MHz. The limitation is due to load requirements to maintain signal integrity.

The PCI-to-PCI bridge must be used to address the PCI requirement not to exceed one load per PCI connector unless it is through a PCI-to-PCI bridge.

The IDSEL signals on the PCI slots can be connected to one of the PCI_AD lines, preferable to the higher order address signals. Reset support can be accomplished by using one of the GPIO pins to generate a reset or through an external decoder of the Expansion bus.

April 2007 HDG Document Number: 316844; Revision: 001US 47

Intel® IXP43X Product Line of Network Processors

Figure 13. PCI Interface

Intel® IXP43X

Product Line of

N etwo r k P r o cesso r s

Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

cPCI J1

PCI Interface

PCI Bus

Bridge

Transpare nt P CI

PCI Slots

3.11.3 PCI Option Interface

The IXP43X network processors can be used in a design as a host or as an option device. This section describes how the IXP43X network processors can be connected as an option device to obtain proper functionality. There are slight differences in the hardware interface when designing for option mode. All routing and board recommendations described in this document apply, however the design must use the device pin connections listed in Table 18.

Table 18. PCI Host/Option Interface Pin Description (Sheet 1 of 3)

Name

PCI_AD[31:0] I/O

PCI_CBE_N[3:0] I/O

PCI_PAR I/O

PCI_FRAME_N I/O

PCI_TRDY_N I/O

Type Field

Device-Pin Connection

All address/data signals must be connected between the two devices.

Connect signals to same pins between the two devices.

Connect signal to same pin between the two devices.

Connect a 10-KΩ pull-up resistor. Connect signal to same pin between

the two devices. Connect a 10-KΩ pull-up resistor.

Option

Type Field

I/O PCI Address/Data bus

I/O PCI Command/Byte Enables

I/O PCI Parity

I/O PCI Cycle Frame

I/O PCI Target Ready

Compact PCI Bus

cPCI J2

B4110-003

Description

IXP43X Product Line of Network Processors

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Hardware Design Guidelines—Intel

IXP43X Product Line of Network Processors

Table 18. PCI Host/Option Interface Pin Description (Sheet 2 of 3)

Name

PCI_IRDY_N I/O

PCI_STOP_N I/O

PCI_PERR_N I/O

PCI_SERR_N I/O

PCI_DEVSEL_N I/O

PCI_IDSEL I

PCI_REQ_N[3:1] I

PCI_REQ_N[0] I

PCI_GNT_N[3:1] O

PCI_GNT_N[0] O

Type Field

Device-Pin Connection

Connect signal to same pin between the two devices.

Connect a 10-KΩ pull-up resistor. Connect signal to same pin between

the two devices. Connect a 10-KΩ pull-up resistor.

Connect signal to same pin between the two devices.

Connect a 10-KΩ pull-up resistor. Connect signal to same pin between

the two devices. Connect a 10-KΩ pull-up resistor.

Connect signal to same pin between the two devices.

Connect a 10-KΩ pull-up resistor. Connect one of the higher order PCI

address signals to the Device. Connect a 10K pull-up resistor to the

Host.

From the Option device, connect output signal PCI_REQ_N[0] to one of the PCI_REQ_N[3:0] inputs to the Host.

Note: the PCI_REQ_N[n] must correspond to the PCI_GNT_N[n], where n must be the same number in the square bracket.

From the Option device, connect output PCI_REQ_N[0] to one of the PCI_REQ_N[3:0] inputs to the Host.

Note: the PCI_REQ_N[n] must correspond to the PCI_GNT_N[n], where n must be the same number in the square bracket.

Connect one of the Host outputs PCI_GNT_N[3:0] to PCI_GNT_N[0] input to the Option.

Note: the PCI_GNT_N[n] must correspond to the PCI_GNT_N[n], where n must be the same number in the square bracket.

Connect one of the Host outputs PCI_GNT_N[3:0] to PCI_GNT_N[0] input to the Option.

Note: the PCI_GNT_N[n] must correspond to the PCI_GNT_N[n], where n must be the same number in the square bracket.

Option

Type Field

I/O Initiator Ready

I/O Stop

I/O Parity Error

I/O System Error

I/O Device Select

I Initialization Device Select

Arbitration Request On the Option device, these signals are not

used, they should be pulled high with a 10-KΩ resistor.

Note: The PCI_REQ_N[n] must correspond

Arbitration Request On the Option device, this signal is an output

and must be connected to one of the PCI_REQ_N[3:0] inputs to the Host.

Note: The PCI_REQ_N[n] must correspond

Arbitration Grant On the Option device, these signals are not

used, they should be pulled high with a 10-K resistor.

Arbitration Grant On the Option device, this signal is an input

and must be connected to one of the PCI_GNT_N[3:0] outputs of the Host.

Note: The PCI_REQ_N[n] must correspond

Description

to the PCI_GNT_N[n], where n must be the same number in the square bracket.

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Intel® IXP43X Product Line of Network Processors

Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

Table 18. PCI Host/Option Interface Pin Description (Sheet 3 of 3)

Name

PCI_INTA_N O/D

PCI_CLKIN I

Type Field

Connect PCI_INTA_N output from the Option to one of the GPIO input signals of the Host. The GPIO signal at the Host must be configure as an input interrupt level sensitive.

Clock must be connected to both devices. Trace lengths must be matched. Use point to point clock distribution.

3.11.4 Design Notes

• The IXP43X network processors do not support the 5 V PCI signal interface by itself. Only the 3.3 V signal interface is supported without signal level conversion; however, it is possible to interface to 5 V logic while using a voltage level converter.

•The PCI Local Bus Specification, Rev. 2.2 requires that the bus is always parked, as some device is always driving the AD lines. You must use pull-ups on these signals. The specification states that the following control lines should be pulled up:

—FRAME_N —TRDY_N —IRDY_N —DEVSEL_N — STOP_N — SERR_N — PERR_N — LOCK_N —INTA_N —INTB_N —INTC_N —INTD_N

• The GPIO pins of the IXP43X network processors slots to request an interrupt from the processors’ PCI controller.

• PCI_INTA_N is used to request interrupts to external PCI Masters. This signal is an open drain and requires a pull-up resistor.

Device-Pin Connection

Option

Type Field

Interrupt A This interrupt is generated from the Option to

O/D

one of the GPIO inputs to the Host. On the Host this signal is not used, it should

be pulled high with a 10-KΩ resistor.

IClock input

can be used by PCI devices on PCI

Description

3.12 JTAG Interface

JTAG is the popular name for IEEE standards 1149.1-1990 and 1149.1a-1993, IEEE Standard Test Access Port and Boundary-Scan Architecture, which provides support

for:

• Board-level boundary-scan connectivity testing

• Connection to software debugging tools through the JTAG interface

• In-system programming of programmable memory and logic devices on the PCB

The interface is controlled through five dedicated test access port (TAP) pins: TDI, TMS , TCK, nTRST, and TDO, as described in the IEEE 1149.1 standard. The boundary-scan test-logic elements include the TAP pins, TAP controller, instruction register, boundary-scan register, bypass register, device identification register, and data-specific registers. These are described in the Intel Developer’s Manual.

The IXP43X network processors can be controlled during debug through a JTAG interface to the processor, the debug tools such as the Macraigor Systems Raven*, EPI Majic*, Wind River Systems* visionPROBE*/ visionICE* or various other JTAG tools plug into the JTAG interface through a connector.

IXP43X Product Line of Network Processors

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IXP43X Product Line of Network Processors

Hardware Design Guidelines—Intel

IXP43X Product Line of Network Processors

3.12.1 Signal Interface

Table 19. Synchronous Serial Peripheral Port Interface

Name

JTG_TMS I Yes

JTG_TDI I Yes

JTG_TDO O O Test Output data.

JTG_TRST_N I Yes

JTG_TCK I Yes

Type Field

Pull Up/

Down

Test mode select. When the JTAG interface is not being used, the signal must be pulled high using a 10-kΩ

resistor. Test Input data.

When the JTAG interface is not being used, the signal must be pulled high using a 10-kΩ resistor.

Test Reset. When the JTAG interface is not being used, the signal must be pulled low using a 10-kΩ

resistor. Test Clock.

When the JTAG interface is not being used, the signal must be pulled high using a 10-kΩ resistor.

3.13 Input System Clock

The IXP43X network processors require a 33.33-MHz reference clock to generate all internal clocks required including core clock and the various buses running internally within the system.

3.13.1 Clock Signals

Table 20. Clock Signals

Recommendations

Name

OSC_IN I

OSC_OUT O No connect

Type Field

3.13.2 Clock Oscillator

While using an external clock oscillator to supply the 33.33-MHz reference system clock, connect the clock oscillator output to the OSC_IN pin through a series termination of 33 Ω as shown in Figure 14. The series termination helps to smooth the rise and fall edges of the clock and eliminate ringing. Leave the OSC_OUT pin unconnected.

Description

Source must be a clock input of 33.33-MHz. Use a series termination resistor, 10 Ω to 33 Ω at the source.

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Intel® IXP43X Product Line of Network Processors

Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

Figure 14. Clock Oscillator Interface Example

3.3 V

OSC_IN

OUT

VDD

33 KΩ

33.33 MHz

OSC_OUT

Intel® IXP43X

Product Line of

Network

Processors

3.13.3 Recommendations for Crystal Selection

The parameters that should be considered while selecting the crystal to be used are:

Frequency 33.33 MHz

Operation Mode Fundamental

Load

Capacitance

Frequency

Tolerance

Frequency

stability over

temperature

Effective Series

Resistance (ESR)

Drive level > 100 uW

18 pF (This is the capacitance value of the discrete component) *Note1

+/- 30 ppm

+/- 50 ppm

20 ohm *Note2

10 KΩ

0.01 µF

B4111-005

Note: 1) The capacitance value here does not include stray capacitance. The design has been

simulated to work with load capacitance up to 36pF.

2) This does not include the stray resistance. The design has been simulated to work up to 40 ohm series resistance.

The Rf and Rs may not needed. Please refer to the crystal vendor datasheet for recommendation.

IXP43X Product Line of Network Processors

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Hardware Design Guidelines—Intel

IXP43X Product Line of Network Processors

Figure 15. Recommended circuit design on PCB for crystal oscillator

osc

osc _in

= 1Mohm

out

xtal

3.14 Power

The IXP43X network processors have separate power supply domains for the processor core, DDRII/I SDRAM memory, and input/output peripherals to enable low power system design.

Table 21. Power Supply

Name

VCC 1.3V 1.3-V power supply input pins are used for the internal logic. VCC33 3.3V 3.3-V power supply input pins are used for the peripheral (I/O) logic.

VCCDDR

VSS GND

USB_v5REF 5.0V

VCCP_OSC 3.3V

VCCF

VSSAUBG GND Specialized ground for USB Band Gap.

VCCAUPLL 1.3V

VCCAUBG 3.3V

Nominal

voltage

†

1.8V or

2.5V

1.3V 1.3-V power supply input pin. Dedicated for Fuse.

1.8-V or 2.5-V power supply input pins are used for the DDRII/I memory interface.

Ground power supply input pins are used for the 3.3-V, 2.5-V, 1.8-V, and the 1.3-V power supplies.

5-V power supply input pins are used for reference voltage. Note: 3.3-V power supply input can be used but caus es damage to the USB controller if signal

pin is shorted to 5V VBUS.

3.3-V power supply input pins are used for peripheral (I/O) logic of the analog oscillator circ uitry. Require special power filtering circuitry. See the Intel

Processors Datasheet

1.3-V power supply input pins are used for USB PLL. Requires special power filtering circuitry.See the Intel

Processors Datasheet

3.3-V power supply input pins are used for USB Band Gap Requires special power filtering circuitry. See the Intel

Processors Datasheet

Description

IXP43X Product Line of Network

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Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

Name

VCCPUSB 3.3V 3.3-V power supply input pins are used for USB IO. VCCUSBCORE 1.3V 1.3-V power supply input pins are used for USB IO core.

VCCA 1.3V

Nominal

voltage

†

1.3-V power supply input pins are used for internal logic of the analog phase lock-loop circuitry. Requires special power filtering circuitry. See the Intel

Processors Datasheet

Description

IXP43X Product Line of Network

3.14.1 Decoupling Capacitance Recommendations

It is common practice to place decoupling capacitors between the supply voltages and ground. Placement can be near the input supply pins and ground, with one 100-nF capacitor per pin. Additional decoupling capacitors can be place all over the board every 0.5" to 1.0". This ensures good return path for currents and reduce power surges and high-frequency noise.

It is also recommended that 4.7-µF to 10-µF capacitors be placed every 2" to 3".

3.14.2 VCC Decoupling

Connect one 100-nF capacitor per each VCC pin. Placement should be as close as possible to the pin. It is also recommended to place a 4.7-µF capacitor near the device.

Use traces as thick as possible to eliminate voltage drops in the connection.

3.14.3 VCC33 Decoupling

Connect one 100-nF capacitor per each Vcc33 pin. Placement should be as close as possible to the pin. It is also recommended to place a 4.7-µF capacitor near the device.

Use traces as thick as possible to eliminate voltage drops in the connection.

3.14.4 VCCDDR Decoupling

Connect one 100-nF capacitor per each VCCDDR pin. Placement should be as close as possible to the pin. It is also recommended to place a 4.7-µF capacitor near the device.

Use traces as thick as possible to eliminate voltage drops in the connection.

3.14.5 Power Sequence

Power sequence is crucial for proper functioning of the IXP43X network processors. For a complete description of power sequencing, see the Intel Network Processors Datasheet.

3.14.6 Reset Timing

Proper reset timing is also a crucial requirement for proper functioning of the IXP43X network processors. There are two reset signal PWRON_RESET_N and RESET_IN_N which required assertion sequence.

For a complete description of their functionality, see the Intel Network Processors Datasheet and its section titled Reset Timings. PWRON_RESET_N is used as a Power Good and RESET_IN_N is used for resetting internal registers.

IXP43X Product Line of

IXP43X Product Line of Network Processors

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Hardware Design Guidelines—Intel

The IXP43X network processors can be configured at reset de-assertion via external, pull-down resistors on the address expansion bus signals EX_ADDR[23:21]. For a complete description, see Section 6, “Boot/Reset Strapping Configuration” on page 22.

IXP43X Product Line of Network Processors

§ §

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Intel® IXP43X Product Line of Network Processors

Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

4.0 General PCB Guide

4.1 PCB Overview

Beginning with components selection, this chapter presents general PCB guidelines. In cases where it is too difficult to adhere to a guideline, engineering judgment must be used. The methods are listed as simple DOs and DO NOT’s.

This chapter does not discuss the functional aspects of any bus, or layout guides for any interfaced devices.

4.2 General Recommendations

It is recommended that boards based on the IXP43X network processors employ a PCB stackup yielding a target impedance of 50 Ω ± 10% with 5 mil nominal trace width. That is, the impedance of the trace when not subjected to the fields created by changing current in neighboring traces.

When calculating flight times, it is important to consider the minimum and maximum impedance of a trace based on the switching of neighboring traces. Using wider spaces between the traces can minimize this trace-to-trace coupling. In addition, these wider spaces reduce crosstalk and settling time.

4.3 Component Selection

• Do not use components faster than necessary Clock rise (fall) time should be as slow as possible, as the spectral content of the

waveform decreases

• Use components with output drive strength (slew-rate) controllable if available

• Use SMT components (not through-hole components) as through-hole (leaded) components have more stub inductance due to the protruding leads.

• Avoid sockets when possible

• Minimize number of connectors

4.4 Component Placement

As shown in Figure 16 on page 57, when placing components, put:

• High-frequency components in the middle

• Medium-frequency around the high-frequency components

• Low-frequency components around the edge of the printed circuit board

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Hardware Design Guidelines—Intel

IXP43X Product Line of Network Processors

Figure 16. Component Placement on a PCB

Medium Frequency

High Frequency

Components

Low FrequencyAnalog Circuit

C O N N E C T O R

PCB

B2264-01

• Place noisy parts (clock, processor, video, and so on.) at least 1.5 – 3 inches away from the edge of the printed circuit board

• Do not place noisy components close to internal/external cables

— Any loose cables picks up noise and acts as an antenna to radiate that noise — Be aware of the peak in-rush surge current into the device pins. This surge

current can inject high-frequency switching noise into power planes of the printed circuit board

• Place high-current components near the power sources

• Do not share the same physical components (such as buffers and inverters) between high-speed and low-speed signals. Use separate parts.

• Place clock drivers and receivers such that clock trace length is minimized

• Place clock generation circuits near a ground stitch location. Place a localized ground plane around the clock circuits and connect the localized plane to system ground plane

• Install clock circuits directly on the printed circuit board, not on sockets

• Clock crystals should lie flat against the board to provide better coupling of electromagnetic fields to the board

4.5 Stack-Up Selection

Stack-up selection directly affects the trace geometry which, in turn, affects the characteristic impedance requirement for the printed-circuit board. Additionally, the clean, noise-free-planes design and placement is significantly important as components run at higher speeds requiring more power.

Considerations include:

• Low-speed, printed-circuit-board construction — for example two-layer boards:

— Advantages:

•Inexpensive

• Manufactured by virtually all printed-circuit-board vendors

— Disadvantages:

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• Poor routing density

• Uncontrolled signal trace impedance

• Lack of power/ground planes, resulting in unacceptable crosstalk

• Relatively high-impedance power distribution circuitry, resulting in noise on the power and ground rails

• High-speed circuits require multi-layer printed circuit boards: — Advantages:

• Controlled-impedance traces

• Low-impedance power distribution

— Disadvantages:

• Higher cost

•More weight

• M anufactured by fewer vendors

• Symmetry is essential to keep the board stack-up symmetric about the center

This minimizes warping

• For best impedance control, have: — No more than two signal layers between every power/ground plane pair — No more than one embedded micro-strip layer under the top/bottom layers

• For best noise control, route adjacent layers orthogonally. Avoid layer-to-layer

parallelism

• Fabrication house must agree on design rules, including: — Trace width, trace separation — Drill/via sizes

• The distance between the signal layer and ground (or power) should be minimized

to reduce the loop area enclosed by the return current

— Use 0.7:1 ratio as a minimum.

For example: 5-mil traces , 7-mil prepreg thickness to adjacent power/ground.

Figure 17 and Figure 18 provides an example for a six-layer and eight-layer board. For

stripline (signals between planes), the stackup should be such that the signal line is closer to one of the planes by a factor of five or more. Then the trace impedance is controlled predominantly by the distance to the nearest plane.

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Figure 17. 8-Layer Stackup

IXP43X Product Line of Network Processors

Solder (Bottom) Side

Figure 18. 6-Layer Stackup

Solder (Bottom) Side

Component (Top) Side

Data

Component (Top) Side

4.5 mil 5 mil

4.5 mil 7 mil

~40 mil

7 mil

4.5 mil

7 mil

4.5 mil

17.8 mil

62 mil

5 mil

62 mil

L1 L2 L3 L4

L5 L6 L7 L8

L1 L2 L3

L4 L5 L6

SIGNAL

POWER

SIGNAL

GND

POWER

Legend

GND

B2244-02

Legend

B2275-02

• Fast and slow transmission line networks must be considered

•PCB-board velocities

•Board FR4 ~ 4.3

• Target impedance of 50 Ω ± 10%

• Trace width: 5 mils

• Signal Layers (1/2 oz. Copper)

• Power Layer (1 oz. Copper)

• Ground (GND) Layer (1 oz. Copper)

§ §

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5.0 General Layout and Routing Guide

5.1 Overview

This chapter provides routing and layout guides for hardware and systems based on the IXP43X network processors.

The high-speed clocking required when designing with the processors requires special attention to signal integrity. In fact, it is highly recommended that the board design be simulated to determine optimum layout for signal integrity. The information in this chapter provides guidelines to aid designers with board layout. In cases where it is too difficult to follow a design rule, engineering judgment must be used.

5.2 General Layout Guidelines

The layout guidelines recommended in this section are based on experience and knowledge gained from previous designs. Layer stacking varies, depending on design complexity, however following standard rules helps minimize potential problems dealing with signal integrity.

The following recommendations help to route a functional board:

• Provide enough routing layers to comply with minimum and maximum timing requirements of the IXP43X network processors and other components.

• Connectors, and mounting holes must be placed in a ways that will not interfere with basic design guidelines in this document.

• Provide uniform impedance throughout the board, specially for high speed areas such us clocking, DDRII/I-SDRAM, PCI, device bus, and so forth.

• Place analog, high-voltage, power supply, low-speed, and high-speed devices in various sections of the board.

• Decoupling capacitors must be placed next to power pins.

• Series termination resistors must be placed close to the source.

• Analog and digital sections of the board must be physically isolated from each other. No common ground, power planes, and signal traces are allowed to cross-isolation zones. Use appropriately sized PCB traces for larger enough to handle peak current. Keep away from high-spe ed digital signals.

• Keep stubs as short as possible (preferably, the electrical length of the stub less than half of the length of the rise time of signal).

• All critical signals should be routed before all other non-critical signals.

• Do not route signals close to the edge of the board, power or ground planes. Route signal at least 50 to 100 mils away from the edge of the plane.

• Try to match buses to the same trace length and keep them in groups adjacent to each other, away from other signals.

• Route processor address, data and control signals using a daisy-chain topology.

• Minimize number of vias and corners on all high speed signals.

• Do not route under crystals or clock oscillators, clock synthesizers, or magnetic devices (ferrites, toroids).

• Maintain trace spacing consistent between differential pairs and match trace length.

• Keep differential signals away from long and parallel, high-speed paths, such as clock signals and data strobe signals.

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• Do not place high-frequency oscillators and switching network devices close to sensitive analog circuits.

• Arrange the board so that return currents for high-speed traces must never jump between planes. Restrict traces to remain on either side of whichever ground plane they start out nearest. This allows the use of naturally grouped horizontal and vertical routing layers.

If signals change between layers, the reference voltage changes, as shown in

Figure 19. This creates discontinuity in the path of the signal.

Figure 19. Signal Changing Reference Planes

Driver

GND

PWR

ByPass Caps

Signal

Trace

The design in Figure 19, routes a signal on the top layer, close to the GND plane, and provides a very good return current path. The signal then is routed to the bottom layer, close to the PWR plane, such that the return current flows to the ground plane through bypass caps. Thus the path for the return currents is less inductive than in the previous case where the signal is routed on the top layer.

5.2.1 General Component Spacing

• Do not place components within 125 mils to the edge of the printed circuit board. For exact dimensions consult your manufacturing vendor.

• Keep a minimum spacing between via and the solder pad edges >

• Position devices that interface with each other close to one another to minimize trace lengths.

VIAs

Return Current

Signal

Receiver

B2269-01

25mil.

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Figure 20. Good Design Practice for VIA Hole Placement

25 mils min

B2266-01

Figure 20 and Figure 21 show good and poor design practices for via placement on

surface-mount boards.

Figure 22 shows minimum pad-to-pad clearance for surface-mount passive

components and PGA or BGA components.

Figure 21. Poor Design Practice for VIA Placement

Flush Via min

Potential Bridge min

B2267-01

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IXP43X Product Line of Network Processors

Figure 22. Pad-to-Pad Clearance of Passive Components to a PGA or BGA

PBGA Package

60 mils min

60 mils min 60 mils min

5.2.2 Clock Signal Cons ide r ations

• Provide good return current paths for clock traces.

• Keep clock traces away from the edge of the board and any other high-speed devices or traces.

• Keep clock traces away from analog signals, including voltage reference signals.

• Clock signals should not cross over a split plane.

• Route clock signals in a single, internal layers and eliminate routing in multiple layers as much as possible.

• Do not route traces or vias under crystals or clock oscillators devices unless there is a plane between the trace and the component.

• Do not route parallel signal traces directly above or below clock traces unless there is a ground or at least a power plane separation between those layers.

• Route clock traces with a minimum number of vias.

• Space clock traces away from other signals three times the trace width on each side.

• Use guard traces when routing on top or bottom layers whenever possible. Guard traces must be connected to ground.

• Do not daisy-chain, instead use point-to-point clock distribution. Place a series termination resistor as close as possible to the source.

• Keep traces short to minimize reflections and signal degradation.

• Maintain control impedance for all clock traces, microstrip or stripline.

B2268 - 01

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— Be aware of propagation delays between a microstrip and stripline. — Calculate capacitive loading of all components and properly compensate with a

series or parallel terminations.

• Measure and match trace lengths for devices that interface with each other and have their clock derived from the same source.

If traces must be long, treat them as transmission lines. Terminate clock traces to match trace impedance.

• If there is a power plane, instead of a ground plane, make sure that the power plane has adequate decoupling to ground, especially near clock drivers and receivers.

5.2.3 MII Signal Considerations

MII signals run at 25 MHz and the required routing guide lines are as follows:

• Minimize the number of vias to two per trace

• Keep traces as short as possible and straight, away from other signals

• Control impedance to maintain at 50 Ω

• the length of Rx or Tx in each group must match

• Avoid sharp corners, using 45° corners instead

5.2.4 USB V2.0 Considerations

The following are recommendations for routing differential pair signal required to by the USB interface:

• T races can be routed in tightly couple structure with 5mil trace width and 10mil air gap, or maintain air gap equal 2X trace width. It is recommended to route manually.

• Match trace length for each differential pair.

• Avoid sharp corners, use 45° corners instead.

• Always use a perfect symmetry within a differential pair.

• Minimize the number vias.

• Avoid routing other signals close by or in parallel to the differential pair, maintaining no less than 50 mil to any other signal.

• Maintain control impedance for each differential pair to 90 Ω +/- 15 Ω.

• Use high value ferrite beads (100 MHz/60 Ω – 100 MHz/240 Ω).

5.2.5 Crosstalk

Crosstalk is caused by capacitance and inductance coupling between signals. It is composed of both backward and forward crosstalk components.

Backward crosstalk creates an induced signal on the network that propagates in the opposite direction of the aggressor signal. Forward crosstalk creates a signal that propagates in the same direction as the aggressor signal.

Circuit board analysis software should be used to analyze your board layout for crosstalk problems.

• To effectively route signals on the PCB, signals are grouped (address, data, and so on.).

— The space between groups can be 3 w (where w is the width of the traces).

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IXP43X Product Line of Network Processors

— Space within a group can be just 1 w. — Space between clock signals or clock to any other signal should be 3 w. The

coupled noise between adjacent traces decreases by the square of the distance between the adjacent traces.

5.2.6 EMI Design Considerations

It is strongly recommended that good electromagnetic interference (EMI) design practices must be followed while designing with the IXP43X network processors.

• Information on spread-spectrum clocking is available in the Intel® IXP4XX Product Line of Network Processors and IXC1100 Control Plane Processor: Spread-

Spectrum Clocking to Reduce EMI Application Note.

• Place high-current devices as closely as possible to the power sources.

• Proper termination of signals can reduce reflections, which can emit a highfrequency component that contribute to more EMI than the original signal itself.

• Ferrite beads can be used to add high frequency loss to a circuit without introducing power loss at DC and low frequencies. They are effective when used to absorb high-frequency oscillations from switching transients or parasitic resonances within a circuit.

• Keep rise and fall times as slow as possible. Signals with fast rise and fall times contain many high-frequency harmonics which can radiate significantly.

• A solid ground is essential at the I/O connector to chassis and ground plane.

• Keep the power plane shorter than the ground plane by at least 5x the spacing between the power and ground planes.

• Stitch together all ground planes around the edge to the board every 100 to 200 mil. This helps reduce EMI radiating out of the board from inner layers.

5.2.7 Trace Impedance

All signal layers require controlled impedance of 50 Ω ±10 % microstrip or stripline (unless otherwise specified) where appropriate. Selecting the appropriate board stackup to minimize impedance variations is very important.

When calculating flight times, it is important to consider the minimum and maximum trace impedance based on the switching neighboring traces.

5.2.8 Power and Ground Plane

Power and ground planes should have sufficient decoupling capacitors to ensure sustainable current needed for high-speed switching devices. See Section 3.14.1,

“Decoupling Capacitance Recommendations” on page 54.

• It is highly recommended to use sufficient internal power and ground planes.

•The Intel appropriate to use power islands in the power plane under the processor, as it will be too expensive to have a power plane for each power source.

• Power islands must be large enough to include the required power supply decoupling capacitance, and the necessary connection to the voltage source and destination.

• Islands can be separated by a minimum of 20-mil air gap.

• Use at least one via per power or ground pin, wherever possible use more vias, depending on current drawn.

IXP43X Product Line requires a number of power supplies. It is

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• Use at least one decoupling capacitor per power pin and place it as close as possible to the pin.

• Minimize the number of traces routed across the air gaps between power islands.

— Each crossing int r oduces signal degradation due to the impedance

discontinuity.

— For traces that must cross air gaps, route them on the side of the board next to

a ground plane to reduce or eliminate signal degradation caused by crossing the gap.

— When this is not possible, then route the trace to cross the gap at a right angle

(90°).

§ §

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6.0 PCI Interface Design Considerations

The IXP43X network processors have a single, 32-bit PCI device module that runs at 33 MHz. This chapter describes some basic guidelines to help design hardware that interfaces with PCI devices.

The PCI module is compatible with the PCI Local Bus Specification, Rev. 2.2. For a complete functional description and physical requirements, see the PCI Local Bus Specification, Rev. 2.2.

6.1 Electrical Interface

The electrical definition is restricted to 3.3 V signaling environment. The device is not 5 V tolerant. All devices interfacing with the PCI module must operate at 3.3 V.

6.2 Topology

Interfacing devices must be connected in a daisy-chain topology. When more than one device is in the bus, connecting stubs must be kept as short as possible.

There is a limitation to the number of devices connected to the internal arbiter. If more than four devices are required to be connected, an external arbiter is required.

The system time budget must be satisfied for 33 MHz cycles. The following equation and timing parameters must be met while routing a board that interfaces with a single PCI device or up to four devices as shown in Figure 23.

≥ T

CYC

VAL

PROP

+ T

SKEW

+ T

where:

= Valid Output Delay

VAL

= Bus Propagation Delay (maximum time for complete flight)

PROP

= Total Clock Skew

SKEW

= Input Setup Time

@33 MHz T

= 30 nSec T

CYC

= 11 nSec T

VAL

= 10 nSec T

PROP

= 2 nSec TSU = 7 nSec

SKEW

When defining the maximum length of segments A and B as shown in Figure 23, the calculation must:

• Include an additional trace length segment from the PCI connector to the input device within the expansion PCI card

• Assume the segment to be 1.5 inch

• Use trace propagation delay of 150 to 190 ps/in as specified by the PCI standard

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Figure 23. PCI Address/Data Topology

Intel® IXP43X

Product Line of

PCI Slot

Network

Processors

Table 22. PCI Address/Data Routing Guidelines

Parameter Routing Guidelines

Signal Group PCI Address/Data Topology Daisy Chain Reference Plane Ground Characteristic Trace Impedance 55 Ω ±10% Nominal Trace Width 5 mils Nominal Trace Separation 10 mils Spacing to Other Groups 20 mils Limit the number of VIAS to 10 per Signal 10

PCI Slo t PCI Slo t PCI Slo t

BBB

B 5196-003

6.3 Clock Distribution

To meet timing and avoid clock overloading, it is recommended to use point-to-point clock distribution as shown in Figure 24.

Clock skew between interfacing devices is very critical and must be met. The maximum skew must be measured between any two components. If designing a motherboard, the skew must be measured to the expansion card device and not to the PCI connector. Ensure that clock skew between all devices does not exceed the values in Section 6.2.

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IXP43X Product Line of Network Processors

Figure 24. PCI Clock Topology

PCI Devices

33 MHz

Table 23. PCI Clock Routing Guidelines

Signal Group PCI Clock Topology Point-to-Point Reference Plane Ground Characteristic Trace Impedance 55 Ω ±10% Nominal Trace Width 5 mils Nominal Trace Separation 10 mils Spacing to Other Groups 20 mils Trace length A Maximum 300 mils

Trace length B

Resistor Rs 22 Ω ±10% Maximum VIAS 6

Driver

Parameter Routing Guidelines

Clock

Intel®

IXP43X

Product Line

of Network

Processors

B4114 -004

There is no limit as long as the trace length is maintained for each clock and that maximum clock skew is not violated.

6.3.1 Trace Length Limits

Maximum trace lengths can be calculated for specific speeds at which the bus is intended to run. The limitations of the maximum trace length can be calculated with the equations shown in Section 6.2. Solve for T trace length. This is a straight-forward calculation, but v ery critical to meet timing. It is recommended to keep the trace lengths as short as possible and not to exceed T

Note: For acceptable signal integrity at up to 33 MHz, it is very important to design the PCB

board with controller impedance in the range of 55 Ω ±10%.

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and use it to calculate the maximum

PROP

Intel® IXP43X Product Line of Network Processors

Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

6.3.2 Routing Guidelines

It is recommended to route signals with respect to an adjacent ground plane. If routing signals over power planes, ensure that the signals are referenced to a single power plane voltage level and not multiple levels. For example, you can route signals over a

3.3 V plane or a 5 V plane, but do not route the same signal over both planes. If signals are routed over split planes, you must connect the splitting planes with 0.01 µF, high-speed capacitors near the signal crossing the split. The capacitors should not be placed more than 0.25 inches from the point at which the signals cross the split.

This manual does not repeat all the guidelines that are already stated in the PCI Local Bus Specification, Rev. 2.2. Refer to the specification when designing a motherboard or an expansion card.

6.3.3 Signal Loading

Shared PCI signals must be limited to one load on each of the PCI slots. Any violation of expansion board or add-on device trace length or loading limits compromises system-signal integrity.

§ §

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7.0 DDRII / DDRI SDRAM

7.1 Introduction

This document is intended to be used as a guide for routing DDRII/DDRI SDRAM based on the Intel

IXP435 Multi-Service Residential Gateway Reference Platform. It contains routing guidelines and simulation results for using x16 Thin Small Outline Package (TSOP) memory devices soldered onto the processor module.

The memory controller only corrects single bit ECC errors on read cycles. The ECC is stored into the DDRII/DDRI SDRAM array along with the data and is checked when the data is read. If the code is incorrect, the MCU corrects the data before reaching the initiator of the read. ECC error scrubbing is done with software. User-defined fault correction software is responsible for scrubbing the memory array and handling dou blebit errors.

To limit double-bit errors from occurring, periodically read the entire usable memory array to allow the hardware unit within the memory controller to correct any single-bit. This also prevents the ECC errors that would have occurred prior to these errors becoming double-bit ECC errors. Implementing this method is system-dependent.

Note: It is important to note that when sub-word writes (byte writes or half-word writes

within a word-aligned boundary) are done to a 32-bit memory with ECC enabled, the memory controller performs read-modify writes. There is a performance impact with read-modify writes that must be considered when writing software.

With read-modify writes, the memory controller reads the 32-bit word that encompasses the byte that is to be written when a byte write is requested. The memory controller modifies the specified byte, calculates a new ECC, and writes the entire 32-bit word back into the memory location it was read from.

The value written back into the memory location contains the 32-bit word with the modified byte and the new ECC value.

The MCU supports two physical banks of DDRII/DDRI SDRAM. The MCU has support for unbuffered DDRI 266 and DDRII 400 in the form of discrete chips only.

The MCU supports a memory subsystem ranging from 32 MB to 1 GB for 32-bit memory systems for DDRI SDRAM, from 64 MB to 512 MB for 32-bit memory systems for DDRII SDRAM, and supports 16 MB for 16-bit memory systems for DDRI SDRAM (non-ECC), and 32 MB for 16-bit memory systems for DDRII SDRAM (non-ECC). An ECC or non-ECC system can be implemented using x8, or x16 devices. Table 25,

Table 26, Table 27 and Table 28 illustrate the supported DDRII/DDRI SDRAM

configurations The two DDRII/DDRI SDRAM chip enables (DDR_CS_N[1:0]) support a DDRII/DDRI

SDRAM memory subsystem consisting of two banks. The base address for the two contiguous banks are programmed in the DDRII/DDRI SDRAM Base Register (SDBR) and is aligned to a 16 MB boundary. The size of each DDRII/DDRI SDRAM bank is programmed with the DDRII/DDRI SDRAM boundary registers (SBR0 and SBR1).

The DDRII/DDRI SDRAM devices comprise four internal leaves. The MCU controls the leaf selects within DDRII/DDRI SDRAM by toggling DDR_BA[0] and DDR_BA[1].

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Table 24. DDRII/I Signal Groups

Group Signal Name Description

D_CK[2:0] / DDR_CK[2:0] DDRII/I SDRAM Differential Clocks

Clocks

Data

Control

Command

D_CK_N[2:0] / DDR_CK_N[2:0]

D_CB[7:0] / DDR_CB[7:0] E CC Data D_DQ[31:0] /

DDR_DQ[31:0] D_DQS[4:0] /

DDR_DQS[4:0] D_DQS_N[4:0] Complementary Data Strobes D_DM[4:0] /

DDR_DM[4:0] D_CKE[1:0] /

DDR_CKE[1:0] D_CS_N[1:0] /

DDR_CS_N[1:0] D_MA[13:0] /

DDR_MA[13:0] D_BA[1:0] / DDR_BA[1:0] Bank Select D_RAS_N / DDR_RAS_N Row Address Select D_CAS_N / DDR_CAS_N Column Address Select D_WE_N / DDR_WE_N Write Enable

DDRII/I SDRAM Inverted Differential Clocks

Data Bus

Data Strobes

Data Mask

Clock Enable - one per bank

Chip Select - one per bank

Address Bus

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Figure 25. Processor-DDRII/I SDRAM Interface

DDRII/I_DQ[31:0]

DDRII/I_MA[13:0]

DDRII/I_CK[2:0]

DDRII/I_CK_N[2:0]

DDRII/I_CKE[1:0]

DDRII/I_CS_N[1: 0]

DDRII/I_BA [1: 0]

DDRII/I_CB[7:0]

DDRII/I_DM[4:0]

DATA[31:0]

ADDRESS[13:0]

CLOCK[2:0], CLOCK#[2:0]

CLOCK ENABLE[1:0]

CHIP SELECT#[1:0]

BANK SE LECT[1:0]

ECC DATA[7:0]

DATA MASK[4:0]

DQ[31:0]

A[13:0]

CK[2:0]

CK#[2:0]

CKE[1:0]

DDR SDRAM

CS#[1:0]

BA[1:0]

DQ[7:0]

DM[4:0]

Intel® IXP43X P roduc t Line of Network Pr ocesso rs

DDRII/I_DQS[4:0]

DDRII/I_WE_N

DDRII/I_RAS_N

DDRII/I_CAS_N

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DATA STROBE[4:0 ]

WRITE#, RAS#, CAS #

Intel® IXP43X Product Line of Network Processors

DQS[4:0]

WE# RAS# CAS#

B3986-003

Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

Table 25. S upported DDRI 32-bit SDRAM Configurations

DDR SDRAM

Technology

128 Mbit

256 Mbit

512 Mbit

1Gbit

DDR SDRAM

Arrangement

16 M x 8

8 M x 16

32 M x 8

16 M x 16

64 M x 8

32 M x 16

128 M x 8

64 M x 16

# Banks

1 2 128 M 4KB 1 2 64 M 2KB 1 2 256 M 4KB 1 2 128 M 2KB 1 2 512 M 8KB 1 2 256 M 4KB 1 2 1 G 8KB 1 2 512 M 4KB

a. Table indicates 32-bit wide memory subsystem sizes. b. Table indicates 32-bit wide memory page sizes. c. Supported with DDR SDRAM only

Address Size Leaf Select Total

Row Column DDR_BA[1] DDR_BA[0]

12 10 ADDR[26] ADDR[25]

12 9 ADDR[25] ADDR[24]

13 10 ADDR[27] ADDR[26]

13 9 ADDR[26] ADDR[25]

13 11 ADDR[28] ADDR[27]

13 10 ADDR[27] ADDR[26]

14 11 ADDR[29] ADDR[28]

14 10 ADDR[28] ADDR[27]

Memory

Size

64 M 4KB

32 M 2KB

128 M 4KB

64 M 2KB

256 M 8KB

128 M 4KB

512 M 8KB

256 M 4KB

Page Size

Table 26. S upported DDRII 32-bit SDRAM Configurations

DDR SDRAM

Technology

256 Mbit

512 Mbit

DDR SDRAM

Arrangement

32M x 8

16M x16

64M x 8

32M x16

# of

Banks

1 2 256MB 4KB 1 2 128MB 2KB 1 2 512MB 4KB 1 2 256MB 4KB

Address Size Leaf Select

Row Column DDR_BA[1] DDR_BA[0]

13 10 ADDR[27] ADDR[26]

13 9 ADDR[26] ADDR[25]

14 10 ADDR[28] ADDR[27]

13 10 ADDR[27] ADDR[26]

Total

Memory

Size

128MB 4KB

64MB 2KB

256MB 4KB

128MB 4KB

Table 27. S upported DDRI 16-bit SDRAM Configurations

DDR SDRAM

Technology

DDR SDRAM

Arrangement

# of

Banks

Address Size Leaf Select

Row Column DDR_BA[1] DDR_BA[0]

128 Mbit 8M x16 1 12 9 ADDR[23] ADDR[22] 16MB 1KB

Total

Memory

Size

Page

Size

Page

Size

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Table 28. Supported DDRII 16-bit SDRAM Configurations

IXP43X Product Line of Network Processors

DDR SDRAM

Technology

256 Mbit 16M x16 1 13 9 ADDR[24] ADDR[23] 32MB 1KB

DDR SDRAM

Arrangement

The DDR_RCOMP signal must be terminated through resistors specified in Figure 26. This allows the DDRII/I controller to make temperature and process adjustments.

# of

Banks

Address Size Leaf Select

Row C olumn

DDR_BA[1

]

DDR_BA[0]

Total

Memory

Size

7.2 DDRII/DDRI RCOMP and Slew Resistances Pin Requirements

Figure 26 shows the requirements for the DDRII/DDRI RCOMP pin.

Figure 26. DDRII/DDRI RCOMP Pin External Resistor Requirements

DDRI

R1 = 3 87Ω

± 1

resistor

DDRII

R1 = 285Ω

± 1

% resistor

DDRIMPCRES

Intel® IXP43X

DDRCRES

Product Line of

Network Processors

Page

Size

DDRSLWCRES

DDRI

R2 = 8 45Ω

R2 = 825Ω

For example, when DDRI SDRAM is used, DDRIMPCRES is connected with 387Ω and DDRSLWCRES is connected with 845Ω resistor to DDRCRES0.

April 2007 HDG Document Number: 316844; Revision: 001US 75

DDRII

± 1

% resistor

± 1

% resistor

Intel® IXP43X Product Line of Network Processors

Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

7.3 DDRII OCD Pin Requirements

Figure 27 shows the requirement for the DDRRES1 and DDRRES2 pins.

Figure 27. DDRII OCD Pin Requirements

DDRRES2

Intel® IXP43X

DDRRES1

resistor

40.2

resistor

0. 1 u F

Note: Since the OCD calibration function is not enabled, DDRRES2 must be pulled to ground

with a 1-KΩ resistor.

7.3.1 Signal-Timing Analysis

Product Li ne

of Netw or k

Processors

Figure 28. DDR Clock Timing Waveform

ih (min )

il(ma x )

test

Table 29. DDR Clock Timings

Symbol Parameter

DDR SDRAM clock Frequency 200 133 MHz

DDR SDRAM clock Cycle Time 5 7.5 ns 1

DDR SDRAM clock High Time 2.15 3.37 ns 1

DDR SDRAM clock Low Time 2.15 3.37 ns 1

DDR SDRAM clock Period Stability 350 350 ps

Notes:

1. See Figure 28, “DDR Clock Timing Waveform” on page 76

2. Vtest is nominally (0.5 * Vtch - Vtcl)

DDR SDRAM clock skew for any differential clock pair (D_CK[2:0] -

skew

D_CK_N[2:0])

ih (min)

il(ma x)

DDR-II 400 DDR-I 266

Min Max Min Max

il(ma x )

100 100 ps

test

Units Notes

tch

tcl

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Hardware Design Guidelines—Intel

IXP43X Product Line of Network Processors

Figure 29. DDR SDRAM Write Timings

ADD R/CTRL

CS[1:0]#

VB3

VB5

VA3

VA5

DQS

DQS#

VB1

Figure 30. DDR SDRAM Read Timings

DQS

VA1

VB4

VA4

April 2007 HDG Document Number: 316844; Revision: 001US 77

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Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

Figure 31. DDR - Write Preamble/Postamble Duration

DQS

VB6

VA6

Table 30. DDRII-400 MHz Interface -- Signal Timings

Symbol Parameter Minimum Nominal Maximum Units Notes

T T

T T T T

Notes:

1. See Figure 29, “DDR SDRAM Write Timings” on page 77

2. See Figure 30, “DDR SDRAM Read Timings” on page 77. The specified minimum requirements for the “Data to strobe

3. See Figure 31, “DDR - Write Preamble/Postamble Duration” on page 78

4. Address/Command pin group; RAS_N, CAS_N, WE_N, MA[13:0], BA[1:0]

5. Designed to JEDEC specification; it is recommended that IBIS models should be used to verify signal integrity on

DQ, CB and DM write output valid time before DQS. 521 ps 1

VB1

DQ, CB and DM write output valid time after DQS. 521 ps 1

VA1

Address and Command write output valid before CK

VB3

rising edge. Address and Command write output valid after CK rising

VA3

edge. DQ, CB and DM read input valid time before DQS rising

VB4

or falling edges. DQ, CB and DM read input valid time after DQS risin g or

VA4

falling edges. CS_N[1:0] control valid before CK rising edge. 1771 ps 4

VB5

CS_N[1:0] control valid after CK rising edge. 1771 ps 4

VA5

DQS write preamble duration. 3750 ps 3

VB6

DQS write postamble duration. 2500 ps 3

VA6

DQ, CB, and DM pulse width (tDIPW) 1750 ps 1

read setup” and “Data from strobe read hold” are determined with the DQS delay programmed for 90 degree phase shift.

1771 ps 1, 4

323 ps 2

individual designs

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Hardware Design Guidelines—Intel

Table 31. DDR II/I SDRAM Interface -- Signal Timings

Symbol Parameter Minimum Nom. Maximum Units Notes

T T T

Notes:

1. See Figure 29, “DDR SDRAM Write Timings” on page 77

2. See Figure 30, “DDR SDRAM Read Timings” on page 77. The specified minimum requirements for “Data to

3. See Figure 31, “DDR - Write Preamble/Postamble Duration” on page 78

4. Address/Command pin group; RAS_N, CAS_N, WE_N, MA[13:0], BA[1:0]

5. Designed to JEDEC specification; it is recommended that IBIS models should be used to verify signal

DQ, CB and DM write output valid time

VB1

before DQS. DQ, CB and DM write output valid time after

VA1

DQS. Address and Command write output valid

VB3

before CK rising edge. Address and Command write output valid

VA3

after CK rising edge. DQ, CB and DM read input valid time before

VB4

DQS rising or falling edges. DQ, CB and DM read input valid time after

VA4

DQS rising or falling edges. CS_N[1:0] control valid before CK rising

VB5

edge. CS_N[1:0] control valid after CK rising edge. 3021 ps 4

VA5

DQS write preamble duration. 5625 ps 3

VB6

DQS write postamble duration. 3750 ps 3

VA6

DQ, CB, and DM pulse width (tDIPW) 1750 ps 1

strobe read setup” and “Data from strobe read hold” are determined with the DQS delay programmed for 90 degree phase shift.

integrity on individual designs

IXP43X Product Line of Network Processors

1146 ps 1

3021 ps 1, 4

948 p s 2

3021 ps 4

7.3.1.0.1 Printed Circuit Board Layer Stackup

The layer stackup used for the Intel

IXP435 Multi-Service Residential Gateway Reference Platform is a 6-layer, printed circuit board with four signal layers and two plane layers.

Details on the voltage reference layout are available in the CAD database or Gerber files database for the Intel

IXP435 Multi-Service Residential Gateway Reference

Platform.

7.3.2 Timing Relationships

The routing guidelines presented in the following subsections define the recommended routing topologies, trace width, spacing geometries, and typical routed lengths for each signal group. These parameters are recommended to achieve optimal signal integrity and timing.

All signal groups are length matched to the DDR clocks. The clocks on the processor module are length matched to within ±10 mils of each other. Once this overall clock length for any given DDR differential clock is determined, the command and control signals can be routed to within the timing specified. A simple summary of the timing results for each signal group is provided in Table 32 on page 80.

Control/Command Group to Clock Summary:

• The maximum allowable difference from any command/control signal to the clock is ±0.6 ns.

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Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

— Table 31 on page 79

Data Group to Strobe Summary:

• The more restrictive data group to strobe timing occurs for read operations — Table 32 on page 80 — Table 33 on page 80

• The maximum allowable difference from any data group signal to the strobe is

±0.25 ns.

— Figure 30 on page 77 — Table 32 on page 80

Strobe to Clock Summary:

• The maximum allowable difference from any data strobe signal to the clock is -

0.475 ns to +0.875 ns — Figure 32 on page 83 — Table 34 on page 83

These are absolute maximum ratings for length mismatch based in ideal printed board conditions (exact signal propagation delays, ideal signal integrity with no reflections or settling, zero rise/fall times, and so on.). T o compensate for these non-ideal conditions, more restrictive length matching conditions should be used based on signal integrity analysis and simulation to provide a buffer zone and avoid possible variations in silicon or printed circuit board manufacture.

Table 32. Timing Relationships

Signal Group Absolute Minimum Length Absolute Maximum Length

Control to Clock Clock – 600 ps Clock + 600 ps

Command to Clock Clock – 600 ps Clock + 600 ps

Data to Strobe Strobe – 250 ps Strobe + 250 ps

Strobe to Clock Clock – 475 ps Clock + 875 ps

In addition to any trace length differentials which must be considered between signal groups, differences in the package length between signals should be considered when determining the total propagation delay of the signals. When using the IXP435 reference platform IBIS model for signal analysis, package characteristics are included in the simulation results.

Table 33. Signal Package Lengths (Sheet 1 of 3)

Group Signal Name Length (mil) Signal Name Length (mil)

Clock

D_CK_N0 /

DDR_CK_N0

D_CK_N1 /

DDR_CK_N1

D_CK_N2 /

DDR_CK_N2

558.19 D_CK0 / DDR_CK0 507.46

385.12 D_CK1 / DDR_CK1 385.12

504.20 D_CK2 / DDR_CK2 548.01

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Hardware Design Guidelines—Intel

IXP43X Product Line of Network Processors

Table 33. Signal Package Lengths (Sheet 2 of 3)

Group Signal Name Length (mil) Signal Name Length (mil)

D_CB0 / DDR_CB0 402.94 D_CB4 / DDR_CB4 385.50 D_CB1 / DDR_CB1 393.93 D_CB5 / DDR_CB5 419.24 D_CB2 / DDR_CB2 377.69 D_CB6 / DDR_CB6 398.22 D_CB3 / DDR_CB3 378.47 D_CB7 / DDR_CB7 435.03

D_DQ0 / DDR_DQ0 447.57

D_DQ1 / DDR_DQ1 449.41

D_DQ2 / DDR_DQ2 394.02

D_DQ3 / DDR_DQ3 366.03

D_DQ4 / DDR_DQ4 449.58

D_DQ5 / DDR_DQ5 470.40

D_DQ6 / DDR_DQ6 413.35

D_DQ7 / DDR_DQ7 384.02

Data

Control

D_DQ8 / DDR_DQ8 368.37

D_DQ9 / DDR_DQ9 399.54

D_DQ10/ DDR_DQ10 374.55

D_DQ11 / DDR_DQ11 398.20

D_DQ12 / DDR_DQ12 396.30

D_DQ13 / DDR_DQ13 408.81

D_DQ14 / DDR_DQ14 371.03

D_DQ15 / DDR_DQ15 388.23

D_DQS0 /

DDR_DQS0

D_DQS1 /

DDR_DQS1

D_DM0 / DDR_DM0 410.19

D_DM1 / DDR_DM1 482.30 D_DM3 / DDR_DM3 536.80 D_DM2 / DDR_DM2 553.44 D_DM4 / DDR_DM4 428.52

D_CKE0 / DDR_CKE0 385.61 D_CKE1 / DDR_CKE1 384.34

D_CS_N0 /

DDR_CS_N0

468.21

371.60

385.35

D_DQ16 /

DDR_DQ16

D_DQ17 /

DDR_DQ17

D_DQ18 /

DDR_DQ18

D_DQ19 /

DDR_DQ19

D_DQ20 /

DDR_DQ20

D_DQ21 /

DDR_DQ21

D_DQ22 /

DDR_DQ22

D_DQ23 /

DDR_DQ23

D_DQ24 /

DDR_DQ24

D_DQ25 /

DDR_DQ25

D_DQ26 /

DDR_DQ26

D_DQ27 /

DDR_DQ27

D_DQ28 /

DDR_DQ28

D_DQ29 /

DDR_DQ29

D_DQ30 /

DDR_DQ30

D_DQ31 /

DDR_DQ31

D_DQS2 /

DDR_DQS2

D_DQS3 /

DDR_DQS3

D_DQS4 /

DDR_DQS4

D_CS_N1 /

DDR_CS_N1

536.32

569.24

545.35

633.70

604.01

608.22

479.46

555.12

472.85

475.30

421.35

419.04

480.43

489.89

430.18

431.50

517.45

463.84

653.53

421.27

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Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

Table 33. Signal Package Lengths (Sheet 3 of 3)

Group Signal Name Length (mil) Signal Name Length (mil)

D_MA0 / DDR_MA0 515.78 D_MA7 / DDR_MA7 438.95 D_MA1 / DDR_MA1 357.69 D_MA8 / DDR_MA8 394.65 D_MA2 / DDR_MA2 509.12 D_MA9 / DDR_MA9 429.78

D_MA3 / DDR_MA3 462.16

D_MA4 / DDR_MA4 444.71

Command

D_MA5 / DDR_MA5 576.87

D_MA6 / DDR_MA6 513.40

D_BA0 / DDR_BA0 530.35 D_BA1 / DDR_BA1 535.27

D_RAS_N /

DDR_RAS_N

D_WE_N /

DDR_WE_N

506.35

513.09

7.3.3 Routing Guidelines

D_MA10 /

DDR_MA10

D_MA11 /

DDR_MA11

D_MA12 /

DDR_MA12

D_MA13 /

DDR_MA13

D_CAS_N /

DDR_CAS_N

378.96

418.37

392.79

433.55

477.26

7.3.3.1 Clock Group

The clock signal group includes the differential clock pairs D_CK[2:0] / DDR_CK[2:0] and D_CK_N[2:0] / DDR_CK_N[2:0].

Here are some tips on how to route the differential clock pairs:

• Ensure that DDR clocks are routed on a single internal layers, except for pin escapes

• A ground plane must be adjacent to the layer where the signals are routed

• Minimize the number of vias used, but ensure that the same number of vias are used in the positive and negative trace

• It is recommended that pin escape vias be located directly adjacent to the ball pads on all clocks

• Traces must be routed for differential mode impedance of 120 Ω

• Surface layer routing should be minimized (top or bottom layers)

• It is recommended to perform pre- and post-layout simulation

A series resistance value in the 25- to 50-Ω range should be used as it adds minimal propagation delay to the signal without adversely varying from the CLK plus DQ propagation delay average. The appropriate v alue for termination resistance should be verified through simulation for the specific topology.

Table 34 provides routing guidelines for signals within this group.

IXP43X Product Line of Network Processors

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Hardware Design Guidelines—Intel

IXP43X Product Line of Network Processors

Figure 32. DDRII Clock Simulation Results: CK Signals

Table 34. Clock Signal Group Routing Guidelines

Parameter Definition

Signal Group Members D_CK[2:0] and D_CK_N[2:0] Topology Differential Pair Point to Point (1 Driver, 4 Receivers) Single Ended Trace Impedance (Z Series Resistor 33 Ω Nominal Trace Width1 Internal (Strip Line) 3.5 mils, External (Micro Strip) 5 mils Nominal Pair Spacing (edge to edge) Minimum Pair to Pair Spacing Any layer 20mils Minimum Spacing to Other DDR Signals 20.0 mils Minimum Spacing to non-DDR Signals 25.0 mils Maximum Via Count 5 per trace Total Trace Length 500 mils to 1000 mils DDR_CK to DDR_CK_N Length Matching Match total length to +/- 10 mils between clocks

Notes:

1. Nominal trace width is determined by board physical characteristics and stack-up. This value should

2. Nominal pair to pair spacing is determined by board physical characteristics and stack-up. This value

be verified with the PWB manufacturer to achieve the desired Zo. should be verified with the PWB manufacturer to achieve the desired Zdiff.

) 50 Ω

Internal (Strip Line) 10.5 mils, External (Micro Strip) 10 mils

7.3.3.2 Data and Control Groups

The data and control signal group includes D_CB[7:0]/DDR_CB[7:0], D_DQ[31:0] / DDR_DQ[31:0], D_DQS[4:0]/DDR_DQS[4:0], D_DM[4:0]/DDR_DM[4:0]., D_CS[1:0]/ DDR_CS[1:0] and D_CKE[1:0]/DDR_CKE[1:0]. The groups should be routed on

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Intel® IXP43X Product Line of Network Processors

Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

internal layers, except for pin escapes. It is recommended that pin escape vias be located directly adjacent to the ball pads on all signals. Surface layer routing should be minimized. The following table provides routing guidelines for signals within these groups.

Figure 33. DDRII Data and Control Simulation Results: DQ and DQS signals

22 ohm

DQSDQS

Table 35. DDRII Data and Control Signal Group Routing Guidelines

Parameter Definition

Signal Group Members

Topology Differential Pair Point to Point (1 Driver, 2 Receivers) Single Ended Trace Impedance (Z Series Resistor 22 Ω Nominal Trace Width1 Internal (Strip Line) 3.5 mils, External (Micro Strip) 5 mils Nominal Pair Spacing (edge to edge) Minimum Pair to Pair Spacing Any layer 20mils

Notes:

1. Nominal trace width is determined by board physical characteristics and stack-up. This value should be verified with the PWB manufacturer to achieve the desired Zo.

2. Nominal pair to pair spacing is determined by board physical characteristics and stack-up. This value should be verified with the PWB manufacturer to achieve the desired Zdiff.

IXP43X Product Line of Network Processors

Intel HDG April 2007 84 Document Number: 316844; Revision: 001US

)50 Ω

D_CB[7:0]/DDR_CB[7:0], D_DQ[31:0] / DDR_DQ[31:0], D_DQS[4:0]/DDR_DQS[4:0], D_DM[4:0]/DDR_DM[4:0]., D_CS[1:0]/DDR_CS[1:0] and D_CKE[1:0]/DDR_CKE[1:0]

Internal (Strip Line) 10.5 mils, External (Micro Strip) 10 mils

Hardware Design Guidelines—Intel

IXP43X Product Line of Network Processors

Table 35. DDRII Data and Control Signal Group Routing Guidelines

Parameter Definition

Minimum Spacing to Other DDR Signals 20.0 mils Minimum Spacing to non-DDR Signals 25.0 mils Maximum Via Count 5 per trace Total Trace Length 1000 mils to 2000 mils

Notes:

1. Nominal trace width is determined by board physical characteristics and stack-up. This value should

2. Nominal pair to pair spacing is determined by board physical characteristics and stack-up. This value

be verified with the PWB manufacturer to achieve the desired Zo. should be verified with the PWB manufacturer to achieve the desired Zdiff.

7.3.3.3 Command Groups

The command signal groups include all signals D_MA[13:0]/DDR_MA[13:0], D_BA[1:0]/DDR_BA[1:0], D_RAS/DDR_RAS, D_CAS/DDR_CAS and D_WE/DDR_WE. The groups should be routed on internal layers, except for pin escapes. It is recommended that pin escape vias be located directly adjacent to the ball pads on all signals. Surface layer routing should be minimized. The following table provides routing guidelines for signals within these groups.

Figure 34. DDRII Command Simulation Results: ADDRESS signals

20ohm20ohm

Table 36. DDRII Command Signal Group Routing Guidelines

Parameter Definition

Signal Group Members

Topology Point to Point (1 Driver, 10Receivers) Single Ended Trace Impedance (Z

Notes:

1. Nominal trace width is determined by board physical characteristics and stack-up. This value should

2. Nominal pair to pair spacing is determined by board physical characteristics and stack-up. This value

April 2007 HDG Document Number: 316844; Revision: 001US 85

be verified with the PWB manufacturer to achieve the desired Zo. should be verified with the PWB manufacturer to achieve the desired Zdiff.

) 50 Ω

D_MA[13:0]/DDR_MA[13:0], D_BA[1:0]/DDR_BA[1:0], D_RAS/DDR_RAS, D_CAS/DDR_CAS and D_WE/DDR_WE.

Intel® IXP43X Product Line of Network Processors

Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

Table 36. DDRII Command Signal Group Routing Guidelines

Parameter Definition

Series Resistor 20 Ω Nominal Trace Width1 Internal (Strip Line) 3.5 mils, External (Micro Strip) 5 mils Nominal Pair Spacing (edge to edge) Minimum Pair to Pair Spacing Any layer 20mils Minimum Spacing to Other DDR Signals 20.0 mils Minimum Spacing to non-DDR Signals 25.0 mils Maximum Via Count 5 per trace Total Trace Length 1500 mils to 2500 mils

Notes:

1. Nominal trace width is determined by board physical characteristics and stack-up. This value should be verified with the PWB manufacturer to achieve the desired Zo.

2. Nominal pair to pair spacing is determined by board physical characteristics and stack-up. This value should be verified with the PWB manufacturer to achieve the desired Zdiff.

Internal (Strip Line) 10.5 mils, External (Micro Strip) 10 mils

§ §

IXP43X Product Line of Network Processors

Intel HDG April 2007 86 Document Number: 316844; Revision: 001US

Intel IXP43X User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Intel® IXP43X Product Line of Network Processors

Contents

Figures

Tables

Revision History

1.0 Introduction

1.1 Content Overview

1.2 Related Documentation

1.3 Acronyms

Table 1. List of Acronyms and Abbreviations (Sheet 1 of 2)

1.4 Overview

Figure 1. Intel® IXP435 Network Processor Block Diagram

1.5 Typical Applications

2.0 System Architecture

2.1 System Architecture Description

2.2 System Memory Map

3.0 General Hardware Design Considerations

Table 2. Signal Type Definitions

3.1 Soft Fusible Features

Table 3. Soft Fusible Features (Sheet 1 of 2)

3.2 DDRII/I SDRAM Interface

3.2.1 Signal Interface

Table 4. DDRII/I SDRAM Interface Pin Description (Sheet 1 of 2)

3.2.2 DDRII/I SDRAM Initialization

3.3 Expansion Bus

3.3.1 Signal Interface

Table 5. Expansion Bus Signal Recommendations (Sheet 1 of 2)

3.3.2 Reset Configuration Straps

Table 6. Boot/Reset Strapping Configuration (Sheet 1 of 2)

3.3.3 8-Bit Device Interface

3.3.4 16-Bit Device Interface

Figure 3. 8/16-Bit Device Interface

3.3.5 Flash Interface

Figure 4. Flash Interface Example

3.4 UART Interface

3.4.1 Signal Interface

Table 8. UART Signal Recommendations

Figure 5. UART Interface Example

3.5 MII Interface

3.5.1 Signal Interface MII

Table 9. MII NPE A Signal Recommendations

Table 10. MII NPE C Signal Recommendations (Sheet 1 of 2)

Table 11. MAC Management Signal Recommendations - NPE A and NPE C

3.5.2 Device Connection, MII

Figure 6. MII Interface Example

3.6 GPIO Interface

3.6.1 Signal Interface

Table 12. GPIO Signal Recommendations

3.6.2 Design Notes

3.7 USB Interface

3.7.1 Signal Interface

Table 13. U SB Host Signal Recommendations

Figure 7. Common Mode Choke

Figure 8. USB RCOMP and ICOMP Pin Requirement

Figure 9. USB Host Down Stream Interface Example

3.8 UTOPIA Level 2 Interface

3.8.1 Signal Interface

Table 14. UTOPIA Level 2/MII_A

3.8.2 Device Connection

Figure 10. UTOPIA Interface Example

3.9 HSS Interface

3.9.1 Signal Interface

Table 15. High-Speed, Serial Interface 0

3.9.2 Device Connection

Figure 11. HSS Interface Example

3.10 SSP Interface

3.10.1 Signal Interface

Table 16. Synchronous Serial Peripheral Port Interface

3.10.2 Device Connection

Figure 12. Serial Flash and SSP Port (SPI) Interface Example

3.11 PCI Interface

3.11.1 Signal Interface

Table 17. PCI Controller (Sheet 1 of 2)

3.11.2 PCI Interface Block Diagram

Figure 13. PCI Interface

3.11.3 PCI Option Interface